JP7525985B2 - Semiconductor wafer transport jig and transport method using same - Google Patents

Description

The present invention relates to a semiconductor wafer transport jig and a transport method using the same.

When wafers are transported into a chamber where they will be heat-treated, for example when polished wafers (PWs) are transported into an epitaxial growth reactor for epitaxial growth, a wafer storage container such as a FOUP (Front-Opening Unified Pod) containing the wafers is docked in the FI (Factory Interface) section of the reactor, and the wafers in the FOUP are transported to the load lock by a wafer transport jig in the FI. The air in the load lock is then replaced with nitrogen, and the wafers are handed over to a wafer transport jig installed in a transfer chamber under nitrogen flow, and the wafers on the wafer transport jig are transported into the chamber (epitaxial growth reactor) where epitaxial growth will be performed. Then, epitaxial growth is performed on the wafers in the chamber.

Figure 4 shows a schematic diagram of a typical wafer transport jig used for loading and unloading wafers into a chamber where heat treatment is performed. In the wafer transport jig of the FI section, for example, as shown in Figure 4, a resin material such as a peak material is used at the contact points between the tip 1' and base 2' of the wafer transport jig 10' and the wafer W', and the wafer W' is transported while chucked by a pusher 3' made of the same material. During transport, it is common to bring the notch of the wafer W' close to the pusher 3'. In the process of removing a PW from a FOUP and transporting it to a load lock, particles are generated when the wafer is chucked with a typical wafer transport jig as shown in Figure 5. When wafer W' is chucked with a pusher, chucking causes W' to move forward at base 2' close to the notch, and particles P are generated when the resin material at the contact position of base 2' is scraped off. These particles adhere to the wafer surface near the notch, and epitaxial growth is carried out in this state, causing epitaxial defects near the notch.

In general, in equipment that performs heat treatment, particularly in current epitaxial growth reactors, the PW before reaction and the epitaxial wafer after reaction are transported using the same FI blade (wafer transport jig), and the edge of the backside of the epitaxial wafer has many defects such as adhered foreign matter and scratches, and repeated contact with resin parts such as peak materials is a cause of material deterioration. Deteriorated resin parts are prone to generating dust, and when the PW is chucked or contacted, particles originating from the resin part are generated. In this way, particles adhere to the wafer surface due to chucking or contact, and when heat treatment such as epitaxial growth is performed on such wafers, the occurrence of defects and other quality deterioration become a problem.

Conventionally, measures have been taken such as adjusting the chucking speed to a slower speed within the operable range and cleaning used resin parts, but it has been difficult to prevent the occurrence of epitaxial defects caused by particles originating from the resin parts. In addition, by replacing the resin parts with new ones with smaller surface roughness, the number of epitaxial defects in the notch area has tended to temporarily decrease, but repeated contact with the epitaxial wafer increases the roughness, making the part more susceptible to dust generation, so it has not been possible to prevent the occurrence of epitaxial defects.

In addition, the following Patent Documents 1 to 4 have proposed wafer transport jigs. Patent Document 1 discloses that in all processes for manufacturing silicon wafers, the contact area between the silicon wafer and a support member acting as a wafer transport jig is limited to an area of 0.50 to 0.80 times the radius of the silicon wafer. Patent Document 2 discloses that high-purity quartz, SiC, etc. are used for the wafer transport jig. Patent Document 3 discloses that in atmospheric pressure CVD, silicon substrates are transported while placed on a SiC tray. However, such methods make transport difficult because the contact area must be limited and the transport jig is made of quartz, SiC, etc., which have a low coefficient of friction.

Patent Document 4 discloses that in a transport device for loading and transporting a substrate such as a glass substrate, the material and area of the loading surface of the transport device are set so as to increase the maximum static friction force between the substrate and the loading surface. However, when the material and area of the loading surface are set in this way so as to increase the maximum static friction force, there is a problem in that dust generation cannot be sufficiently suppressed.

JP 2007-281030 A Japanese Patent Application Publication No. 10-223718 International Publication No. 2017/018300 JP 2001-351962 A

The present invention was made in consideration of the above problems, and aims to provide a semiconductor wafer transport jig and a transport method using the same that suppresses the generation of particles that are thought to cause defects when the wafer is transported into and out of a chamber where heat treatment is performed.

In order to achieve the above object, the present invention provides a semiconductor wafer transport jig for transporting a semiconductor wafer into and out of a chamber in which a heat treatment is performed, the transport jig comprising:
The semiconductor wafer has a tip portion and a base portion made of a resin member for supporting the back surface of the semiconductor wafer,
The present invention provides a semiconductor wafer transport jig, characterized in that the tip portion has at least two steps for supporting the semiconductor wafer at different contact positions of the semiconductor wafer transport jig.

With such a semiconductor wafer transport jig, the contact position between the semiconductor wafer and the semiconductor wafer transport jig can be changed when the semiconductor wafer is transported into and out of the chamber where heat treatment is performed, which makes it possible to suppress deterioration of the area where the semiconductor wafer comes into contact with the semiconductor wafer transport jig when the semiconductor wafer is transported in and out. As a result, less dust is generated due to contact and particle generation is reduced, making it possible to suppress deterioration in the quality of semiconductor wafers due to heat treatment, such as the occurrence of epitaxial defects caused by particles.

In this case, it is preferable that the resin member is a peak material.

In this way, if the resin material at the tip and base is PEEK material, particle generation can be further suppressed.

In this case, it is also preferable that the device further includes a pusher for chucking the semiconductor wafer.

With this type of semiconductor wafer transport jig, the semiconductor wafer can be chucked when being transported in and out, making it easier to transport the semiconductor wafer. Furthermore, with this type of semiconductor wafer transport jig, even when the semiconductor wafer is chucked, deterioration of the parts that come into contact with the semiconductor wafer transport jig can be suppressed, reducing particle generation and quality deterioration due to heat treatment.

The present invention also provides a semiconductor wafer transport method for transporting a semiconductor wafer into and out of a chamber for performing a heat treatment using the semiconductor wafer transport jig described above, comprising the steps of:
The semiconductor wafer transport method is characterized in that the semiconductor wafer is placed on a different one of the at least two steps, thereby changing the contact position when the semiconductor wafer is carried into and out of the chamber.

With this type of semiconductor wafer transport method, the contact position between the semiconductor wafer and the semiconductor wafer transport jig can be changed when the semiconductor wafer is transported into and out of the chamber where heat treatment is performed, thereby suppressing deterioration of the portion of the semiconductor wafer that comes into contact with the semiconductor wafer transport jig when the semiconductor wafer is transported in and out. As a result, less dust is generated due to contact, and particle generation is reduced, making it possible to suppress quality deterioration due to heat treatment, such as the occurrence of epitaxial defects caused by particles.

The semiconductor wafer transport jig of the present invention can change the contact position between the semiconductor wafer and the semiconductor wafer transport jig when the semiconductor wafer is carried into and removed from the chamber where heat treatment is applied. The semiconductor wafer transport method of the present invention also changes the contact position between the semiconductor wafer and the semiconductor wafer transport jig when the semiconductor wafer is carried into and removed from the chamber where heat treatment is applied. This makes it possible to suppress deterioration of the portion of the semiconductor wafer that contacts the semiconductor wafer transport jig when the semiconductor wafer is carried in and out. As a result, dust generation due to contact is reduced, and particle generation is reduced, making it possible to suppress quality deterioration due to heat treatment, such as the occurrence of epitaxial defects caused by particles.

1A to 1C are diagrams showing examples of the structure of the tip and base parts of a semiconductor wafer transport jig according to the present invention. 1 is a schematic diagram of an example of a semiconductor wafer transport jig of the present invention. FIG. 13 is a diagram showing stack maps of epitaxial defects in an example and a comparative example, and an average number of epitaxial defects occurring near a notch. FIG. 1 is a schematic diagram of a typical wafer transport jig used for loading and unloading a wafer into and from a chamber where a heat treatment is performed. 1 is a schematic diagram showing particle generation when a wafer is chucked by a general wafer transport jig; 1A and 1B are diagrams showing the structure of a tip portion and a base portion of a typical semiconductor wafer transport jig;

As mentioned above, in epitaxial growth reactors, the pre-reaction PW (polished wafer) and the post-reaction epitaxial wafer are generally transported using the same wafer transport jig. The back edge of the epitaxial wafer has many defects such as adhered foreign matter and scratches, and repeated contact with resin materials such as peak materials during the above transport causes deterioration of the resin materials. Deteriorated resin materials tend to generate dust, and particles originating from the resin materials are generated when the PW is chucked or contacted. The particles generated by scraping the resin material at the contact area adhere to the wafer surface, mainly near the notch. When heat treatment such as epitaxial growth is performed in this state, quality deterioration due to heat treatment such as epitaxial defects occurring near the notch has become a problem.

After extensive research into these problems, the inventors discovered that if at least two steps could be provided at the tip of the semiconductor wafer transport jig, and the contact position could be changed between when the semiconductor wafer is carried into the chamber where heat treatment is performed and when it is carried out of the chamber after heat treatment, deterioration of the portion of the semiconductor wafer that comes into contact with the semiconductor wafer transport jig when the semiconductor wafer is carried in and out would be suppressed, reducing dust generation due to contact and particle generation, thereby suppressing deterioration in quality due to heat treatment, such as the generation of epitaxial defects caused by particles, and thus completing the present invention.

That is, the present invention is a semiconductor wafer transport jig for transporting a semiconductor wafer into and out of a chamber in which a heat treatment is performed, comprising:
The semiconductor wafer has a tip portion and a base portion made of a resin member for supporting the back surface of the semiconductor wafer,
The semiconductor wafer transport jig is characterized in that the tip portion has at least two steps for supporting the semiconductor wafer at different contact positions of the semiconductor wafer transport jig.

Figure 6 shows the structure of the tip and base of a typical semiconductor wafer transport jig. As shown in Figure 6, a typical conventional semiconductor wafer transport jig has only one step at tip 1'. In this case, when the semiconductor wafer W' is transported into and out of the chamber (CH) where the heat treatment is performed, the semiconductor wafer W' comes into contact with the same contact position of tip 1' and base 2' (when the semiconductor wafer W' is inserted into and removed from the chamber (CH) in Figure 6), accelerating the deterioration of the semiconductor wafer transport jig.

On the other hand, with the semiconductor wafer transport jig of the present invention, the contact position between the semiconductor wafer and the semiconductor wafer transport jig can be changed when the semiconductor wafer is carried into and out of the chamber where heat treatment is performed, so deterioration of the portion of the semiconductor wafer that comes into contact with the semiconductor wafer transport jig when the semiconductor wafer is carried in and out can be suppressed. This reduces dust generation due to contact and reduces particle generation, making it possible to suppress quality deterioration due to heat treatment, such as the occurrence of epitaxial defects caused by particles.

The present invention will be described in detail below with reference to the drawings as an example of an embodiment, but the present invention is not limited to this.

The semiconductor wafer transport jig of the present invention has a tip and a base made of a resin material.

Figure 1 shows an example of the structure of the tip and base of the semiconductor wafer transport jig of the present invention. As shown in Figure 1, the semiconductor wafer transport jig of the present invention has a tip 1 made of a resin material with at least two steps. The semiconductor wafer is supported by the tip 1 and base 2, and the base 2 is also made of a resin material. The resin material is not particularly limited, but for example, a peak material can be used. Peak material is less likely to generate dust than other resin materials, so by using a peak material as the resin material, the generation of particles can be further suppressed.

As shown in FIG. 2, the semiconductor wafer transport jig 10 of the present invention may further have a pusher 3 for chucking the semiconductor wafer W in addition to the tip portion 1 and base portion 2. With such a semiconductor wafer transport jig, the semiconductor wafer can be chucked when transporting the semiconductor wafer, making it easier to transport the semiconductor wafer. Furthermore, with such a semiconductor wafer transport jig, even when the semiconductor wafer is chucked, deterioration of the portion that comes into contact with the semiconductor wafer transport jig can be suppressed, reducing particle generation and suppressing quality deterioration due to heat treatment. In this way, the structure other than the tip portion 1 can be the same as that of a general wafer transport jig shown in FIG. 4.

As shown in FIG. 1, if the tip 1 has at least two stages, an upper stage 11 and a lower stage 12, for example, the semiconductor wafer W can be placed on the upper stage 11 when being carried into the chamber and on the lower stage 12 when being carried out, thereby changing the contact position between the semiconductor wafer and the semiconductor wafer transport jig and suppressing deterioration of the semiconductor wafer transport jig. In addition, the number of stages provided at the tip should be at least two, and there is no particular limit to the number of stages.

Next, a method for transporting a semiconductor wafer when epitaxial growth is performed on the semiconductor wafer using such a semiconductor wafer transport jig will be described. Below, the semiconductor wafer transport method of the present invention will be described using the case of epitaxial growth as an example, but the semiconductor wafer transport method of the present invention is not limited to the case of epitaxial growth, and can be used more generally when transporting a semiconductor wafer in and out of a chamber where various heat treatments are performed.

As shown in Figure 1, when using a semiconductor wafer transport jig with a tip portion with two steps, the semiconductor wafer W is first loaded into the chamber where epitaxial growth will be performed by placing the semiconductor wafer W on, for example, the upper step 11 of the tip portion 1 made of a resin member of the semiconductor wafer transport jig so that the back surface of the semiconductor wafer is in contact with the upper step 11 and loading the semiconductor wafer into the chamber (when inserting CH in Figure 1), and then setting the semiconductor wafer on the susceptor. After that, epitaxial growth of a silicon single crystal film is performed on the front surface of the semiconductor wafer that has been loaded into the chamber.

This epitaxial growth is carried out by heating the temperature of the semiconductor wafer to a predetermined growth temperature (e.g., 1000°C to 1200°C) using a heater, and then supplying epitaxial growth gas containing a silicon source gas (e.g., trichlorosilane) and a carrier gas (e.g., hydrogen) onto the surface of the semiconductor wafer while rotating the susceptor. When epitaxial growth is complete, the heater controls the temperature inside the reaction chamber to a predetermined unloading temperature (e.g., above room temperature and below 800°C).

After epitaxial growth is complete, the epitaxial wafer W is placed on the lower tier 12 of the tip 1 of the semiconductor wafer transport jig, which is made of a resin member, and removed from the chamber (removal of CH in Figure 1). When transporting the semiconductor wafer, it is not necessary to place the semiconductor wafer on the upper tier when loading and the lower tier when unloading; it may be on the lower tier when loading and the upper tier when unloading. Also, if there are more than two tiers, a combination of two different tiers can be used for different loading and unloading. The point is to place the wafer on different tiers when loading and unloading. By placing the wafer on different tiers when loading and unloading in this way, the contact position of the semiconductor wafer at the base will also be different when loading and unloading.

With this type of semiconductor wafer transport method, the contact position is changed between when the semiconductor wafer is transported into the chamber and when it is transported out of the chamber after undergoing heat treatment such as epitaxial growth, so deterioration of the area where the semiconductor wafer comes into contact with the semiconductor wafer transport jig when the semiconductor wafer is transported in and out is suppressed. As a result, less dust is generated due to contact, and particle generation is reduced, making it possible to suppress quality deterioration due to heat treatment, such as the occurrence of epitaxial defects caused by particles.

The following examples and comparative examples are presented to more specifically explain the present invention, but the present invention is not limited to these.

(Example)
As shown in FIG. 1, the peak material at the tip of the semiconductor wafer transport jig has a two-stage structure, and the semiconductor wafer transport jig shown in FIG. 2 was used to transport the PW to and from the chamber where epitaxial growth is performed. When the PW is placed on the semiconductor wafer transport jig 10 and introduced into the chamber, the PW is placed on the upper stage 11 of the peak material at the tip 1 and then transported into the chamber, and epitaxial growth is performed. When the epitaxial wafer is then removed from the chamber, it is placed on the lower stage 12 of the peak material at the tip 1 so that the contact position of the peak material at the base 2 is different at the time of transporting in and the time of removing. The epitaxial defects of the removed epitaxial wafers (N=914 sheets) were measured, and it was confirmed whether the epitaxial defects of the notch portion near the contact position of the base of the wafer transport jig were improved compared to the following comparative example. The peak material at the tip had a step of 0.6 mm, and the wafer overlap of the upper stage 11 was 4 mm. When the substrate was carried in or out, it was chucked by a pusher 3 and transported.

Comparative Example
As shown in Fig. 4, epitaxial growth was performed in the same manner as in the example, except that a commonly used wafer transport jig with one step was used so that the contact position was the same when the wafer was transported into and out of the chamber, and the epitaxial defects of the removed epitaxial wafers (N = 899 wafers) were measured. The step of the peak material at the tip was 0.8 mm.

Figure 3 shows stack maps of epitaxial defects for the Example (N = 914 wafers) and Comparative Example (N = 899 wafers), and the average number of epitaxial defects that occurred near the notch. Note that the notch is not shown in Figure 3, but "near the notch" refers to the notch area enclosed by a square in Figure 3. As shown in Figure 3, the average number of epitaxial defects was 0.05/wf and 0.12/wf in the Example and Comparative Example, respectively, and the Example showed an improvement in the number of epitaxial defects that occurred in the notch area compared to the Comparative Example.

The above results show that the semiconductor wafer transport jig and semiconductor wafer transport method of the present invention can suppress deterioration of the portion of the semiconductor wafer that contacts the semiconductor wafer transport jig when the semiconductor wafer is transported in and out, and reduce particle generation, thereby suppressing quality deterioration due to heat treatment, such as the generation of epitaxial defects caused by particles.

The present invention is not limited to the above-described embodiment. The above-described embodiment is merely an example, and anything that has substantially the same configuration as the technical idea described in the claims of the present invention and exhibits similar effects is included within the technical scope of the present invention.

10, 10'...Transport system,
1, 1'...tip portion, 11...upper section, 12...lower section,
2, 2'...base portion, 3, 3'...pusher,
W, W': wafer, P: particle.

Claims (3)

A semiconductor wafer transport jig for transporting a semiconductor wafer into and out of a chamber in which a heat treatment is performed,
The semiconductor wafer has a tip portion and a base portion made of a resin member for supporting the back surface of the semiconductor wafer,
At least two steps are provided on the tip portion for supporting the semiconductor wafer at different contact positions of the semiconductor wafer transport jig , and each of the at least two steps has an upper surface that contacts the semiconductor wafer and has an inclined surface that becomes lower toward the base portion,
the base portion has an upper surface that contacts the semiconductor wafer and has an inclined surface that becomes lower toward the tip portion,
a semiconductor wafer transport jig further comprising, in addition to said tip portion and said base portion, a pusher for chucking said semiconductor wafer. The semiconductor wafer transport jig according to claim 1, characterized in that the resin member is a PEEK material. A semiconductor wafer transport method for transporting a semiconductor wafer into and out of a chamber for performing a heat treatment, using the semiconductor wafer transport jig according to claim 1 or 2, comprising:
A semiconductor wafer transport method, characterized in that the semiconductor wafer is placed on a different one of the at least two steps, thereby changing the contact position when the semiconductor wafer is carried into and out of the chamber.

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