JP7526706B2 - Wiring board and method for manufacturing the same - Google Patents

Description

The present invention relates to a wiring board and a method for manufacturing a wiring board.

When mounting a semiconductor element such as an IC chip or an LED element on a mounting board, a method is used in which the semiconductor element is mounted on a wiring board and then the bumps or other connection terminals of the wiring board are mounted on the mounting board. For example, in the invention described in Patent Document 1, an electronic component, which is a semiconductor element, is mounted on a wiring board via bumps. On the side of the wiring board opposite the surface on which the electronic component is mounted, i.e., the back side, a conductive layer is provided so as to protrude from the insulating layer. The conductive layer functions as an external connection terminal and is electrically connected to an external circuit (e.g., the mounting board) via a solder ball.

In addition, in the invention described in Patent Document 2, a multilayer wiring board on which an IC chip is mounted is provided with a solder resist layer with an opening formed on the back side. A connection terminal mainly composed of a copper layer is exposed in the opening, and the exposed surface of the connection terminal is covered with a plating layer. The plating layer is, for example, a nickel-gold plating layer formed by sequentially applying electroless nickel plating and electroless gold plating.

JP 2011-114121 A JP 2013-118301 A

The wiring board described in Patent Document 1 has a structure in which the conductive layer serving as the connection terminal to be soldered to the mounting board protrudes from the rear surface of the wiring board, and therefore when mounted on the mounting board, a gap called a standoff occurs between the wiring board and the mounting board. When a standoff occurs, the heat dissipation performance from the wiring board to the mounting board decreases, and there is also a risk of the mounting being tilted.

On the other hand, in the case of the wiring board described in Patent Document 2, the connection terminals for connecting to the mounting board are recessed from the surface of the multilayer wiring board, so solder balls are required when mounting to the mounting board. This creates a height for the solder balls, which may result in tilted mounting. The size of the solder balls is restricted by the size of the recess, and if the size of the solder balls becomes large, restrictions are also imposed on the wiring on the mounting board.

A wiring board according to a first aspect of the present invention comprises an element connection terminal provided on the main surface side of the substrate to which a semiconductor element is connected, an external connection terminal for external connection provided on the back surface side of the substrate, and a substrate insulating layer provided with wiring connecting the element connection terminal and the external connection terminal, wherein the external connection terminal has a first conductive layer having a connection surface exposed on the back surface side of the substrate insulating layer, and a second conductive layer laminated on the first conductive layer, provided within the substrate insulating layer and connected to the wiring, and the first conductive layer is formed of an exterior plating metal, and the connection surface is flush with the back surface of the substrate insulating layer.
A method for manufacturing a wiring board according to a second aspect of the present invention is a method for manufacturing a wiring board having an external connection terminal including a first conductive layer formed of an exterior plating metal and a second conductive layer provided in the substrate insulating layer and laminated on the first conductive layer, the connection surface being flush with the substrate insulating layer, the method including forming the first conductive layer on a support substrate, laminating the second conductive layer on the first conductive layer, sealing the first conductive layer and the second conductive layer laminated on the support substrate with an insulating member to form the substrate insulating layer, and removing the support substrate from the first conductive layer and the substrate insulating layer to expose surfaces of the first conductive layer and the substrate insulating layer that contact the support substrate in a flush state, and forming the connection surface and the substrate insulating layer.

The present invention makes it possible to reduce standoff when mounted on a mounting board.

FIG. 1 is a diagram showing a schematic cross-sectional structure of a semiconductor device using a wiring board according to the present embodiment. FIG. 2 is a diagram illustrating the standoff. 3A to 3C are diagrams for explaining an example of a method for manufacturing a wiring board and a semiconductor device. FIG. 4 is a diagram showing a process subsequent to that shown in FIG. FIG. 5 is a diagram showing a process subsequent to that shown in FIG. FIG. 6 is a diagram showing a process subsequent to that shown in FIG. FIG. 7 is a diagram showing a process subsequent to that shown in FIG. FIG. 8 is a diagram illustrating the anchor structure. FIG. 9 is a diagram illustrating a first modified example of the manufacturing method. FIG. 10 is a diagram showing a process subsequent to that shown in FIG. FIG. 11 is a diagram illustrating a second modified example of the manufacturing method. FIG. 12 is a diagram showing a process subsequent to that shown in FIG. FIG. 13 is a diagram illustrating a third modified example of the manufacturing method. FIG. 14 is a diagram illustrating a fourth modified example of the manufacturing method.

Each embodiment of the present invention will be described below with reference to the drawings. In the drawings shown below, the shape, size, such as length, width, thickness, and the ratio of length, width, and thickness of each component are shown in shapes, sizes, and ratios that are different from the actual shapes, sizes, and ratios as appropriate to clarify the configuration of the invention. Therefore, the shape, size, and length, width, and thickness ratios of each component shown in the drawings should not be considered in comparison with the same elements of the same component or the same elements of other components.

Figure 1 is a diagram showing a schematic cross-sectional structure of a semiconductor device 1. The semiconductor device 1 includes semiconductor elements 10a, 10b and a wiring board 20 on which the semiconductor elements 10a, 10b are mounted. The semiconductor elements 10a, 10b are sealed with an electrically insulating sealing resin 30. The wiring board 20 is a board having conductor wiring provided in an interlayer insulating layer 200, and has a board main surface 21 that is the mounting surface for the semiconductor elements 10a, 10b, and a board back surface 22 opposite the board main surface 21.

In the example shown in FIG. 1, the conductor wiring includes an element connection terminal 201 provided on the main surface of the substrate, an external connection terminal 202 provided on the rear surface of the substrate, and an interlayer wiring 203 connecting the element connection terminal 201 and the external connection terminal 202. The semiconductor elements 10a and 10b are mounted on the wiring substrate 20 by soldering the terminals 100 of the semiconductor elements 10a and 10b to the corresponding element connection terminals 201.

The external connection terminal 202 provided on the back side of the substrate is a terminal for mounting the semiconductor device 1 on a mounting substrate (not shown). The external connection terminal 202 has a two-layer structure having a second conductive layer 202a and a first conductive layer 202b exposed on the back side of the substrate, and the first conductive layer 202b is solder-bonded to the wiring of the mounting substrate. The back surface 200S of the interlayer insulating layer 200 and the exposed solder connection surface 202S of the first conductive layer 202b are on the same plane, and the back surface 22 of the substrate is a flat surface without any irregularities.

In this embodiment, the external connection terminal 202 that is soldered to the mounting board has a two-layer structure of a second conductive layer 202a of Cu and a first conductive layer 202b on which a solder connection surface 202S is formed, and the first conductive layer 202b is formed of an exterior plating metal suitable for solder bonding. The exterior plating metal has excellent solder wettability and can perform appropriate solder bonding with the mounting board. Examples of exterior plating metals that can be used include Ag, Ni, Sn, Pd, Au, and Ti. The first conductive layer 202b may be a conductive layer made of any of these metals, or multiple types of metals may be formed in layers. For example, three types of metals, Ag, Ni, and Pd, are selected, and the first conductive layer 202b is configured from the mounting surface side as an Au layer-Pd layer-Ni layer.

In addition, in the wiring board described in Patent Document 1, for example, as shown in FIG. 2(a), the solder connection surface 202S of the external connection terminal 202 is provided so as to protrude from the back surface of the interlayer insulating layer 200. Therefore, when the semiconductor device 1 is mounted on the mounting substrate 50 (see FIG. 2(b)), the standoff h, which is the gap height between the back surface of the semiconductor element 1 and the mounting substrate 50, becomes larger by the amount of the protruding external connection terminal 202. When the standoff h is large, a semiconductor device 1 having a large number of external connection terminals 202 is likely to tilt when mounted on the mounting substrate 50. For example, when the semiconductor element 10 is an LED element, if the semiconductor device 1 tilts when mounted on the mounting substrate 50, the optical axis of the LED element will tilt.

In the case of the wiring board described in Patent Document 2, for example, as shown in FIG. 2(c), the connection terminals 45 are recessed from the rear surface of the interlayer insulating layer 200, so solder balls 52 are required when mounting on the mounting substrate 50. The size of the solder balls 52 must be increased according to the size of the recess, which may result in a standoff that may cause mounting tilt. Furthermore, if the size of the solder balls 52 is increased, restrictions are placed on the arrangement of the wiring 51a, 51b on the mounting substrate 50 side.

On the other hand, in this embodiment, the back surface 200S of the interlayer insulating layer 200 and the exposed solder connection surface 202S of the first conductive layer 202b are on the same plane, and the back surface 22 of the substrate is a flat surface without any irregularities, so the standoff can be made almost zero. Therefore, it is possible to prevent the occurrence of tilt of the semiconductor device 1 when mounted on the substrate as described above. In addition, since the standoff is almost zero, it is possible to improve the heat dissipation performance from the wiring substrate 20 to the mounting substrate 50. In addition, by reducing the standoff, it is possible to prevent the inconvenience of tilting the optical axis of the LED element as described above.

Next, a method for manufacturing the semiconductor device 1 shown in FIG. 1 will be described. FIGS. 3 to 7 are cross-sectional views showing an example of the manufacturing method. Note that although FIGS. 3 to 7 show the manufacturing process for one semiconductor device 1, the support substrate 40 for forming the semiconductor device 1 is a substrate larger than one semiconductor device 1, and many semiconductor devices 1 are formed on the support substrate 40. In addition, the metal used for the first conductive layer 202b will be described below using Ni as an example.

3(a), a Ni plating layer that will become the first conductive layer 202b described above is formed on the upper surface of the support substrate 40 by electrolytic plating. Hereinafter, the Ni plating layer will be denoted by the same reference numeral 202b as the first conductive layer 202b. The thickness of the Ni plating layer 202b is, for example, about 1 to 3 μm. The semiconductor device 1 is formed on this support substrate 40, and the support substrate 40 supports the back side of the semiconductor device 1. Finally, the support substrate 40 is removed from the semiconductor device 1. In this embodiment, a Cu plate with a thickness of about 100 μm is used for the support substrate 40, but the material and thickness of the support substrate 40 are appropriately set according to the contents of the removal process, as described later.

In the process shown in FIG. 3(b), a photoresist 211 is formed on the entire surface of the Ni plating layer 202b. The photoresist 211 is formed by laminating a dry film type photosensitive resist film with a laminator. The thickness of the photoresist 211 is set to be the same as the thickness of the second conductive layer 202a. For example, it is set to about 10 μm.

In the step shown in FIG. 3(c), the photoresist 211 is exposed using a photomask 212. The photomask 212 has non-transparent portions 212a in a pattern shape corresponding to the shape of the external connection terminals 202, and transparent portions 212b around the non-transparent portions 212a. By exposure using the photomask 212, the photoresist 211 is exposed to light at portions 211b corresponding to the transparent portions 212b.

In the step shown in FIG. 3(d), the photomask 212 is removed, and then the photoresist 211 is developed to remove the non-exposed portions 211a of the photoresist 211. As a result, openings 211c are formed in the photoresist 211 in a pattern shape corresponding to the shape of the external connection terminals 202.

In the process shown in FIG. 4(a), the openings 211c of the photoresist 211 are plated with Cu by electrolytic plating to form the second conductive layer 202a. Then, in the process shown in FIG. 4(b), the exposed portions 211b of the photoresist 211 are removed.

In the process shown in FIG. 4(c), the Ni plating layer 202b is etched with an etching solution that reacts with Ni. The etching solution used is an etching solution that has excellent etching selectivity between Ni and Cu, such as an etching solution containing potassium hydrogen sulfate. In this etching process, the second conductive layer 202a of Cu formed on the Ni plating layer 202b functions as a mask. Therefore, only the part of the Ni plating layer that does not overlap with the second conductive layer 202a is etched, and the first conductive layer 202b made of the Ni plating layer is formed.

In the process shown in FIG. 4(d), the insulating film is laminated with a laminator to form the interlayer insulating layer 200. As a result, the second conductive layer 202a and the first conductive layer 202b are sealed with the interlayer insulating layer 200.

In the process shown in FIG. 5(a), a via hole 200a is formed in the interlayer insulating layer 200 on each second conductive layer 202a using a laser device. In the process shown in FIG. 5(b), a Cu film 212 with a thickness of about 1 μm or less is formed by electroless plating on the entire exposed upper surface of the substrate shown in FIG. 5(a), i.e., on the upper surface of the interlayer insulating layer 200, the side surface of the via hole 200a, and the upper surface of the second conductive layer 202a exposed at the bottom of the via hole 200a.

In the process shown in FIG. 5(c), a photoresist 221 having an opening pattern shape similar to the shape of the element connection terminal is formed in the same process as the photoresist 211 shown in FIG. 3(d). The thickness of the photoresist 221 is preferably formed thicker than the element connection terminal to an extent that allows for thickness tolerance. For example, when the element connection terminal is set to 10 μm, the thickness is set to about 19 μm. The photoresist 221 is laminated and formed on the entire upper surface side of the substrate shown in FIG. 5(b), and the photoresist 221 is exposed using a photomask having a non-transmitting portion having the same shape as the element connection terminal 201 (see FIG. 1), and is developed to remove the non-exposed portion having the same shape as the element connection terminal 201. As a result, the photoresist 221 has a photoexposed portion 221b and an opening 221c having the same shape as the element connection terminal 201.

In the process shown in FIG. 5(d), electrolytic plating is performed using the Cu film 212 as the base metal for the current path to form a Cu layer 213 in the opening 221c. As a result, the opening 221c and the via hole 200a are filled with Cu plating.

In the process shown in FIG. 6(a), the photoresist 221 is removed. As a result, the Cu film 212 and the Cu layer 213 are exposed. In the process shown in FIG. 6(b), the exposed Cu film 212 and the Cu layer 213 are etched to remove the Cu film 212 that is not covered by the Cu layer 213. As a result, an element connection terminal 201 made of Cu formed on the interlayer insulating layer 200 and an interlayer wiring 203 made of Cu in the via hole 200a are formed. In the process shown in FIG. 6(c), the terminals of the semiconductor elements 10a and 10b are connected to the element connection terminal 201.

In the process shown in FIG. 7(a), the semiconductor elements 10a and 10b and the element connection terminals 201 are sealed with sealing resin 30. In the process shown in FIG. 7(b), the support substrate 40 is etched away with an etching solution that reacts with Cu. As the etching solution, an etching solution that has excellent etching selectivity between Ni and Cu, such as an etching solution containing potassium hydrogen sulfate, is used. Alternatively, the support substrate 40 may be removed by mechanical grinding. Alternatively, when a glass substrate is used as the support substrate 40, the support substrate 40 may be removed by peeling it off.

Figure 7 (c) is a diagram showing the process of mounting the semiconductor device 1 on the mounting substrate 50. The semiconductor element 10a of the semiconductor device 1 is connected to the wiring 51a of the mounting substrate 50, and the semiconductor element 10b is connected to the wiring 51b of the mounting substrate 50. Solder balls 52 are provided on the wiring 51a and 51b, and the wiring 51a and 51b are solder-connected to the second metal layer 202b of the external connection terminal 202.

In FIG. 4(c), when the Ni plating layer 202b is etched using the Cu second conductive layer 202a as a mask, as shown in FIG. 8(a), the side 2020 of the Ni plating layer 202b between the second conductive layer 202a and the support substrate 40 is recessed inward (i.e., in the region below the second conductive layer 202a rather than on the peripheral side surface of the second conductive layer 202a) to form a concave shape (the shape of the region indicated by the symbol A in FIG. 8(a)). Therefore, when the interlayer insulating layer 200 is formed to cover the second conductive layer 202a and the first conductive layer 202b in the next step, the interlayer insulating layer 200 will fill up to the concave region of the side surface 2020 as shown in FIG. 8(b). In this manner, by forming a structure in which the interlayer insulating layer 200 fills the recessed area of the side surface 2020, the interlayer insulating layer 200 functions as an anchor that attempts to hold the external connection terminal 202 within the interlayer insulating layer 200, and even if the external connection terminal 202 is a thin film formed by plating, it is prevented from falling off the interlayer insulating layer 200.

(Variation 1)
9 and 10 are diagrams for explaining a first modified example of the manufacturing method. In the first modified example, a Ni plating layer 202b is formed on the upper surface of the support substrate 40 in the same manner as in the process of FIG. 3(a) described above, and then the process shown in FIG. 9(a) is performed. In the process shown in FIG. 9(a), a Cu plating layer for forming the first conductive layer 202b described above is formed on the entire upper surface of the Ni plating layer 202b by electrolytic plating. Hereinafter, the Cu plating layer will be represented by the same reference numeral 202a as the second conductive layer 202a. The thickness of the Cu plating layer 202a is, for example, about 10 μm.

In the process shown in FIG. 9(b), a photoresist 231 is formed on the entire upper surface of the Cu plating layer 202a. The photoresist 231 is formed by laminating a dry film type photosensitive resist film with a laminator.

In the step shown in FIG. 9(c), the photoresist 231 is exposed using a photomask 232. The photomask 232 has transparent portions 232b in a pattern shape corresponding to the shape of the external connection terminals 202, and non-transparent portions 232a around the transparent portions 232b. By exposure using the photomask 232, the photoresist 231 is exposed to light at portions 231b corresponding to the transparent portions 232b.

In the process shown in FIG. 10(a), the photomask 232 in FIG. 9(c) is removed, and then the photoresist 231 is developed to remove the non-exposed portions 231a of the photoresist 231. As a result, as shown in FIG. 10(a), a resist pattern 231b corresponding to the shape of the external connection terminal 202 is formed.

In the process shown in FIG. 10(b), the resist pattern 231b is used as a mask to perform etching processing on the Cu plating layer 202a and the Ni plating layer 202b in that order. As a result, the Cu plating layer 202a and the Ni plating layer 202b in the portions where the resist pattern 231b is not placed are removed, leaving the Cu plating layer as the second conductive layer 202a of the external connection terminal 202 and the Ni plating layer as the first conductive layer 202b of the external connection terminal 202.

In the step shown in FIG. 10(c), the resist pattern 231b is removed. As a result, similar to the configuration shown in FIG. 4(c), external connection terminals 202 are formed on the support substrate 40. Thereafter, the same processes as those shown in FIG. 4(d) to FIG. 7(b) are performed, and the semiconductor device 1 shown in FIG. 7(b) is completed.

(Variation 2)
11 and 12 are diagrams for explaining a second modified example of the manufacturing method. In the process shown in FIG. 11(a), a photoresist 241 is formed on the entire surface of the support substrate 40. The photoresist 241 is formed by laminating a dry film type photosensitive resist film with a laminator. The thickness of the photoresist 241 is set to a thickness equivalent to the thickness of the external connection terminal 202, that is, the sum of the thickness of the second conductive layer 202a and the thickness of the first conductive layer 202b. The support substrate 40 is a Cu plate having a thickness of about 100 μm, as in the case of the above-mentioned embodiment (FIG. 3(a)).

In the process shown in FIG. 11(b), the photoresist 241 is exposed using a photomask 212 similar to that in the process shown in FIG. 3(c). The photomask 212 has non-transparent portions 212a in a pattern shape corresponding to the shape of the external connection terminals 202, and transparent portions 212b around the non-transparent portions 212a. By exposure using the photomask 212, the photoresist 241 is exposed to light at portions 241b corresponding to the transparent portions 212b.

In the step shown in FIG. 11(c), the photomask 212 is removed, and then the photoresist 241 is developed to remove the non-exposed portions 241a of the photoresist 241. As a result, openings 241c are formed in the photoresist 241 in a pattern shape corresponding to the shape of the external connection terminals 202.

In the process shown in FIG. 12(a), a Ni plating layer is formed in the opening 241c by electrolytic plating to form the first conductive layer 202b of the external connection terminal 202. The thickness of the Ni plating layer 202b is, for example, about 1 to 3 μm. In the process shown in FIG. 12(b), a Cu plating layer is formed in the opening 241c by electrolytic plating to form the second conductive layer 202a of the external connection terminal 202. The thickness of the Cu plating layer 202a is, for example, about 10 μm.

In the step shown in FIG. 12(c), the photoresist 241 is removed. As a result, similar to the configuration shown in FIG. 4(c), an external connection terminal 202 is formed on the support substrate 40, in which a first conductive layer 202b of Ni is laminated with a second conductive layer 202a of Cu. Thereafter, the same processes as those shown in FIG. 4(d) to FIG. 7(b) described above are performed, and the semiconductor device 1 shown in FIG. 7(b) is completed.

(Variation 3)
13 is a diagram for explaining a modified example 3 of the manufacturing method. Conventionally, as a method for forming a wiring material for an electronic device, a method for forming a conductive pattern by a printing method using a metal ink or a metal paste in which metal particles with a particle size on the order of nanometers are dispersed in a dispersion medium such as an organic solvent is known. In the modified example 3, the second conductive layer 202a and the first conductive layer 202b of the external connection terminal 202 are formed by a printing method.

In the process shown in FIG. 13(a), a terminal pattern 251 made of a metal paste containing Ni metal particles is printed on the support substrate 40 by screen printing. The thickness of the terminal pattern 251 is set so that the thickness after firing is approximately 1 to 3 μm. In the process shown in FIG. 13(b), the terminal pattern 251 is fired to form the first conductive layer 202b.

In the process shown in FIG. 13(c), a terminal pattern 252 of a metal paste containing Cu metal particles is printed on the first conductive layer 202b by screen printing. The thickness of the terminal pattern 25 is set so that the thickness after firing is about 10 μm. In the process shown in FIG. 13(d), the terminal pattern 252 is fired to form the second conductive layer 202a. As a result, an external connection terminal 202 consisting of the second conductive layer 202a and the first conductive layer 202b is formed on the support substrate 40. Thereafter, the same processes as those shown in FIG. 4(d) to FIG. 7(b) are performed, and the semiconductor device 1 shown in FIG. 7(b) is completed.

(Variation 4)
14 is a diagram illustrating a fourth modified example of the manufacturing method. In the third modified example described above, the second conductive layer 202a and the first conductive layer 202b of the external connection terminal 202 are formed by printing a metal paste and then firing the printed metal paste. In the fourth modified example, the element connection terminal 201 and the interlayer wiring 203 in FIG. 1 are formed by printing. Note that any of the above-described embodiment and the first to third modified examples may be applied to the process of forming the second conductive layer 202a and the first conductive layer 202b of the external connection terminal 202 on the support substrate 40.

In the process shown in FIG. 14(a), the support substrate 40 on which the external connection terminals 202 are formed is subjected to the same process as the processes shown in FIG. 4(d) and FIG. 5(a). That is, the external connection terminals 202 are sealed with an interlayer insulating layer 200, and via holes 200a are formed in the interlayer insulating layer 200 on each second conductive layer 202a using a laser device.

In the process shown in FIG. 14(b), a metal paste element connection terminal pattern 253 is printed by screen printing so that the via hole 200a is filled with the metal paste containing Cu metal particles. The thickness of the element connection terminal pattern 253 (height from the upper surface of the interlayer insulating layer 200) is set so that the thickness after firing is the thickness of the element connection terminal 201.

In the process shown in FIG. 14(c), the element connection terminal pattern 253 of metal paste is fired to form the element connection terminal 201 and the interlayer wiring 203. After that, the same processes as those shown in FIG. 6(c) to FIG. 7(b) described above are performed, and the semiconductor device 1 shown in FIG. 7(b) is completed.

According to the above-described embodiment and modifications, the following effects are achieved.
(1) As shown in FIG. 1 , the wiring board 20 includes an element connection terminal 201 provided on the main surface 21 of the board to which a semiconductor element is connected, an external connection terminal 202 for external connection provided on the rear surface 22 of the board, and an interlayer insulating layer 200 as a board insulating layer provided with wiring 203 connecting the element connection terminal 201 and the external connection terminal 202, wherein the external connection terminal 202 includes a first conductive layer 202b having a solder connection surface 202S exposed on the rear surface side of the board insulating layer 200, and a second conductive layer 202a laminated on the first conductive layer 202b, provided within the board insulating layer 200, and connected to the wiring 203, wherein the first conductive layer 202b is formed of an exterior plating metal, and the solder connection surface 202S is flush with the rear surface 200S of the interlayer insulating layer 200.

In the configuration shown in FIG. 1, the back surface 200S of the interlayer insulating layer 200 and the exposed solder connection surface 202S of the first conductive layer 202b are on the same plane, and the back surface 22 of the substrate is a flat surface without any irregularities, so that the standoff can be reduced to almost zero. As a result, tilting of the semiconductor device 1 during substrate mounting can be prevented, and the heat dissipation performance from the wiring substrate 20 to the mounting substrate 50 can be improved. Note that the metal used for the second conductive layer 202a should preferably have a volume resistivity of 3.0 μΩ·cm or less, and metals such as Cu and Ag are used.

In addition, the first conductive layer 202b on which the solder connection surface 202S of the external connection terminal 202 is formed is made of an exterior plating metal, so it has excellent wettability and can reduce the occurrence of voids in the solder joint area.

(2) The metals for exterior plating include Ag, Ni, Sn, Pd, Au, and Ti as metal species, and the first conductive layer 202b is a conductive layer made of any of the plurality of metal species, or a conductive layer formed by laminating two or more of the plurality of metal species in layers. For example, three types of Au, Ni, and Pd may be selected, and the first conductive layer 202b may be configured as an Au layer-Pd layer-Ni layer from the mounting surface side. For example, when forming the layer that will become the first conductive layer 202b in FIG. 3(a), an Au layer, a Pd layer, and a Ni layer are formed in this order from the mounting surface side by electroless multilayer plating. Furthermore, when Ti is used for the first conductive layer 202b, the diffusion rate at the solder bonding temperature is smaller than that of Cu, so that solder erosion and the occurrence of Kirkendall voids can be suppressed.

(3) As shown in FIG. 8(b), the side surface 2020 of the first conductive layer 202b is recessed relative to the side surface of the second conductive layer 202a laminated on the first conductive layer 202b, and the recessed area of the concave shape is filled with a part of the interlayer insulating layer 200. Therefore, the interlayer insulating layer 200 filled in the recessed area of the side surface 2020 functions as an anchor that locks the external connection terminal 202 in the interlayer insulating layer 200, and prevents the external connection terminal 202 from falling off the interlayer insulating layer 200.

(4) In the method of manufacturing the wiring board shown in Figures 3 to 7, as shown in Figure 4 (c), the first conductive layer 202b is formed on the support substrate 40, the second conductive layer 202a is laminated on the first conductive layer 202b, and the first conductive layer 202b and the second conductive layer 202a laminated on the support substrate 40 are sealed with an insulating member to form the interlayer insulating layer 200. Then, as shown in Figure 7 (c), by removing the support substrate 40 from the first conductive layer 202b and the interlayer insulating layer 200, the surfaces of the first conductive layer 202b and the interlayer insulating layer 200 that contact the support substrate 40 (i.e., the solder connection surface 202S and the back surface 200S) are exposed in a flush state. As a result, the standoff when the semiconductor device 1 is mounted on the mounting substrate 50 can be reduced to almost zero.

(5) In the method of manufacturing a wiring board shown in Figures 3 to 7, a film 202b of a metal for exterior plating is formed on the support substrate 40 as shown in Figure 3(a), a second conductive layer 202a is formed on the film 202b as shown in Figure 4(b), and the film 202b is etched using the second conductive layer 202a as a mask to form a first conductive layer 202b as shown in Figure 4(c).

(6) In the method of manufacturing a wiring board shown in Figures 9 and 10, a film 202b of a metal for exterior plating is formed on a support substrate 40 as shown in Figure 9(a), and then a Cu film 202a is formed as a conductive layer on the film 202b. As shown in Figure 10(a), a mask 231b having a pattern shape identical to that of the external connection terminal 202 is formed on the Cu film 202a. As shown in Figure 10(b), the film 202b and the Cu film 202a are etched using the mask 231b to form a first conductive layer 202b and a second conductive layer 202a in a laminated state on the support substrate 40.

(7) In the method of manufacturing a wiring board shown in Figures 11 and 12, a resist layer 241 having an opening 241c of the same shape as the external connection terminal 202 is formed on a support substrate 40 as shown in Figure 11(c), a first conductive layer 202b is formed on the support substrate 40 in the opening 241c as shown in Figure 12(a), and a second conductive layer 202a is formed on the first conductive layer 202b as shown in Figure 12(b).

(8) In the method of manufacturing the wiring board shown in FIG. 13, as shown in FIG. 13(a), a metal paste or metal ink containing Ni metal particles is printed on the support substrate 40 by a printing method to form a terminal pattern 251, which is a first printed layer having the pattern shape of the external connection terminal 202, as shown in FIG. 13(b), the terminal pattern 251 is fired to form the first conductive layer 202b, as shown in FIG. 13(c), a metal paste or metal ink containing Cu metal particles is printed on the first conductive layer 202b by a printing method to form a terminal pattern 252, which is a second printed layer having the pattern shape of the external connection terminal 202, as shown in FIG. 13(d), and the terminal pattern 252 is fired to form the second conductive layer 202a.

(9) Furthermore, in a preferred method for manufacturing a wiring board, the support substrate 40 is a copper metal plate, and the support substrate 40 is removed by etching.

Although various embodiments and modifications have been described above, the present invention is not limited to these. Other embodiments that are conceivable within the scope of the technical concept of the present invention are also included within the scope of the present invention.

1...semiconductor device, 10a, 10b...semiconductor element, 20...wiring board, 21...substrate main surface, 22...substrate back surface, 30...sealing resin, 40...supporting board, 50...mounting board, 200...interlayer insulating layer, 201...element connection terminal, 202...external connection terminal, 202a...second conductive layer, 202b...first conductive layer, 202S...solder connection surface, 203...interlayer wiring, 211, 221, 231, 241...photoresist, 2020...side surface

Claims (5)

an element connection terminal provided on the main surface side of the substrate and to which a semiconductor element is connected;
An external connection terminal for external connection provided on the back side of the board;
a substrate insulating layer provided with wiring connecting the element connection terminals and the external connection terminals;
the external connection terminal has a connection surface exposed on the back surface side of the substrate insulating layer, and includes a first conductive layer made of a single layer , and a second conductive layer laminated on the first conductive layer, provided within the substrate insulating layer, and connected to the wiring;
the first conductive layer is formed of an exterior plating metal, and the connection surface is flush with the rear surface of the substrate insulating layer;
A wiring board, wherein a layer side of the first conductive layer has a concave shape recessed relative to a layer side of the second conductive layer stacked on the first conductive layer, and a portion of the substrate insulating layer is filled in the concave recessed area. 2. The wiring board according to claim 1,
The exterior plating metal contains Ag, Ni, Sn, Pd, Au, and Ti as metal species,
The first conductive layer is a conductive layer made of any one of the plurality of metal types. A method for manufacturing a wiring board, comprising: an external connection terminal having a connection surface exposed on a back surface side of a substrate insulating layer, the external connection terminal including a first conductive layer formed of an exterior plating metal; and a second conductive layer provided in the substrate insulating layer and laminated on the first conductive layer, the connection surface being flush with the back surface of the substrate insulating layer, the method comprising the steps of:
forming the first conductive layer on a supporting substrate;
forming the second conductive layer on the first conductive layer;
forming the substrate insulating layer by sealing the first conductive layer and the second conductive layer formed on the support substrate with an insulating member;
removing the support substrate from the first conductive layer and the substrate insulating layer to expose surfaces of the first conductive layer and the substrate insulating layer that contact the support substrate in a flush state, and forming the connection surface and a back surface of the substrate insulating layer;
forming a film of the metal for exterior plating on the supporting substrate;
forming the second conductive layer on the film of the exterior plating metal;
A method for manufacturing a wiring board, comprising: etching the film of the metal for exterior plating using the second conductive layer as a mask, thereby forming the first conductive layer consisting of a single layer having a layer side that is concavely shaped relative to the layer side of the second conductive layer. 4. The method for manufacturing a wiring board according to claim 3,
The support substrate is a copper metal plate,
The method for manufacturing a wiring board further comprises removing the support substrate by etching. 4. The method for manufacturing a wiring board according to claim 3,
The exterior plating metal contains Ag, Ni, Sn, Pd, Au, and Ti as metal species,
The method for manufacturing a wiring board, wherein the first conductive layer is a conductive layer made of any one of the plurality of metal types.

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