JP7528448B2 - CIRCUIT DEVICE, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC APPARATUS - Google Patents

Description

The present invention relates to circuit devices, electro-optical devices, electronic devices, etc.

In display devices such as projectors, a configuration is known in which a substrate on which a display driver is mounted and a display panel are connected by a flexible substrate. For example, Patent Document 1 discloses a liquid crystal device in which a liquid crystal panel and a printed circuit board are electrically connected via a flexible wiring substrate bonded to an element substrate of the liquid crystal panel, and a control circuit and an image signal processing circuit are mounted on the printed circuit board. Patent Document 2 discloses a liquid crystal display device in which a phase expansion drive video signal is supplied from outside the substrate to a substrate on which a pixel array is provided.

JP 2005-157304 A JP 2008-139610 A

In recent years, as electro-optical panels have become increasingly high-definition, the drive time per pixel has become shorter, making it desirable to transmit data voltage signals from the display driver to the electro-optical panel at high speed. However, in a configuration in which a board on which a display driver is mounted is connected to a display panel by a flexible board or the like, there is a problem in that it is difficult to transmit data voltage signals from the display driver to the electro-optical panel at high speed because the flexible board has a parasitic wiring load capacitance.

One aspect of the present disclosure relates to a circuit device including: a distortion adjustment circuit that receives a data voltage signal from a display driver, adjusts waveform distortion of the data voltage signal, and outputs an adjusted signal; a first voltage buffer circuit that is composed of transistors with a first voltage resistance and buffers the adjusted signal to output a first output signal; and a second voltage buffer circuit that is composed of transistors with a second voltage resistance higher than the first voltage resistance and amplifies the first output signal to output a second output signal to an electro-optical panel.

Another aspect of the present disclosure relates to an electro-optical device including the circuit device described above, the display driver, and the electro-optical panel.

Yet another aspect of the present disclosure relates to an electronic device that includes the circuit device described above.

1 shows an example of the configuration of a conventional electro-optical device. 4 shows an example of the waveform of a data voltage signal in a conventional electro-optical device. 1 shows a first configuration example of an electro-optical device. 2 shows examples of circuit configurations of a display driver, a circuit device, and an electro-optical panel. 3 shows a first detailed configuration example of a circuit device. 4 shows an example of signal waveforms in a circuit device according to a first detailed configuration example. 4 shows a second detailed configuration example of the circuit device. 11 is a first waveform example illustrating the operation of the monitor circuit. 11 is a first waveform example illustrating the operation of the monitor circuit. 11 is a second waveform example illustrating the operation of the monitor circuit. 4 shows a third detailed configuration example of the circuit device. 13 shows an example of the configuration of a circuit device when performing coupling correction. FIG. 4 is a waveform diagram illustrating coupling correction. FIG. 4 is a waveform diagram illustrating coupling correction. FIG. 4 is a waveform diagram illustrating coupling correction. A detailed example of the level shifter configuration. 13 shows a second configuration example of an electro-optical device. Example of electronic device configuration.

A preferred embodiment of the present disclosure will be described in detail below. Note that the present embodiment described below does not unduly limit the content described in the claims, and not all of the configurations described in the present embodiment are necessarily essential components.

1 shows an example of the configuration of a conventional electro-optical device 1. The electro-optical device 1 includes a display driver 2, a connector 3, a flexible substrate 4, an electro-optical panel 5, and a substrate 6.

The electro-optical panel 5 is a liquid crystal display panel, and one end of the flexible substrate 4 is connected to the glass substrate of the liquid crystal display panel. The substrate 6 is a printed circuit board, and is provided with a display driver 2 and a connector 3. The other end of the flexible substrate 4 is connected to the connector 3, and the display driver 2 and the electro-optical panel 5 are electrically connected via the wiring on the flexible substrate 4.

The data voltage signal and control signal output by the display driver 2 are transmitted by the wiring of the flexible substrate 4 and input to the electro-optical panel 5. The display driver 2 sequentially outputs grayscale voltages corresponding to each pixel, and the grayscale voltages in this time series are input to the electro-optical panel 5 as data voltage signals. Then, the grayscale voltages corresponding to each selected pixel are written to the pixels selected sequentially by the control signal.

Figure 2 shows an example of the waveform of a data voltage signal in the electro-optical device 1. Figure 2 shows an example of the waveform of a data voltage signal after passing through the flexible substrate 4, i.e., at the input of the electro-optical panel 5.

In the waveform shown by the solid line, TGA corresponds to the period for driving one pixel. Parasitic capacitance and parasitic resistance exist in the wiring of the flexible substrate 4, and there is also a resistor for electrostatic protection at the input of the electro-optical panel 5, so distortion occurs in the waveform of the data voltage signal. Distortion here means that the waveform of the signal that reaches the electro-optical panel 5 is deformed compared to the original waveform of the signal output by the display driver 2. How the waveform is distorted depends on the frequency characteristics of the transmission path, but Figure 2 shows an example waveform when the high-frequency components of a square wave are reduced.

To achieve high quality display, it is necessary to write accurate grayscale voltages to the pixels, but to write accurate grayscale voltages to the pixels, the data voltage signal must reach the target voltage at least at the end of the period TGA. For example, if the number of pixels in the electro-optical panel 5 is doubled without changing the number of driving amplifiers in the display driver 2, the period for driving one pixel will be half of TGA, as shown in TGB. The higher the pixel density or the frame rate, the shorter the period TGB becomes, so the higher the possibility that the data voltage signal will not reach the target voltage at the end of the period TGB increases. Since the distortion of the waveform is determined by the frequency characteristics of the transmission path, there is a limit to shortening the period TGB. In other words, it becomes necessary to increase the transfer rate of the data voltage signal with the increase in pixel density or frame rate, or both, but the distortion of the waveform caused by the flexible substrate 4 makes it difficult to improve the transfer rate.

Figure 3 shows a first configuration example of an electro-optical device 10 in this embodiment. The electro-optical device 10 includes a display driver 12, a connector 13, a flexible substrate 14, an electro-optical panel 15, a substrate 16, and a circuit device 100.

The substrate 16 is a circuit board on which circuit components such as an integrated circuit device can be mounted, for example a printed circuit board. The display driver 12 and the connector 13 are mounted on the substrate 16. The substrate 16 may further include a display controller for controlling the display driver 12. The display driver 12 generates a data voltage signal and a control signal for driving the electro-optical panel 15 based on the display data, and outputs the data voltage signal and the control signal. The display driver 12 is, for example, an integrated circuit device. The display driver 12 and the connector 13 are electrically connected by wiring provided on the substrate 16. The wiring provided on the substrate 16 is connected to wiring provided on the flexible substrate 14 via the connector 13.

The flexible substrate 14, also known as an FPC, is a flexible circuit board that can be bent. FPC stands for Flexible Printed Circuits. The circuit device 100 is mounted on the flexible substrate 14. The input terminals of the circuit device 100 are connected to wiring provided on the flexible substrate 14 and electrically connected to the connector 13.

The circuit device 100 is, for example, an integrated circuit device known as an IC. The circuit device 100 is an IC manufactured by a semiconductor process, and is a semiconductor chip in which circuit elements are formed on a semiconductor substrate. A data voltage signal and a control signal output from the display driver 12 are input to the input terminal of the circuit device 100 via wiring provided on the substrate 16, the connector 13, and wiring provided on the flexible substrate 14.

The circuit device 100 adjusts the waveform distortion of the input data voltage signal and outputs the data voltage signal after the distortion adjustment. The circuit device 100 also level-shifts the input control signal and outputs the level-shifted control signal. The distortion-adjusted data signal and the level-shifted control signal output from the circuit device 100 are input to the electro-optical panel 15 via wiring provided on the flexible substrate 14.

As shown in FIG. 3, the circuit device 100 is disposed on the flexible substrate 14 closer to the electro-optical panel 15 than the display driver 12. The circuit device 100 is disposed so that the wiring length between the circuit device 100 and the electro-optical panel 15 is a predetermined length or less so that the data voltage signal after distortion adjustment is not affected by waveform distortion due to wiring between the circuit device 100 and the electro-optical panel 15. The wiring length between the circuit device 100 and the electro-optical panel 15 is set to a predetermined length or less according to the transfer rate of the data voltage signal required according to the resolution and frame rate of the image displayed on the electro-optical panel. Specifically, when a full high-definition (2K×1K dot) image is displayed on the electro-optical panel 15 at a frame rate of 120 fps (the period for driving one pixel is about 72 ns), if the transfer rate of the data voltage signal is about 3.6 Gbps, it is preferable that the wiring length between the electro-optical panel 15 and the circuit device 100 is 7 cm or less. Furthermore, when a full HD (2K×1K dot) image is displayed on the electro-optic panel 15 at 240 fps (the period for driving one pixel is about 36 ns), which is twice the frame rate, the transfer rate of the data voltage signal is twice as fast, or about 7.2 Gbps, and it is preferable that the wiring length between the electro-optic panel 15 and the circuit device 100 is half, or 3.5 cm or less. Furthermore, when a full HD (2K×1K dot) image is displayed on the electro-optic panel 15 at 480 fps (the period for driving one pixel is about 18 ns), which is four times the frame rate, the transfer rate of the data voltage signal is four times as fast, or about 14.4 Gbps, and it is preferable that the wiring length between the electro-optic panel 15 and the circuit device 100 is about 1.75 cm or less, which is about one-quarter. Furthermore, when displaying an image with four times the resolution, 4K (4K x 2K dots), on the electro-optical panel 15 at a frame rate of 120 fps (the period for driving one pixel is approximately 72 ns), if the transfer rate of the data voltage signal is four times that of the original, at approximately 14.4 Gbps, it is preferable to set the wiring length between the electro-optical panel 15 and the circuit device 100 to approximately one-quarter, or 1.75 cm or less.

The input terminal of the electro-optical panel 15 is connected to the output terminal of the circuit device 100 by wiring provided on the flexible substrate 14. The electro-optical panel 15 displays an image based on the data voltage signal wave-shaped by the circuit device 100 and the control signal level-shifted by the circuit device 100. The electro-optical panel 15 is also called a display panel, and is, for example, a liquid crystal display panel. The liquid crystal display panel includes a glass substrate and a pixel array formed on the glass substrate. The liquid crystal display panel can also include a circuit formed on the glass substrate and configured by TFTs, and a transparent electrode wiring formed on the glass substrate that connects the circuit and the pixel array. TFT is an abbreviation for Thin Film Transistor. When the electro-optical device 10 is applied to a projector, the electro-optical panel 15 is inserted between a light source and a projection optical system, and the light transmitted through the electro-optical panel 15 is imaged on the screen by the projection optical system, thereby projecting an image on the screen. The electro-optical device 10 is not limited to projectors and can be applied to various display devices. The electro-optical panel 15 is not limited to a liquid crystal display panel, and may be an organic EL display panel or the like.

Figure 4 shows an example of the circuit configuration of the display driver 12, the circuit device 100, and the electro-optical panel 15. The display driver 12 includes a control circuit 21, D/A conversion circuits DAC1 to DACn, amplifier circuits AM1 to AMn, and output terminals TD1 to TDn, TS. n is an integer equal to or greater than 2. The circuit device 100 includes waveform shaping circuits HSC1 to HSCn, a level shifter 190, input terminals TI1 to TIn, TIS, and output terminals TQ1 to TQn, TQS. The electro-optical panel 15 includes a switch circuit 51, a pixel array 52, and input terminals TP1 to TPn, TPS.

Below, the operation will be explained using the phase expansion driving method as an example, but this is not limited to this, and for example, the electro-optical device 10 may also adopt a demultiplex driving method.

The control circuit 21 outputs the first to nth display data to the D/A conversion circuits DAC1 to DACn. The control circuit 21 also outputs a control signal for controlling the switch circuit 51 to the output terminal TS. The D/A conversion circuits DAC1 to DACn D/A convert the first to nth display data into first to nth voltages. The amplifier circuits AM1 to AMn output the first to nth data voltage signals by buffering or amplifying the first to nth voltages. Taking the first data voltage signal as an example, the grayscale value of the first display data changes in synchronization with the switching timing of the switch circuit 51, and a time-series grayscale voltage corresponding to the time-series grayscale value is output from the amplifier circuit AM1 as the first data voltage signal.

The output terminals TD1 to TDn, TS are electrically connected to the input terminals TI1 to TIn, TIS of the circuit device 100 via the substrate 16, the connector 13, and the flexible substrate 14. The first to n-th data voltage signals input to the input terminals TI1 to TIn are input to the waveform shaping circuits HSC1 to HSCn. The waveform shaping circuits HSC1 to HSCn adjust the waveform distortion of the first to n-th data voltage signals so that they approach the waveforms of the original first to n-th data voltage signals output by the amplifier circuits AM1 to AMn, and output the adjusted first to n-th data voltage signals to the output terminals TQ1 to TQn. The control signal input to the input terminal TIS is also input to the level shifter 190. The level shifter 190 level-shifts the control signal to the operating voltage of the TFT that constitutes the switch circuit 51, and outputs the level-shifted control signal to the output terminal TQS.

The output terminals TQ1 to TQn, TQS of the circuit device 100 are electrically connected to the input terminals TP1 to TPn, TPS of the electro-optical panel 15 via the flexible substrate 14. The first to n-th data voltage signals input to the input terminals TP1 to TPn and the control signal input to the input terminal TPS are input to the switch circuit 51. The pixel array 52 has first to m-th data lines, which are electrically connected to the switch circuit 51. m is an integer of 2n or more. The first to m-th data lines are arranged in that order in the horizontal scanning direction. Hereinafter, the scan line selected in a certain horizontal scanning period is called the selected scan line. The switch circuit 51 connects the input terminals TP1 to TPn to the first to n-th data lines based on the control signal. At this time, a data voltage signal is written to the pixels connected to the selected scan line and the first to n-th data lines. Next, the switch circuit 51 connects the input terminals TP1 to TPn to the (n+1)th to (2n)th data lines based on the control signal. At this time, a data voltage signal is written to the pixels connected to the selected scanning line and the (n+1)th to (2n)th data lines. This is repeated up to the mth data line, so that a grayscale voltage is written to the pixels of one scanning line.

2. Waveform Shaping Circuit The following describes the details of the waveform shaping circuits HSC1 to HSCn of the circuit device 100. Only the configuration related to HSCi will be illustrated and described below, where i is an arbitrary integer between 1 and n.

Figure 5 shows a first detailed configuration example of the circuit device 100. The circuit device 100 includes a waveform shaping circuit HSCi, a memory unit 180, an input terminal TIi, and an output terminal TQi. The waveform shaping circuit HSCi includes a distortion adjustment circuit 130, a first voltage-resistant buffer circuit 110, a second voltage-resistant buffer circuit 120, and a capacitance C3.

Capacitance C3 is the capacitance of the electrostatic protection circuit with respect to the input terminal TIi. One end of capacitance C3 is connected to the data voltage signal input node NA, and the other end is connected to the ground node NG. The data voltage signal input node NA is connected to the input terminal TIi. Capacitance C3 is a capacitor included in the electrostatic protection circuit, or a parasitic capacitance of the electrostatic protection circuit, or a combination of both.

The distortion adjustment circuit 130 receives a data voltage signal DVS from the display driver via wiring on the flexible substrate, adjusts the waveform distortion of the data voltage signal DVS, and outputs an adjusted signal TGS. The distortion adjustment circuit 130 includes a voltage divider circuit 105, a first capacitor C1, and a second capacitor C2.

The voltage division circuit 105 is provided between a data voltage signal input node NA to which the data voltage signal DVS is input, and a ground node NG. Specifically, the voltage division circuit 105 includes a first resistor R1 and a second resistor R2. The first resistor R1 is provided between the data voltage signal input node NA and a voltage division node NB. That is, one end of the first resistor R1 is connected to the data voltage signal input node NA, and the other end is connected to the voltage division node NB. The second resistor R2 is provided between the voltage division node NB and the ground node NG. That is, one end of the second resistor R2 is connected to the voltage division node NB, and the other end is connected to the ground node NG.

The first capacitor C1 is provided between the data voltage signal input node NA and the voltage division node NB. That is, one end of the first capacitor C1 is connected to the data voltage signal input node NA, and the other end is connected to the voltage division node NB. The capacitance value of the second capacitor C2 is variable, and the second capacitor C2 is provided between the voltage division node NB and the ground node NG. That is, one end of the second capacitor C2 is connected to the voltage division node NB, and the other end is connected to the ground node NG. The second capacitor C2 is a variable capacitance circuit whose capacitance value is variably controlled based on, for example, capacitance setting data. The variable capacitance circuit includes a capacitor array and a switch array. The switch array selects one or more capacitors designated by the capacitance setting data from among the multiple capacitors that make up the capacitor array. As a result, the selected one or more capacitors are connected in parallel between the voltage division node NB and the ground node NG.

The storage unit 180 stores the capacitance setting data and outputs the capacitance setting data to the second capacitor C2. The storage unit 180 is a register or a memory. The memory is a RAM or a non-volatile memory, etc. The storage unit 180 may be configured to be accessible from an external device such as a display controller via an interface circuit (not shown). In this case, the capacitance setting data is written from the external device to the storage unit 180. The storage unit 180 may be provided for each of the waveform shaping circuits HSC1 to HSCn. Alternatively, the storage unit 180 may be provided in common to all of the waveform shaping circuits HSC1 to HSCn. In this case, the capacitance setting data may be individually set for each of the waveform shaping circuits HSC1 to HSCn.

The voltage division node NB is connected to a first input node, which is an input node of the first voltage-resistant buffer circuit 110. That is, the distortion adjustment circuit 130 outputs the signal of the voltage division node NB to the first voltage-resistant buffer circuit 110 as an adjusted signal TGS. This adjusted signal TGS is a signal in which the waveform distortion of the data voltage signal DVS has been adjusted. This point will be explained below. Note that hereinafter, the symbol NB is also used for the first input node.

Figure 5 shows the parasitic resistance RP and parasitic capacitances CP1 and CP2 that are parasitic on the flexible substrate. RP1 and CP1 are the parasitic resistance and parasitic capacitance that occur between the output terminal TDi of the display driver 12 and the input terminal TIi of the circuit device 100. CP2 is the parasitic capacitance that occurs between the output terminal TDi and ground.

Figure 6 shows an example of a signal waveform in the circuit device 100. As an example, the amplifier circuit AMi outputs a data voltage signal of a rectangular wave with a pulse width corresponding to the driving period of one pixel.

As shown in the upper diagram of FIG. 6, the data voltage signal DVS input to the distortion adjustment circuit 130 is distorted by the parasitic resistance RP and parasitic capacitances CP1 and CP2 of the flexible substrate, and the capacitance C3 of the electrostatic protection circuit. FIG. 6 shows an example of a waveform in which the high-frequency components of a square wave are reduced. As shown in the middle diagram of FIG. 6, the adjusted signal TGS output by the distortion adjustment circuit 130 has a smaller amplitude than the data voltage signal DVS, and has less distortion than the data voltage signal DVS.

Specifically, the amplitude of the adjusted signal TGS is determined by the voltage division ratio of the voltage divider circuit 105. In addition, the frequency characteristics of the distortion adjustment circuit 130 are determined by the voltage division ratio of the voltage divider circuit 105 and the capacitance ratio of the first capacitor C1 and the second capacitor C2, and the waveform distortion of the data voltage signal DVS is adjusted by the frequency characteristics. By setting the capacitance value of the second capacitor C2 so that the voltage division ratio and the capacitance ratio are the same, an adjusted signal TGS with corrected distortion is obtained.

More specifically, the capacitance value of the second capacitor C2 is set so that the voltage division ratio and capacitance ratio including the parasitic resistance and parasitic capacitance of the flexible substrate and the like are the same, and thus the adjusted signal TGS in which the distortion has been corrected is obtained. Here, the resistance values of RP, R1, and R2 are rp, r1, and r2, and the capacitance values of CP1, C1, and C2 are cp1, c1, and c2. The voltage division ratio including the parasitic resistance and parasitic capacitance is rp+r1:r2, and the capacitance ratio is cp1+c1:c2. The capacitance value of the second capacitor C2 is set so that these ratios are the same. Since rp and cp1 are unknown, the capacitance value of the second capacitor C2 may be determined, for example, based on the results of actually measuring the waveform or the results of a circuit simulation. Alternatively, a monitor circuit may be built into the circuit device 100 as described later, and the capacitance value of the second capacitor C2 may be automatically set based on the monitor results. It should be noted that the voltage division ratio and the capacitance ratio do not need to be strictly the same. In other words, as long as the distortion of the data voltage signal DVS is appropriately adjusted, the voltage division ratio and capacitance ratio may be different.

According to this embodiment, by providing the distortion adjustment circuit 130, it is possible to adjust the distortion of the data voltage signal DVS, which has a waveform distortion caused by being transmitted by a flexible substrate or the like. As a result, by providing the circuit device 100, it becomes possible to transmit a high-speed data voltage signal that would not be able to be transmitted by a flexible substrate if the circuit device 100 were not provided, and it becomes possible to accommodate the high pixel count of the electro-optical panel 15.

In addition, according to this embodiment, by providing the voltage division circuit 105, it is possible to make the voltage division ratio rp+r1:r2 and the capacitance ratio cp1+c1:c2 the same. Qualitatively, in the path from the output node of the amplifier circuit AMi to the voltage division node NB of the distortion adjustment circuit 130, the voltage division ratio rp+r1:r2 determines the gain of the low frequency band, and the capacitance ratio cp1+c1:c2 determines the gain of the high frequency band. When the voltage division ratio and the capacitance value are the same, the gain of the low frequency band and the gain of the high frequency band become the same, and the frequency characteristics in the above path become close to flat. This results in an adjusted signal TGS with less distortion. Note that if the capacitance value of the second capacitor C2 is increased, the high frequency components of the adjusted signal TGS relatively decrease, and if the capacitance value of the second capacitor C2 is decreased, the high frequency components of the adjusted signal TGS relatively increase.

In this embodiment, the input impedance of the distortion adjustment circuit 130 is lower than the input impedance of the input terminal TPi of the electro-optic panel 15 to which the second output signal QS2 is input. The input impedance of the distortion adjustment circuit 130 is the input impedance of the distortion adjustment circuit 130 as seen from the input terminal TIi. The second output signal QS2 is the output signal of the second voltage-resistant buffer circuit 120. In this way, the waveform distortion of the data voltage signal input to the electro-optic panel 15 when the circuit device 100 is provided is smaller than the waveform distortion of the data voltage signal input to the electro-optic panel 15 when the circuit device 100 is not provided. In this embodiment, the data voltage signal is further distortion-adjusted by the distortion adjustment circuit 130, making it possible to transmit the data voltage signal at high speed.

Next, the first voltage-resistant buffer circuit 110 and the second voltage-resistant buffer circuit 120 in FIG. 5 will be described.

The first voltage-resistant buffer circuit 110 is composed of transistors of a first voltage-resistant type, and buffers the regulated signal TGS to output a first output signal QS1. Specifically, the first voltage-resistant buffer circuit 110 includes an operational amplifier ABF1 composed of transistors of the first voltage-resistant type.

The first voltage-resistant buffer circuit 110 is a voltage follower circuit configured by an operational amplifier ABF1. That is, the non-inverting input node of the operational amplifier ABF1 is connected to a first input node NB. The inverting input node of the operational amplifier ABF1 is connected to the output node of the operational amplifier ABF1. The output node of the operational amplifier ABF1 is the output node of the first voltage-resistant buffer circuit 110, which is referred to as a first output node NC. The first output node NC is connected to a second input node, which is an input node of the second voltage-resistant buffer circuit 120. Hereinafter, the symbol NC is also used for the second input node.

The second voltage-resistant buffer circuit 120 is composed of transistors with a second voltage resistance higher than the first voltage resistance, and amplifies the first output signal QS1 to output the second output signal QS2 to the electro-optical panel 15. As shown in the lower diagram of FIG. 6, the second voltage-resistant buffer circuit 120 has a gain greater than 1, and increases the amplitude of the first output signal QS1 to output it as the second output signal QS2. For example, the second voltage-resistant buffer circuit 120 has a gain such that the amplitude of the second output signal QS2 is approximately the same as the amplitude of the data voltage signal DVS. The gain of the second voltage-resistant buffer circuit 120 is approximately the reciprocal of the voltage division ratio of the voltage divider circuit 105. Specifically, the second voltage-resistant buffer circuit 120 includes an operational amplifier ABF2 composed of transistors with a second voltage resistance, and resistors RBF1 and RBF2.

The second voltage-resistant buffer circuit 120 is a non-inverting amplifier circuit. That is, the non-inverting input node of the operational amplifier ABF2 is connected to the second input node NC. The output node of the operational amplifier ABF2 is connected to one end of the resistor RBF1, and the inverting input node of the operational amplifier ABF2 is connected to the other end of the resistor RBF1 and one end of the resistor RBF2. The other end of the resistor RBF2 is connected to the ground node NG. The output node of the operational amplifier ABF2 is the output node of the second voltage-resistant buffer circuit 120, which is referred to as the second output node ND. The second output node ND is connected to the output terminal TQi.

The breakdown voltage of a transistor is the maximum rated voltage that can be applied to the terminal of the transistor, and is determined, for example, by the semiconductor process. The breakdown voltage of a transistor is determined by the thickness of the gate oxide film, the impurity concentration of the impurity region, and the electric field relaxation structure. That is, the first breakdown voltage transistor and the second breakdown voltage transistor differ in at least one of the thickness of the gate oxide film, the impurity concentration of the impurity region, and the electric field relaxation structure. For example, when a process having two types of transistors, high and low breakdown voltages, is used, the first breakdown voltage corresponds to the low breakdown voltage, and the second breakdown voltage corresponds to the high breakdown voltage. Alternatively, when a process having three types of transistors, high, medium, and low breakdown voltages, is used, the first breakdown voltage corresponds to the low breakdown voltage, and the second breakdown voltage corresponds to the medium or high breakdown voltage. Alternatively, the first breakdown voltage corresponds to the medium breakdown voltage, and the second breakdown voltage corresponds to the high breakdown voltage.

According to this embodiment, the distortion adjustment circuit 130 performs voltage division, so that the first voltage-resistant buffer circuit 110 can be configured with transistors having a first voltage-resistant voltage that is lower than the second voltage-resistant voltage. The second voltage-resistant voltage is a voltage-resistant voltage required to drive the electro-optical panel 15. By configuring the first voltage-resistant buffer circuit 110 with transistors having a first voltage-resistant voltage that is lower than the second voltage-resistant voltage, it is possible to reduce the size, speed, and power consumption of the first voltage-resistant buffer circuit 110.

7 shows a second detailed configuration example of the circuit device 100. In Fig. 7, the circuit device 100 further includes a monitor circuit 140. Note that components already described are given the same reference numerals, and descriptions of those components will be omitted as appropriate.

The monitor circuit 140 compares the first output signal QS1 with the reference signal RFQ, and outputs a distortion adjustment signal TYS to the distortion adjustment circuit 130 based on the result of the comparison. The distortion adjustment circuit 130 adjusts the waveform distortion of the data voltage signal DVS based on the distortion adjustment signal TYS. Specifically, the monitor circuit 140 includes an adjustment controller 141, a comparator 143, and a reference output circuit 144.

The reference output circuit 144 outputs a reference signal RFQ. The comparator 143 compares the first output signal QS1 with the reference signal RFQ. Specifically, the first output signal QS1 is input to a first input node of the comparator 143, and the reference signal RFQ is input to a second input node of the comparator 143. FIG. 7 shows an example in which the first input node is a non-inverting input node and the second input node is an inverting input node. The adjustment controller 141 outputs a distortion adjustment signal TYS based on the output signal CPQ of the comparator 143.

The adjustment controller 141 includes a memory unit 180 that stores capacitance setting data, and outputs a distortion adjustment signal TYS based on the capacitance setting data. The distortion adjustment signal TYS may be either a digital signal or an analog signal. For example, the adjustment controller 141 may output the capacitance setting data as the distortion adjustment signal TYS. In this case, the second capacitor C2 has the configuration described in FIG. 5. Alternatively, the adjustment controller 141 may D/A convert the capacitance setting data and output the voltage after the D/A conversion as the distortion adjustment signal TYS. In this case, the second capacitor C2 is a MOS capacitor or a variable capacitance diode, etc.

The monitor circuit 140 has an adjustment mode that determines the capacitance value of the second capacitor C2, and a fixed mode that fixes the capacitance value to the value set in the adjustment mode. For example, the adjustment mode is set when the electro-optical device 10 is started up or during a retrace period in driving the electro-optical panel, and the fixed mode is set during a period in which pixel driving is performed in driving the electro-optical panel.

In the adjustment mode, the adjustment controller 141 changes the set value of the capacitance setting data, determines the capacitance setting data based on the output signal CPQ of the comparator 143 at each set value, and stores the determined capacitance setting data in the memory unit 180. In the fixed mode, the adjustment controller 141 outputs the distortion adjustment signal TYS to the second capacitor C2 based on the capacitance setting data stored in the memory unit 180 in the adjustment mode.

Figures 8 and 9 are a first waveform example explaining the operation of the monitor circuit 140. In this example, the reference output circuit 144 outputs a reference signal RFQ with a pulse waveform. The display driver 12 outputs a data voltage signal with a pulse waveform synchronized with the reference signal RFQ. The display driver outputs the data voltage signal so that the pulse waveform of the ideal first output signal QS1 in the absence of waveform distortion matches the pulse waveform of the reference signal RFQ. For example, the adjustment controller 141 outputs a synchronization signal to the reference output circuit 144 and the display driver 12, and based on the synchronization signal, the reference output circuit 144 outputs the reference signal RFQ, and the display driver 12 outputs the data voltage signal.

Figure 8 shows an example of a waveform in which the actual first output signal QS1 has an excessive amount of high-frequency components compared to the ideal first output signal QS1. In this case, the output signal CPQ of the comparator 143 becomes high level when the reference signal RFQ rises, and becomes low level when the reference signal RFQ falls.

Figure 9 shows an example of a waveform in which the high-frequency components of the actual first output signal QS1 are too small compared to the ideal first output signal QS1. In this case, the output signal CPQ of the comparator 143 becomes low level when the reference signal RFQ rises, and becomes high level when the reference signal RFQ falls.

The adjustment controller 141 determines the capacitance setting data when switching between the state of FIG. 8 and the state of FIG. 9 as the final capacitance setting data. For example, the adjustment controller 141 gradually increases the capacitance value of the second capacitor C2 from the minimum set value. It starts from the state of FIG. 8, and the high-frequency components of the first output signal QS1 decrease, and when a certain capacitance value is reached, it switches to the state of FIG. 9. The capacitance setting data at this switch, or immediately before that, is adopted as the final capacitance setting data.

Figure 10 is a second waveform example illustrating the operation of the monitor circuit 140. In this example, the reference output circuit 144 outputs a constant reference voltage as the reference signal RFQ. The display driver 12 outputs a data voltage signal with a pulse waveform. The reference output circuit 144 outputs a reference voltage that is slightly higher than the pulse waveform of the ideal first output signal QS1 when the waveform is not distorted.

10 shows an example of a waveform when the actual first output signal QS1 has an excessive amount of high-frequency components compared to the ideal first output signal QS1. In this case, the output signal CPQ of the comparator 143 becomes high level at the rising edge of the first output signal QS1. When the actual first output signal QS1 has an excessively small amount of high-frequency components compared to the ideal first output signal QS1, the output signal CPQ of the comparator 143 remains low level.

The adjustment controller 141 determines the capacitance setting data at the time when the state of FIG. 10 switches to a state where the output signal CPQ of the comparator 143 remains at a low level as the final capacitance setting data. For example, the adjustment controller 141 gradually increases the capacitance value of the second capacitor C2 from the minimum set value. It starts from the state of FIG. 10, and the high-frequency components of the first output signal QS1 decrease until a certain capacitance value is reached, at which point the output signal CPQ of the comparator 143 switches to a state where it remains at a low level. The capacitance setting data at this time, or immediately before this, is adopted as the final capacitance setting data.

Figure 11 is a third detailed configuration example of the circuit device 100. In Figure 11, the monitor circuit 140 includes an adjustment controller 141 and a comparator 143. Note that components that have already been described are given the same reference numerals, and descriptions of those components will be omitted as appropriate.

The monitor circuit 140 compares the data voltage signal DVS with the second output signal QS2, and outputs the distortion adjustment signal TYS to the distortion adjustment circuit 130 based on the result of the comparison. Specifically, the comparator 143 compares the data voltage signal DVS with the second output signal QS2. The second output signal QS2 is input to a first input node of the comparator 143, and the data voltage signal DVS is input to a second input node of the comparator 143. FIG. 11 shows an example in which the first input node is a non-inverting input node and the second input node is an inverting input node. The adjustment controller 141 outputs the distortion adjustment signal TYS based on the output signal CPQ of the comparator 143.

The operation in the adjustment mode and the fixed mode is the same as that described in the second detailed configuration example in Figs. 7 to 9. That is, the reference signal RFQ in Figs. 7 to 9 should be replaced with the data voltage signal DVS in Fig. 11, and the first output signal QS1 in Figs. 7 to 9 should be replaced with the second output signal QS2 in Fig. 11.

5, the input impedance of the distortion adjustment circuit 130 is lower than the input impedance of the input terminal TPi of the electro-optic panel 15 to which the second output signal QS2 is input. As a result, when the circuit device 100 is provided, the waveform distortion of the data voltage signal input to the circuit device 100 is smaller than the waveform distortion of the data voltage signal input to the electro-optic panel 15 when the circuit device 100 is not provided. Therefore, if the waveform of the second output signal QS2 can be adjusted to be the same as the waveform of the data voltage signal DVS, the waveform distortion of the data voltage signal input to the electro-optic panel 15 is improved more than when the circuit device 100 is not provided. In this embodiment, the monitor circuit 140 sets the capacitance value of the second capacitor C2 so that the data voltage signal DVS and the second output signal QS2 are similar.

4. Coupling Correction An embodiment in which coupling occurring between adjacent wirings in the flexible substrate 14 is corrected will be described. Fig. 12 shows a configuration example of a circuit device 100 in which coupling correction is performed. The circuit device 100 includes input terminals TI1 to TI3, distortion adjustment circuits 131 to 133, inverting amplifier circuits 151 to 153, coupling circuits 161 to 163, 172, and 173, first withstand voltage buffer circuits 111 to 113, second withstand voltage buffer circuits 121 to 123, and output terminals TQ1 to TQ3. Fig. 12 shows only the configuration corresponding to the waveform shaping circuits HSC1 to HSC3 in Fig. 4, but the same configuration is repeated up to the waveform shaping circuit HSCn.

The data voltage signal DVS1 is input to the distortion adjustment circuit 131 from the input terminal TI1. Similarly, the data voltage signals DVS2 and DVS3 are input to the distortion adjustment circuits 132 and 133 from the input terminals TI2 and TI3. Each of the distortion adjustment circuits 131 to 133 has the same configuration as the distortion adjustment circuit 130, each of the first voltage-resistant buffer circuits 111 to 113 has the same configuration as the first voltage-resistant buffer circuit 110, and each of the second voltage-resistant buffer circuits 121 to 123 has the same configuration as the second voltage-resistant buffer circuit 120, so the description of these circuit configurations is omitted. The second voltage-resistant buffer circuit 121 outputs an output signal QS21 to the output terminal TQ1. Similarly, the second voltage-resistant buffer circuits 122 and 123 output output signals QS22 and QS23 to the output terminals TQ2 and TQ3. However, a coupling circuit CPL1 is connected between the voltage division node of the distortion adjustment circuit 131 and the input node of the first voltage-resistant buffer circuit 111. The coupling circuit CPL1 is a capacitor and a resistor connected in parallel. Similarly, coupling circuits CPL2 and CPL3 are connected between the voltage division nodes of the distortion adjustment circuits 132 and 133 and the input nodes of the first voltage-resistant buffer circuits 112 and 113.

The inverting amplifier circuit 151 inverts and amplifies the adjusted signal from the distortion adjustment circuit 131, and outputs the inverted and amplified signal as the output signal HZQ1. Similarly, the inverting amplifier circuits 152 and 153 invert and amplify the adjusted signals from the distortion adjustment circuits 132 and 133, and output the inverted and amplified signals as the output signals HZQ2 and HZQ3. Each of the inverting amplifier circuits 151 to 153 is composed of an operational amplifier, an input resistor, and a feedback resistor.

The coupling circuit 161 is provided between the output node of the inverting amplifier circuit 151 and the input node of the first voltage-resistant buffer circuit 112. The coupling circuit 161 is, for example, a capacitor, one end of which is connected to the output node of the inverting amplifier circuit 151 and the other end of which is connected to the input node of the first voltage-resistant buffer circuit 112. Similarly, the coupling circuit 162 is provided between the output node of the inverting amplifier circuit 152 and the input node of the first voltage-resistant buffer circuit 113.

The coupling circuit 172 is provided between the output node of the inverting amplifier circuit 152 and the input node of the first voltage-resistant buffer circuit 111. The coupling circuit 172 is, for example, a capacitor, one end of which is connected to the output node of the inverting amplifier circuit 152 and the other end of which is connected to the input node of the first voltage-resistant buffer circuit 111. Similarly, the coupling circuit 173 is provided between the output node of the inverting amplifier circuit 153 and the input node of the first voltage-resistant buffer circuit 112.

Figures 13 to 15 are waveform diagrams explaining coupling correction. Figure 13 shows data voltage signals DVS1 to DVS3. Pulses PA1 to PA3 correspond to the original data voltage signals output by the display driver 12. Pulses CA12, CA21, CA23, and CA32 are generated by coupling in the transmission path of the flexible substrate 14 and the like. Specifically, pulses CA12 and CA21 are crosstalk between the wiring connected to the input terminals TI1 and TI2, and pulses CA23 and CA32 are crosstalk between the wiring connected to the input terminals TI2 and TI3.

Figure 14 shows output signals HZQ1 to HZQ3 of the inverting amplifier circuit 152. The output signals HZQ1 to HZQ3 are inverted signals of the data voltage signals DVS1 to DVS3. Note that although the pulse amplitudes are illustrated to be the same in Figures 13 and 14, in reality the pulse amplitudes may be different in Figures 13 and 14. Specifically, the pulse amplitudes in Figure 14 are determined according to the voltage division ratios of the distortion adjustment circuits 131 to 133 and the gains of the inverting amplifier circuits 151 to 153.

Figure 15 shows output signals QS21 to QS23 of the second voltage-resistant buffer circuits 121 to 123. According to the configuration of Figure 12, the first voltage-resistant buffer circuit 111 adds the output signal HZQ2 of the inverting amplifier circuit 152 to the data voltage signal DVS1. The first voltage-resistant buffer circuit 112 adds the output signals HZQ1 and HZQ3 of the inverting amplifier circuits 151 and 153 to the data voltage signal DVS2. The first voltage-resistant buffer circuit 113 adds the output signal HZQ2 of the inverting amplifier circuit 152 to the data voltage signal DVS3. As a result, pulses due to coupling in the transmission path are reduced in the output signals QS21 to QS23, and pulses corresponding to the original data voltage signal remain.

The addition ratio in the first voltage-resistant buffer circuits 111 to 113 may be set so that pulses due to coupling in the transmission path are reduced. Taking pulse CA12 in FIG. 13 as an example, the addition ratio may be set so that pulse CA12 in FIG. 13 is cancelled by the pulse of HZQ1 in FIG. 14, which corresponds to pulse PA1 in FIG. 13. This addition ratio is set, for example, by the gain of the inverting amplifier circuits 151 to 153.

In this embodiment, for example, the distortion adjustment circuit 130 is the first distortion adjustment circuit, and the distortion adjustment circuit is the second distortion adjustment circuit. In this case, the first voltage-resistant buffer circuit 112 is the second first-voltage-resistant buffer circuit, and the second voltage-resistant buffer circuit 122 is the second second-voltage-resistant buffer circuit. However, any one of the multiple distortion adjustment circuits included in the circuit device 100 may be the first distortion adjustment circuit. The distortion adjustment circuit next to the first distortion adjustment circuit is the second distortion adjustment circuit.

5. Level Shifter Fig. 16 shows a detailed configuration example of the level shifter 190. Fig. 16 shows an example in which the manufacturing process of the circuit device 100 includes a low-voltage process, a medium-voltage process, and a high-voltage process.

The level shifter 190 includes a first level shifter LS1 and a second level shifter LS2. The power supply voltage VDL is a power supply voltage supplied to a circuit of a low-voltage process. The power supply voltage VDM is a power supply voltage supplied to a circuit of a medium-voltage process, and is higher than the power supply voltage VDL. The power supply voltage VDH is a power supply voltage supplied to a circuit of a high-voltage process, and is higher than the power supply voltage VDM. The first level shifter LS1 level-shifts the control signal CTI from the input terminal TIS from VDL to VDM, and outputs the level-shifted control signal LSQ1. The second level shifter LS2 level-shifts the control signal LSQ1 from VDM to VDH, and outputs the level-shifted control signal CTQ to the output terminal TQS.

17 shows a second configuration example of the electro-optical device 10. The electro-optical device 10 includes a display driver 12, a connector 13, an electro-optical panel 15, a substrate 16, a group of fine coaxial cables 17, a connector 18, and a circuit device 100. Note that components already described are given the same reference numerals, and descriptions of those components will be omitted as appropriate.

The fine-coaxial cable group 17 includes a number of fine-coaxial cables, one end of which is connected to the connector 13 and the other end of which is connected to the connector 18. One fine-coaxial cable is provided for each output of the display driver 12. The fine-coaxial cable is a very thin coaxial cable, for example, a coaxial cable with an outer diameter of 1 mm or less.

The connector 18 is mounted on one end of the flexible substrate 19. The other end of the flexible substrate 19 is connected to the electro-optical panel 15, and the circuit device 100 is mounted on the flexible substrate 19. The data voltage signal and control signal output by the display driver 12 are input to the circuit device 100 via the fine coaxial cables 17 and the flexible substrate 19. The configuration and operation of the circuit device 100 are as described above.

18 shows an example of the configuration of an electronic device 300 including a circuit device 100. The electronic device 300 includes an electro-optical device 10, a processing device 310, a display controller 320, a storage unit 330, a communication unit 340, and an operation unit 360. The electro-optical device 10 includes a display driver 12, the circuit device 100, and an electro-optical panel 15.

Specific examples of electronic device 300 include various electronic devices equipped with a display device, such as a projector, a head-mounted display, a mobile information terminal, an in-vehicle device, a portable game terminal, and an information processing device. Examples of in-vehicle devices include a meter panel and a car navigation system.

The operation unit 360 is a user interface that accepts various operations from the user. For example, it is a button, a mouse, a keyboard, a touch panel attached to the electro-optical panel 15, etc. The communication unit 340 is a data interface that inputs and outputs image data and control data. The communication unit 340 is, for example, a wireless communication interface such as a wireless LAN or a short-distance wireless communication, or a wired communication interface such as a wired LAN or a USB. The storage unit 330 stores data input from the communication unit 340, or functions as a working memory for the processing device 310. The storage unit 330 is, for example, a memory such as a RAM or a ROM, a magnetic storage device such as a HDD, or an optical storage device such as a CD drive or a DVD drive. The display controller 320 processes image data input from the communication unit 340 or stored in the storage unit 330 and transfers it to the display driver 12. The display driver 12 outputs a data voltage signal and a control signal based on the image data transferred from the display controller 320. The circuit device 100 adjusts the distortion of the data voltage signal and shifts the level of the control signal, and outputs them to the electro-optical panel 15. As a result, an image is displayed on the electro-optical panel 15. The processing device 310 controls the electronic device 300 and performs various signal processing, etc. The processing device 310 is, for example, a processor such as a CPU or MPU, or an ASIC, etc.

For example, when the electronic device 300 is a projector, the electronic device 300 further includes a light source and an optical system. The optical system is, for example, a lens, a prism, a mirror, etc. When the electro-optical panel 15 is a transmissive type, the optical device causes light from a light source to enter the electro-optical panel 15 and projects the light transmitted through the electro-optical panel 15 onto a screen. When the electro-optical panel 15 is a reflective type, the optical device causes light from a light source to enter the electro-optical panel 15 and projects the light reflected from the electro-optical panel 15 onto a screen.

The circuit device of this embodiment described above includes a distortion adjustment circuit, a first voltage-resistant buffer circuit, and a second voltage-resistant buffer circuit. The distortion adjustment circuit receives a data voltage signal from the display driver, adjusts the waveform distortion of the data voltage signal, and outputs an adjusted signal. The first voltage-resistant buffer circuit is composed of transistors with a first voltage resistance, buffers the adjusted signal, and outputs a first output signal. The second voltage-resistant buffer circuit is composed of transistors with a second voltage resistance higher than the first voltage resistance, amplifies the first output signal, and outputs a second output signal to the electro-optical panel.

In this way, the distortion adjustment circuit can adjust the distortion of the data voltage signal that has become distorted in waveform due to transmission via a flexible substrate or the like. As a result, by providing the circuit device, it becomes possible to transmit high-speed data voltage signals that would not be possible to transmit via a flexible substrate if the circuit device were not provided. The ability to transmit high-speed data voltage signals makes it possible to accommodate the increasing number of pixels in electro-optical panels.

In this embodiment, the distortion adjustment circuit may also have a voltage division circuit. The voltage division circuit may be provided between a data voltage signal input node to which a data voltage signal is input, and a ground node. A voltage division node of the voltage division circuit may be connected to a first input node of the first voltage-resistant buffer circuit.

In this way, it is possible to make the voltage division ratio and capacitance ratio for the data voltage signal the same on the path from the display driver output to the voltage division node of the distortion adjustment circuit. When the voltage division ratio and capacitance value are the same, the gain in the low frequency band and the gain in the high frequency band become the same, and the frequency characteristics on the above path become nearly flat. This results in an adjusted signal with less distortion.

In this embodiment, the distortion adjustment circuit may also have a first capacitor and a second capacitor. The first capacitor may be provided between the data voltage signal input node and the voltage division node. The second capacitor may be provided between the voltage division node and a ground node, and may have a variable capacitance value.

In this way, the capacitance ratio is adjusted by adjusting the capacitance value of the second capacitor. This makes it possible to make the voltage division ratio and capacitance ratio for the data voltage signal the same on the path from the output of the display driver to the voltage division node of the distortion adjustment circuit.

In this embodiment, the voltage divider circuit may also have a first resistor and a second resistor. The first resistor may be provided between the data voltage signal input node and the voltage division node. The second resistor may be provided between the voltage division node and a ground node.

In this way, the data voltage signal can be divided by the first resistor and the second resistor. The above-mentioned voltage division ratio is determined by the parasitic resistance of the transmission path such as the flexible board, the first resistor, and the second resistor.

In addition, in this embodiment, the input impedance of the distortion adjustment circuit may be lower than the input impedance of the input terminal of the electro-optical panel to which the second output signal is input.

In this way, the waveform distortion of the data voltage signal input to the circuit device when the circuit device is provided is smaller than the waveform distortion of the data voltage signal input to the electro-optical panel when the circuit device is not provided. In this embodiment, the data voltage signal is further distortion-adjusted by the distortion adjustment circuit, making it possible to transmit the data voltage signal at high speed.

In this embodiment, the circuit device may also include a monitor circuit. The monitor circuit may compare the first output signal with a reference signal and output a distortion adjustment signal to the distortion adjustment circuit based on the result of the comparison. The distortion adjustment circuit may adjust the waveform distortion of the data voltage signal based on the distortion adjustment signal.

In this way, the monitor circuit can compare the first output signal with the reference signal, and based on the comparison result, determine a distortion adjustment signal that enables the distortion adjustment circuit to appropriately reduce waveform distortion.

In this embodiment, the monitor circuit may have a reference output circuit, a comparator, and an adjustment controller. The reference output circuit may output a reference signal. The comparator may compare the first output signal with the reference signal. The adjustment controller may output a distortion adjustment signal based on the output signal of the comparator.

In this way, the comparator compares the first output signal with the reference signal, and the adjustment controller outputs a distortion adjustment signal based on the output signal of the comparator, allowing the monitor circuit to output a distortion adjustment signal.

In this embodiment, the circuit device may also include a monitor circuit. The monitor circuit may compare the data voltage signal with the second output signal and output a distortion adjustment signal to the distortion adjustment circuit based on the result of the comparison. The distortion adjustment circuit may adjust the waveform distortion of the data voltage signal based on the distortion adjustment signal.

In this way, the monitor circuit can compare the data voltage signal with the second output signal, and based on the comparison result, determine a distortion adjustment signal that enables the distortion adjustment circuit to appropriately reduce waveform distortion.

In this embodiment, the monitor circuit may also include a comparator and an adjustment controller. The comparator may compare the data voltage signal with the second output signal. The adjustment controller may output a distortion adjustment signal based on the output signal of the comparator.

In this way, the comparator compares the data voltage signal with the second output signal, and the adjustment controller outputs a distortion adjustment signal based on the output signal of the comparator, allowing the monitor circuit to output a distortion adjustment signal.

In this embodiment, the data voltage signal may be a signal in which multiple grayscale voltages are output in a time series.

When the transfer rate of such a data voltage signal increases, the length of the period during which one gradation voltage is output becomes shorter. This makes the signal more susceptible to waveform distortion. According to this embodiment, the distortion adjustment circuit adjusts the waveform distortion of the data voltage signal, thereby increasing the transfer rate of the data voltage signal.

In the present embodiment, the circuit device may include a second distortion adjustment circuit, a second first-voltage-resistant buffer circuit, a second second-voltage-resistant buffer circuit, an inverting amplifier circuit, and a coupling circuit. The second distortion adjustment circuit may receive a second data voltage signal from the display driver, adjust the waveform distortion of the second data voltage signal, and output a second adjusted signal. The second first-voltage-resistant buffer circuit may be composed of transistors with a first voltage resistance, and may buffer the second adjusted signal to output a third output signal. The second second-voltage-resistant buffer circuit may be composed of transistors with a second voltage resistance, and may buffer the third output signal to output a fourth output signal to the electro-optical panel. The inverting amplifier circuit may invert and amplify the second adjusted signal. The coupling circuit may be provided between the output node of the inverting amplifier circuit and the first input node of the first voltage-resistant buffer circuit.

Crosstalk occurs between the data voltage signal and the second data voltage signal due to coupling in the transmission path. According to this embodiment, the output signal of the inverting amplifier circuit is added to the adjusted signal output by the distortion adjustment circuit. In other words, the second adjusted signal output by the second distortion adjustment circuit is subtracted from the adjusted signal output by the distortion adjustment circuit. This reduces the crosstalk components contained in the data voltage signal.

The electro-optical device of this embodiment also includes any of the circuit devices described above, a display driver, and an electro-optical panel.

In this embodiment, the electro-optical device may also include a flexible substrate. A circuit device may be provided on the flexible substrate, and the flexible substrate may be connected to the electro-optical panel.

The electronic device of this embodiment also includes any of the circuit devices described above.

Although the present embodiment has been described in detail above, it will be readily apparent to those skilled in the art that many modifications are possible that do not substantially deviate from the novel matters and effects of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader or similar meaning may be replaced with that different term anywhere in the specification or drawings. All combinations of the present embodiment and modifications are also included within the scope of the present disclosure. Furthermore, the configurations and operations of the circuit device, display driver, electro-optical panel, electro-optical device, and electronic device are not limited to those described in the present embodiment, and various modifications are possible.

10...electro-optical device, 12...display driver, 13...connector, 14...flexible substrate, 15...electro-optical panel, 16...substrate, 17...group of thin coaxial cables, 18...connector, 19...flexible substrate, 21...control circuit, 51...switch circuit, 52...pixel array, 100...circuit device, 105...voltage division circuit, 110-113...first voltage-resistant buffer circuit, 120-123...second voltage-resistant buffer circuit, 130-133...distortion adjustment circuit, 140...monitor circuit, 141...adjustment controller, 143...comparator, 144...reference output circuit, 151- 153...inverting amplifier circuit, 161-163, 172, 173...coupling circuit, 180...storage unit, 190...level shifter, 300...electronic device, 310...processing device, 320...display controller, 330...storage unit, 340...communication unit, 360...operation unit, C1...first capacitor, C2...second capacitor, CTI...control signal, DVS...data voltage signal, HSC1-HSCn...wave shaping circuit, NA...data voltage signal input node, NB...voltage division node, QS1...first output signal, QS2...second output signal, RFQ...reference signal, TGS...adjusted signal, TYS...distortion adjustment signal

Claims (11)

a distortion adjustment circuit which receives a data voltage signal from a display driver, adjusts a waveform distortion of the data voltage signal, and outputs an adjusted signal;
a first voltage-resistant buffer circuit configured with a first voltage-resistant transistor and configured to buffer the regulated signal and output a first output signal;
a second withstand voltage buffer circuit configured with transistors having a second withstand voltage higher than the first withstand voltage, amplifying the first output signal and outputting a second output signal to an electro-optical panel;
Including,
The distortion adjustment circuit includes:
a first resistor provided between a data voltage signal input node to which the data voltage signal is input and a first input node of the first voltage-resistant buffer circuit;
a second resistor provided between the first input node and a ground node;
a first capacitor provided between the data voltage signal input node and the first input node;
a second capacitor having a variable capacitance, the second capacitor being provided between the first input node and the ground node;
having
a capacitance value of the second capacitor is set so that a voltage division ratio of the data voltage signal by the first resistor and the second resistor, including a parasitic resistance and a parasitic capacitance in a flexible substrate on which the circuit device is mounted , is equal to a capacitance ratio of the first capacitor and the second capacitor ;
When the resistance value of the first resistor is r1, the resistance value of the second resistor is r2, the capacitance value of the first capacitor is c1, the capacitance value of the second capacitor is c2, the resistance value of the parasitic resistor between the output terminal of the display driver and the input terminal to which the data voltage signal is input is rp, and the capacitance value of the parasitic capacitance between the output terminal and the input terminal is cp1,
The voltage division ratio is rp+r1:r2,
The circuit device , wherein the capacitance ratio is cp1+c1:c2 . a distortion adjustment circuit which receives a data voltage signal from a display driver, adjusts a waveform distortion of the data voltage signal, and outputs an adjusted signal;
a first voltage-resistant buffer circuit configured with a first voltage-resistant transistor and configured to buffer the regulated signal and output a first output signal;
a second withstand voltage buffer circuit configured with transistors having a second withstand voltage higher than the first withstand voltage, amplifying the first output signal and outputting a second output signal to an electro-optical panel;
A monitor circuit;
Including,
The distortion adjustment circuit includes:
a first resistor provided between a data voltage signal input node to which the data voltage signal is input and a first input node of the first voltage-resistant buffer circuit;
a second resistor provided between the first input node and a ground node;
a first capacitor provided between the data voltage signal input node and the first input node;
a second capacitor having a variable capacitance, the second capacitor being provided between the first input node and the ground node;
having
The monitor circuit includes:
a reference output circuit that outputs a reference signal having a pulse waveform;
a comparator for comparing the first output signal with the reference signal;
an adjustment controller that sets the capacitance value of the second capacitor based on the output signal of the comparator ;
having
the display driver outputs the data voltage signal having a pulse waveform synchronized with the reference signal;
The circuit device according to claim 1, wherein the adjustment controller sets a capacitance value of the second capacitor based on an output signal of the comparator at the rising and falling edges of the reference signal . a distortion adjustment circuit which receives a data voltage signal from a display driver, adjusts a waveform distortion of the data voltage signal, and outputs an adjusted signal;
a first voltage-resistant buffer circuit configured with a first voltage-resistant transistor and configured to buffer the regulated signal and output a first output signal;
a second withstand voltage buffer circuit configured with transistors having a second withstand voltage higher than the first withstand voltage, amplifying the first output signal and outputting a second output signal to an electro-optical panel;
A monitor circuit;
Including,
The distortion adjustment circuit includes:
a first resistor provided between a data voltage signal input node to which the data voltage signal is input and a first input node of the first voltage-resistant buffer circuit;
a second resistor provided between the first input node and a ground node;
a first capacitor provided between the data voltage signal input node and the first input node;
a second capacitor having a variable capacitance, the second capacitor being provided between the first input node and the ground node;
having
The monitor circuit includes:
a reference output circuit that outputs a constant reference voltage as a reference signal;
a comparator for comparing the first output signal with the reference signal;
an adjustment controller that sets the capacitance value of the second capacitor based on the output signal of the comparator ;
having
The display driver outputs the data voltage signal in a pulse waveform;
The circuit device , characterized in that the adjustment controller sets the capacitance value of the second capacitor based on the output signal of the comparator at the rising edge of the first output signal . a distortion adjustment circuit which receives a data voltage signal from a display driver, adjusts a waveform distortion of the data voltage signal, and outputs an adjusted signal;
a first voltage-resistant buffer circuit configured with a first voltage-resistant transistor and configured to buffer the regulated signal and output a first output signal;
a second withstand voltage buffer circuit configured with transistors having a second withstand voltage higher than the first withstand voltage, amplifying the first output signal and outputting a second output signal to an electro-optical panel;
A monitor circuit;
Including,
The distortion adjustment circuit includes:
a first resistor provided between a data voltage signal input node to which the data voltage signal is input and a first input node of the first voltage-resistant buffer circuit;
a second resistor provided between the first input node and a ground node;
a first capacitor provided between the data voltage signal input node and the first input node;
a second capacitor having a variable capacitance, the second capacitor being provided between the first input node and the ground node;
having
The monitor circuit includes:
a comparator for comparing the data voltage signal with the second output signal;
an adjustment controller that sets the capacitance value of the second capacitor based on the output signal of the comparator ;
having
The display driver outputs the data voltage signal in a pulse waveform;
The circuit device according to claim 1, wherein the adjustment controller sets a capacitance value of the second capacitor based on an output signal of the comparator at the rising and falling edges of the data voltage signal. 5. The circuit device according to claim 1,
The input impedance of the distortion adjustment circuit is
a second output signal having a lower input impedance than an input terminal of the electro-optical panel to which the second output signal is input; 6. The circuit device according to claim 1,
The circuit device according to claim 1, wherein the data voltage signal is a signal in which a plurality of gray-scale voltages are output in time series. 7. The circuit device according to claim 1,
a second distortion adjustment circuit that receives a second data voltage signal from the display driver, adjusts a waveform distortion of the second data voltage signal, and outputs a second adjusted signal;
a second first-voltage withstand buffer circuit configured with the first-voltage withstand transistor and configured to buffer the second adjusted signal and output a third output signal;
a second second-voltage withstand buffer circuit configured with the second-voltage withstand transistor and configured to buffer the third output signal and output a fourth output signal to the electro-optical panel;
an inverting amplifier circuit that inverts and amplifies the second adjusted signal;
a coupling circuit provided between an output node of the inverting amplifier circuit and the first input node of the first high-voltage buffer circuit;
Including,
the adjusted signal output by the distortion adjustment circuit and the output signal of the coupling circuit are added together, and the resultant signal is input to the first input node of the first voltage-resistant buffer circuit;
a gain of the inverting amplifier circuit is set so that a pulse signal appearing in the adjusted signal due to crosstalk of a pulse signal of the second data voltage signal is reduced by the output signal of the coupling circuit. A circuit arrangement according to any one of claims 1 to 7 ;
The display driver;
The electro-optical panel;
1. An electro-optical device comprising: 9. The electro-optical device according to claim 8 ,
An electro-optical device comprising: a flexible substrate provided with the circuit device and connected to the electro-optical panel. 10. The electro-optical device according to claim 9 ,
The data voltage signal is input from the display driver to one end of the flexible substrate;
the other end of the flexible substrate is connected to the electro-optical panel;
the circuit device is provided on the other end side of the flexible substrate,
The distortion adjustment circuit adjusts waveform distortion caused by the data voltage signal passing through wiring on the flexible substrate. An electronic device comprising the circuit device according to claim 1 .

Images