JP7528583B2 - Semiconductor Device - Google Patents

Description

This disclosure relates to a semiconductor device.

Nitride semiconductors have characteristics such as a high saturation electron velocity and a wide band gap. For this reason, various studies are being conducted on utilizing these characteristics to apply nitride semiconductors to high-voltage and high-output semiconductor devices. For example, the band gap of GaN, a type of nitride semiconductor, is 3.4 eV, which is larger than the band gap of Si (1.1 eV) and the band gap of GaAs (1.4 eV). For this reason, GaN has a high breakdown field strength and is extremely promising as a material for semiconductor devices for power supplies that operate at high voltages and obtain high output.

As semiconductor devices using nitride semiconductors, there have been many reports on field effect transistors, particularly high electron mobility transistors (HEMTs). For example, in the case of GaN-based HEMTs, AlGaN/GaN-HEMTs, which use GaN as an electron transport layer (channel layer) and AlGaN as an electron supply layer, have attracted attention. In AlGaN/GaN-HEMTs, distortion occurs in AlGaN due to the difference in lattice constant between GaN and AlGaN. Then, a high concentration of two-dimensional electron gas (2DEG) is obtained due to the piezoelectric polarization and spontaneous polarization of AlGaN generated by this distortion. Therefore, AlGaN/GaN-HEMTs are expected to be used as highly efficient switching elements and high-voltage power devices for electric vehicles, etc.

International Publication No. 2018/037530

Technologies proposed to improve breakdown voltage include a field plate structure that reduces the electric field, and a structure that reduces the electric field by intentionally reducing the electron density in the region on the drain electrode side. These technologies can improve the breakdown voltage when the transistor is in the off state (off breakdown voltage). However, even if a drain voltage that would not cause breakdown in the off state is applied to a transistor with high off breakdown voltage, breakdown may occur if a large drain current flows in the on state.

The objective of this disclosure is to provide a semiconductor device that can improve the on-state breakdown voltage.

According to one embodiment of the present disclosure, there is provided a semiconductor device comprising: a semiconductor laminate structure of compound semiconductors; and a source electrode, a gate electrode, and a drain electrode provided above the semiconductor laminate structure, wherein the semiconductor laminate structure comprises a base, an electron transit layer provided on the base, an electron supply layer provided on the electron transit layer, and an n-type layer provided between the gate electrode and the drain electrode in a planar view, the n-type layer having a lower surface in contact with the base and an upper surface located above an interface between the base and the electron transit layer , and the upper surface of the n-type layer is covered with the electron supply layer .

This disclosure makes it possible to improve the on-state breakdown voltage.

1 is a cross-sectional view showing a semiconductor device according to a first embodiment. FIG. 11 is a cross-sectional view showing a semiconductor device according to a second embodiment. 11A to 11C are cross-sectional views (part 1) illustrating a method for manufacturing a semiconductor device according to a second embodiment. 13A to 13C are cross-sectional views (part 2) illustrating the method for manufacturing a semiconductor device according to the second 13A to 13C are cross-sectional views (part 3) showing the method for manufacturing a semiconductor device according to the second embodiment. 13A to 13C are cross-sectional views (part 4) illustrating the method for manufacturing a semiconductor device according to the second embodiment. 5 is a cross-sectional view (part 5) showing the method for manufacturing a semiconductor device according to the second embodiment; 6 is a cross-sectional view (part 6) showing the method for manufacturing a semiconductor device according to the second embodiment; FIG. 11 is a cross-sectional view showing a semiconductor device according to a third embodiment. 11A to 11C are cross-sectional views (part 1) illustrating a method for manufacturing a semiconductor device according to a third embodiment. 13A to 13C are cross-sectional views (part 2) illustrating the method for manufacturing a semiconductor device according to the third embodiment. 13A to 13C are cross-sectional views (part 3) illustrating the method for manufacturing a semiconductor device according to the third embodiment. FIG. 13 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. 13A to 13C are cross-sectional views (part 1) illustrating a method for manufacturing a semiconductor device according to a fourth embodiment. 13A to 13C are cross-sectional views (part 2) showing the method for manufacturing a semiconductor device according to the fourth embodiment. FIG. 1 is a cross-sectional view showing a semiconductor device according to a reference example. FIG. 13 is a diagram showing the relationship between drain voltage and saturated output. FIG. 11 is a diagram showing the relationship between the distance between a gate electrode and an n-type layer and the off-leak current in a plan view. FIG. 13 is a diagram showing a discrete package according to a fifth embodiment. FIG. 13 is a wiring diagram showing a PFC circuit according to a sixth embodiment. FIG. 13 is a wiring diagram showing a power supply device according to a seventh embodiment. FIG. 13 is a wiring diagram showing an amplifier according to an eighth embodiment.

First, the mechanism of destruction caused by electrons having high energy will be briefly explained. Electrons are accelerated in one direction by an electric field. If the acceleration continues without scattering, the electrons will have high kinetic energy. When the electrons collide with the crystal lattice from a state in which the kinetic energy is very high, electrons are ionized from the atoms that constitute the crystal, and two electrons are generated from one electron (impact ionization). Furthermore, if these two electrons are accelerated again and have very high energy, a chain reaction of impact ionization may occur. This phenomenon is called an avalanche phenomenon, and it becomes a positive loop in which the number of electrons increases rapidly. In addition, two-dimensional electron gas is generated near the interface between the electron transport layer and the electron supply layer, but when impact ionization occurs, the electrons may spread throughout the entire thickness direction of the electron transport layer. In other words, the electrons may travel near the bottom surface of the electron transport layer. In this way, when impact ionization occurs, the drain current increases rapidly. And the transistor may be destroyed due to the sudden increase in drain current. The inventor of the present application has conducted extensive research to suppress the above-mentioned avalanche phenomenon. As a result, they came to the conclusion that it is possible to improve the on-state breakdown voltage by intentionally limiting the high energy of electrons.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that in this specification and drawings, components having substantially the same functional configurations may be denoted by the same reference numerals to avoid redundant description.

First Embodiment
First, a first embodiment will be described. The first embodiment relates to a semiconductor device including a high electron mobility transistor (HEMT). Fig. 1 is a cross-sectional view showing the semiconductor device according to the first embodiment.

As shown in FIG. 1, the semiconductor device 100 according to the first embodiment has a semiconductor laminate structure 101 of compound semiconductors, and a source electrode 1s, a gate electrode 1g, and a drain electrode 1d provided above the semiconductor laminate structure 101. The semiconductor laminate structure 101 has a base 110, an electron transit layer 120 provided on the base 110, an electron supply layer 130 provided on the electron transit layer 120, and an n-type layer 140 provided between the gate electrode 1g and the drain electrode 1d in a planar view. The n-type layer 140 has a lower surface 141 in contact with the base 110 and an upper surface 142 located above the interface 102 between the base 110 and the electron transit layer 120.

In the semiconductor device 100, a two-dimensional electron gas (2DEG) is generated near the interface between the electron transit layer 120 and the electron supply layer 130. In the on state, electrons move from the source electrode 1s to the drain electrode 1d through the 2DEG. At this time, in a plan view, an n-type layer 140 exists between the gate electrode 1g and the drain electrode 1d, and ionized donor-type impurities exist in the n-type layer 140. Therefore, electrons that have passed under the gate electrode 1g are likely to be scattered by the donor-type impurities when they enter the n-type layer 140 or travel near the n-type layer 140. Such scattering of electrons occurs frequently before the electrons reach the drain electrode 1d. Since the kinetic energy of the electrons decreases with each scattering, the electrons are limited to have high kinetic energy, and the occurrence of impact ionization is suppressed. Furthermore, since the lower surface 141 of the n-type layer 140 is in contact with the base 110, the electrons can also be prevented from bypassing the n-type layer 140 below. Therefore, according to the first embodiment, it is possible to suppress destruction caused by impact ionization. In other words, it is possible to improve the on-state breakdown voltage, and destruction is less likely to occur even if a large drain current flows.

Second Embodiment
Next, a second embodiment will be described. The second embodiment relates to a semiconductor device including a GaN-based HEMT. Fig. 2 is a cross-sectional view showing the semiconductor device according to the second embodiment.

As shown in FIG. 2, the semiconductor device 200 according to the second embodiment has a substrate 211 and a semiconductor laminate structure 201 of compound semiconductors provided on the substrate 211. The semiconductor laminate structure 201 has, for example, an initial layer 212, a buffer layer 213, an electron transit layer 220, an electron supply layer 230, a cap layer 250, and an n-type layer 240.

The substrate 211 is, for example, a Si substrate. The initial layer 212 is, for example, an AlN layer having a thickness of 100 nm to 200 nm. The buffer layer 213 is, for example, an Al _x Ga _1-x N layer having a thickness of 400 nm to 600 nm. The Al composition x of the buffer layer 213 is, for example, 0.2 at the bottom surface of the buffer layer 213 and 0.8 at the top surface, and increases stepwise from the bottom surface to the top surface. The electron transit layer 220 is, for example, a GaN layer (i-GaN layer) having a thickness of 100 nm to 1000 nm and not intentionally doped with impurities. The electron supply layer 230 is, for example, an n-type Al _y Ga _1-y N layer (n-AlGaN layer) having a thickness of 20 nm to 100 nm. The Al composition y of the electron supply layer 230 is, for example, 0.2. The electron supply layer 230 is doped with, for example, Si at a concentration of about 5×10 ¹⁸ cm ⁻³ . The cap layer 250 is, for example, a GaN layer with a thickness of 1 nm to 10 nm. The cap layer 250 may be doped with an n-type impurity such as Si. The buffer layer 213 is an example of an underlayer.

A recess 245 is formed in the electron transit layer 220 and the buffer layer 213. The recess 245 is formed from the upper surface of the electron transit layer 220 to the middle of the buffer layer 213 in the thickness direction. The depth of the recess 245 with respect to the upper surface of the buffer layer 213 is, for example, 150 nm to 250 nm. The n-type layer 240 is formed in the recess 245. The n-type layer 240 has a lower surface 241 in contact with the buffer layer 213 and an upper surface 242 located above the interface 202 between the buffer layer 213 and the electron transit layer 220. The upper surface 242 is located approximately 30 nm to 100 nm below the upper surface of the electron transit layer 220, and a part of the electron supply layer 230 enters the recess 245 and is in contact with the upper surface 242 of the n-type layer 240. The n-type layer 240 is an n-type GaN layer (n-GaN layer) and contains ionized donor-type impurities such as Si or Ge. The concentration of the donor-type impurities in the n-type layer 240 is, for example, 1×10 ¹⁶ cm ^-3 to 1×10 ¹⁹ cm ^-3 . The lower limit of the donor-type impurity concentration is preferably 1×10 ¹⁷ cm ^-3 , and the upper limit of the donor-type impurity concentration is preferably 1×10 ¹⁸ cm ^-3 .

In the semiconductor laminated structure 201, an element isolation region that defines an element region is formed, and in the element region, a source recess 260s and a drain recess 260d are formed in the cap layer 250 and the electron supply layer 230. The recesses 260s and 260d are formed from the upper surface of the cap layer 250 to the middle of the thickness direction of the electron supply layer 230. A source electrode 1s is formed in the recess 260s, and a drain electrode 1d is formed in the recess 260d. A passivation film 270 that covers the source electrode 1s and the drain electrode 1d is formed on the cap layer 250. An opening 260g located between the source electrode 1s and the drain electrode 1d in a plan view is formed in the passivation film 270, and a gate electrode 1g that contacts the cap layer 250 through the opening 260g is formed. The gate electrode 1g may be formed so as to ride up on the passivation film 270.

The source electrode 1s and the drain electrode 1d include, for example, a Ti film having a thickness of 50 nm to 150 nm and an Al film having a thickness of 100 nm to 500 nm thereon. The gate electrode 1g includes, for example, a Ni film having a thickness of 10 nm to 50 nm and an Au film having a thickness of 300 nm to 500 nm thereon, and is in Schottky contact with the semiconductor laminate structure 201. The passivation film 270 is, for example, a film of an oxide, nitride or oxynitride of Si, Al, Hf, Zr, Ti, Ta or W, and is preferably a film of Si nitride (SiN). The thickness of the passivation film 270 is, for example, 2 nm to 500 nm, and is preferably about 100 nm.

In plan view, the n-type layer 240 is located between the gate electrode 1g and the drain electrode 1d, and the distance L between the gate electrode 1g and the n-type layer 240 is preferably 50 nm or more. If the distance L is less than 50 nm, the potential distribution around the gate electrode 1g is easily affected by the n-type layer 240. This makes it difficult for the depletion layer to extend at the end of the gate electrode on the drain electrode 1d side, and there is a risk of an increase in off-leak current. In addition, for example, the distance between the gate electrode 1g and the drain electrode 1d is about 5 μm, and the dimension of the n-type layer 240 in the direction in which electrons travel is about 300 nm to 500 nm.

In the semiconductor device 200, 2DEG is generated near the interface between the electron transit layer 220 and the electron supply layer 230. In the on-state, electrons move from the source electrode 1s to the drain electrode 1d through the 2DEG. At this time, in a plan view, an n-type layer 240 exists between the gate electrode 1g and the drain electrode 1d, and ionized donor-type impurities exist in the n-type layer 240. Therefore, as in the first embodiment, the occurrence of impact ionization is suppressed. Furthermore, since the lower surface 241 of the n-type layer 240 is in contact with the buffer layer 213, the bypass of electrons below the n-type layer 240 can also be suppressed. Therefore, according to the second embodiment, destruction caused by impact ionization can be suppressed. In other words, the on-state breakdown voltage can be improved, and destruction is less likely to occur even if a large drain current flows.

Next, a method for manufacturing the semiconductor device 200 according to the second embodiment will be described. Figures 3 to 8 are cross-sectional views showing the method for manufacturing the semiconductor device 200 according to the second embodiment.

First, as shown in FIG. 3, an initial layer 212, a buffer layer 213, and an electron transit layer 220 are formed on a Si substrate 211. The initial layer 212, the buffer layer 213, and the electron transit layer 220 can be formed by a crystal growth method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

When nitride semiconductor layers such as the initial layer 212, the buffer layer 213, and the electron transport layer 220 are formed by MOCVD, a mixed gas of, for example, trimethylaluminum (TMA) gas as an Al source, trimethylgallium (TMG) gas as a Ga source, and ammonia (NH ₃ ) gas as an N source is used. At this time, the presence or absence of supply of trimethylaluminum gas and trimethylgallium gas and the flow rate are appropriately set according to the composition of the nitride semiconductor layer to be grown. The flow rate of ammonia gas, which is a common raw material for each nitride semiconductor layer, is, for example, about 100 ccm to 10 LM. In addition, for example, the growth pressure is about 50 Torr to 300 Torr, and the growth temperature is about 1000°C to 1200°C.

Next, as shown in FIG. 4, recesses 245 are formed in the electron transit layer 220 and the buffer layer 213. The recesses 245 are formed from the upper surface of the electron transit layer 220 to midway through the thickness direction of the buffer layer 213. To form the recesses 245, for example, a photoresist pattern having an opening in the area where the recesses 245 are to be formed is formed on the electron transit layer 220, and dry etching is performed using a chlorine-based gas with this pattern as a mask. The photoresist pattern is then removed.

Thereafter, as shown in FIG. 5, the n-type layer 240 is formed in the recess 245. In forming the n-type layer 240, for example, a photoresist pattern having an opening corresponding to the recess 245 is formed on the electron transit layer 220, and the n-type layer 240 is grown using this pattern as a mask. Then, the photoresist pattern is removed. The n-type layer 240 can be formed by a crystal growth method such as MOCVD and MBE. When forming the n-type layer 240 by MOCVD, for example, monosilane (SiH ₄ ) gas as a Si source or monogermane (GeH ₄ ) gas as a Ge source is added to a mixed gas of trimethylgallium gas and ammonia gas. The photoresist pattern used in forming the recess 245 may be used in forming the n-type layer 240 without removing this pattern.

Next, as shown in FIG. 6, the electron supply layer 230 and the cap layer 250 are formed on the electron transit layer 220 and the n-type layer 240. The electron supply layer 230 and the cap layer 250 can be formed by a crystal growth method such as MOCVD or MBE. In this way, a semiconductor laminate structure 201 is formed, which includes the initial layer 212, the buffer layer 213, the electron transit layer 220, the electron supply layer 230, the cap layer 250, and the n-type layer 240.

Next, as shown in FIG. 7, the cap layer 250 and the surface portion of the electron supply layer 230 are removed in the region below the source electrode 1s and the region below the drain electrode 1d. This removal can be performed, for example, by dry etching using a resist mask. As a result, a source recess 260s and a drain recess 260d that expose the electron supply layer 230 are formed in the semiconductor laminate structure 201.

Thereafter, as shown in FIG. 8, a source electrode 1s is formed in the recess 260s, and a drain electrode 1d is formed in the recess 260d. The source electrode 1s and the drain electrode 1d can be formed, for example, by a lift-off method. That is, the region where the source electrode 1s is to be formed and the region where the drain electrode 1d is to be formed are exposed, and a photoresist pattern covering the other regions is formed, and a metal film is formed by deposition using this pattern as a growth mask, and this pattern is removed together with the metal film thereon. In forming the metal film, for example, a Ti film having a thickness of 50 nm to 150 nm is formed, and an Al film having a thickness of 100 nm to 500 nm is formed thereon. Next, for example, _a heat treatment (for example, rapid thermal annealing (RTA)) is performed at 400° C. to 1000° C. (for example, 600° C.) in an N 2 atmosphere to obtain an ohmic contact.

8, a passivation film 270 is formed on the cap layer 250 to cover the source electrode 1s and the drain electrode 1d. The passivation film 270 can be formed by, for example, a plasma CVD method. The passivation film 270 may also be formed by an ALD method or a sputtering method. Next, an opening 260g is formed in the passivation film 270 between the source electrode 1s and the drain electrode 1d. Then, a gate electrode 1g is formed in the opening 260g. The gate electrode 1g can be formed by, for example, a lift-off method. That is, a photoresist pattern is formed to expose the area where the gate electrode 1g is to be formed, and a metal film is formed by deposition using this pattern as a growth mask, and this pattern is removed together with the metal film thereon. In forming the metal film, for example, a Ni film having a thickness of 10 nm to 50 nm is formed, and an Au film having a thickness of 300 nm to 500 nm is formed on top of it.

In this manner, the semiconductor device 200 according to the second embodiment can be manufactured.

Third Embodiment
Next, a third embodiment will be described. The third embodiment relates to a semiconductor device including a GaN-based HEMT. Fig. 9 is a cross-sectional view showing the semiconductor device according to the third embodiment.

In the semiconductor device 300 according to the third embodiment, as shown in FIG. 9, a recess 345 is formed in the buffer layer 213 instead of the recess 245. The depth of the recess 345 with respect to the upper surface of the buffer layer 213 is, for example, 150 nm to 250 nm. The n-type layer 240 is formed in the recess 345 so as to protrude upward from the upper surface of the buffer layer 213. The electron transit layer 220 is formed so as to cover the upper surface 242 of the n-type layer 240. The electron supply layer 230 is formed on the electron transit layer 220 and is not in contact with the upper surface 242 of the n-type layer 240. The other configurations are the same as those of the second embodiment.

The third embodiment also provides the same effect as the second embodiment.

Next, a method for manufacturing the semiconductor device 300 according to the third embodiment will be described. Figures 10 to 12 are cross-sectional views showing the method for manufacturing the semiconductor device 300 according to the third embodiment.

First, as shown in FIG. 10, the process up to the formation of the buffer layer 213 is performed in the same manner as in the second embodiment. Next, a recess 345 is formed in the buffer layer 213. Thereafter, as shown in FIG. 11, the n-type layer 240 is formed in the recess 345 so as to protrude upward from the upper surface of the buffer layer 213. Next, as shown in FIG. 12, the electron transit layer 220, the electron supply layer 230, and the cap layer 250 are formed on the buffer layer 213 and the n-type layer 240. Thereafter, the process after the formation of the source recess 260s and the drain recess 260d is performed in the same manner as in the second embodiment.

In this manner, the semiconductor device 300 according to the third embodiment can be manufactured.

Fourth Embodiment
Next, a fourth embodiment will be described. The fourth embodiment relates to a semiconductor device including a GaN-based HEMT. Fig. 13 is a cross-sectional view showing the semiconductor device according to the fourth embodiment.

As shown in FIG. 13, the semiconductor device 400 according to the fourth embodiment has an insulating film 480 that covers the upper surface 242 of the n-type layer 240 in the recess 245. The insulating film 480 is interposed between the n-type layer 240 and the electron supply layer 230. The insulating film 480 is, for example, a Si oxide film or a Si nitride film with a thickness of 5 nm to 20 nm. The other configurations are the same as those of the second embodiment.

The fourth embodiment also provides the same effect as the second embodiment. Furthermore, the fourth embodiment can significantly reduce the gate leakage current flowing between the electron supply layer 230 and the n-type layer 240.

The electron supply layer 230 may be amorphous near the interface with the insulating film 480. In this case, the 2DEG between the gate electrode 1g and the drain electrode 1d is smaller than when the entire electron supply layer 230 is crystalline, and electric field concentration can be alleviated.

The upper surface of the insulating film 480 may be located above the upper surface of the electron transport layer 220.

Next, a method for manufacturing the semiconductor device 400 according to the fourth embodiment will be described. Figures 14 and 15 are cross-sectional views showing the method for manufacturing the semiconductor device 400 according to the fourth embodiment.

First, as shown in FIG. 14, the process up to the formation of the recess 245 is performed in the same manner as in the second embodiment. Next, the n-type layer 240 and the insulating film 480 are formed in the recess 245. In forming the n-type layer 240 and the insulating film 480, for example, a photoresist pattern having an opening corresponding to the recess 245 is formed on the electron transit layer 220, and the n-type layer 240 is grown using this pattern as a mask, and the insulating film 480 is formed on the n-type layer 240. Then, the photoresist pattern is removed. The n-type layer 240 can be formed by a crystal growth method such as the MOCVD method and the MBE method. The insulating film 480 can be formed by the CVD method. The photoresist pattern used to form the recess 245 may not be removed, and this pattern may be used when forming the n-type layer 240 and the insulating film 480.

Next, as shown in FIG. 15, the electron supply layer 230 and the cap layer 250 are formed on the electron transit layer 220 and the insulating film 480. The electron supply layer 230 may be amorphous near the interface with the insulating film 480 without being crystallized. After that, the processes following the formation of the source recess 260s and the drain recess 260d are performed in the same manner as in the second embodiment.

In this manner, the semiconductor device 400 according to the fourth embodiment can be manufactured.

Here, the first simulation performed by the inventors of the present application will be described. In the first simulation, the relationship between drain voltage and saturation output was calculated for the semiconductor device 200 according to the second embodiment and the semiconductor device 900 according to the reference example shown in FIG. 16. The results are shown in FIG. 17. FIG. 16 is a cross-sectional view showing the semiconductor device according to the reference example. FIG. 17 is a diagram showing the relationship between drain voltage and saturation output. As shown in FIG. 17, the semiconductor device 900 according to the reference example breaks down at a drain voltage of about 40 V, whereas the second embodiment can operate at a drain voltage of about 70 V.

Next, a second simulation performed by the inventors of the present application will be described. In the second simulation, the relationship between the distance L between the gate electrode 1g and the n-type layer 240 in a plan view and the off-leakage current was calculated for the semiconductor device 200 according to the second embodiment. The results are shown in FIG. 18. FIG. 18 is a diagram showing the relationship between the distance L between the gate electrode 1g and the n-type layer 240 in a plan view and the off-leakage current. As shown in FIG. 18, when the distance L is 50 nm or more, the off-leakage current is very small.

Fifth Embodiment
Next, a fifth embodiment will be described. The fifth embodiment relates to a discrete package of a HEMT. Fig. 19 is a diagram showing the discrete package according to the fifth embodiment.

In the fifth embodiment, as shown in FIG. 19, the back surface of a semiconductor device 1210 having a structure similar to any one of the first to fourth embodiments is fixed to a land (die pad) 1233 using a die attachment agent 1234 such as solder. A wire 1235d such as an Al wire is connected to a drain pad 1226d to which a drain electrode 1d is connected, and the other end of the wire 1235d is connected to a drain lead 1232d integrated with the land 1233. A wire 1235s such as an Al wire is connected to a source pad 1226s connected to a source electrode 1s, and the other end of the wire 1235s is connected to a source lead 1232s independent from the land 1233. A wire 1235g such as an Al wire is connected to a gate pad 1226g connected to a gate electrode 1g, and the other end of the wire 1235g is connected to a gate lead 1232g independent from the land 1233. The land 1233 and the semiconductor device 1210 are packaged in the mold resin 1231 so that a portion of the gate lead 1232g, a portion of the drain lead 1232d, and a portion of the source lead 1232s protrude.

Such a discrete package can be manufactured, for example, as follows. First, the semiconductor device 1210 is fixed to the land 1233 of the lead frame using a die attachment agent 1234 such as solder. Next, by bonding using wires 1235g, 1235d, and 1235s, the gate pad 1226g is connected to the gate lead 1232g of the lead frame, the drain pad 1226d is connected to the drain lead 1232d of the lead frame, and the source pad 1226s is connected to the source lead 1232s of the lead frame. After that, sealing is performed using mold resin 1231 by the transfer molding method. Next, the lead frame is separated.

Sixth Embodiment
Next, a sixth embodiment will be described. The sixth embodiment relates to a PFC (Power Factor Correction) circuit including a HEMT. Fig. 20 is a wiring diagram showing the PFC circuit according to the sixth embodiment.

The PFC circuit 1250 includes a switch element (transistor) 1251, a diode 1252, a choke coil 1253, capacitors 1254 and 1255, a diode bridge 1256, and an AC power supply (AC) 1257. The drain electrode of the switch element 1251 is connected to the anode terminal of the diode 1252 and one terminal of the choke coil 1253. The source electrode of the switch element 1251 is connected to one terminal of the capacitor 1254 and one terminal of the capacitor 1255. The other terminal of the capacitor 1254 is connected to the other terminal of the choke coil 1253. The other terminal of the capacitor 1255 is connected to the cathode terminal of the diode 1252. A gate driver is connected to the gate electrode of the switch element 1251. The AC 1257 is connected between both terminals of the capacitor 1254 via the diode bridge 1256. A DC power supply (DC) is connected between both terminals of the capacitor 1255. In this embodiment, a semiconductor device having a structure similar to any of the first to fourth embodiments is used for the switch element 1251.

When manufacturing the PFC circuit 1250, the switch element 1251 is connected to the diode 1252 and the choke coil 1253, etc., using, for example, solder.

Seventh Embodiment
Next, a seventh embodiment will be described. The seventh embodiment relates to a power supply device equipped with a HEMT, suitable for use as a server power supply. Fig. 21 is a wiring diagram showing the power supply device according to the seventh embodiment.

The power supply device is provided with a high-voltage primary circuit 1261, a low-voltage secondary circuit 1262, and a transformer 1263 disposed between the primary circuit 1261 and the secondary circuit 1262.

The primary side circuit 1261 includes a PFC circuit 1250 according to the sixth embodiment, and an inverter circuit, for example a full-bridge inverter circuit 1260, connected between both terminals of a capacitor 1255 of the PFC circuit 1250. The full-bridge inverter circuit 1260 includes multiple (four in this example) switch elements 1264a, 1264b, 1264c, and 1264d.

The secondary circuit 1262 is provided with multiple (here, three) switch elements 1265a, 1265b, and 1265c.

In this embodiment, the switch element 1251 of the PFC circuit 1250 constituting the primary side circuit 1261 and the switch elements 1264a, 1264b, 1264c, and 1264d of the full bridge inverter circuit 1260 are made of semiconductor devices having a structure similar to that of any of the first to fourth embodiments. On the other hand, the switch elements 1265a, 1265b, and 1265c of the secondary side circuit 1262 are made of ordinary MIS type FETs (field effect transistors) using silicon.

Eighth embodiment
Next, an eighth embodiment will be described. The eighth embodiment relates to an amplifier including a HEMT. Fig. 22 is a wiring diagram showing the amplifier according to the eighth embodiment.

The amplifier includes a digital predistortion circuit 1271, mixers 1272a and 1272b, and a power amplifier 1273.

The digital predistortion circuit 1271 compensates for nonlinear distortion of the input signal. The mixer 1272a mixes the input signal, for which nonlinear distortion has been compensated, with an AC signal. The power amplifier 1273 includes a semiconductor device having a structure similar to that of any of the first to fourth embodiments, and amplifies the input signal mixed with the AC signal. Note that in this embodiment, for example, by switching a switch, the output signal can be mixed with the AC signal by the mixer 1272b and sent to the digital predistortion circuit 1271. This amplifier can be used as a high-frequency amplifier or a high-output amplifier. The high-frequency amplifier can be used, for example, in a transmitting/receiving device for a mobile phone base station, a radar device, and a microwave generating device.

In the present disclosure, the substrate may be a silicon carbide (SiC) substrate, a sapphire substrate, a silicon substrate, an AlN substrate, a GaN substrate, or a diamond substrate. The substrate may be conductive, semi-insulating, or insulating. If an electron transport layer can be formed on the substrate, the substrate may be used as a base.

The structures of the gate electrode, source electrode, and drain electrode are not limited to those in the above-described embodiment. For example, they may be composed of a single layer. Furthermore, the method of forming them is not limited to the lift-off method. Furthermore, if ohmic characteristics are obtained, the heat treatment after the formation of the source electrode and drain electrode may be omitted. Heat treatment may be performed after the formation of the gate electrode.

In the above embodiment, a Schottky gate structure is used as the gate electrode structure, but a MIS (metal-insulator-semiconductor) gate structure may also be used.

Although the preferred embodiments have been described above in detail, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

Various aspects of this disclosure are summarized below as appendices.

(Appendix 1)
A semiconductor laminate structure of compound semiconductors;
a source electrode, a gate electrode and a drain electrode provided above the semiconductor laminate structure;
having
The semiconductor laminate structure includes:
The base and
an electron transport layer provided on the underlayer;
an electron supply layer provided on the electron transit layer;
an n-type layer provided between the gate electrode and the drain electrode in a plan view;
having
The n-type layer is
A lower surface in contact with the substrate;
an upper surface located above an interface between the base and the electron transport layer;
A semiconductor device comprising:
(Appendix 2)
A recess is formed on the upper surface of the base,
2. The semiconductor device according to claim 1, wherein the n-type layer is provided in the recess.
(Appendix 3)
3. The semiconductor device according to claim 1, wherein the electron transport layer has an opening exposing an upper surface of the n-type layer.
(Appendix 4)
4. The semiconductor device according to claim 3, further comprising an insulating film provided in the opening and covering an upper surface of the n-type layer.
(Appendix 5)
5. The semiconductor device according to claim 1, wherein a distance between the gate electrode and the n-type layer is 50 nm or more in a plan view.
(Appendix 6)
6. The semiconductor device according to claim 1, wherein the n-type layer contains a donor-type impurity at a concentration of 1×10 ¹⁶ cm ⁻³ or more and 1×10 ¹⁹ cm ⁻³ or less.
(Appendix 7)
7. The semiconductor device according to claim 1, wherein an upper surface of the n-type layer is located lower than an upper surface of the electron transit layer.
(Appendix 8)
8. An amplifier comprising the semiconductor device according to claim 1.
(Appendix 9)
A power supply device comprising the semiconductor device according to any one of claims 1 to 7.

1s: source electrode 1d: drain electrode 1g: gate electrode 100, 200, 300, 400: semiconductor device 101, 201: semiconductor laminate structure 110: base 120, 220: electron transit layer 130, 230: electron supply layer 140, 240: n-type layer 141, 241: lower surface 142, 242: upper surface 213: buffer layer 245, 345: recess

Claims (7)

A semiconductor laminate structure of compound semiconductors;
a source electrode, a gate electrode and a drain electrode provided above the semiconductor laminate structure;
having
The semiconductor laminate structure includes:
The base and
an electron transport layer provided on the underlayer;
an electron supply layer provided on the electron transit layer;
an n-type layer provided between the gate electrode and the drain electrode in a plan view;
having
The n-type layer is
A lower surface in contact with the substrate;
an upper surface located above an interface between the base and the electron transport layer;
having
a top surface of the n-type layer being covered with the electron supply layer , A recess is formed on the upper surface of the base,
2. The semiconductor device according to claim 1, wherein the n-type layer is provided in the recess. The semiconductor device according to claim 1 or 2, characterized in that an opening exposing the upper surface of the n-type layer is formed in the electron transport layer. The semiconductor device according to claim 3, further comprising an insulating film disposed in the opening and covering the upper surface of the n-type layer. 4. The semiconductor device according to claim 1, wherein the electron supply layer is in contact with an upper surface of the n-type layer. 6. The semiconductor device according to claim 1, wherein the distance between the gate electrode and the n-type layer is 50 nm or more in a plan view. 7. The semiconductor device according to claim 1, wherein the n-type layer contains a donor-type impurity at a concentration of 1×10 ¹⁶ cm ⁻³ or more and 1×10 ¹⁹ cm ⁻³ or less.

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