JP7529098B2 - Transmitting device and transmitting method - Google Patents

Description

This technology relates to a transmission device and a transmission method, and in particular to a transmission device and a transmission method that can ensure good communication quality, for example, in data transmission using LDPC codes.

LDPC (Low Density Parity Check) codes have high error correction capabilities, and in recent years have been widely adopted in transmission methods for digital broadcasting, such as DVB (Digital Video Broadcasting)-S.2 in Europe, DVB-T.2, DVB-C.2, and ATSC (Advanced Television Systems Committee) 3.0 in the United States (see, for example, Non-Patent Document 1).

Recent research has shown that LDPC codes, like turbo codes, can achieve performance approaching the Shannon limit as the code length is increased. In addition, LDPC codes have the property that the minimum distance is proportional to the code length, which gives them good block error probability characteristics. Another advantage is that the so-called error floor phenomenon observed in the decoding characteristics of turbo codes and the like hardly occurs.

ATSC Standard:Physical Layer Protocol(A/322), 7 September 2016

In data transmission using LDPC codes, for example, the LDPC codes are converted (symbolized) into symbols for orthogonal modulation (digital modulation) such as QPSK (Quadrature Phase Shift Keying), and the symbols are mapped to signal points of the orthogonal modulation and transmitted.

Data transmission using LDPC codes like those described above is becoming more widespread around the world, and there is a demand to ensure good communication (transmission) quality.

This technology was developed in light of these circumstances, and makes it possible to ensure good communication quality in data transmission using LDPC codes.

The first transmission device/method of the present technology includes an encoding unit/step for performing LDPC coding of information bits of an information length K=N×r based on an extended parity check matrix in which rows and columns of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 2/16 are each extended by a predetermined puncture length L, generating an extended LDPC code having parity bits of a parity length M=N+LK, and puncturing the beginning of the information bits of the extended LDPC code by the puncture length L to generate a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 2/16, the extended parity check matrix being represented by a predetermined value M1 and the information length K=N×r. the A matrix having M1 rows and K columns is located at the top left of the extended parity check matrix, a B matrix having a staircase structure adjacent to the right of the A matrix, having M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, having M1 rows and N+LK-M1 columns, a C matrix adjacent below the A matrix and the B matrix, having N+LK-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, having N+LK-M1 rows and N+LK-M1 columns, wherein the puncture length L is 0, the predetermined value M1 is 1800, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents positions of elements of 1 of the A matrix and the C matrix for every 360 columns,
1444 1737 1780 9182 9748 9954 11859 23510 36957 41211 41804 41857 42268 42854 45152 46217 46448 52760 57528 59998 60168
281 1279 1468 9650 11337 15973 21859 24346 25864 28317 33522 35344 40280 43576 43942 50851 53221 57076 57561 59922 59962
132 758 1470 2901 2957 3365 4567 7062 10939 12288 20818 35122 39299 41903 43394 44289 49129 51394 53222 53899 56037
9 756 1510 3127 4867 15380 16575 17906 19275 20944 25462 27021 31939 34367 36491 39391 45013 45505 47768 50626 51547
188 252 1181 2939 4132 7944 12352 15443 17831 18785 18904 22672 23400 30518 30652 45102 51500 52032 52868 60341
496 564 1527 2708 2751 3658 6451 8212 11654 17193 21558 23963 28394 30554 30628 35052 44835 45090 49804 52979
793 858 1710 3561 10566 11369 17707 20970 22329 22383 24607 31237 38613 42719 43867 45715 50453 51882 55535 60316
689 980 1657 2690 4633 11070 16939 18443 20748 21753 25742 30361 31544 31693 33019 40842 47042 48850 52130 56606
198 281 1664 3384 12801 17438 24093 29656 30578 31929 35921 38919 38984 40957 43262 48155 50743 56398 56427 59215
457 1065 1196 2861 12717 15390 16655 17899 18300 22233 31560 32716 34991 43324 46709 51328 52891 54292 56334 59229
1307 1481 1599 13551 21460 22804 23439 32551 32671 35941 36329 40096 41474 45156 50568 55578 55667 56581 59061 60009
99 485 708 4043 5527 5824 7489 8809 15871 17753 18297 18507 19070 22839 28023 41124 43165 50873 51968 57000
188 412 1641 1833 5707 7556 10610 12636 14533 26728 27604 31757 32972 34677 36279 38315 42252 43155 53121 57503
300 794 1153 6459 7063 13526 17788 18308 21233 21439 22250 28514 32042 32160 36140 44273 49289 50434 51163 56471
757 1336 1440 5560 6283 10080 10986 13051 17638 22870 31581 35463 41212 42195 43305 46746 49564 56412 58207 59477
106 1195 1474 6273 14321 14746 16496 17016 17214 19472 27450 33489 40638 42896 43150 47624 51106 51339 53730 55816
98 1002 1336 2076 9328 10989 13413 13916 14455 17863 19776 24981 31172 39450 40385 43348 44833 46967 52917 58029
262 1363 1605 4715 8438 8794 12188 18208 19803 28570 36281 38576 39120 40344 44994 45827 46559 49914 50771 56658
870 1743 1764 5521 8695 11745 15888 16359 16412 33151 37033 38281 38499 39026 41174 44818 53168 56178 58405 60285
861 1142 1169 2232 4370 9265 10442 15376 15947 19420 24577 29045 36440 38242 41035 47841 49589 50529 52662 59907
231 913 1440 2695 6369 7938 8296 12107 14329 19324 25096 26108 35369 38516 41289 43604 52617 57130 59909 60020
214 667 762 3988 6762 14360 15257 18298 18943 19364 29813 33804 35106 36373 39451 39478 45683 47618 48539 59814
1144 1150 1746 1800 7038 11454 18376 18819 21869 26781 33351 35591 46571 49235 49956 50749 51642 53390 56404 58103
308 317 1510 5176 12653 13311 15884 18075 22371 26021 27004 29283 30382 32114 32978 35790 47224 48249 51701 57840
2786 5188 6809 7110 7138 7167 8042 12569 15301 27503 27894 32875 35277 48267 49051 57363
6186 6554 12052 14220 15013 15388 22130 27207 30084 30620 31562 36834 38446 52593 56791 60017
8810 12703 21600 21640 22233 26157 27268 27384 33020 39679 49298 51854 52364 53298 55215 59802
2670 6309 10054 11421 11750 11901 12053 12752 17466 28571 29910 32369 34446 38373 49448 51729
11357 12810 13252 14755 22824 30867 32868 33512 34862 35560 38704 41861 42805 43103 48692 55234
The transmitting device/method is as follows.

A first receiving device/method of the present technology includes a coding step of performing LDPC coding of information bits of an information length K=N×r based on an extended parity check matrix in which rows and columns of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 2/16 are each extended by a predetermined puncture length L, generating an extended LDPC code having parity bits of a parity length M=N+LK, and puncturing a leading portion of the information bits of the extended LDPC code by the puncture length L to generate a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 2/16, wherein the extended parity check matrix is M expressed by a predetermined value M1 and the information length K=N×r. the A matrix having 1 row and K columns and located at the top left of the extended parity check matrix, a B matrix having a staircase structure and adjacent to the right of the A matrix, and having M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, and having M1 rows and N+LK-M1 columns, a C matrix adjacent below the A matrix and the B matrix, and having N+LK-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, and having N+LK-M1 rows and N+LK-M1 columns,
1444 1737 1780 9182 9748 9954 11859 23510 36957 41211 41804 41857 42268 42854 45152 46217 46448 52760 57528 59998 60168
281 1279 1468 9650 11337 15973 21859 24346 25864 28317 33522 35344 40280 43576 43942 50851 53221 57076 57561 59922 59962
132 758 1470 2901 2957 3365 4567 7062 10939 12288 20818 35122 39299 41903 43394 44289 49129 51394 53222 53899 56037
9 756 1510 3127 4867 15380 16575 17906 19275 20944 25462 27021 31939 34367 36491 39391 45013 45505 47768 50626 51547
188 252 1181 2939 4132 7944 12352 15443 17831 18785 18904 22672 23400 30518 30652 45102 51500 52032 52868 60341
496 564 1527 2708 2751 3658 6451 8212 11654 17193 21558 23963 28394 30554 30628 35052 44835 45090 49804 52979
793 858 1710 3561 10566 11369 17707 20970 22329 22383 24607 31237 38613 42719 43867 45715 50453 51882 55535 60316
689 980 1657 2690 4633 11070 16939 18443 20748 21753 25742 30361 31544 31693 33019 40842 47042 48850 52130 56606
198 281 1664 3384 12801 17438 24093 29656 30578 31929 35921 38919 38984 40957 43262 48155 50743 56398 56427 59215
457 1065 1196 2861 12717 15390 16655 17899 18300 22233 31560 32716 34991 43324 46709 51328 52891 54292 56334 59229
1307 1481 1599 13551 21460 22804 23439 32551 32671 35941 36329 40096 41474 45156 50568 55578 55667 56581 59061 60009
99 485 708 4043 5527 5824 7489 8809 15871 17753 18297 18507 19070 22839 28023 41124 43165 50873 51968 57000
188 412 1641 1833 5707 7556 10610 12636 14533 26728 27604 31757 32972 34677 36279 38315 42252 43155 53121 57503
300 794 1153 6459 7063 13526 17788 18308 21233 21439 22250 28514 32042 32160 36140 44273 49289 50434 51163 56471
757 1336 1440 5560 6283 10080 10986 13051 17638 22870 31581 35463 41212 42195 43305 46746 49564 56412 58207 59477
106 1195 1474 6273 14321 14746 16496 17016 17214 19472 27450 33489 40638 42896 43150 47624 51106 51339 53730 55816
98 1002 1336 2076 9328 10989 13413 13916 14455 17863 19776 24981 31172 39450 40385 43348 44833 46967 52917 58029
262 1363 1605 4715 8438 8794 12188 18208 19803 28570 36281 38576 39120 40344 44994 45827 46559 49914 50771 56658
870 1743 1764 5521 8695 11745 15888 16359 16412 33151 37033 38281 38499 39026 41174 44818 53168 56178 58405 60285
861 1142 1169 2232 4370 9265 10442 15376 15947 19420 24577 29045 36440 38242 41035 47841 49589 50529 52662 59907
231 913 1440 2695 6369 7938 8296 12107 14329 19324 25096 26108 35369 38516 41289 43604 52617 57130 59909 60020
214 667 762 3988 6762 14360 15257 18298 18943 19364 29813 33804 35106 36373 39451 39478 45683 47618 48539 59814
1144 1150 1746 1800 7038 11454 18376 18819 21869 26781 33351 35591 46571 49235 49956 50749 51642 53390 56404 58103
308 317 1510 5176 12653 13311 15884 18075 22371 26021 27004 29283 30382 32114 32978 35790 47224 48249 51701 57840
2786 5188 6809 7110 7138 7167 8042 12569 15301 27503 27894 32875 35277 48267 49051 57363
6186 6554 12052 14220 15013 15388 22130 27207 30084 30620 31562 36834 38446 52593 56791 60017
8810 12703 21600 21640 22233 26157 27268 27384 33020 39679 49298 51854 52364 53298 55215 59802
2670 6309 10054 11421 11750 11901 12053 12752 17466 28571 29910 32369 34446 38373 49448 51729
11357 12810 13252 14755 22824 30867 32868 33512 34862 35560 38704 41861 42805 43103 48692 55234
The receiving device/method includes a decoding unit/step for decoding the punctured LDPC code obtained from data transmitted by a transmission method as described above.

A second transmission device/method of the present technology includes an encoding unit/step for performing LDPC coding of information bits of an information length K=N×r based on an extended parity check matrix in which rows and columns of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 3/16 are each extended by a predetermined puncture length L, generating an extended LDPC code having parity bits of a parity length M=N+LK, and puncturing the beginning of the information bits of the extended LDPC code by the puncture length L to generate a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 3/16, wherein the extended parity check matrix is represented by a predetermined value M1 and the information length K=N×r. the A matrix having M1 rows and K columns is located at the top left of the extended parity check matrix, a B matrix having a staircase structure adjacent to the right of the A matrix, having M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, having M1 rows and N+LK-M1 columns, a C matrix adjacent below the A matrix and the B matrix, having N+LK-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, having N+LK-M1 rows and N+LK-M1 columns, wherein the puncture length L is 0, the predetermined value M1 is 1800, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents positions of elements of 1 of the A matrix and the C matrix for every 360 columns,
853 875 1192 2465 3004 4879 9062 21593 24043 26616 30909 32017 35006 42135 44268 56020
161 519 1556 3317 6015 14909 15760 21148 30072 32655 33940 34834 43430 44798 51284 52169
177 999 1683 6976 17610 18152 19591 22312 25036 27303 28584 47608 47749 50216 52322 54007
981 1000 1625 1630 6933 13217 13956 15319 22642 29483 31921 35465 43602 44250 46505 55678
1204 1242 1653 3066 6095 16862 20154 21430 23418 26408 30979 34093 41103 48385 54547 55093
316 1355 1562 2665 5222 6575 18299 19639 24268 30959 37721 47966 48255 51808 53697 56010
183 219 615 2859 6967 8044 13949 22294 28922 29355 32175 32276 33861 49675 52583 53512
263 342 1684 7426 14417 20396 27461 30075 33740 36812 38204 38420 41612 43083 45914 56035
256 870 921 3023 4662 5225 5276 19284 26034 35397 38524 44936 45178 46351 50860 51813
289 898 1442 9135 10774 13951 14133 19070 21192 27854 32118 43657 43859 43934 52772 53659
256 690 1324 3582 7066 8507 26854 34507 40768 44943 47952 50512 52080 52872 53733 53773
238 1037 1388 1929 6395 10653 21299 23085 26467 26836 27834 44924 47310 49393 53742 55883
976 1217 1469 7718 16449 19465 19983 22386 24762 28308 32395 33589 35997 41034 42118 43799
265 368 1365 1375 1808 7556 14593 15079 19648 36077 40397 41971 44940 47570 52522 55839
802 1656 1689 5554 6787 11067 15764 19656 31740 31762 36046 42258 45165 49245 52732 53420
265 307 1299 2775 6738 22483 26322 27615 30628 34194 38024 38787 46089 48680 49115 51063
698 747 1241 2898 5218 7964 15358 17928 28069 29537 33641 36103 40207 40701 42823 42929
70 293 799 16494 16696 20008 21050 23735 34060 34555 35068 37664 45312 47748 50957 52382
1151 1163 1751 7025 10775 15100 22260 24718 28905 30853 33020 43261 46849 48258 54212 56122
279 457 775 8025 13383 16978 19254 23110 28197 31454 33060 38532 41429 41621 42149 54927
494 1130 1351 18525 22446 31344 31582 38324 42396 46010 48804 49241 49379 51987 52296 53133
177 508 1032 3547 8103 13357 14344 15876 20386 22050 23593 35305 47409 53297 55610 56093
988 1091 1785 3400 5144 7245 10179 12918 32871 33462 34484 38318 43410 44103 44267 52837
520 564 1757 12204 16894 17249 21480 21541 23760 28325 36266 40606 46094 48779 55501 56065
914 943 1111 3641 4232 10215 14134 16582 23445 28767 28862 32260 35952 39907 41846 47553
466 554 1697 4921 6953 7034 7052 10648 11628 19174 27830 29210 31722 32281 52559 55802
1135 1273 1408 2599 3618 4903 7210 17368 21014 21287 21926 24070 27741 29801 36137 44272
524 801 1767 4093 9721 12200 19463 29280 31587 33577 39747 43688 46627 49807 51345 55969
489 1390 1756 3050 12113 20477 21376 26797 27049 28907 31534 32746 33345 40582 41970 55911
432 1520 1598 9292 11552 16985 18417 21847 21960 24287 25489 34478 40990 44004 47573 53982
301 592 849 1944 4128 8341 16783 19249 24983 43892 44041 44474 44942 44959 50738 54935
118 558 1470 4368 10132 11791 16523 22408 23766 25111 25426 25779 35005 42742 46197 53118
310 1059 1322 3609 7107 10048 13161 32141 33369 35206 36131 38746 44545 47963 48414
256 346 845 7363 10375 12492 13091 27987 32113 34846 36223 39863 44450 46526 49216
607 683 954 5473 10617 18484 20018 26971 28190 37592 39069 39740 43575 45676 48149
244 635 1208 5450 8082 25030 25149 28411 29333 31324 36972 42071 43401 47088 52085
2841 5514 16122 18061 18199 20340 22525 25022 29914 31732 46415
7567 22860 23157 24194 24622 29643 31255 32355 36379 38228 51173
24002 24459 25897 26955 31168 31630 39183 46791 47323 51503 55241
4817 8291 10219 13991 14318 28549 28836 30491 36884 46310 54625
8275 9585 11678 37216 38932 45186 46287 48023 48862 53636 56067
The transmitting device/method is as follows.

A second receiving device/method of the present technology includes a coding step of performing LDPC coding of information bits of an information length K=N×r based on an extended parity check matrix in which rows and columns of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 3/16 are each extended by a predetermined puncture length L, generating an extended LDPC code having parity bits of a parity length M=N+LK, and puncturing a leading portion of the information bits of the extended LDPC code by the puncture length L to generate a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 3/16, wherein the extended parity check matrix is M expressed by a predetermined value M1 and the information length K=N×r. the A matrix having 1 row and K columns and located at the top left of the extended parity check matrix, a B matrix having a staircase structure and adjacent to the right of the A matrix, and having M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, and having M1 rows and N+LK-M1 columns, a C matrix adjacent below the A matrix and the B matrix, and having N+LK-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, and having N+LK-M1 rows and N+LK-M1 columns,
853 875 1192 2465 3004 4879 9062 21593 24043 26616 30909 32017 35006 42135 44268 56020
161 519 1556 3317 6015 14909 15760 21148 30072 32655 33940 34834 43430 44798 51284 52169
177 999 1683 6976 17610 18152 19591 22312 25036 27303 28584 47608 47749 50216 52322 54007
981 1000 1625 1630 6933 13217 13956 15319 22642 29483 31921 35465 43602 44250 46505 55678
1204 1242 1653 3066 6095 16862 20154 21430 23418 26408 30979 34093 41103 48385 54547 55093
316 1355 1562 2665 5222 6575 18299 19639 24268 30959 37721 47966 48255 51808 53697 56010
183 219 615 2859 6967 8044 13949 22294 28922 29355 32175 32276 33861 49675 52583 53512
263 342 1684 7426 14417 20396 27461 30075 33740 36812 38204 38420 41612 43083 45914 56035
256 870 921 3023 4662 5225 5276 19284 26034 35397 38524 44936 45178 46351 50860 51813
289 898 1442 9135 10774 13951 14133 19070 21192 27854 32118 43657 43859 43934 52772 53659
256 690 1324 3582 7066 8507 26854 34507 40768 44943 47952 50512 52080 52872 53733 53773
238 1037 1388 1929 6395 10653 21299 23085 26467 26836 27834 44924 47310 49393 53742 55883
976 1217 1469 7718 16449 19465 19983 22386 24762 28308 32395 33589 35997 41034 42118 43799
265 368 1365 1375 1808 7556 14593 15079 19648 36077 40397 41971 44940 47570 52522 55839
802 1656 1689 5554 6787 11067 15764 19656 31740 31762 36046 42258 45165 49245 52732 53420
265 307 1299 2775 6738 22483 26322 27615 30628 34194 38024 38787 46089 48680 49115 51063
698 747 1241 2898 5218 7964 15358 17928 28069 29537 33641 36103 40207 40701 42823 42929
70 293 799 16494 16696 20008 21050 23735 34060 34555 35068 37664 45312 47748 50957 52382
1151 1163 1751 7025 10775 15100 22260 24718 28905 30853 33020 43261 46849 48258 54212 56122
279 457 775 8025 13383 16978 19254 23110 28197 31454 33060 38532 41429 41621 42149 54927
494 1130 1351 18525 22446 31344 31582 38324 42396 46010 48804 49241 49379 51987 52296 53133
177 508 1032 3547 8103 13357 14344 15876 20386 22050 23593 35305 47409 53297 55610 56093
988 1091 1785 3400 5144 7245 10179 12918 32871 33462 34484 38318 43410 44103 44267 52837
520 564 1757 12204 16894 17249 21480 21541 23760 28325 36266 40606 46094 48779 55501 56065
914 943 1111 3641 4232 10215 14134 16582 23445 28767 28862 32260 35952 39907 41846 47553
466 554 1697 4921 6953 7034 7052 10648 11628 19174 27830 29210 31722 32281 52559 55802
1135 1273 1408 2599 3618 4903 7210 17368 21014 21287 21926 24070 27741 29801 36137 44272
524 801 1767 4093 9721 12200 19463 29280 31587 33577 39747 43688 46627 49807 51345 55969
489 1390 1756 3050 12113 20477 21376 26797 27049 28907 31534 32746 33345 40582 41970 55911
432 1520 1598 9292 11552 16985 18417 21847 21960 24287 25489 34478 40990 44004 47573 53982
301 592 849 1944 4128 8341 16783 19249 24983 43892 44041 44474 44942 44959 50738 54935
118 558 1470 4368 10132 11791 16523 22408 23766 25111 25426 25779 35005 42742 46197 53118
310 1059 1322 3609 7107 10048 13161 32141 33369 35206 36131 38746 44545 47963 48414
256 346 845 7363 10375 12492 13091 27987 32113 34846 36223 39863 44450 46526 49216
607 683 954 5473 10617 18484 20018 26971 28190 37592 39069 39740 43575 45676 48149
244 635 1208 5450 8082 25030 25149 28411 29333 31324 36972 42071 43401 47088 52085
2841 5514 16122 18061 18199 20340 22525 25022 29914 31732 46415
7567 22860 23157 24194 24622 29643 31255 32355 36379 38228 51173
24002 24459 25897 26955 31168 31630 39183 46791 47323 51503 55241
4817 8291 10219 13991 14318 28549 28836 30491 36884 46310 54625
8275 9585 11678 37216 38932 45186 46287 48023 48862 53636 56067
The receiving device/method includes a decoding unit/step for decoding the punctured LDPC code obtained from data transmitted by a transmission method as described above.

A third transmission device/method of the present technology includes an encoding unit/step for performing LDPC coding of information bits of an information length K=N×r based on an extended parity check matrix in which rows and columns of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 4/16 are each extended by a predetermined puncture length L, generating an extended LDPC code having parity bits of a parity length M=N+LK, and puncturing the beginning of the information bits of the extended LDPC code by the puncture length L to generate a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 4/16, wherein the extended parity check matrix is represented by a predetermined value M1 and the information length K=N×r. the A matrix having M1 rows and K columns is located at the top left of the extended parity check matrix, a B matrix having a staircase structure adjacent to the right of the A matrix, having M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, having M1 rows and N+LK-M1 columns, a C matrix adjacent below the A matrix and the B matrix, having N+LK-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, having N+LK-M1 rows and N+LK-M1 columns, wherein the puncture length L is 0, the predetermined value M1 is 1800, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents positions of elements of 1 of the A matrix and the C matrix for every 360 columns,
797 853 885 2412 8763 16966 18074 21725 21923 22276 32414 49532 51711
39 1096 1305 6276 13449 16227 24628 29368 31384 32207 45115 47748 51161
44 427 1193 4543 10898 29586 34143 40123 44170 46228 47353 48962 49856
541 736 844 4479 7200 16262 18160 24649 29159 42952 43829 47067 48307
95 1342 1783 9131 12031 12989 13202 14244 27356 29527 32789 36795 38709
494 1203 1652 5475 16812 21005 24490 28736 31487 37840 39565 50301 50448
1532 1581 1705 10606 12678 17526 28502 35833 44124 47833 49541 51702 51831
96 185 1188 2754 2775 5499 6292 6895 9799 27158 28509 39985 48544
749 1007 1624 9110 12545 20317 27165 31146 36658 40218 45870 48593 49397
1163 1355 1556 4652 6091 6978 8979 14330 25366 27509 27927 33954 51511
1168 1311 1320 2096 3187 5119 20693 29188 35325 36538 41740 44821 47836
288 1399 1422 10030 12443 15396 19379 26774 30623 40397 40494 47324 48652
570 809 1622 8966 13182 24760 25846 37786 38499 41477 47218 49514 51673
44 208 811 3742 8390 20577 24033 26195 29483 39222 40429 45529 45643
97 1161 1310 2693 19471 21117 24844 29355 37875 38827 42599 46927 51585
620 1416 1679 12977 15285 17224 20748 22381 25697 28626 33138 37912 39470
368 1367 1465 11725 13919 13945 33353 37326 38778 40727 40875 48487 51103
1427 1519 1736 6497 10328 15345 17776 24008 29435 47926 48682 48686 49250
23 1169 1460 5251 10379 24722 25285 32822 35089 37814 44950 45474 47146
32 681 1568 6384 9728 21530 22557 24432 31527 33435 36375 37151 39510
918 1286 1362 2738 2808 5037 7483 16549 20933 31061 33375 39562 50975
844 925 1507 8014 14804 15472 22057 31449 32226 32974 34809 41852 50676
1104 1753 1780 6605 22820 24244 26745 28587 30929 33797 34123 42029 43723
296 351 1799 9595 9770 15297 17910 19571 20521 35468 38937 48238 50795
638 760 1027 15495 15806 27803 29165 32046 34804 38592 38949 39457 47996
676 1548 1687 15931 17206 27071 28999 29312 30437 39081 44646 46366 48245
164 1436 1470 3335 8452 10611 14735 17314 17457 21853 32068 49268 51360
673 987 1570 3322 4946 6830 12027 22997 28126 30952 31702 32262 40857
773 1139 1404 9840 16019 16640 18064 24251 25181 42571 46539 50656 51750
726 730 1282 9539 10718 15690 27181 28022 29831 32767 40892 45045 51229
178 355 896 3493 13148 14855 15297 17187 20332 26479 36876 38772 41342
174 909 992 4685 6611 6649 9973 10846 18348 21866 29851 48524 51503
256 1273 1407 4650 6765 16547 19484 19834 20323 22294 27570 33457 40893
27 60 100 1530 9640 11387 12526 16343 17977 24156 29307 43317 51005
908 1009 1256 15318 24411 27373 28956 29096 37447 40401 45949 47505 50608
871 1022 1050 2987 11235 11367 14631 18902 19810 40712 41044 44083 50666
322 663 669 8710 10150 15826 17085 22493 31938 37858 40689 44018 49689
589 846 1413 2627 4519 7841 15480 24061 40839 41475 41591 46883 50613
963 1135 1395 1610 5107 10991 17300 20822 21073 23236 30712 39982 42668
729 792 1696 3391 4018 6677 15323 31211 32245 38603 39662 44737 48810
274 376 1003 8907 11493 11611 25418 25885 33368 36485 41225 44260 45485
1174 1245 1412 3510 9590 17010 20708 25956 28271 29603 33362 37097 42952
813 1030 1452 5147 9859 19468 34863 35407 36002 36716 40288 42835 44337
211 230 1694 5157 23173 23285 26293 27140 29110 34165 38861 40227 43477
537 933 1476 2748 5211 5376 14853 16889 18857 20875 22806 29035 29444
697 709 765 6009 27426 29923 33631 35433 36206 43172 47174 50955
833 1096 1648 4459 13016 22371 22757 23977 26422 28211 29254 43701
214 521 895 2147 3200 3525 3561 6699 7730 7845 9000 9570 11204 11446 11570 12462 13469 14396 15475 17540 18804 18944 19321 19550 20001 25062 25567 26342 26709 27146 27392 27428 30782 32176 32956 33240 34420 35150 35263 35879 36407 37210 37393 37420 38892 40202 40583 40665 41816 42558 42720 43063 43442 44348 44378 45052 47033 49514 49845 50084 51647
7599 9277 13898 16320 19617 28012 30567 42423 43056
15934 20819 25195 28421 31073 31750 33551 35982 37823
5377 13795 16639 20686 22150 32586 33922 40431 42255
3368 14716 15016 20925 23397 25910 28917 36663 40946
3478 4545 5802 12334 27955 29363 42818 48135 48995
The transmitting device/method is as follows.

A third receiving device/method of the present technology includes a coding step of performing LDPC coding of information bits of an information length K=N×r based on an extended parity check matrix in which rows and columns of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 4/16 are each extended by a predetermined puncture length L, generating an extended LDPC code having parity bits of a parity length M=N+LK, and puncturing a leading portion of the information bits of the extended LDPC code by the puncture length L to generate a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 4/16, wherein the extended parity check matrix is M expressed by a predetermined value M1 and the information length K=N×r. the A matrix having 1 row and K columns and located at the top left of the extended parity check matrix, a B matrix having a staircase structure and adjacent to the right of the A matrix, and having M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, and having M1 rows and N+LK-M1 columns, a C matrix adjacent below the A matrix and the B matrix, and having N+LK-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, and having N+LK-M1 rows and N+LK-M1 columns,
797 853 885 2412 8763 16966 18074 21725 21923 22276 32414 49532 51711
39 1096 1305 6276 13449 16227 24628 29368 31384 32207 45115 47748 51161
44 427 1193 4543 10898 29586 34143 40123 44170 46228 47353 48962 49856
541 736 844 4479 7200 16262 18160 24649 29159 42952 43829 47067 48307
95 1342 1783 9131 12031 12989 13202 14244 27356 29527 32789 36795 38709
494 1203 1652 5475 16812 21005 24490 28736 31487 37840 39565 50301 50448
1532 1581 1705 10606 12678 17526 28502 35833 44124 47833 49541 51702 51831
96 185 1188 2754 2775 5499 6292 6895 9799 27158 28509 39985 48544
749 1007 1624 9110 12545 20317 27165 31146 36658 40218 45870 48593 49397
1163 1355 1556 4652 6091 6978 8979 14330 25366 27509 27927 33954 51511
1168 1311 1320 2096 3187 5119 20693 29188 35325 36538 41740 44821 47836
288 1399 1422 10030 12443 15396 19379 26774 30623 40397 40494 47324 48652
570 809 1622 8966 13182 24760 25846 37786 38499 41477 47218 49514 51673
44 208 811 3742 8390 20577 24033 26195 29483 39222 40429 45529 45643
97 1161 1310 2693 19471 21117 24844 29355 37875 38827 42599 46927 51585
620 1416 1679 12977 15285 17224 20748 22381 25697 28626 33138 37912 39470
368 1367 1465 11725 13919 13945 33353 37326 38778 40727 40875 48487 51103
1427 1519 1736 6497 10328 15345 17776 24008 29435 47926 48682 48686 49250
23 1169 1460 5251 10379 24722 25285 32822 35089 37814 44950 45474 47146
32 681 1568 6384 9728 21530 22557 24432 31527 33435 36375 37151 39510
918 1286 1362 2738 2808 5037 7483 16549 20933 31061 33375 39562 50975
844 925 1507 8014 14804 15472 22057 31449 32226 32974 34809 41852 50676
1104 1753 1780 6605 22820 24244 26745 28587 30929 33797 34123 42029 43723
296 351 1799 9595 9770 15297 17910 19571 20521 35468 38937 48238 50795
638 760 1027 15495 15806 27803 29165 32046 34804 38592 38949 39457 47996
676 1548 1687 15931 17206 27071 28999 29312 30437 39081 44646 46366 48245
164 1436 1470 3335 8452 10611 14735 17314 17457 21853 32068 49268 51360
673 987 1570 3322 4946 6830 12027 22997 28126 30952 31702 32262 40857
773 1139 1404 9840 16019 16640 18064 24251 25181 42571 46539 50656 51750
726 730 1282 9539 10718 15690 27181 28022 29831 32767 40892 45045 51229
178 355 896 3493 13148 14855 15297 17187 20332 26479 36876 38772 41342
174 909 992 4685 6611 6649 9973 10846 18348 21866 29851 48524 51503
256 1273 1407 4650 6765 16547 19484 19834 20323 22294 27570 33457 40893
27 60 100 1530 9640 11387 12526 16343 17977 24156 29307 43317 51005
908 1009 1256 15318 24411 27373 28956 29096 37447 40401 45949 47505 50608
871 1022 1050 2987 11235 11367 14631 18902 19810 40712 41044 44083 50666
322 663 669 8710 10150 15826 17085 22493 31938 37858 40689 44018 49689
589 846 1413 2627 4519 7841 15480 24061 40839 41475 41591 46883 50613
963 1135 1395 1610 5107 10991 17300 20822 21073 23236 30712 39982 42668
729 792 1696 3391 4018 6677 15323 31211 32245 38603 39662 44737 48810
274 376 1003 8907 11493 11611 25418 25885 33368 36485 41225 44260 45485
1174 1245 1412 3510 9590 17010 20708 25956 28271 29603 33362 37097 42952
813 1030 1452 5147 9859 19468 34863 35407 36002 36716 40288 42835 44337
211 230 1694 5157 23173 23285 26293 27140 29110 34165 38861 40227 43477
537 933 1476 2748 5211 5376 14853 16889 18857 20875 22806 29035 29444
697 709 765 6009 27426 29923 33631 35433 36206 43172 47174 50955
833 1096 1648 4459 13016 22371 22757 23977 26422 28211 29254 43701
214 521 895 2147 3200 3525 3561 6699 7730 7845 9000 9570 11204 11446 11570 12462 13469 14396 15475 17540 18804 18944 19321 19550 20001 25062 25567 26342 26709 27146 27392 27428 30782 32176 32956 33240 34420 35150 35263 35879 36407 37210 37393 37420 38892 40202 40583 40665 41816 42558 42720 43063 43442 44348 44378 45052 47033 49514 49845 50084 51647
7599 9277 13898 16320 19617 28012 30567 42423 43056
15934 20819 25195 28421 31073 31750 33551 35982 37823
5377 13795 16639 20686 22150 32586 33922 40431 42255
3368 14716 15016 20925 23397 25910 28917 36663 40946
3478 4545 5802 12334 27955 29363 42818 48135 48995
The receiving device/method includes a decoding unit/step for decoding the punctured LDPC code obtained from data transmitted by a transmission method as described above.

A fourth transmission device/method of the present technology includes an encoding unit/step for performing LDPC coding of information bits of an information length K=N×r based on an extended parity check matrix in which rows and columns of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 5/16 are each extended by a predetermined puncture length L, generating an extended LDPC code having parity bits of a parity length M=N+LK, and puncturing a head of the information bits of the extended LDPC code by the puncture length L to generate a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 5/16, wherein the extended parity check matrix is M1 expressed by a predetermined value M1 and the information length K=N×r. a B matrix of a staircase structure adjacent to the right of the A matrix, having M1 rows and M1 columns; a Z matrix which is a zero matrix adjacent to the right of the B matrix, having M1 rows and N+LK-M1 columns; a C matrix adjacent below the A matrix and the B matrix, having N+LK-M1 rows and K+M1 columns; and a D matrix which is an identity matrix adjacent to the right of the C matrix, having N+LK-M1 rows and N+LK-M1 columns, wherein the puncture length L is 1800, the predetermined value M1 is 3600, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents positions of elements of 1 of the A matrix and the C matrix for every 360 columns,
1500 1594 4158 4611 4621 9708 14082 14260 16777 17457 21985 22308 23963 24554 25344 27485 27516 28008 30174 30625 31378 31 525 35873 36202 45585 47150 47845 49311
851 2755 5753 8521 10162 12036 16914 17857 18538 22342 24470 28199 33144 34233 35459 35506 38894 39300 41198 41995 42243 4 3310 44187 44969 46306 46719 47907 48844
803 828 7874 8667 12187 15086 16097 20436 21143 22142 27188 29052 30895 30927 30963 31563 34591 35419 36521 38142 38825 42 538 43514 44432 45634 47807 47953
3442 3596 4211 4790 5276 5379 6950 8256 10939 13398 13563 13720 18074 22070 22760 26767 27057 28054 29148 33155 33760 3850 0 42760 44861 45653 46507 48695
1337 3179 3936 4019 4207 4915 5953 6200 7596 10085 10241 15048 16788 25083 27412 27478 28623 33014 33168 33296 34087 35922 36818 38225 40169 41762 46370
230 2417 2466 10915 19279 39243 39762 42664 45750
595 1792 2788 16000 19698 28701 38882 45250 46449
764 1619 2243 10130 25528 38421 44789 45032 48064
779 1651 3431 4707 8887 24180 36687 37770 39583
136 1352 3105 9580 25493 28929 29003 43731 44941
0 2147 3434 4402 19742 21221 37419 46590 49082
1658 1953 2935 17606 21613 29311 33878 46163 47126
804 1362 2596 15920 25368 28032 32218 37251 38385
733 3180 3549 12710 14684 32429 36039 39164 47531
807 2668 2811 23227 39984 42091 45708 46426 47788
1142 3373 3414 4219 7793 11379 15389 28832 32362
246 2670 3141 11465 24513 25038 31936 36501 45021
1365 2399 3107 4460 24713 30758 32422 38041 43379
323 578 1392 22591 26966 35332 35884 36454 38254
24 78 229 8741 17149 21008 30309 32441 38141
587 1595 3531 9258 15476 30673 33744 41847 44930
980 2136 2883 18306 22032 31618 33154 45208 48127
1518 1796 2304 7939 24330 29552 33426 39907 41568
599 681 3597 10689 10811 19776 20651 34661 46473
970 1152 2675 13311 15762 16363 26575 37047 48249
1872 1968 2620 16207 31197 33577 37990 42868 45881
1105 1351 3374 28454 28667 37692 42083 46115
1019 1816 3153 7354 14190 15535 29787 40081
114 1127 3412 17706 21953 31166 48855 49247
411 1346 2860 6474 12912 28627 30225 31396
109 1895 2803 8192 22957 30924 32515 39258
1067 1547 3218 10928 18459 24102 24958 48228
1022 2939 3593 16210 20143 22128 36148 48748
1826 2281 3110 10706 11745 27544 29705 32385
165 1794 3038 13953 15929 20587 35639 37360
122 1107 1776 7992 15442 26707 28761 39718
344 1449 2018 7930 11023 11967 18210 48998
203 2541 3360 6249 8145 10115 16796 19830 39389 39409
1333 1476 1855 4261 5127 16893 20060 23938 25433 32522
1972 3154 3539 10244 10601 12317 18404 29191 35539 41261
1621 1817 3280 15943 26444 28455 28595 29822 38852 48190
2048 2565 2660 4707 12386 15311 19315 20091 24908 37754
2825 3043 3516 9940 11806 11981 20375 20597 22471 31060
2597 2792 3444 11226 16387 17531 18473 25142 39461 42139
439 2788 3511 3684 5549 16067 23077 39829 39920 44862
1076 2271 2797 6573 12043 17816 20967 21726 23200 38056
553 2080 2948 5535 16026 22119 23794 37157 46602 46720
112 2115 3084 8090 10494 13165 29078 31417 33314 39595
2275 2449 3058 10121 12474 12563 25072 25610 39483 43489
741 2186 2270 5146 10831 17517 20875 29107 35695 41244
1693 1902 2907 6756 10924 18965 24040 33793 41089 42464
2469 2514 2769 6664 8813 8938 19741 23113 34293 45892
1761 2326 2998 17255 23220 26747 28416 37450 38574 41110
1083 1375 1867 4468 6706 6899 15494 19170 28463 28858
1394 1412 1510 7439 27005 29288 32683 34307 34607 45091
2477 2978 3539 22378 23848 24738 28734 31460 41873 45398
191 803 1500 9030 14071 26093 26432 27827 35890 47458
556 2942 3114 10130 11981 33368 34732 42472 47188 47655
425 2875 2946 16084 19184 26801 27069 27090 31317 34103
121 1674 3258 5208 13340 26019 37492 38723 40779 49200
3968 7741 12550 32061
17972 19666 20231 33590
9086 34375 41691 42567
12168 14189 15095 49129
19291 26450 29950 39068
19852 25195 35124 36192
10447 32405 36184 40786
8911 19949 27496 41273
14679 16883 20951 29727
30296 32681 34757 36501
The transmitting device/method is as follows.

A fourth receiving apparatus/method of the present technology includes a coding step of performing LDPC coding of information bits of an information length K=N×r based on an extended parity check matrix in which rows and columns of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 5/16 are each extended by a predetermined puncture length L, generating an extended LDPC code having parity bits of a parity length M=N+LK, and puncturing a head of the information bits of the extended LDPC code by the puncture length L to generate a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 5/16, wherein the extended parity check matrix has M1 rows represented by a predetermined value M1 and the information length K=N×r. the A matrix having K columns and located at the top left of the extended parity check matrix, a B matrix having a staircase structure adjacent to the right of the A matrix, having M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, having M1 rows and N+LK-M1 columns, a C matrix adjacent below the A matrix and the B matrix, having N+LK-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, having N+LK-M1 rows and N+LK-M1 columns, wherein the puncture length L is 1800, the predetermined value M1 is 3600, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents positions of elements of 1 of the A matrix and the C matrix for every 360 columns,
1500 1594 4158 4611 4621 9708 14082 14260 16777 17457 21985 22308 23963 24554 25344 27485 27516 28008 30174 30625 31378 31 525 35873 36202 45585 47150 47845 49311
851 2755 5753 8521 10162 12036 16914 17857 18538 22342 24470 28199 33144 34233 35459 35506 38894 39300 41198 41995 42243 4 3310 44187 44969 46306 46719 47907 48844
803 828 7874 8667 12187 15086 16097 20436 21143 22142 27188 29052 30895 30927 30963 31563 34591 35419 36521 38142 38825 42 538 43514 44432 45634 47807 47953
3442 3596 4211 4790 5276 5379 6950 8256 10939 13398 13563 13720 18074 22070 22760 26767 27057 28054 29148 33155 33760 3850 0 42760 44861 45653 46507 48695
1337 3179 3936 4019 4207 4915 5953 6200 7596 10085 10241 15048 16788 25083 27412 27478 28623 33014 33168 33296 34087 35922 36818 38225 40169 41762 46370
230 2417 2466 10915 19279 39243 39762 42664 45750
595 1792 2788 16000 19698 28701 38882 45250 46449
764 1619 2243 10130 25528 38421 44789 45032 48064
779 1651 3431 4707 8887 24180 36687 37770 39583
136 1352 3105 9580 25493 28929 29003 43731 44941
0 2147 3434 4402 19742 21221 37419 46590 49082
1658 1953 2935 17606 21613 29311 33878 46163 47126
804 1362 2596 15920 25368 28032 32218 37251 38385
733 3180 3549 12710 14684 32429 36039 39164 47531
807 2668 2811 23227 39984 42091 45708 46426 47788
1142 3373 3414 4219 7793 11379 15389 28832 32362
246 2670 3141 11465 24513 25038 31936 36501 45021
1365 2399 3107 4460 24713 30758 32422 38041 43379
323 578 1392 22591 26966 35332 35884 36454 38254
24 78 229 8741 17149 21008 30309 32441 38141
587 1595 3531 9258 15476 30673 33744 41847 44930
980 2136 2883 18306 22032 31618 33154 45208 48127
1518 1796 2304 7939 24330 29552 33426 39907 41568
599 681 3597 10689 10811 19776 20651 34661 46473
970 1152 2675 13311 15762 16363 26575 37047 48249
1872 1968 2620 16207 31197 33577 37990 42868 45881
1105 1351 3374 28454 28667 37692 42083 46115
1019 1816 3153 7354 14190 15535 29787 40081
114 1127 3412 17706 21953 31166 48855 49247
411 1346 2860 6474 12912 28627 30225 31396
109 1895 2803 8192 22957 30924 32515 39258
1067 1547 3218 10928 18459 24102 24958 48228
1022 2939 3593 16210 20143 22128 36148 48748
1826 2281 3110 10706 11745 27544 29705 32385
165 1794 3038 13953 15929 20587 35639 37360
122 1107 1776 7992 15442 26707 28761 39718
344 1449 2018 7930 11023 11967 18210 48998
203 2541 3360 6249 8145 10115 16796 19830 39389 39409
1333 1476 1855 4261 5127 16893 20060 23938 25433 32522
1972 3154 3539 10244 10601 12317 18404 29191 35539 41261
1621 1817 3280 15943 26444 28455 28595 29822 38852 48190
2048 2565 2660 4707 12386 15311 19315 20091 24908 37754
2825 3043 3516 9940 11806 11981 20375 20597 22471 31060
2597 2792 3444 11226 16387 17531 18473 25142 39461 42139
439 2788 3511 3684 5549 16067 23077 39829 39920 44862
1076 2271 2797 6573 12043 17816 20967 21726 23200 38056
553 2080 2948 5535 16026 22119 23794 37157 46602 46720
112 2115 3084 8090 10494 13165 29078 31417 33314 39595
2275 2449 3058 10121 12474 12563 25072 25610 39483 43489
741 2186 2270 5146 10831 17517 20875 29107 35695 41244
1693 1902 2907 6756 10924 18965 24040 33793 41089 42464
2469 2514 2769 6664 8813 8938 19741 23113 34293 45892
1761 2326 2998 17255 23220 26747 28416 37450 38574 41110
1083 1375 1867 4468 6706 6899 15494 19170 28463 28858
1394 1412 1510 7439 27005 29288 32683 34307 34607 45091
2477 2978 3539 22378 23848 24738 28734 31460 41873 45398
191 803 1500 9030 14071 26093 26432 27827 35890 47458
556 2942 3114 10130 11981 33368 34732 42472 47188 47655
425 2875 2946 16084 19184 26801 27069 27090 31317 34103
121 1674 3258 5208 13340 26019 37492 38723 40779 49200
3968 7741 12550 32061
17972 19666 20231 33590
9086 34375 41691 42567
12168 14189 15095 49129
19291 26450 29950 39068
19852 25195 35124 36192
10447 32405 36184 40786
8911 19949 27496 41273
14679 16883 20951 29727
30296 32681 34757 36501
The receiving device/method includes a decoding unit/step for decoding the punctured LDPC code obtained from data transmitted by a transmission method.

A fifth transmission device/method of the present technology includes an encoding unit/step for performing LDPC coding of information bits of an information length K=N×r based on an extended parity check matrix in which rows and columns of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 6/16 are each extended by a predetermined puncture length L, generating an extended LDPC code having parity bits of a parity length M=N+LK, and puncturing a leading portion of the information bits of the extended LDPC code by the puncture length L to generate a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 6/16, wherein the extended parity check matrix is M1 expressed by a predetermined value M1 and the information length K=N×r. a B matrix of a staircase structure adjacent to the right of the A matrix, having M1 rows and M1 columns; a Z matrix which is a zero matrix adjacent to the right of the B matrix, having M1 rows and N+LK-M1 columns; a C matrix adjacent below the A matrix and the B matrix, having N+LK-M1 rows and K+M1 columns; and a D matrix which is an identity matrix adjacent to the right of the C matrix, having N+LK-M1 rows and N+LK-M1 columns, wherein the puncture length L is 1800, the predetermined value M1 is 3600, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents positions of elements of 1 of the A matrix and the C matrix for every 360 columns,
1594 1610 4443 4633 4971 5913 7301 7706 13474 16147 16681 17638 20084 20205 20247 20540 22484 27085 28185 29116 31096 3306 8 41272 41610 43034
1883 2386 4525 5861 6762 8505 10987 11467 13389 15284 15934 22445 22893 24837 26162 26697 29883 30925 35299 38596 38645 41 614 42730 43699 44169
1048 1205 7615 12049 12746 13032 13602 14263 14911 15606 21519 26057 26528 28217 28266 29323 31302 32457 32579 34903 35105 36007 40006 43828 44649
1621 1937 3806 4192 4345 4436 4464 5013 7744 9969 10235 10276 10910 12816 16020 17524 20323 30904 31663 35163 35398 35957 39093 42657 44993
49 1822 3711 3892 4990 10239 12492 18990 19520 21406 24318 24612 25751 26767 30148 31680 32384 33296 34983 35934 38715 402 86 42291 42485 42998
220 302 3574 5681 9506 24907 31216 34098 36706
26 88 1979 6254 17793 31399 31963 38968 41759
571 2797 2843 10391 18284 24224 26323 35575 43222
2778 2865 3374 13146 22196 23479 29472 40894 43961
513 2641 3267 12546 22339 22592 33324 37388 43058
89 416 2750 8737 9111 19495 26529 35507 39319
1522 1795 3155 3952 19544 28293 40910 43137 44782
68 1271 2663 22635 26043 31010 37397 42214 42940
1102 1410 2026 14095 14851 19343 23303 25716 33443
2257 2649 2734 13712 40173 42230 42240 43221 44414
714 2565 2880 4450 12908 34192 35997 36455 40728
1546 3319 3372 7492 10636 16725 26425 42426 42880
41 927 2263 6416 10637 22272 29323 34364 39763
1681 2598 3263 4337 19277 28170 31112 39274 39685
1624 2266 2712 7713 10204 19680 20781 32234 32824
1839 2578 2725 4403 4475 6187 8251 15794 34791
1372 2107 2310 8695 10370 22033 31001 38223 44215
1045 2138 3259 14898 16935 20360 28114 30232 36792
2326 3271 3510 21052 22158 24249 25709 30136 35176
347 2043 2984 10440 10461 11558 18257 42040 44932
562 1425 2428 12400 14792 16918 24373 34372 44049
959 1004 2630 14983 26147 28239 28571 33730 34758
2366 3093 3321 16340 19265 26290 28817 42082 42430
1812 2687 3030 7047 13181 15320 27308 36719 39868
118 933 1127 16601 20206 28560 42837 44651 44924
411 1346 2869 4816 6186 12098 26338 28747 28842
1985 2151 2804 7754 21167 21405 29764 35907 40584
1067 1689 3513 10225 15350 17157 22215 37316 44909
1306 1452 2564 15049 24636 29181 29918 39466 44466
558 640 2085 5522 9131 12991 24658 28599 38510
971 1333 2524 5076 14312 16292 23989 28218 37668
345 1819 2012 7598 7602 10348 11079 16828 20223
206 3490 3577 7652 9484 15485 18215 32891 36012
207 2085 2818 4223 4981 18437 18907 20797 29779
1043 1602 1711 17049 26349 37701 37805 39929 44226
528 686 2519 22288 24424 26040 27266 35523 44395
974 2063 3540 23885 24211 26226 27093 33120 34243
84 689 1292 14234 17834 34458 36109 38609 44075
656 1321 1335 9564 11031 20663 28540 33454
2798 3040 3447 10523 15178 16147 17112 23143
2785 2827 3514 3648 5406 8631 21247 36454
983 2859 3241 6313 15981 16459 29725 35759
662 1428 2716 9984 19352 21403 27521 37417
1460 1582 3397 5327 14857 27868 34040 42479
116 353 3081 9834 12252 26703 28884 30421
2275 2449 2838 9493 11608 23271 38776 39806
704 1750 2835 10462 12221 28740 29710 37673
121 2008 2529 16240 19331 23089 25481 36984
1207 1650 2956 6464 10252 30913 31894 38888
1272 2513 2764 6370 8377 8517 31368 41960
1538 1761 2999 21345 26055 30346 34230 35254
1125 1822 2953 6588 14341 16087 19369 25097
60 246 1224 19668 19837 21037 26085 26484
2023 2447 3295 7065 24779 29935 31328 32089
2977 3291 3536 20569 22895 26291 28856 38257
198 1500 1594 8474 12821 24065 24273 25489
829 2542 3457 9560 9981 11130 37448 39505
2452 3433 3465 8505 30616 36656 37451 38882
1828 2189 2401 5065 14917 17648 24809 24869
1674 1760 3256 5017 12401 34198 35372 44967
329 2242 2945 3841 11713 18179 18567 30756
1134 2993 3068 8595 13252 14014 31475 44841
671 1250 2076 18266 23182 24268 32218 33106 33153 35797
532 2267 2927 8343 13630 15565 18426 25262 27191 37728
1363 2100 2454 15244 19187 23000 25655 28410 29916 33402
251 1469 2315 13593 15859 19414 26073 29034 35496 37152
112 1736 2508 5876 14259 14532 21456 35968 37533 42515
25233 26394
5080 6930
12302 41997
27483 36076
5116 36815
11841 28243
18326 37978
22431 36141
35950 40525
41824 42674
The transmitting device/method is as follows.

A fifth receiving device/method of the present technology includes a coding step of performing LDPC coding of information bits of an information length K=N×r based on an extended parity check matrix in which rows and columns of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 6/16 are each extended by a predetermined puncture length L, generating an extended LDPC code having parity bits of a parity length M=N+LK, and puncturing a head of the information bits of the extended LDPC code by the puncture length L to generate a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 6/16, wherein the extended parity check matrix has M1 rows represented by a predetermined value M1 and the information length K=N×r. the A matrix having K columns and located at the top left of the extended parity check matrix, a B matrix having a staircase structure adjacent to the right of the A matrix, having M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, having M1 rows and N+LK-M1 columns, a C matrix adjacent below the A matrix and the B matrix, having N+LK-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, having N+LK-M1 rows and N+LK-M1 columns, wherein the puncture length L is 1800, the predetermined value M1 is 3600, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents positions of elements of 1 of the A matrix and the C matrix for every 360 columns,
1594 1610 4443 4633 4971 5913 7301 7706 13474 16147 16681 17638 20084 20205 20247 20540 22484 27085 28185 29116 31096 3306 8 41272 41610 43034
1883 2386 4525 5861 6762 8505 10987 11467 13389 15284 15934 22445 22893 24837 26162 26697 29883 30925 35299 38596 38645 41 614 42730 43699 44169
1048 1205 7615 12049 12746 13032 13602 14263 14911 15606 21519 26057 26528 28217 28266 29323 31302 32457 32579 34903 35105 36007 40006 43828 44649
1621 1937 3806 4192 4345 4436 4464 5013 7744 9969 10235 10276 10910 12816 16020 17524 20323 30904 31663 35163 35398 35957 39093 42657 44993
49 1822 3711 3892 4990 10239 12492 18990 19520 21406 24318 24612 25751 26767 30148 31680 32384 33296 34983 35934 38715 402 86 42291 42485 42998
220 302 3574 5681 9506 24907 31216 34098 36706
26 88 1979 6254 17793 31399 31963 38968 41759
571 2797 2843 10391 18284 24224 26323 35575 43222
2778 2865 3374 13146 22196 23479 29472 40894 43961
513 2641 3267 12546 22339 22592 33324 37388 43058
89 416 2750 8737 9111 19495 26529 35507 39319
1522 1795 3155 3952 19544 28293 40910 43137 44782
68 1271 2663 22635 26043 31010 37397 42214 42940
1102 1410 2026 14095 14851 19343 23303 25716 33443
2257 2649 2734 13712 40173 42230 42240 43221 44414
714 2565 2880 4450 12908 34192 35997 36455 40728
1546 3319 3372 7492 10636 16725 26425 42426 42880
41 927 2263 6416 10637 22272 29323 34364 39763
1681 2598 3263 4337 19277 28170 31112 39274 39685
1624 2266 2712 7713 10204 19680 20781 32234 32824
1839 2578 2725 4403 4475 6187 8251 15794 34791
1372 2107 2310 8695 10370 22033 31001 38223 44215
1045 2138 3259 14898 16935 20360 28114 30232 36792
2326 3271 3510 21052 22158 24249 25709 30136 35176
347 2043 2984 10440 10461 11558 18257 42040 44932
562 1425 2428 12400 14792 16918 24373 34372 44049
959 1004 2630 14983 26147 28239 28571 33730 34758
2366 3093 3321 16340 19265 26290 28817 42082 42430
1812 2687 3030 7047 13181 15320 27308 36719 39868
118 933 1127 16601 20206 28560 42837 44651 44924
411 1346 2869 4816 6186 12098 26338 28747 28842
1985 2151 2804 7754 21167 21405 29764 35907 40584
1067 1689 3513 10225 15350 17157 22215 37316 44909
1306 1452 2564 15049 24636 29181 29918 39466 44466
558 640 2085 5522 9131 12991 24658 28599 38510
971 1333 2524 5076 14312 16292 23989 28218 37668
345 1819 2012 7598 7602 10348 11079 16828 20223
206 3490 3577 7652 9484 15485 18215 32891 36012
207 2085 2818 4223 4981 18437 18907 20797 29779
1043 1602 1711 17049 26349 37701 37805 39929 44226
528 686 2519 22288 24424 26040 27266 35523 44395
974 2063 3540 23885 24211 26226 27093 33120 34243
84 689 1292 14234 17834 34458 36109 38609 44075
656 1321 1335 9564 11031 20663 28540 33454
2798 3040 3447 10523 15178 16147 17112 23143
2785 2827 3514 3648 5406 8631 21247 36454
983 2859 3241 6313 15981 16459 29725 35759
662 1428 2716 9984 19352 21403 27521 37417
1460 1582 3397 5327 14857 27868 34040 42479
116 353 3081 9834 12252 26703 28884 30421
2275 2449 2838 9493 11608 23271 38776 39806
704 1750 2835 10462 12221 28740 29710 37673
121 2008 2529 16240 19331 23089 25481 36984
1207 1650 2956 6464 10252 30913 31894 38888
1272 2513 2764 6370 8377 8517 31368 41960
1538 1761 2999 21345 26055 30346 34230 35254
1125 1822 2953 6588 14341 16087 19369 25097
60 246 1224 19668 19837 21037 26085 26484
2023 2447 3295 7065 24779 29935 31328 32089
2977 3291 3536 20569 22895 26291 28856 38257
198 1500 1594 8474 12821 24065 24273 25489
829 2542 3457 9560 9981 11130 37448 39505
2452 3433 3465 8505 30616 36656 37451 38882
1828 2189 2401 5065 14917 17648 24809 24869
1674 1760 3256 5017 12401 34198 35372 44967
329 2242 2945 3841 11713 18179 18567 30756
1134 2993 3068 8595 13252 14014 31475 44841
671 1250 2076 18266 23182 24268 32218 33106 33153 35797
532 2267 2927 8343 13630 15565 18426 25262 27191 37728
1363 2100 2454 15244 19187 23000 25655 28410 29916 33402
251 1469 2315 13593 15859 19414 26073 29034 35496 37152
112 1736 2508 5876 14259 14532 21456 35968 37533 42515
25233 26394
5080 6930
12302 41997
27483 36076
5116 36815
11841 28243
18326 37978
22431 36141
35950 40525
41824 42674
The receiving device/method includes a decoding unit/step for decoding the punctured LDPC code obtained from data transmitted by a transmission method as described above.

A sixth transmission device/method of the present technology includes an encoding unit/step for performing LDPC coding of information bits of an information length K=N×r based on an extended parity check matrix in which rows and columns of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 7/16 are each extended by a predetermined puncture length L, generating an extended LDPC code having parity bits of a parity length M=N+LK, and puncturing a head of the information bits of the extended LDPC code by the puncture length L to generate a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 7/16, wherein the extended parity check matrix is M1 expressed by a predetermined value M1 and the information length K=N×r. a B matrix of a staircase structure adjacent to the right of the A matrix, having M1 rows and M1 columns; a Z matrix which is a zero matrix adjacent to the right of the B matrix, having M1 rows and N+LK-M1 columns; a C matrix adjacent below the A matrix and the B matrix, having N+LK-M1 rows and K+M1 columns; and a D matrix which is an identity matrix adjacent to the right of the C matrix, having N+LK-M1 rows and N+LK-M1 columns, wherein the puncture length L is 2160 and the predetermined value M1 is 3960, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents positions of elements of 1 of the A matrix and the C matrix for every 360 columns,
1764 2277 5400 7275 7702 16018 16086 17361 18724 18869 19132 20243 21595 25512 26606 30134 36052 39329 41031
181 1916 4788 5993 10696 12604 13012 24557 24787 25876 26693 28545 32349 33375 35357 36872 37706 38697 40205
1627 3867 5245 5631 6206 7958 12408 14675 15078 16069 20924 24234 29887 31630 32133 34527 34618 35147 37843
1103 2230 7388 9550 10439 11627 13165 14144 18256 22833 26008 26531 28108 28741 29963 31479 31923 39255 39995
1285 2355 4577 6689 10485 12036 16455 18963 19252 23741 30895 31196 35315 36358 36604 38535 39352 40937 40994
3065 4434 5307 7286 7705 9549 9848 11017 11901 12627 17746 21303 23749 24143 25301 25977 32801 37365 38172
434 2357 3026 7873 22006 27928 31085 34076
1003 2078 2558 6023 7076 9453 23248 40783
275 2594 2879 4212 4816 24471 29358 33606
304 2655 3449 9926 16670 32754 33277 38132
657 1983 3058 14006 17331 24307 37692 38764
865 1808 3134 21758 27257 31888 37426 40019
562 1861 3800 12068 20650 30577 33391 39300
97 459 2970 5360 8808 17885 24492 36388
1655 1901 3486 3965 18266 21707 26083 39858
106 2971 3601 4603 17049 21044 24058 34168
105 2632 3687 12222 15389 17985 18580 24844
1067 1887 3012 11816 23805 27159 31152 32102
412 3506 3688 11340 12998 28025 30295 32802
884 2933 3112 19905 33377 35257 38730 39998
3709 3756 3774 7360 10333 13454 15712 24711
58 2494 2959 6474 10296 20685 26935 36360
1854 2850 3654 4678 18001 28593 35963 36270
1830 2363 2518 7949 10035 18345 29534 31920
1646 2020 2811 4203 4779 6289 30475 32063
465 1178 2986 18151 20386 25654 27386 40357
640 2615 3354 8542 14478 25967 25995 37471
1082 1285 3179 18952 26721 27915 37670 40010
1737 1976 2546 7547 20613 23824 25055 32654
741 1013 3328 9668 9749 17082 38386 40974
1268 1476 2671 11835 14049 22600 31513 40179
1045 1108 2992 14156 23244 24154 31043 31798
2421 2602 3798 15389 17884 24140 35871 38752
819 2169 2955 14408 22625 25191 35170 36437
334 922 3167 5119 13570 15530 39099 41014
1221 1589 2395 8195 17835 24255 33626 40708
860 2308 2450 5038 6315 23489 26114 32851
406 1679 3105 14968 19909 27383 37072 40206
633 1863 1959 14480 16090 18913 34193 41012
1488 1699 2837 14716 22731 26859 27454 35998
700 1266 2120 5664 24568 24724 31262 35236
900 1067 2778 5274 15361 17755 22211 33252
1025 2008 2182 7489 7536 15899 18803 24702
383 648 716 5156 6037 9277 30214 38571
389 1155 2887 6102 17079 19192 23080 32918
1471 1635 2511 4547 5272 14725 20498 21659
2171 3539 3896 9346 9694 10999 15963 34494
1994 2216 2771 20692 24115 32560 37794 40140
1080 2162 2696 21197 22485 25015 30419 31363
97 755 1419 13499 16636 31603 35313 40181
1469 1655 3110 9088 10592 17584 19236 26283
2952 3076 3849 10157 14317 15196 16053 35195
1861 3105 3862 3994 5564 6074 8451 19756
3145 3155 3597 14101 15059 15459 27355 32750
259 873 3006 18016 18676 19887 25385 34337
613 1595 3868 5572 14023 20249 31223 38780
200 3129 3397 7639 9614 11741 26530 28039
2223 2694 3117 9231 11140 21370 27439 35476
779 1905 3630 11778 26510 27390 33035 34468
137 624 2206 15239 18045 21398 23580 29951
1327 1763 3312 6477 9861 28455 34353 35567
2717 2763 3044 8185 8380 17045 28844 38259
265 1105 3295 22148 24070 27939 31377 32371
1785 2042 3249 6558 15036 15184 18135 23151
271 1032 1352 4622 18315 19571 24142 24376
2392 2686 3656 7062 22999 24868 27626 28882
2726 3295 3893 19111 21109 26599 35039 37863
1650 1757 2170 5928 12800 22404 22521 23554
474 912 2810 9299 9649 34316 36020 39568
721 3776 3815 8297 28150 29224 33574 35496
2009 2400 3282 14124 16587 22933 22980 28722
132 1845 3587 11790 22121 31459 32442 40951
142 361 1061 4265 11230 16948 17367 27128
1250 2600 3374 8456 12596 28890 34813 40879
738 1025 1617 17079 22449 25340 30369 32737
1876 2731 2841 9438 17215 23350 27295 34083
453 1144 3263 12936 18049 25084 25595 29278
2369 2850 2997 6628 14441 17901 21329 23717
1671 2580 3055 12903 14917 24143 26800 33983
1516 1907 2756 5106 13479 13748 32931
1708 3245 3727
216 2078 2179
137 316 3665
834 2278 3108
5345 33686
11281 26022
17244 34746
20829 33069
32952 37029
38235 38952
12779 36842
5081 34190
8352 9285
37937 39131
21873 26915
The transmitting device/method is as follows.

A sixth receiving device/method of the present technology includes a coding step of performing LDPC coding of information bits of an information length K=N×r based on an extended parity check matrix in which rows and columns of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 7/16 are each extended by a predetermined puncture length L, generating an extended LDPC code having parity bits of a parity length M=N+LK, and puncturing a head of the information bits of the extended LDPC code by the puncture length L to generate a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 7/16, wherein the extended parity check matrix has M1 rows represented by a predetermined value M1 and the information length K=N×r. the A matrix having K columns and located at the top left of the extended parity check matrix, a B matrix having a staircase structure adjacent to the right of the A matrix, having M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, having M1 rows and N+LK-M1 columns, a C matrix adjacent below the A matrix and the B matrix, having N+LK-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, having N+LK-M1 rows and N+LK-M1 columns, wherein the puncture length L is 2160 and the predetermined value M1 is 3960, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents positions of elements of 1 of the A matrix and the C matrix for every 360 columns,
1764 2277 5400 7275 7702 16018 16086 17361 18724 18869 19132 20243 21595 25512 26606 30134 36052 39329 41031
181 1916 4788 5993 10696 12604 13012 24557 24787 25876 26693 28545 32349 33375 35357 36872 37706 38697 40205
1627 3867 5245 5631 6206 7958 12408 14675 15078 16069 20924 24234 29887 31630 32133 34527 34618 35147 37843
1103 2230 7388 9550 10439 11627 13165 14144 18256 22833 26008 26531 28108 28741 29963 31479 31923 39255 39995
1285 2355 4577 6689 10485 12036 16455 18963 19252 23741 30895 31196 35315 36358 36604 38535 39352 40937 40994
3065 4434 5307 7286 7705 9549 9848 11017 11901 12627 17746 21303 23749 24143 25301 25977 32801 37365 38172
434 2357 3026 7873 22006 27928 31085 34076
1003 2078 2558 6023 7076 9453 23248 40783
275 2594 2879 4212 4816 24471 29358 33606
304 2655 3449 9926 16670 32754 33277 38132
657 1983 3058 14006 17331 24307 37692 38764
865 1808 3134 21758 27257 31888 37426 40019
562 1861 3800 12068 20650 30577 33391 39300
97 459 2970 5360 8808 17885 24492 36388
1655 1901 3486 3965 18266 21707 26083 39858
106 2971 3601 4603 17049 21044 24058 34168
105 2632 3687 12222 15389 17985 18580 24844
1067 1887 3012 11816 23805 27159 31152 32102
412 3506 3688 11340 12998 28025 30295 32802
884 2933 3112 19905 33377 35257 38730 39998
3709 3756 3774 7360 10333 13454 15712 24711
58 2494 2959 6474 10296 20685 26935 36360
1854 2850 3654 4678 18001 28593 35963 36270
1830 2363 2518 7949 10035 18345 29534 31920
1646 2020 2811 4203 4779 6289 30475 32063
465 1178 2986 18151 20386 25654 27386 40357
640 2615 3354 8542 14478 25967 25995 37471
1082 1285 3179 18952 26721 27915 37670 40010
1737 1976 2546 7547 20613 23824 25055 32654
741 1013 3328 9668 9749 17082 38386 40974
1268 1476 2671 11835 14049 22600 31513 40179
1045 1108 2992 14156 23244 24154 31043 31798
2421 2602 3798 15389 17884 24140 35871 38752
819 2169 2955 14408 22625 25191 35170 36437
334 922 3167 5119 13570 15530 39099 41014
1221 1589 2395 8195 17835 24255 33626 40708
860 2308 2450 5038 6315 23489 26114 32851
406 1679 3105 14968 19909 27383 37072 40206
633 1863 1959 14480 16090 18913 34193 41012
1488 1699 2837 14716 22731 26859 27454 35998
700 1266 2120 5664 24568 24724 31262 35236
900 1067 2778 5274 15361 17755 22211 33252
1025 2008 2182 7489 7536 15899 18803 24702
383 648 716 5156 6037 9277 30214 38571
389 1155 2887 6102 17079 19192 23080 32918
1471 1635 2511 4547 5272 14725 20498 21659
2171 3539 3896 9346 9694 10999 15963 34494
1994 2216 2771 20692 24115 32560 37794 40140
1080 2162 2696 21197 22485 25015 30419 31363
97 755 1419 13499 16636 31603 35313 40181
1469 1655 3110 9088 10592 17584 19236 26283
2952 3076 3849 10157 14317 15196 16053 35195
1861 3105 3862 3994 5564 6074 8451 19756
3145 3155 3597 14101 15059 15459 27355 32750
259 873 3006 18016 18676 19887 25385 34337
613 1595 3868 5572 14023 20249 31223 38780
200 3129 3397 7639 9614 11741 26530 28039
2223 2694 3117 9231 11140 21370 27439 35476
779 1905 3630 11778 26510 27390 33035 34468
137 624 2206 15239 18045 21398 23580 29951
1327 1763 3312 6477 9861 28455 34353 35567
2717 2763 3044 8185 8380 17045 28844 38259
265 1105 3295 22148 24070 27939 31377 32371
1785 2042 3249 6558 15036 15184 18135 23151
271 1032 1352 4622 18315 19571 24142 24376
2392 2686 3656 7062 22999 24868 27626 28882
2726 3295 3893 19111 21109 26599 35039 37863
1650 1757 2170 5928 12800 22404 22521 23554
474 912 2810 9299 9649 34316 36020 39568
721 3776 3815 8297 28150 29224 33574 35496
2009 2400 3282 14124 16587 22933 22980 28722
132 1845 3587 11790 22121 31459 32442 40951
142 361 1061 4265 11230 16948 17367 27128
1250 2600 3374 8456 12596 28890 34813 40879
738 1025 1617 17079 22449 25340 30369 32737
1876 2731 2841 9438 17215 23350 27295 34083
453 1144 3263 12936 18049 25084 25595 29278
2369 2850 2997 6628 14441 17901 21329 23717
1671 2580 3055 12903 14917 24143 26800 33983
1516 1907 2756 5106 13479 13748 32931
1708 3245 3727
216 2078 2179
137 316 3665
834 2278 3108
5345 33686
11281 26022
17244 34746
20829 33069
32952 37029
38235 38952
12779 36842
5081 34190
8352 9285
37937 39131
21873 26915
The receiving device/method includes a decoding unit/step for decoding the punctured LDPC code obtained from data transmitted by a transmission method as described above.

A seventh transmission device/method of the present technology includes an encoding unit/step for performing LDPC coding of information bits of an information length K=N×r based on an extended parity check matrix in which rows and columns of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 8/16 are each extended by a predetermined puncture length L, generating an extended LDPC code having parity bits of a parity length M=N+LK, and puncturing a leading portion of the information bits of the extended LDPC code by the puncture length L to generate a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 8/16, wherein the extended parity check matrix is M1 expressed by a predetermined value M1 and the information length K=N×r. a B matrix of a staircase structure adjacent to the right of the A matrix, having M1 rows and M1 columns; a Z matrix which is a zero matrix adjacent to the right of the B matrix, having M1 rows and N+LK-M1 columns; a C matrix adjacent below the A matrix and the B matrix, having N+LK-M1 rows and K+M1 columns; and a D matrix which is an identity matrix adjacent to the right of the C matrix, having N+LK-M1 rows and N+LK-M1 columns, wherein the puncture length L is 2520 and the predetermined value M1 is 5040, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents positions of elements of 1 of the A matrix and the C matrix for every 360 columns,
2184 2245 5483 5692 9320 18011 18064 18150 20189 23469 23662 25407 28189 35779 37071
1855 3613 5755 7904 12491 14272 19654 22065 22316 23975 24503 26458 29567 34455 35556
928 4740 6537 8736 9455 16185 18167 22537 22768 26005 32031 32179 33566 34966 35808
3986 4696 5295 8034 12188 12339 14298 19661 22499 22837 28343 29201 30056 36868 36872
1049 2606 9166 13000 17407 22535 24035 24090 26423 27147 28104 29196 34765 36183 36195
2475 2705 6586 10659 14652 15858 18555 22635 25610 26796 32144 33131 35581 37072
1339 1594 5556 5731 5735 7423 7924 8287 10173 21406 26174 26965 30831 35028
2095 2692 4542 11957 16923 21339 22995 35510
753 3913 4481 24115 25745 28475 29334 34983
531 2404 4091 6823 7730 13085 21741 25943
764 2602 5000 5777 6649 28284 28457 30648
173 2884 3453 7716 16017 26720 33781 34558
804 3989 4026 10353 16302 20995 22614 29946
1369 1438 4721 11804 19454 24989 29745 33895
2413 3865 4900 9605 12227 19796 34068 35639
2280 3614 3994 5794 8725 17288 29042 32667
189 729 2807 18569 20422 29775 33106 35601
13 1942 3075 5647 16437 28792 33944 36951
2322 2774 4133 14911 23058 26276 35482 36145
1156 1915 1988 13753 20275 22750 28129 28615
1027 3254 3826 12792 25306 33398 34900 36579
1000 3662 3934 12247 28784 30051 30448 34971
2208 4777 4895 7995 15270 34546 35050 35465
865 1301 2776 5447 7236 25204 28825 33009
931 2280 3123 18312 20000 26379 29091 35547
161 313 1976 10118 19510 24067 25236 29200
495 2033 3478 18349 21388 27692 27945 29298
40 123 466 8627 14489 23804 25266 29217
1919 2239 5036 9020 10230 13401 26202 31868
2984 2990 4559 13817 15317 17982 24664 30694
4263 4578 4900 18514 19432 21056 22195 25540
486 2865 4044 10378 16367 19558 31611 37057
773 785 4692 13690 15318 17028 26614 28889
1128 2525 4918 13514 14018 21695 28403 28447
1378 2785 3945 19557 24360 26125 32618 35109
1622 2734 4728 21208 22587 28908 32086 34795
1490 2885 4429 7668 12440 13368 15096 30591
157 4782 5028 7007 8693 14921 17912 24354
1887 2821 4004 5990 7023 11617 23891 31527
2659 3026 3929 8247 18589 18766 25496 30000
1493 4505 4919 10166 15487 19375 20018 37009
1459 2038 4184 13922 16641 25405 27889 36692
2552 3118 4424 10018 10774 20992 21805 22999
1575 3751 4248 12315 13683 16910 20849 27503
169 1552 4011 8140 13348 21198 22677 22961
485 1610 2021 6883 8078 10259 10833 36872
717 3562 4705 8210 14216 16365 30074 30100
284 2060 2603 5600 6111 16526 16904 25280
1464 2306 2405 15402 22597 31453 33154 36507
793 858 958 19518 21177 22969 27465 34316
2755 4039 4916 13740 21014 22548 23393 27868
2346 2859 3724 5804 11163 13257 16059 16537
3034 3827 4257 10753 10848 16863 17910 30215
699 2077 3036 14789 28159 29959 32060 35741
842 1479 1651 8903 20126 29843 30172 36359
60 216 2154 13804 29952 30425 30451 33882
1561 2138 3179 7117 10997 17696 18819 29502
1929 2926 4119 6462 9997 17945 19143 35222
1408 3721 4733 6077 8220 23897 24532 32454
758 1062 3265 22844 25290 26795 30309 32198
723 974 2366 11325 11639 20444 30190 33000
3057 3184 4157 6124 10032 14829 22920 27535
1908 2681 3314 10175 15746 19286 30891 31312
337 3329 4284 16428 26550 26938 27394 29675
601 626 4671 7188 18716 20787 25752 31716
2736 3729 3853 14610 18790 21261 31327
1514 1926 2616 7216 7346 13375 15951
385 2731 2776 17442 17618 18488 26842
2847 3447 4837 7730 21494 25421 27060
4167 4675 4950 18125 19852 24594 31885
2100 2258 2839 6788 12190 20838 22037
598 1160 2512 9977 27667 31266 35818
726 918 4356 25915 26856 35644 35900
603 4023 4286 21322 24461 26414 31230
1378 1712 2601 6187 19972 21466 33990
2477 3873 5026 6147 11847 28736 31098
458 983 3395 5246 16300 16685 26054
1591 4194 4296 8941 12584 26579 36950
956 1266 1722 21007 23498 27878 29947
1791 2382 3477 27827
753 1172 3171 21799
577 1793 4156 14329
1221 1909 2872 23737
3201 3437 3627 24180
1422 2384 2680 17127
350 2057 3244 29775
1494 3096 4085 12712
1925 2736 3505 20471
167 1300 1330 30100
2178 4141 4741 6802
169 2635 2776 7608
1061 3955 4667 23473
185 995 4044 24130
1792 2284 4178 30200
3947 4503 4756 34653
1198 4107 4470 5969
9656
8810
34388
35438
20498
24839
23256
9966
25861
11305
7639
21600
13763
25619
The transmitting device/method is as follows.

A seventh receiving apparatus/method of the present technology includes a coding step of performing LDPC coding of information bits of an information length K=N×r based on an extended parity check matrix in which rows and columns of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 8/16 are each extended by a predetermined puncture length L, generating an extended LDPC code having parity bits of a parity length M=N+LK, and puncturing a head of the information bits of the extended LDPC code by the puncture length L to generate a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 8/16, wherein the extended parity check matrix has M1 rows represented by a predetermined value M1 and the information length K=N×r. the A matrix having K columns and located at the top left of the extended parity check matrix, a B matrix having a staircase structure adjacent to the right of the A matrix, having M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, having M1 rows and N+LK-M1 columns, a C matrix adjacent below the A matrix and the B matrix, having N+LK-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, having N+LK-M1 rows and N+LK-M1 columns, wherein the puncture length L is 2520 and the predetermined value M1 is 5040, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents positions of elements of 1 of the A matrix and the C matrix for every 360 columns,
2184 2245 5483 5692 9320 18011 18064 18150 20189 23469 23662 25407 28189 35779 37071
1855 3613 5755 7904 12491 14272 19654 22065 22316 23975 24503 26458 29567 34455 35556
928 4740 6537 8736 9455 16185 18167 22537 22768 26005 32031 32179 33566 34966 35808
3986 4696 5295 8034 12188 12339 14298 19661 22499 22837 28343 29201 30056 36868 36872
1049 2606 9166 13000 17407 22535 24035 24090 26423 27147 28104 29196 34765 36183 36195
2475 2705 6586 10659 14652 15858 18555 22635 25610 26796 32144 33131 35581 37072
1339 1594 5556 5731 5735 7423 7924 8287 10173 21406 26174 26965 30831 35028
2095 2692 4542 11957 16923 21339 22995 35510
753 3913 4481 24115 25745 28475 29334 34983
531 2404 4091 6823 7730 13085 21741 25943
764 2602 5000 5777 6649 28284 28457 30648
173 2884 3453 7716 16017 26720 33781 34558
804 3989 4026 10353 16302 20995 22614 29946
1369 1438 4721 11804 19454 24989 29745 33895
2413 3865 4900 9605 12227 19796 34068 35639
2280 3614 3994 5794 8725 17288 29042 32667
189 729 2807 18569 20422 29775 33106 35601
13 1942 3075 5647 16437 28792 33944 36951
2322 2774 4133 14911 23058 26276 35482 36145
1156 1915 1988 13753 20275 22750 28129 28615
1027 3254 3826 12792 25306 33398 34900 36579
1000 3662 3934 12247 28784 30051 30448 34971
2208 4777 4895 7995 15270 34546 35050 35465
865 1301 2776 5447 7236 25204 28825 33009
931 2280 3123 18312 20000 26379 29091 35547
161 313 1976 10118 19510 24067 25236 29200
495 2033 3478 18349 21388 27692 27945 29298
40 123 466 8627 14489 23804 25266 29217
1919 2239 5036 9020 10230 13401 26202 31868
2984 2990 4559 13817 15317 17982 24664 30694
4263 4578 4900 18514 19432 21056 22195 25540
486 2865 4044 10378 16367 19558 31611 37057
773 785 4692 13690 15318 17028 26614 28889
1128 2525 4918 13514 14018 21695 28403 28447
1378 2785 3945 19557 24360 26125 32618 35109
1622 2734 4728 21208 22587 28908 32086 34795
1490 2885 4429 7668 12440 13368 15096 30591
157 4782 5028 7007 8693 14921 17912 24354
1887 2821 4004 5990 7023 11617 23891 31527
2659 3026 3929 8247 18589 18766 25496 30000
1493 4505 4919 10166 15487 19375 20018 37009
1459 2038 4184 13922 16641 25405 27889 36692
2552 3118 4424 10018 10774 20992 21805 22999
1575 3751 4248 12315 13683 16910 20849 27503
169 1552 4011 8140 13348 21198 22677 22961
485 1610 2021 6883 8078 10259 10833 36872
717 3562 4705 8210 14216 16365 30074 30100
284 2060 2603 5600 6111 16526 16904 25280
1464 2306 2405 15402 22597 31453 33154 36507
793 858 958 19518 21177 22969 27465 34316
2755 4039 4916 13740 21014 22548 23393 27868
2346 2859 3724 5804 11163 13257 16059 16537
3034 3827 4257 10753 10848 16863 17910 30215
699 2077 3036 14789 28159 29959 32060 35741
842 1479 1651 8903 20126 29843 30172 36359
60 216 2154 13804 29952 30425 30451 33882
1561 2138 3179 7117 10997 17696 18819 29502
1929 2926 4119 6462 9997 17945 19143 35222
1408 3721 4733 6077 8220 23897 24532 32454
758 1062 3265 22844 25290 26795 30309 32198
723 974 2366 11325 11639 20444 30190 33000
3057 3184 4157 6124 10032 14829 22920 27535
1908 2681 3314 10175 15746 19286 30891 31312
337 3329 4284 16428 26550 26938 27394 29675
601 626 4671 7188 18716 20787 25752 31716
2736 3729 3853 14610 18790 21261 31327
1514 1926 2616 7216 7346 13375 15951
385 2731 2776 17442 17618 18488 26842
2847 3447 4837 7730 21494 25421 27060
4167 4675 4950 18125 19852 24594 31885
2100 2258 2839 6788 12190 20838 22037
598 1160 2512 9977 27667 31266 35818
726 918 4356 25915 26856 35644 35900
603 4023 4286 21322 24461 26414 31230
1378 1712 2601 6187 19972 21466 33990
2477 3873 5026 6147 11847 28736 31098
458 983 3395 5246 16300 16685 26054
1591 4194 4296 8941 12584 26579 36950
956 1266 1722 21007 23498 27878 29947
1791 2382 3477 27827
753 1172 3171 21799
577 1793 4156 14329
1221 1909 2872 23737
3201 3437 3627 24180
1422 2384 2680 17127
350 2057 3244 29775
1494 3096 4085 12712
1925 2736 3505 20471
167 1300 1330 30100
2178 4141 4741 6802
169 2635 2776 7608
1061 3955 4667 23473
185 995 4044 24130
1792 2284 4178 30200
3947 4503 4756 34653
1198 4107 4470 5969
9656
8810
34388
35438
20498
24839
23256
9966
25861
11305
7639
21600
13763
25619
The receiving device/method includes a decoding unit/step for decoding the punctured LDPC code obtained from data transmitted by a transmission method as described above.

An eighth transmission device/method of the present technology includes a coding unit/step for performing LDPC coding of information bits of an information length K=N×r based on an extended parity check matrix in which rows and columns of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 9/16 are each extended by a predetermined puncture length L, generating an extended LDPC code having parity bits of a parity length M=N+LK, and puncturing a leading portion of the information bits of the extended LDPC code by the puncture length L to generate a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 9/16, wherein the extended parity check matrix is M1 expressed by a predetermined value M1 and the information length K=N×r. a B matrix of a staircase structure adjacent to the right of the A matrix, having M1 rows and M1 columns; a Z matrix which is a zero matrix adjacent to the right of the B matrix, having M1 rows and N+LK-M1 columns; a C matrix adjacent below the A matrix and the B matrix, having N+LK-M1 rows and K+M1 columns; and a D matrix which is an identity matrix adjacent to the right of the C matrix, having N+LK-M1 rows and N+LK-M1 columns, wherein the puncture length L is 1800 and the predetermined value M1 is 9000, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents positions of elements of 1 of the A matrix and the C matrix every 360 columns,
3681 3750 3985 4255 8583 9468 12078 12353 15700 16492 17127 18174 18264 22392 23070 25263 29195 32034
804 4119 5315 5489 8261 9514 10099 10268 14359 16861 21050 21439 23880 24274 26637 30518 30944 31195
3684 4224 4412 7772 8017 10100 12529 15888 16518 18089 19685 28054 28297 28345 28897 29827 30402 31794
2013 2073 4993 6278 6716 10271 13971 14141 14727 17892 21649 22734 24394 25979 26485 30156 30617 31322
671 4057 4827 6795 8726 11791 15912 16773 16823 21296 24678 28589 29419 30212 30976 31701 32035
2831 3625 4812 9421 10678 11313 11919 13859 24185 26543
105 197 4569 12767 18835 20708 21307 21922 29762 30542
1939 3334 7927 12368 22520 24007 25355 26414 27639 30526
935 4228 7324 10281 10930 14811 20832 21012 24721 31868
451 1279 6541 9174 9524 23917 24447 24765 27400 30105
596 3093 7695 12690 12805 20513 26844 26874 27238 30238
3165 4948 8257 13864 15261 19334 23340 27303 29834 30592
4311 6608 8867 12314 17011 19562 29621 29653 29867 31831
246 1043 4063 9880 12133 14403 17673 21772 26756 28865
3800 4310 7891 9005 17892 22752 29776 30960 31922
169 3202 6707 9267 19608 21494 24264 27783 30896
2756 3526 5061 14144 15208 17722 19974 23683 25622
5640 6672 8062 10253 14587 17029 23586 29354 30935
1780 6399 7013 13407 14129 26025 27047 27302 28430
3867 8295 8448 11173 12961 16355 23417 30645 30840
114 2303 5658 10578 12954 19396 23278 26133 29150
4205 6484 8154 9468 9855 17738 25225 28855 29327
4064 5671 6785 11073 12684 17900 18543 24915 25278
4591 6432 6812 9172 9497 10443 11612 15805 26385
3429 5317 5699 11875 12763 19252 24194 28715 31645
2334 5348 8140 15322 16398 18377 22674 23119 27452
5806 8178 8750 18695 19361 20500 21337 23747 26594
868 5108 7470 12695 12827 13362 17150 30388 32036
1401 3377 6069 13887 15223 16423 20548 26114 31525
2388 2511 6647 15288 20979 21546 22893 25768 26293
5918 7740 8309 16069 17648 21533 21638 30421 30592
4531 6710 7575 10870 14321 15801 22289 27422 29206
282 2349 2823 16122 18235 22889 30845 31790 32028
1028 3364 7170 9696 10463 13676 21633 22408 22987
4747 5376 7037 11344 18790 18904 23562 26963 29547
2666 4221 8779 12684 15548 16845 19631 27773 32000
3277 3636 6417 15359 20686 23258 23607 28911 31760
1394 1613 4705 10030 14240 20469 21907 25971 28392
2428 3334 6308 9823 14969 16081 20361 21680 27204
870 4539 5033 11210 11227 12757 13164 16363 18278
519 8424 8966 11266 12282 15631 17138 25283 27009
562 4648 7031 9367 9769 17258 17524 18469 23544
2607 4017 4276 12525 16477 21617 28004 29179 31638
1311 1705 6279 19425 20643 21524 21927 26759 30022
2440 5160 8827 19724 20470 21579 22088 25426 26076
247 1718 3238 15685 16926 26381 27070 28504 31522
1646 3308 3325 12196 13145 18495 22879 25613 31074
2777 6991 7582 12852 15441 16518 19845 27107 31491
24 1098 6964 10014
3834 7138 8104 27290
2467 2695 6985 23538
597 1655 2786 26365
3412 3568 3869 22313
1378 3631 7350 30759
396 2426 3965 30636
294 5276 6622 28723
889 5479 5831 13814
1355 5011 7082 24636
1737 5683 7638 12279
4248 4328 7871 13506
1867 5466 7068 23531
1400 5020 7410 9775
2727 3409 6324 21177
4027 4240 7262 16737
1442 7380 7650 24201
601 6169 6278 26698
1070 3198 6038 11626
616 3835 8339 28168
4424 5809 6656 26638
3857 4561 4879 27896
2696 2722 4665 17776
643 2333 3072 10579
232 4876 4956 18710
3486 3535 6104 29906
774 5073 6030 23656
4617 6194 7445 31653
4163 5489 8227 28295
3675 3991 4940 18635
496 2003 4758 20333
1062 2059 4493 25301
1380 7374 8642 28926
1294 1639 8662 30961
5866 6147 7653 11713
5458 7184 7361 20695
2463 4602 6018 16857
320 4682 8140 19724
4410 6923 8975 26037
306 1921 7301 11104
57 1768 5604 17338
2839 3153 5912 28608
1091 6051 7495 31918
1681 2099 2259 16924
4490 5186 6994 25446
3188 4252 6208 25437
1342 5660 7305 21071
1048 3204 7421 15675
2197 3412 5125 22484
5721 6143 6479 22800
2531 4216 4794 17691
628 3665 5783 26756
2660 5527 7289 14552
3432 4895 6255 20101
288 2324 2375 27024
3898 7386 8459 10265
301 4717 4972 10844
1895 7065 8334 22255
331 1779 7214 22726
3202 4096 7467 27090
27017
29554
30755
30289
14496
29460
27770
9663
12310
11707
30095
30852
20107
23269
22090
12537
23969
13527
10911
20907
15272
23822
31661
13732
21787
The transmitting device/method is as follows.

An eighth receiving device/method of the present technology includes a coding step of performing LDPC coding of information bits of an information length K=N×r based on an extended parity check matrix in which rows and columns of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 9/16 are each extended by a predetermined puncture length L, generating an extended LDPC code having parity bits of a parity length M=N+LK, and puncturing a head of the information bits of the extended LDPC code by the puncture length L to generate a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 9/16, wherein the extended parity check matrix has M1 rows represented by a predetermined value M1 and the information length K=N×r. the A matrix having K columns and located at the top left of the extended parity check matrix, a B matrix having a staircase structure adjacent to the right of the A matrix, having M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, having M1 rows and N+LK-M1 columns, a C matrix adjacent below the A matrix and the B matrix, having N+LK-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, having N+LK-M1 rows and N+LK-M1 columns, wherein the puncture length L is 1800 and the predetermined value M1 is 9000, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents positions of elements of 1 of the A matrix and the C matrix for every 360 columns,
3681 3750 3985 4255 8583 9468 12078 12353 15700 16492 17127 18174 18264 22392 23070 25263 29195 32034
804 4119 5315 5489 8261 9514 10099 10268 14359 16861 21050 21439 23880 24274 26637 30518 30944 31195
3684 4224 4412 7772 8017 10100 12529 15888 16518 18089 19685 28054 28297 28345 28897 29827 30402 31794
2013 2073 4993 6278 6716 10271 13971 14141 14727 17892 21649 22734 24394 25979 26485 30156 30617 31322
671 4057 4827 6795 8726 11791 15912 16773 16823 21296 24678 28589 29419 30212 30976 31701 32035
2831 3625 4812 9421 10678 11313 11919 13859 24185 26543
105 197 4569 12767 18835 20708 21307 21922 29762 30542
1939 3334 7927 12368 22520 24007 25355 26414 27639 30526
935 4228 7324 10281 10930 14811 20832 21012 24721 31868
451 1279 6541 9174 9524 23917 24447 24765 27400 30105
596 3093 7695 12690 12805 20513 26844 26874 27238 30238
3165 4948 8257 13864 15261 19334 23340 27303 29834 30592
4311 6608 8867 12314 17011 19562 29621 29653 29867 31831
246 1043 4063 9880 12133 14403 17673 21772 26756 28865
3800 4310 7891 9005 17892 22752 29776 30960 31922
169 3202 6707 9267 19608 21494 24264 27783 30896
2756 3526 5061 14144 15208 17722 19974 23683 25622
5640 6672 8062 10253 14587 17029 23586 29354 30935
1780 6399 7013 13407 14129 26025 27047 27302 28430
3867 8295 8448 11173 12961 16355 23417 30645 30840
114 2303 5658 10578 12954 19396 23278 26133 29150
4205 6484 8154 9468 9855 17738 25225 28855 29327
4064 5671 6785 11073 12684 17900 18543 24915 25278
4591 6432 6812 9172 9497 10443 11612 15805 26385
3429 5317 5699 11875 12763 19252 24194 28715 31645
2334 5348 8140 15322 16398 18377 22674 23119 27452
5806 8178 8750 18695 19361 20500 21337 23747 26594
868 5108 7470 12695 12827 13362 17150 30388 32036
1401 3377 6069 13887 15223 16423 20548 26114 31525
2388 2511 6647 15288 20979 21546 22893 25768 26293
5918 7740 8309 16069 17648 21533 21638 30421 30592
4531 6710 7575 10870 14321 15801 22289 27422 29206
282 2349 2823 16122 18235 22889 30845 31790 32028
1028 3364 7170 9696 10463 13676 21633 22408 22987
4747 5376 7037 11344 18790 18904 23562 26963 29547
2666 4221 8779 12684 15548 16845 19631 27773 32000
3277 3636 6417 15359 20686 23258 23607 28911 31760
1394 1613 4705 10030 14240 20469 21907 25971 28392
2428 3334 6308 9823 14969 16081 20361 21680 27204
870 4539 5033 11210 11227 12757 13164 16363 18278
519 8424 8966 11266 12282 15631 17138 25283 27009
562 4648 7031 9367 9769 17258 17524 18469 23544
2607 4017 4276 12525 16477 21617 28004 29179 31638
1311 1705 6279 19425 20643 21524 21927 26759 30022
2440 5160 8827 19724 20470 21579 22088 25426 26076
247 1718 3238 15685 16926 26381 27070 28504 31522
1646 3308 3325 12196 13145 18495 22879 25613 31074
2777 6991 7582 12852 15441 16518 19845 27107 31491
24 1098 6964 10014
3834 7138 8104 27290
2467 2695 6985 23538
597 1655 2786 26365
3412 3568 3869 22313
1378 3631 7350 30759
396 2426 3965 30636
294 5276 6622 28723
889 5479 5831 13814
1355 5011 7082 24636
1737 5683 7638 12279
4248 4328 7871 13506
1867 5466 7068 23531
1400 5020 7410 9775
2727 3409 6324 21177
4027 4240 7262 16737
1442 7380 7650 24201
601 6169 6278 26698
1070 3198 6038 11626
616 3835 8339 28168
4424 5809 6656 26638
3857 4561 4879 27896
2696 2722 4665 17776
643 2333 3072 10579
232 4876 4956 18710
3486 3535 6104 29906
774 5073 6030 23656
4617 6194 7445 31653
4163 5489 8227 28295
3675 3991 4940 18635
496 2003 4758 20333
1062 2059 4493 25301
1380 7374 8642 28926
1294 1639 8662 30961
5866 6147 7653 11713
5458 7184 7361 20695
2463 4602 6018 16857
320 4682 8140 19724
4410 6923 8975 26037
306 1921 7301 11104
57 1768 5604 17338
2839 3153 5912 28608
1091 6051 7495 31918
1681 2099 2259 16924
4490 5186 6994 25446
3188 4252 6208 25437
1342 5660 7305 21071
1048 3204 7421 15675
2197 3412 5125 22484
5721 6143 6479 22800
2531 4216 4794 17691
628 3665 5783 26756
2660 5527 7289 14552
3432 4895 6255 20101
288 2324 2375 27024
3898 7386 8459 10265
301 4717 4972 10844
1895 7065 8334 22255
331 1779 7214 22726
3202 4096 7467 27090
27017
29554
30755
30289
14496
29460
27770
9663
12310
11707
30095
30852
20107
23269
22090
12537
23969
13527
10911
20907
15272
23822
31661
13732
21787
The receiving device/method includes a decoding unit/step for decoding the punctured LDPC code obtained from data transmitted by a transmission method as described above.

In the first transmission device/method of the present technology, LDPC coding of information bits of information length K=N×r is performed based on an extended parity check matrix in which the rows and columns of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 2/16 are each extended by a predetermined puncture length L, and an extended LDPC code having parity bits of parity length M=N+LK is generated. Furthermore, the head of the information bits of the extended LDPC code is punctured by the puncture length L, and a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 2/16 is generated. The extended parity check matrix includes an A matrix at the top left of the extended parity check matrix, which has M1 rows and K columns and is represented by a predetermined value M1 and the information length K=N×r, a B matrix of a staircase structure adjacent to the right of the A matrix, which has M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, which has M1 rows and N+LK-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which has N+LK-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, which has N+LK-M1 rows and N+LK-M1 columns, wherein the puncture length L is 0, the predetermined value M1 is 1800, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents the positions of elements of 1 of the A matrix and the C matrix every 360 columns,
1444 1737 1780 9182 9748 9954 11859 23510 36957 41211 41804 41857 42268 42854 45152 46217 46448 52760 57528 59998 60168
281 1279 1468 9650 11337 15973 21859 24346 25864 28317 33522 35344 40280 43576 43942 50851 53221 57076 57561 59922 59962
132 758 1470 2901 2957 3365 4567 7062 10939 12288 20818 35122 39299 41903 43394 44289 49129 51394 53222 53899 56037
9 756 1510 3127 4867 15380 16575 17906 19275 20944 25462 27021 31939 34367 36491 39391 45013 45505 47768 50626 51547
188 252 1181 2939 4132 7944 12352 15443 17831 18785 18904 22672 23400 30518 30652 45102 51500 52032 52868 60341
496 564 1527 2708 2751 3658 6451 8212 11654 17193 21558 23963 28394 30554 30628 35052 44835 45090 49804 52979
793 858 1710 3561 10566 11369 17707 20970 22329 22383 24607 31237 38613 42719 43867 45715 50453 51882 55535 60316
689 980 1657 2690 4633 11070 16939 18443 20748 21753 25742 30361 31544 31693 33019 40842 47042 48850 52130 56606
198 281 1664 3384 12801 17438 24093 29656 30578 31929 35921 38919 38984 40957 43262 48155 50743 56398 56427 59215
457 1065 1196 2861 12717 15390 16655 17899 18300 22233 31560 32716 34991 43324 46709 51328 52891 54292 56334 59229
1307 1481 1599 13551 21460 22804 23439 32551 32671 35941 36329 40096 41474 45156 50568 55578 55667 56581 59061 60009
99 485 708 4043 5527 5824 7489 8809 15871 17753 18297 18507 19070 22839 28023 41124 43165 50873 51968 57000
188 412 1641 1833 5707 7556 10610 12636 14533 26728 27604 31757 32972 34677 36279 38315 42252 43155 53121 57503
300 794 1153 6459 7063 13526 17788 18308 21233 21439 22250 28514 32042 32160 36140 44273 49289 50434 51163 56471
757 1336 1440 5560 6283 10080 10986 13051 17638 22870 31581 35463 41212 42195 43305 46746 49564 56412 58207 59477
106 1195 1474 6273 14321 14746 16496 17016 17214 19472 27450 33489 40638 42896 43150 47624 51106 51339 53730 55816
98 1002 1336 2076 9328 10989 13413 13916 14455 17863 19776 24981 31172 39450 40385 43348 44833 46967 52917 58029
262 1363 1605 4715 8438 8794 12188 18208 19803 28570 36281 38576 39120 40344 44994 45827 46559 49914 50771 56658
870 1743 1764 5521 8695 11745 15888 16359 16412 33151 37033 38281 38499 39026 41174 44818 53168 56178 58405 60285
861 1142 1169 2232 4370 9265 10442 15376 15947 19420 24577 29045 36440 38242 41035 47841 49589 50529 52662 59907
231 913 1440 2695 6369 7938 8296 12107 14329 19324 25096 26108 35369 38516 41289 43604 52617 57130 59909 60020
214 667 762 3988 6762 14360 15257 18298 18943 19364 29813 33804 35106 36373 39451 39478 45683 47618 48539 59814
1144 1150 1746 1800 7038 11454 18376 18819 21869 26781 33351 35591 46571 49235 49956 50749 51642 53390 56404 58103
308 317 1510 5176 12653 13311 15884 18075 22371 26021 27004 29283 30382 32114 32978 35790 47224 48249 51701 57840
2786 5188 6809 7110 7138 7167 8042 12569 15301 27503 27894 32875 35277 48267 49051 57363
6186 6554 12052 14220 15013 15388 22130 27207 30084 30620 31562 36834 38446 52593 56791 60017
8810 12703 21600 21640 22233 26157 27268 27384 33020 39679 49298 51854 52364 53298 55215 59802
2670 6309 10054 11421 11750 11901 12053 12752 17466 28571 29910 32369 34446 38373 49448 51729
11357 12810 13252 14755 22824 30867 32868 33512 34862 35560 38704 41861 42805 43103 48692 55234
It has become.

In the first receiving device/method of the present technology, the punctured LDPC code obtained from the data transmitted by the first transmission method is decoded.

In the second transmission device/method of the present technology, LDPC coding of information bits of information length K=N×r is performed based on an extended parity check matrix in which the rows and columns of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 3/16 are each extended by a predetermined puncture length L, and an extended LDPC code having parity bits of parity length M=N+LK is generated. Furthermore, the head of the information bits of the extended LDPC code is punctured by the puncture length L, and a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 3/16 is generated. The extended parity check matrix includes an A matrix at the top left of the extended parity check matrix, which has M1 rows and K columns and is represented by a predetermined value M1 and the information length K=N×r, a B matrix of a staircase structure adjacent to the right of the A matrix, which has M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, which has M1 rows and N+LK-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which has N+LK-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, which has N+LK-M1 rows and N+LK-M1 columns, wherein the puncture length L is 0, the predetermined value M1 is 1800, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents the positions of elements of 1 of the A matrix and the C matrix every 360 columns,
853 875 1192 2465 3004 4879 9062 21593 24043 26616 30909 32017 35006 42135 44268 56020
161 519 1556 3317 6015 14909 15760 21148 30072 32655 33940 34834 43430 44798 51284 52169
177 999 1683 6976 17610 18152 19591 22312 25036 27303 28584 47608 47749 50216 52322 54007
981 1000 1625 1630 6933 13217 13956 15319 22642 29483 31921 35465 43602 44250 46505 55678
1204 1242 1653 3066 6095 16862 20154 21430 23418 26408 30979 34093 41103 48385 54547 55093
316 1355 1562 2665 5222 6575 18299 19639 24268 30959 37721 47966 48255 51808 53697 56010
183 219 615 2859 6967 8044 13949 22294 28922 29355 32175 32276 33861 49675 52583 53512
263 342 1684 7426 14417 20396 27461 30075 33740 36812 38204 38420 41612 43083 45914 56035
256 870 921 3023 4662 5225 5276 19284 26034 35397 38524 44936 45178 46351 50860 51813
289 898 1442 9135 10774 13951 14133 19070 21192 27854 32118 43657 43859 43934 52772 53659
256 690 1324 3582 7066 8507 26854 34507 40768 44943 47952 50512 52080 52872 53733 53773
238 1037 1388 1929 6395 10653 21299 23085 26467 26836 27834 44924 47310 49393 53742 55883
976 1217 1469 7718 16449 19465 19983 22386 24762 28308 32395 33589 35997 41034 42118 43799
265 368 1365 1375 1808 7556 14593 15079 19648 36077 40397 41971 44940 47570 52522 55839
802 1656 1689 5554 6787 11067 15764 19656 31740 31762 36046 42258 45165 49245 52732 53420
265 307 1299 2775 6738 22483 26322 27615 30628 34194 38024 38787 46089 48680 49115 51063
698 747 1241 2898 5218 7964 15358 17928 28069 29537 33641 36103 40207 40701 42823 42929
70 293 799 16494 16696 20008 21050 23735 34060 34555 35068 37664 45312 47748 50957 52382
1151 1163 1751 7025 10775 15100 22260 24718 28905 30853 33020 43261 46849 48258 54212 56122
279 457 775 8025 13383 16978 19254 23110 28197 31454 33060 38532 41429 41621 42149 54927
494 1130 1351 18525 22446 31344 31582 38324 42396 46010 48804 49241 49379 51987 52296 53133
177 508 1032 3547 8103 13357 14344 15876 20386 22050 23593 35305 47409 53297 55610 56093
988 1091 1785 3400 5144 7245 10179 12918 32871 33462 34484 38318 43410 44103 44267 52837
520 564 1757 12204 16894 17249 21480 21541 23760 28325 36266 40606 46094 48779 55501 56065
914 943 1111 3641 4232 10215 14134 16582 23445 28767 28862 32260 35952 39907 41846 47553
466 554 1697 4921 6953 7034 7052 10648 11628 19174 27830 29210 31722 32281 52559 55802
1135 1273 1408 2599 3618 4903 7210 17368 21014 21287 21926 24070 27741 29801 36137 44272
524 801 1767 4093 9721 12200 19463 29280 31587 33577 39747 43688 46627 49807 51345 55969
489 1390 1756 3050 12113 20477 21376 26797 27049 28907 31534 32746 33345 40582 41970 55911
432 1520 1598 9292 11552 16985 18417 21847 21960 24287 25489 34478 40990 44004 47573 53982
301 592 849 1944 4128 8341 16783 19249 24983 43892 44041 44474 44942 44959 50738 54935
118 558 1470 4368 10132 11791 16523 22408 23766 25111 25426 25779 35005 42742 46197 53118
310 1059 1322 3609 7107 10048 13161 32141 33369 35206 36131 38746 44545 47963 48414
256 346 845 7363 10375 12492 13091 27987 32113 34846 36223 39863 44450 46526 49216
607 683 954 5473 10617 18484 20018 26971 28190 37592 39069 39740 43575 45676 48149
244 635 1208 5450 8082 25030 25149 28411 29333 31324 36972 42071 43401 47088 52085
2841 5514 16122 18061 18199 20340 22525 25022 29914 31732 46415
7567 22860 23157 24194 24622 29643 31255 32355 36379 38228 51173
24002 24459 25897 26955 31168 31630 39183 46791 47323 51503 55241
4817 8291 10219 13991 14318 28549 28836 30491 36884 46310 54625
8275 9585 11678 37216 38932 45186 46287 48023 48862 53636 56067
It has become.

In the second receiving device/method of the present technology, the punctured LDPC code obtained from the data transmitted by the second transmission method is decoded.

In the third transmission device/method of the present technology, LDPC coding of information bits of information length K=N×r is performed based on an extended parity check matrix in which the rows and columns of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 4/16 are each extended by a predetermined puncture length L, and an extended LDPC code having parity bits of parity length M=N+LK is generated. Furthermore, the head of the information bits of the extended LDPC code is punctured by the puncture length L, and a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 4/16 is generated. The extended parity check matrix includes an A matrix at the top left of the extended parity check matrix, which has M1 rows and K columns and is represented by a predetermined value M1 and the information length K=N×r, a B matrix of a staircase structure adjacent to the right of the A matrix, which has M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, which has M1 rows and N+LK-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which has N+LK-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, which has N+LK-M1 rows and N+LK-M1 columns, wherein the puncture length L is 0, the predetermined value M1 is 1800, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents the positions of elements of 1 of the A matrix and the C matrix every 360 columns,
797 853 885 2412 8763 16966 18074 21725 21923 22276 32414 49532 51711
39 1096 1305 6276 13449 16227 24628 29368 31384 32207 45115 47748 51161
44 427 1193 4543 10898 29586 34143 40123 44170 46228 47353 48962 49856
541 736 844 4479 7200 16262 18160 24649 29159 42952 43829 47067 48307
95 1342 1783 9131 12031 12989 13202 14244 27356 29527 32789 36795 38709
494 1203 1652 5475 16812 21005 24490 28736 31487 37840 39565 50301 50448
1532 1581 1705 10606 12678 17526 28502 35833 44124 47833 49541 51702 51831
96 185 1188 2754 2775 5499 6292 6895 9799 27158 28509 39985 48544
749 1007 1624 9110 12545 20317 27165 31146 36658 40218 45870 48593 49397
1163 1355 1556 4652 6091 6978 8979 14330 25366 27509 27927 33954 51511
1168 1311 1320 2096 3187 5119 20693 29188 35325 36538 41740 44821 47836
288 1399 1422 10030 12443 15396 19379 26774 30623 40397 40494 47324 48652
570 809 1622 8966 13182 24760 25846 37786 38499 41477 47218 49514 51673
44 208 811 3742 8390 20577 24033 26195 29483 39222 40429 45529 45643
97 1161 1310 2693 19471 21117 24844 29355 37875 38827 42599 46927 51585
620 1416 1679 12977 15285 17224 20748 22381 25697 28626 33138 37912 39470
368 1367 1465 11725 13919 13945 33353 37326 38778 40727 40875 48487 51103
1427 1519 1736 6497 10328 15345 17776 24008 29435 47926 48682 48686 49250
23 1169 1460 5251 10379 24722 25285 32822 35089 37814 44950 45474 47146
32 681 1568 6384 9728 21530 22557 24432 31527 33435 36375 37151 39510
918 1286 1362 2738 2808 5037 7483 16549 20933 31061 33375 39562 50975
844 925 1507 8014 14804 15472 22057 31449 32226 32974 34809 41852 50676
1104 1753 1780 6605 22820 24244 26745 28587 30929 33797 34123 42029 43723
296 351 1799 9595 9770 15297 17910 19571 20521 35468 38937 48238 50795
638 760 1027 15495 15806 27803 29165 32046 34804 38592 38949 39457 47996
676 1548 1687 15931 17206 27071 28999 29312 30437 39081 44646 46366 48245
164 1436 1470 3335 8452 10611 14735 17314 17457 21853 32068 49268 51360
673 987 1570 3322 4946 6830 12027 22997 28126 30952 31702 32262 40857
773 1139 1404 9840 16019 16640 18064 24251 25181 42571 46539 50656 51750
726 730 1282 9539 10718 15690 27181 28022 29831 32767 40892 45045 51229
178 355 896 3493 13148 14855 15297 17187 20332 26479 36876 38772 41342
174 909 992 4685 6611 6649 9973 10846 18348 21866 29851 48524 51503
256 1273 1407 4650 6765 16547 19484 19834 20323 22294 27570 33457 40893
27 60 100 1530 9640 11387 12526 16343 17977 24156 29307 43317 51005
908 1009 1256 15318 24411 27373 28956 29096 37447 40401 45949 47505 50608
871 1022 1050 2987 11235 11367 14631 18902 19810 40712 41044 44083 50666
322 663 669 8710 10150 15826 17085 22493 31938 37858 40689 44018 49689
589 846 1413 2627 4519 7841 15480 24061 40839 41475 41591 46883 50613
963 1135 1395 1610 5107 10991 17300 20822 21073 23236 30712 39982 42668
729 792 1696 3391 4018 6677 15323 31211 32245 38603 39662 44737 48810
274 376 1003 8907 11493 11611 25418 25885 33368 36485 41225 44260 45485
1174 1245 1412 3510 9590 17010 20708 25956 28271 29603 33362 37097 42952
813 1030 1452 5147 9859 19468 34863 35407 36002 36716 40288 42835 44337
211 230 1694 5157 23173 23285 26293 27140 29110 34165 38861 40227 43477
537 933 1476 2748 5211 5376 14853 16889 18857 20875 22806 29035 29444
697 709 765 6009 27426 29923 33631 35433 36206 43172 47174 50955
833 1096 1648 4459 13016 22371 22757 23977 26422 28211 29254 43701
214 521 895 2147 3200 3525 3561 6699 7730 7845 9000 9570 11204 11446 11570 12462 13469 14396 15475 17540 18804 18944 19321 19550 20001 25062 25567 26342 26709 27146 27392 27428 30782 32176 32956 33240 34420 35150 35263 35879 36407 37210 37393 37420 38892 40202 40583 40665 41816 42558 42720 43063 43442 44348 44378 45052 47033 49514 49845 50084 51647
7599 9277 13898 16320 19617 28012 30567 42423 43056
15934 20819 25195 28421 31073 31750 33551 35982 37823
5377 13795 16639 20686 22150 32586 33922 40431 42255
3368 14716 15016 20925 23397 25910 28917 36663 40946
3478 4545 5802 12334 27955 29363 42818 48135 48995
It has become.

In the third receiving device/method of the present technology, the punctured LDPC code obtained from the data transmitted by the third transmission method is decoded.

In a fourth transmission device/method of the present technology, LDPC coding is performed on information bits of information length K=N×r based on an extended parity check matrix in which the rows and columns of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 5/16 are each extended by a predetermined puncture length L, and an extended LDPC code having parity bits of parity length M=N+LK is generated. Furthermore, the head of the information bits of the extended LDPC code is punctured by the puncture length L, and a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 5/16 is generated. The extended parity check matrix includes an A matrix at the top left of the extended parity check matrix, which has M1 rows and K columns and is represented by a predetermined value M1 and the information length K=N×r, a B matrix of a staircase structure adjacent to the right of the A matrix, which has M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, which has M1 rows and N+LK-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which has N+LK-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, which has N+LK-M1 rows and N+LK-M1 columns, wherein the puncture length L is 1800, the predetermined value M1 is 3600, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents the positions of elements of 1 of the A matrix and the C matrix for every 360 columns,
1500 1594 4158 4611 4621 9708 14082 14260 16777 17457 21985 22308 23963 24554 25344 27485 27516 28008 30174 30625 31378 31 525 35873 36202 45585 47150 47845 49311
851 2755 5753 8521 10162 12036 16914 17857 18538 22342 24470 28199 33144 34233 35459 35506 38894 39300 41198 41995 42243 4 3310 44187 44969 46306 46719 47907 48844
803 828 7874 8667 12187 15086 16097 20436 21143 22142 27188 29052 30895 30927 30963 31563 34591 35419 36521 38142 38825 42 538 43514 44432 45634 47807 47953
3442 3596 4211 4790 5276 5379 6950 8256 10939 13398 13563 13720 18074 22070 22760 26767 27057 28054 29148 33155 33760 3850 0 42760 44861 45653 46507 48695
1337 3179 3936 4019 4207 4915 5953 6200 7596 10085 10241 15048 16788 25083 27412 27478 28623 33014 33168 33296 34087 35922 36818 38225 40169 41762 46370
230 2417 2466 10915 19279 39243 39762 42664 45750
595 1792 2788 16000 19698 28701 38882 45250 46449
764 1619 2243 10130 25528 38421 44789 45032 48064
779 1651 3431 4707 8887 24180 36687 37770 39583
136 1352 3105 9580 25493 28929 29003 43731 44941
0 2147 3434 4402 19742 21221 37419 46590 49082
1658 1953 2935 17606 21613 29311 33878 46163 47126
804 1362 2596 15920 25368 28032 32218 37251 38385
733 3180 3549 12710 14684 32429 36039 39164 47531
807 2668 2811 23227 39984 42091 45708 46426 47788
1142 3373 3414 4219 7793 11379 15389 28832 32362
246 2670 3141 11465 24513 25038 31936 36501 45021
1365 2399 3107 4460 24713 30758 32422 38041 43379
323 578 1392 22591 26966 35332 35884 36454 38254
24 78 229 8741 17149 21008 30309 32441 38141
587 1595 3531 9258 15476 30673 33744 41847 44930
980 2136 2883 18306 22032 31618 33154 45208 48127
1518 1796 2304 7939 24330 29552 33426 39907 41568
599 681 3597 10689 10811 19776 20651 34661 46473
970 1152 2675 13311 15762 16363 26575 37047 48249
1872 1968 2620 16207 31197 33577 37990 42868 45881
1105 1351 3374 28454 28667 37692 42083 46115
1019 1816 3153 7354 14190 15535 29787 40081
114 1127 3412 17706 21953 31166 48855 49247
411 1346 2860 6474 12912 28627 30225 31396
109 1895 2803 8192 22957 30924 32515 39258
1067 1547 3218 10928 18459 24102 24958 48228
1022 2939 3593 16210 20143 22128 36148 48748
1826 2281 3110 10706 11745 27544 29705 32385
165 1794 3038 13953 15929 20587 35639 37360
122 1107 1776 7992 15442 26707 28761 39718
344 1449 2018 7930 11023 11967 18210 48998
203 2541 3360 6249 8145 10115 16796 19830 39389 39409
1333 1476 1855 4261 5127 16893 20060 23938 25433 32522
1972 3154 3539 10244 10601 12317 18404 29191 35539 41261
1621 1817 3280 15943 26444 28455 28595 29822 38852 48190
2048 2565 2660 4707 12386 15311 19315 20091 24908 37754
2825 3043 3516 9940 11806 11981 20375 20597 22471 31060
2597 2792 3444 11226 16387 17531 18473 25142 39461 42139
439 2788 3511 3684 5549 16067 23077 39829 39920 44862
1076 2271 2797 6573 12043 17816 20967 21726 23200 38056
553 2080 2948 5535 16026 22119 23794 37157 46602 46720
112 2115 3084 8090 10494 13165 29078 31417 33314 39595
2275 2449 3058 10121 12474 12563 25072 25610 39483 43489
741 2186 2270 5146 10831 17517 20875 29107 35695 41244
1693 1902 2907 6756 10924 18965 24040 33793 41089 42464
2469 2514 2769 6664 8813 8938 19741 23113 34293 45892
1761 2326 2998 17255 23220 26747 28416 37450 38574 41110
1083 1375 1867 4468 6706 6899 15494 19170 28463 28858
1394 1412 1510 7439 27005 29288 32683 34307 34607 45091
2477 2978 3539 22378 23848 24738 28734 31460 41873 45398
191 803 1500 9030 14071 26093 26432 27827 35890 47458
556 2942 3114 10130 11981 33368 34732 42472 47188 47655
425 2875 2946 16084 19184 26801 27069 27090 31317 34103
121 1674 3258 5208 13340 26019 37492 38723 40779 49200
3968 7741 12550 32061
17972 19666 20231 33590
9086 34375 41691 42567
12168 14189 15095 49129
19291 26450 29950 39068
19852 25195 35124 36192
10447 32405 36184 40786
8911 19949 27496 41273
14679 16883 20951 29727
30296 32681 34757 36501
It has become.

In the fourth receiving device/method of the present technology, the punctured LDPC code obtained from the data transmitted by the fourth transmission method is decoded.

In the fifth transmission device/method of the present technology, LDPC coding of information bits of information length K=N×r is performed based on an extended parity check matrix in which the rows and columns of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 6/16 are each extended by a predetermined puncture length L, and an extended LDPC code having parity bits of parity length M=N+LK is generated. Furthermore, the head of the information bits of the extended LDPC code is punctured by the puncture length L, and a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 6/16 is generated. The extended parity check matrix includes an A matrix at the top left of the extended parity check matrix, which has M1 rows and K columns and is represented by a predetermined value M1 and the information length K=N×r, a B matrix of a staircase structure adjacent to the right of the A matrix, which has M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, which has M1 rows and N+LK-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which has N+LK-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, which has N+LK-M1 rows and N+LK-M1 columns, wherein the puncture length L is 1800, the predetermined value M1 is 3600, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents the positions of elements of 1 of the A matrix and the C matrix for every 360 columns,
1594 1610 4443 4633 4971 5913 7301 7706 13474 16147 16681 17638 20084 20205 20247 20540 22484 27085 28185 29116 31096 3306 8 41272 41610 43034
1883 2386 4525 5861 6762 8505 10987 11467 13389 15284 15934 22445 22893 24837 26162 26697 29883 30925 35299 38596 38645 41 614 42730 43699 44169
1048 1205 7615 12049 12746 13032 13602 14263 14911 15606 21519 26057 26528 28217 28266 29323 31302 32457 32579 34903 35105 36007 40006 43828 44649
1621 1937 3806 4192 4345 4436 4464 5013 7744 9969 10235 10276 10910 12816 16020 17524 20323 30904 31663 35163 35398 35957 39093 42657 44993
49 1822 3711 3892 4990 10239 12492 18990 19520 21406 24318 24612 25751 26767 30148 31680 32384 33296 34983 35934 38715 402 86 42291 42485 42998
220 302 3574 5681 9506 24907 31216 34098 36706
26 88 1979 6254 17793 31399 31963 38968 41759
571 2797 2843 10391 18284 24224 26323 35575 43222
2778 2865 3374 13146 22196 23479 29472 40894 43961
513 2641 3267 12546 22339 22592 33324 37388 43058
89 416 2750 8737 9111 19495 26529 35507 39319
1522 1795 3155 3952 19544 28293 40910 43137 44782
68 1271 2663 22635 26043 31010 37397 42214 42940
1102 1410 2026 14095 14851 19343 23303 25716 33443
2257 2649 2734 13712 40173 42230 42240 43221 44414
714 2565 2880 4450 12908 34192 35997 36455 40728
1546 3319 3372 7492 10636 16725 26425 42426 42880
41 927 2263 6416 10637 22272 29323 34364 39763
1681 2598 3263 4337 19277 28170 31112 39274 39685
1624 2266 2712 7713 10204 19680 20781 32234 32824
1839 2578 2725 4403 4475 6187 8251 15794 34791
1372 2107 2310 8695 10370 22033 31001 38223 44215
1045 2138 3259 14898 16935 20360 28114 30232 36792
2326 3271 3510 21052 22158 24249 25709 30136 35176
347 2043 2984 10440 10461 11558 18257 42040 44932
562 1425 2428 12400 14792 16918 24373 34372 44049
959 1004 2630 14983 26147 28239 28571 33730 34758
2366 3093 3321 16340 19265 26290 28817 42082 42430
1812 2687 3030 7047 13181 15320 27308 36719 39868
118 933 1127 16601 20206 28560 42837 44651 44924
411 1346 2869 4816 6186 12098 26338 28747 28842
1985 2151 2804 7754 21167 21405 29764 35907 40584
1067 1689 3513 10225 15350 17157 22215 37316 44909
1306 1452 2564 15049 24636 29181 29918 39466 44466
558 640 2085 5522 9131 12991 24658 28599 38510
971 1333 2524 5076 14312 16292 23989 28218 37668
345 1819 2012 7598 7602 10348 11079 16828 20223
206 3490 3577 7652 9484 15485 18215 32891 36012
207 2085 2818 4223 4981 18437 18907 20797 29779
1043 1602 1711 17049 26349 37701 37805 39929 44226
528 686 2519 22288 24424 26040 27266 35523 44395
974 2063 3540 23885 24211 26226 27093 33120 34243
84 689 1292 14234 17834 34458 36109 38609 44075
656 1321 1335 9564 11031 20663 28540 33454
2798 3040 3447 10523 15178 16147 17112 23143
2785 2827 3514 3648 5406 8631 21247 36454
983 2859 3241 6313 15981 16459 29725 35759
662 1428 2716 9984 19352 21403 27521 37417
1460 1582 3397 5327 14857 27868 34040 42479
116 353 3081 9834 12252 26703 28884 30421
2275 2449 2838 9493 11608 23271 38776 39806
704 1750 2835 10462 12221 28740 29710 37673
121 2008 2529 16240 19331 23089 25481 36984
1207 1650 2956 6464 10252 30913 31894 38888
1272 2513 2764 6370 8377 8517 31368 41960
1538 1761 2999 21345 26055 30346 34230 35254
1125 1822 2953 6588 14341 16087 19369 25097
60 246 1224 19668 19837 21037 26085 26484
2023 2447 3295 7065 24779 29935 31328 32089
2977 3291 3536 20569 22895 26291 28856 38257
198 1500 1594 8474 12821 24065 24273 25489
829 2542 3457 9560 9981 11130 37448 39505
2452 3433 3465 8505 30616 36656 37451 38882
1828 2189 2401 5065 14917 17648 24809 24869
1674 1760 3256 5017 12401 34198 35372 44967
329 2242 2945 3841 11713 18179 18567 30756
1134 2993 3068 8595 13252 14014 31475 44841
671 1250 2076 18266 23182 24268 32218 33106 33153 35797
532 2267 2927 8343 13630 15565 18426 25262 27191 37728
1363 2100 2454 15244 19187 23000 25655 28410 29916 33402
251 1469 2315 13593 15859 19414 26073 29034 35496 37152
112 1736 2508 5876 14259 14532 21456 35968 37533 42515
25233 26394
5080 6930
12302 41997
27483 36076
5116 36815
11841 28243
18326 37978
22431 36141
35950 40525
41824 42674
It has become.

In the fifth receiving device/method of the present technology, the punctured LDPC code obtained from the data transmitted by the fifth transmission method is decoded.

In a sixth transmission device/method of the present technology, LDPC coding is performed on information bits of information length K=N×r based on an extended parity check matrix in which the rows and columns of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 7/16 are each extended by a predetermined puncture length L, and an extended LDPC code having parity bits of parity length M=N+LK is generated. Furthermore, the head of the information bits of the extended LDPC code is punctured by the puncture length L, and a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 7/16 is generated. The extended parity check matrix includes an A matrix at the top left of the extended parity check matrix, which has M1 rows and K columns and is represented by a predetermined value M1 and the information length K=N×r, a B matrix of a staircase structure adjacent to the right of the A matrix, which has M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, which has M1 rows and N+LK-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which has N+LK-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, which has N+LK-M1 rows and N+LK-M1 columns, wherein the puncture length L is 2160, the predetermined value M1 is 3960, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents the positions of elements of 1 of the A matrix and the C matrix for every 360 columns,
1764 2277 5400 7275 7702 16018 16086 17361 18724 18869 19132 20243 21595 25512 26606 30134 36052 39329 41031
181 1916 4788 5993 10696 12604 13012 24557 24787 25876 26693 28545 32349 33375 35357 36872 37706 38697 40205
1627 3867 5245 5631 6206 7958 12408 14675 15078 16069 20924 24234 29887 31630 32133 34527 34618 35147 37843
1103 2230 7388 9550 10439 11627 13165 14144 18256 22833 26008 26531 28108 28741 29963 31479 31923 39255 39995
1285 2355 4577 6689 10485 12036 16455 18963 19252 23741 30895 31196 35315 36358 36604 38535 39352 40937 40994
3065 4434 5307 7286 7705 9549 9848 11017 11901 12627 17746 21303 23749 24143 25301 25977 32801 37365 38172
434 2357 3026 7873 22006 27928 31085 34076
1003 2078 2558 6023 7076 9453 23248 40783
275 2594 2879 4212 4816 24471 29358 33606
304 2655 3449 9926 16670 32754 33277 38132
657 1983 3058 14006 17331 24307 37692 38764
865 1808 3134 21758 27257 31888 37426 40019
562 1861 3800 12068 20650 30577 33391 39300
97 459 2970 5360 8808 17885 24492 36388
1655 1901 3486 3965 18266 21707 26083 39858
106 2971 3601 4603 17049 21044 24058 34168
105 2632 3687 12222 15389 17985 18580 24844
1067 1887 3012 11816 23805 27159 31152 32102
412 3506 3688 11340 12998 28025 30295 32802
884 2933 3112 19905 33377 35257 38730 39998
3709 3756 3774 7360 10333 13454 15712 24711
58 2494 2959 6474 10296 20685 26935 36360
1854 2850 3654 4678 18001 28593 35963 36270
1830 2363 2518 7949 10035 18345 29534 31920
1646 2020 2811 4203 4779 6289 30475 32063
465 1178 2986 18151 20386 25654 27386 40357
640 2615 3354 8542 14478 25967 25995 37471
1082 1285 3179 18952 26721 27915 37670 40010
1737 1976 2546 7547 20613 23824 25055 32654
741 1013 3328 9668 9749 17082 38386 40974
1268 1476 2671 11835 14049 22600 31513 40179
1045 1108 2992 14156 23244 24154 31043 31798
2421 2602 3798 15389 17884 24140 35871 38752
819 2169 2955 14408 22625 25191 35170 36437
334 922 3167 5119 13570 15530 39099 41014
1221 1589 2395 8195 17835 24255 33626 40708
860 2308 2450 5038 6315 23489 26114 32851
406 1679 3105 14968 19909 27383 37072 40206
633 1863 1959 14480 16090 18913 34193 41012
1488 1699 2837 14716 22731 26859 27454 35998
700 1266 2120 5664 24568 24724 31262 35236
900 1067 2778 5274 15361 17755 22211 33252
1025 2008 2182 7489 7536 15899 18803 24702
383 648 716 5156 6037 9277 30214 38571
389 1155 2887 6102 17079 19192 23080 32918
1471 1635 2511 4547 5272 14725 20498 21659
2171 3539 3896 9346 9694 10999 15963 34494
1994 2216 2771 20692 24115 32560 37794 40140
1080 2162 2696 21197 22485 25015 30419 31363
97 755 1419 13499 16636 31603 35313 40181
1469 1655 3110 9088 10592 17584 19236 26283
2952 3076 3849 10157 14317 15196 16053 35195
1861 3105 3862 3994 5564 6074 8451 19756
3145 3155 3597 14101 15059 15459 27355 32750
259 873 3006 18016 18676 19887 25385 34337
613 1595 3868 5572 14023 20249 31223 38780
200 3129 3397 7639 9614 11741 26530 28039
2223 2694 3117 9231 11140 21370 27439 35476
779 1905 3630 11778 26510 27390 33035 34468
137 624 2206 15239 18045 21398 23580 29951
1327 1763 3312 6477 9861 28455 34353 35567
2717 2763 3044 8185 8380 17045 28844 38259
265 1105 3295 22148 24070 27939 31377 32371
1785 2042 3249 6558 15036 15184 18135 23151
271 1032 1352 4622 18315 19571 24142 24376
2392 2686 3656 7062 22999 24868 27626 28882
2726 3295 3893 19111 21109 26599 35039 37863
1650 1757 2170 5928 12800 22404 22521 23554
474 912 2810 9299 9649 34316 36020 39568
721 3776 3815 8297 28150 29224 33574 35496
2009 2400 3282 14124 16587 22933 22980 28722
132 1845 3587 11790 22121 31459 32442 40951
142 361 1061 4265 11230 16948 17367 27128
1250 2600 3374 8456 12596 28890 34813 40879
738 1025 1617 17079 22449 25340 30369 32737
1876 2731 2841 9438 17215 23350 27295 34083
453 1144 3263 12936 18049 25084 25595 29278
2369 2850 2997 6628 14441 17901 21329 23717
1671 2580 3055 12903 14917 24143 26800 33983
1516 1907 2756 5106 13479 13748 32931
1708 3245 3727
216 2078 2179
137 316 3665
834 2278 3108
5345 33686
11281 26022
17244 34746
20829 33069
32952 37029
38235 38952
12779 36842
5081 34190
8352 9285
37937 39131
21873 26915
It has become.

In the sixth receiving device/method of the present technology, the punctured LDPC code obtained from the data transmitted by the sixth transmission method is decoded.

In the seventh transmission device/method of the present technology, LDPC coding of information bits of information length K=N×r is performed based on an extended parity check matrix in which the rows and columns of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 8/16 are each extended by a predetermined puncture length L, and an extended LDPC code having parity bits of parity length M=N+LK is generated. Furthermore, the head of the information bits of the extended LDPC code is punctured by the puncture length L, and a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 8/16 is generated. The extended parity check matrix includes an A matrix at the top left of the extended parity check matrix, which has M1 rows and K columns and is represented by a predetermined value M1 and the information length K=N×r, a B matrix of a staircase structure adjacent to the right of the A matrix, which has M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, which has M1 rows and N+LK-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which has N+LK-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, which has N+LK-M1 rows and N+LK-M1 columns, wherein the puncture length L is 2520, the predetermined value M1 is 5040, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents the positions of elements of 1 of the A matrix and the C matrix for every 360 columns,
2184 2245 5483 5692 9320 18011 18064 18150 20189 23469 23662 25407 28189 35779 37071
1855 3613 5755 7904 12491 14272 19654 22065 22316 23975 24503 26458 29567 34455 35556
928 4740 6537 8736 9455 16185 18167 22537 22768 26005 32031 32179 33566 34966 35808
3986 4696 5295 8034 12188 12339 14298 19661 22499 22837 28343 29201 30056 36868 36872
1049 2606 9166 13000 17407 22535 24035 24090 26423 27147 28104 29196 34765 36183 36195
2475 2705 6586 10659 14652 15858 18555 22635 25610 26796 32144 33131 35581 37072
1339 1594 5556 5731 5735 7423 7924 8287 10173 21406 26174 26965 30831 35028
2095 2692 4542 11957 16923 21339 22995 35510
753 3913 4481 24115 25745 28475 29334 34983
531 2404 4091 6823 7730 13085 21741 25943
764 2602 5000 5777 6649 28284 28457 30648
173 2884 3453 7716 16017 26720 33781 34558
804 3989 4026 10353 16302 20995 22614 29946
1369 1438 4721 11804 19454 24989 29745 33895
2413 3865 4900 9605 12227 19796 34068 35639
2280 3614 3994 5794 8725 17288 29042 32667
189 729 2807 18569 20422 29775 33106 35601
13 1942 3075 5647 16437 28792 33944 36951
2322 2774 4133 14911 23058 26276 35482 36145
1156 1915 1988 13753 20275 22750 28129 28615
1027 3254 3826 12792 25306 33398 34900 36579
1000 3662 3934 12247 28784 30051 30448 34971
2208 4777 4895 7995 15270 34546 35050 35465
865 1301 2776 5447 7236 25204 28825 33009
931 2280 3123 18312 20000 26379 29091 35547
161 313 1976 10118 19510 24067 25236 29200
495 2033 3478 18349 21388 27692 27945 29298
40 123 466 8627 14489 23804 25266 29217
1919 2239 5036 9020 10230 13401 26202 31868
2984 2990 4559 13817 15317 17982 24664 30694
4263 4578 4900 18514 19432 21056 22195 25540
486 2865 4044 10378 16367 19558 31611 37057
773 785 4692 13690 15318 17028 26614 28889
1128 2525 4918 13514 14018 21695 28403 28447
1378 2785 3945 19557 24360 26125 32618 35109
1622 2734 4728 21208 22587 28908 32086 34795
1490 2885 4429 7668 12440 13368 15096 30591
157 4782 5028 7007 8693 14921 17912 24354
1887 2821 4004 5990 7023 11617 23891 31527
2659 3026 3929 8247 18589 18766 25496 30000
1493 4505 4919 10166 15487 19375 20018 37009
1459 2038 4184 13922 16641 25405 27889 36692
2552 3118 4424 10018 10774 20992 21805 22999
1575 3751 4248 12315 13683 16910 20849 27503
169 1552 4011 8140 13348 21198 22677 22961
485 1610 2021 6883 8078 10259 10833 36872
717 3562 4705 8210 14216 16365 30074 30100
284 2060 2603 5600 6111 16526 16904 25280
1464 2306 2405 15402 22597 31453 33154 36507
793 858 958 19518 21177 22969 27465 34316
2755 4039 4916 13740 21014 22548 23393 27868
2346 2859 3724 5804 11163 13257 16059 16537
3034 3827 4257 10753 10848 16863 17910 30215
699 2077 3036 14789 28159 29959 32060 35741
842 1479 1651 8903 20126 29843 30172 36359
60 216 2154 13804 29952 30425 30451 33882
1561 2138 3179 7117 10997 17696 18819 29502
1929 2926 4119 6462 9997 17945 19143 35222
1408 3721 4733 6077 8220 23897 24532 32454
758 1062 3265 22844 25290 26795 30309 32198
723 974 2366 11325 11639 20444 30190 33000
3057 3184 4157 6124 10032 14829 22920 27535
1908 2681 3314 10175 15746 19286 30891 31312
337 3329 4284 16428 26550 26938 27394 29675
601 626 4671 7188 18716 20787 25752 31716
2736 3729 3853 14610 18790 21261 31327
1514 1926 2616 7216 7346 13375 15951
385 2731 2776 17442 17618 18488 26842
2847 3447 4837 7730 21494 25421 27060
4167 4675 4950 18125 19852 24594 31885
2100 2258 2839 6788 12190 20838 22037
598 1160 2512 9977 27667 31266 35818
726 918 4356 25915 26856 35644 35900
603 4023 4286 21322 24461 26414 31230
1378 1712 2601 6187 19972 21466 33990
2477 3873 5026 6147 11847 28736 31098
458 983 3395 5246 16300 16685 26054
1591 4194 4296 8941 12584 26579 36950
956 1266 1722 21007 23498 27878 29947
1791 2382 3477 27827
753 1172 3171 21799
577 1793 4156 14329
1221 1909 2872 23737
3201 3437 3627 24180
1422 2384 2680 17127
350 2057 3244 29775
1494 3096 4085 12712
1925 2736 3505 20471
167 1300 1330 30100
2178 4141 4741 6802
169 2635 2776 7608
1061 3955 4667 23473
185 995 4044 24130
1792 2284 4178 30200
3947 4503 4756 34653
1198 4107 4470 5969
9656
8810
34388
35438
20498
24839
23256
9966
25861
11305
7639
21600
13763
25619
It has become.

In the seventh receiving device/method of the present technology, the punctured LDPC code obtained from the data transmitted by the seventh transmission method is decoded.

In the eighth transmission device/method of the present technology, LDPC coding of information bits of information length K=N×r is performed based on an extended parity check matrix in which the rows and columns of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 9/16 are each extended by a predetermined puncture length L, and an extended LDPC code having parity bits of parity length M=N+LK is generated. Furthermore, the head of the information bits of the extended LDPC code is punctured by the puncture length L, and a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 9/16 is generated. The extended parity check matrix includes an A matrix at the top left of the extended parity check matrix, which has M1 rows and K columns and is represented by a predetermined value M1 and the information length K=N×r, a B matrix of a staircase structure adjacent to the right of the A matrix, which has M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, which has M1 rows and N+LK-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which has N+LK-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, which has N+LK-M1 rows and N+LK-M1 columns, wherein the puncture length L is 1800, the predetermined value M1 is 9000, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents the positions of elements of 1 of the A matrix and the C matrix every 360 columns,
3681 3750 3985 4255 8583 9468 12078 12353 15700 16492 17127 18174 18264 22392 23070 25263 29195 32034
804 4119 5315 5489 8261 9514 10099 10268 14359 16861 21050 21439 23880 24274 26637 30518 30944 31195
3684 4224 4412 7772 8017 10100 12529 15888 16518 18089 19685 28054 28297 28345 28897 29827 30402 31794
2013 2073 4993 6278 6716 10271 13971 14141 14727 17892 21649 22734 24394 25979 26485 30156 30617 31322
671 4057 4827 6795 8726 11791 15912 16773 16823 21296 24678 28589 29419 30212 30976 31701 32035
2831 3625 4812 9421 10678 11313 11919 13859 24185 26543
105 197 4569 12767 18835 20708 21307 21922 29762 30542
1939 3334 7927 12368 22520 24007 25355 26414 27639 30526
935 4228 7324 10281 10930 14811 20832 21012 24721 31868
451 1279 6541 9174 9524 23917 24447 24765 27400 30105
596 3093 7695 12690 12805 20513 26844 26874 27238 30238
3165 4948 8257 13864 15261 19334 23340 27303 29834 30592
4311 6608 8867 12314 17011 19562 29621 29653 29867 31831
246 1043 4063 9880 12133 14403 17673 21772 26756 28865
3800 4310 7891 9005 17892 22752 29776 30960 31922
169 3202 6707 9267 19608 21494 24264 27783 30896
2756 3526 5061 14144 15208 17722 19974 23683 25622
5640 6672 8062 10253 14587 17029 23586 29354 30935
1780 6399 7013 13407 14129 26025 27047 27302 28430
3867 8295 8448 11173 12961 16355 23417 30645 30840
114 2303 5658 10578 12954 19396 23278 26133 29150
4205 6484 8154 9468 9855 17738 25225 28855 29327
4064 5671 6785 11073 12684 17900 18543 24915 25278
4591 6432 6812 9172 9497 10443 11612 15805 26385
3429 5317 5699 11875 12763 19252 24194 28715 31645
2334 5348 8140 15322 16398 18377 22674 23119 27452
5806 8178 8750 18695 19361 20500 21337 23747 26594
868 5108 7470 12695 12827 13362 17150 30388 32036
1401 3377 6069 13887 15223 16423 20548 26114 31525
2388 2511 6647 15288 20979 21546 22893 25768 26293
5918 7740 8309 16069 17648 21533 21638 30421 30592
4531 6710 7575 10870 14321 15801 22289 27422 29206
282 2349 2823 16122 18235 22889 30845 31790 32028
1028 3364 7170 9696 10463 13676 21633 22408 22987
4747 5376 7037 11344 18790 18904 23562 26963 29547
2666 4221 8779 12684 15548 16845 19631 27773 32000
3277 3636 6417 15359 20686 23258 23607 28911 31760
1394 1613 4705 10030 14240 20469 21907 25971 28392
2428 3334 6308 9823 14969 16081 20361 21680 27204
870 4539 5033 11210 11227 12757 13164 16363 18278
519 8424 8966 11266 12282 15631 17138 25283 27009
562 4648 7031 9367 9769 17258 17524 18469 23544
2607 4017 4276 12525 16477 21617 28004 29179 31638
1311 1705 6279 19425 20643 21524 21927 26759 30022
2440 5160 8827 19724 20470 21579 22088 25426 26076
247 1718 3238 15685 16926 26381 27070 28504 31522
1646 3308 3325 12196 13145 18495 22879 25613 31074
2777 6991 7582 12852 15441 16518 19845 27107 31491
24 1098 6964 10014
3834 7138 8104 27290
2467 2695 6985 23538
597 1655 2786 26365
3412 3568 3869 22313
1378 3631 7350 30759
396 2426 3965 30636
294 5276 6622 28723
889 5479 5831 13814
1355 5011 7082 24636
1737 5683 7638 12279
4248 4328 7871 13506
1867 5466 7068 23531
1400 5020 7410 9775
2727 3409 6324 21177
4027 4240 7262 16737
1442 7380 7650 24201
601 6169 6278 26698
1070 3198 6038 11626
616 3835 8339 28168
4424 5809 6656 26638
3857 4561 4879 27896
2696 2722 4665 17776
643 2333 3072 10579
232 4876 4956 18710
3486 3535 6104 29906
774 5073 6030 23656
4617 6194 7445 31653
4163 5489 8227 28295
3675 3991 4940 18635
496 2003 4758 20333
1062 2059 4493 25301
1380 7374 8642 28926
1294 1639 8662 30961
5866 6147 7653 11713
5458 7184 7361 20695
2463 4602 6018 16857
320 4682 8140 19724
4410 6923 8975 26037
306 1921 7301 11104
57 1768 5604 17338
2839 3153 5912 28608
1091 6051 7495 31918
1681 2099 2259 16924
4490 5186 6994 25446
3188 4252 6208 25437
1342 5660 7305 21071
1048 3204 7421 15675
2197 3412 5125 22484
5721 6143 6479 22800
2531 4216 4794 17691
628 3665 5783 26756
2660 5527 7289 14552
3432 4895 6255 20101
288 2324 2375 27024
3898 7386 8459 10265
301 4717 4972 10844
1895 7065 8334 22255
331 1779 7214 22726
3202 4096 7467 27090
27017
29554
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29460
27770
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30095
30852
20107
23269
22090
12537
23969
13527
10911
20907
15272
23822
31661
13732
21787
It has become.

In the eighth receiving device/method of the present technology, the punctured LDPC code obtained from the data transmitted by the eighth transmission method is decoded.

The transmitting device and the receiving device may be independent devices or may be internal blocks constituting a single device.

This technology makes it possible to ensure good communication quality in data transmission using LDPC codes.

Note that the effects described here are not necessarily limited to those described herein and may be any of the effects described in this disclosure.

FIG. 2 is a diagram illustrating a check matrix H of an LDPC code. 1 is a flowchart illustrating a procedure for decoding an LDPC code. FIG. 2 is a diagram illustrating an example of a check matrix of an LDPC code. FIG. 13 is a diagram illustrating an example of a Tanner graph of a parity check matrix. FIG. 13 is a diagram illustrating an example of a variable node. FIG. 2 is a diagram illustrating an example of a check node. 1 is a diagram illustrating an example of the configuration of an embodiment of a transmission system to which the present technology is applied. 2 is a block diagram showing a configuration example of a transmitting device 11. FIG. 13 is a block diagram showing an example of the configuration of a bit interleaver 116. FIG. FIG. 13 is a diagram illustrating an example of a check matrix. FIG. 13 is a diagram illustrating an example of a parity matrix. 1 is a diagram illustrating a check matrix of an LDPC code defined in the DVB-T.2 standard. 1 is a diagram illustrating a check matrix of an LDPC code defined in the DVB-T.2 standard. FIG. 1 is a diagram illustrating an example of a Tanner graph for decoding an LDPC code. FIG. 1 is a diagram showing an example of a parity matrix H _T having a staircase structure and a Tanner graph corresponding to the parity matrix H _T. 11 is a diagram showing an example of a parity matrix H _T of a check matrix H corresponding to an LDPC code after parity interleaving. FIG. 11 is a flowchart illustrating an example of processing performed by a bit interleaver 116 and a mapper 117. 2 is a block diagram showing an example of the configuration of an LDPC encoder 115. FIG. 11 is a flowchart illustrating an example of a process of the LDPC encoder 115. FIG. 13 is a diagram showing an example of a parity check matrix initial value table with a coding rate of 1/4 and a code length of 16200. 11 is a diagram for explaining a method of obtaining a check matrix H from a check matrix initial value table. FIG. FIG. 2 is a diagram illustrating a structure of a check matrix. FIG. 13 is a diagram illustrating an example of a check matrix initial value table. 13 is a diagram illustrating a matrix A generated from a check matrix initial value table. FIG. FIG. 1 is a diagram for explaining parity interleaving of a B matrix. 11 is a diagram illustrating a C matrix generated from a check matrix initial value table. FIG. FIG. 1 is a diagram for explaining parity interleaving of a D matrix. FIG. 13 is a diagram showing a parity check matrix obtained by performing column permutation as parity deinterleaving to restore parity interleaving to its original state. FIG. 13 is a diagram showing a transformed check matrix obtained by performing row permutation on a check matrix. FIG. 13 is a diagram showing an example of a Tanner graph of an ensemble of degree sequences with column weight 3 and row weight 6. FIG. 13 is a diagram showing an example of a Tanner graph of a multi-edge type ensemble. FIG. 11 is a diagram illustrating an example of coordinates of a UC signal point when the modulation method is QPSK. FIG. 11 is a diagram showing an example of the coordinates of signal points of a 2D-NUC when the modulation method is 16QAM. FIG. 11 is a diagram showing an example of the coordinates of signal points of 1D-NUC when the modulation method is 1024QAM. FIG. 1 is a diagram showing the relationship between a 1024QAM symbol y and a position vector u. FIG. 1 is a diagram illustrating an example of coordinates z and _q of signal points of QPSK-UC. FIG. 1 is a diagram illustrating an example of coordinates z and _q of signal points of QPSK-UC. FIG. 1 is a diagram illustrating an example of coordinates z _{and q} of 16QAM-UC signal points. FIG. 1 is a diagram illustrating an example of coordinates z _{and q} of 16QAM-UC signal points. FIG. 13 is a diagram illustrating an example of coordinates z _{and q} of 64QAM-UC signal points. FIG. 13 is a diagram illustrating an example of coordinates z _{and q} of 64QAM-UC signal points. FIG. 13 is a diagram illustrating an example of coordinates z _{and q} of signal points of 256QAM-UC. FIG. 13 is a diagram illustrating an example of coordinates z _{and q} of signal points of 256QAM-UC. FIG. 13 is a diagram illustrating an example of coordinates z _{and q} of 1024QAM-UC signal points. FIG. 13 is a diagram illustrating an example of coordinates z _{and q} of 1024QAM-UC signal points. FIG. 13 is a diagram illustrating an example of coordinates z _{and q} of 4096QAM-UC signal points. FIG. 13 is a diagram illustrating an example of coordinates z _{and q} of 4096QAM-UC signal points. FIG. 13 is a diagram illustrating an example of coordinates _zs of a signal point of 16QAM-2D-NUC. FIG. 13 is a diagram illustrating an example of coordinates _zs of signal points of 64QAM-2D-NUC. FIG. 13 is a diagram illustrating an example of coordinates _zs of signal points of 256QAM-2D-NUC. FIG. 13 is a diagram illustrating an example of coordinates _zs of signal points of 256QAM-2D-NUC. FIG. 11 is a diagram illustrating an example of coordinates _zs of a signal point of 1024QAM-1D-NUC. FIG. 1 is a diagram showing the relationship between a 1024QAM symbol y and a position vector u. FIG. 13 is a diagram showing an example of coordinates _zs of signal points of 4096QAM-1D-NUC. 1 is a diagram showing the relationship between a 4096QAM symbol y and a position vector u. 1 is a diagram showing the relationship between a 4096QAM symbol y and a position vector u. FIG. 2 is a diagram for explaining block interleaving performed by the block interleaver 25. FIG. 2 is a diagram for explaining block interleaving performed by the block interleaver 25. 11 is a diagram illustrating group-wise interleaving performed by group-wise interleaver 24. FIG. FIG. 13 is a diagram illustrating an example of a GW pattern for an LDPC code having a code length N of 69120 bits. 2 is a block diagram showing a configuration example of a receiving device 12. FIG. 13 is a block diagram showing an example of the configuration of a bit deinterleaver 165. FIG. 11 is a flowchart illustrating an example of processing performed by a demapper 164, a bit deinterleaver 165, and an LDPC decoder 166. FIG. 2 is a diagram illustrating an example of a check matrix of an LDPC code. 11 is a diagram showing an example of a matrix (transformed parity check matrix) obtained by performing row permutation and column permutation on a parity check matrix; FIG. FIG. 13 is a diagram showing an example of a transformed check matrix divided into 5×5 units. FIG. 11 is a block diagram showing an example of the configuration of a decoding device that performs P node operations collectively. 13 is a block diagram showing an example of the configuration of an LDPC decoder 166. FIG. 11 is a diagram for explaining block deinterleaving performed by block deinterleaver 54. FIG. 13 is a block diagram showing another example configuration of the bit deinterleaver 165. FIG. 1 is a block diagram showing a first exemplary configuration of a receiving system to which a receiving device 12 can be applied. 11 is a block diagram showing a second exemplary configuration of a receiving system to which the receiving device 12 can be applied. FIG. FIG. 13 is a block diagram showing a third exemplary configuration of a receiving system to which the receiving device 12 can be applied. FIG. 1 is a diagram illustrating a punctured LDPC code. 1 is a diagram illustrating a structure of an extended parity check matrix of the Type A method for encoding K information bits into an extended LDPC code of N+L bits. 1 is a diagram illustrating a structure of an extended parity check matrix of the Type B method for encoding K information bits into an extended LDPC code of N+L bits. 11 is a flowchart illustrating an example of processing (encoding processing) of the LDPC encoder 115 when a punctured LDPC code with a code length N=69120 is used for data transmission. 13 is a flowchart illustrating an example of processing (decoding processing) of the LDPC decoder 166 when a punctured LDPC code with a code length N=69120 is used for data transmission. 13 is a diagram showing an example of a check matrix initial value table representing a type-A extended check matrix of a type-A extended LDPC code for (69k, 2/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-A extended check matrix of a type-A extended LDPC code for (69k, 2/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-A extended check matrix of a type-A extended LDPC code for (69k, 3/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-A extended check matrix of a type-A extended LDPC code for (69k, 3/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-A extended check matrix of a type-A extended LDPC code for (69k, 4/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-A extended check matrix of a type-A extended LDPC code for (69k, 4/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-A extended check matrix of a type-A extended LDPC code for (69k, 5/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-A extended check matrix of a type-A extended LDPC code for (69k, 5/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-A extended check matrix of a type-A extended LDPC code for (69k, 6/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-A extended check matrix of a type-A extended LDPC code for (69k, 6/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-A extended check matrix of a type-A extended LDPC code for (69k, 7/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-A extended check matrix of a type-A extended LDPC code for (69k, 7/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-A extended check matrix of a type-A extended LDPC code for (69k, 7/16). FIG. FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-A extended check matrix of a type-A extended LDPC code for (69k, 8/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-A extended check matrix of a type-A extended LDPC code for (69k, 8/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-A extended check matrix of a type-A extended LDPC code for (69k, 8/16). 13 is a diagram showing an example of a check matrix initial value table representing a type-A extended check matrix of a type-A extended LDPC code for (69k, 9/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-A extended check matrix of a type-A extended LDPC code for (69k, 9/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-A extended check matrix of a type-A extended LDPC code for (69k, 9/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-A extended check matrix of a type-A extended LDPC code for (69k, 9/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-B extended check matrix of a type-B extended LDPC code for (69k, 9/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-B extended check matrix of a type-B extended LDPC code for (69k, 9/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-B extended check matrix of a type-B extended LDPC code for (69k, 9/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-B extended check matrix of a type-B extended LDPC code for (69k,10/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-B extended check matrix of a type-B extended LDPC code for (69k,10/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-B extended check matrix of a type-B extended LDPC code for (69k,10/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-B extended check matrix of a type-B extended LDPC code for (69k,10/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-B extended check matrix of a type-B extended LDPC code for (69k,11/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-B extended check matrix of a type-B extended LDPC code for (69k,11/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-B extended check matrix of a type-B extended LDPC code for (69k,11/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-B extended check matrix of a type-B extended LDPC code for (69k,11/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-B extended check matrix of a type-B extended LDPC code for (69k, 12/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-B extended check matrix of a type-B extended LDPC code for (69k, 12/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-B extended check matrix of a type-B extended LDPC code for (69k, 12/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-B extended check matrix of a type-B extended LDPC code for (69k, 12/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-B extended check matrix of a type-B extended LDPC code for (69k,13/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-B extended check matrix of a type-B extended LDPC code for (69k,13/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-B extended check matrix of a type-B extended LDPC code for (69k,13/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-B extended check matrix of a type-B extended LDPC code for (69k,13/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-B extended check matrix of a type-B extended LDPC code for (69k,14/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-B extended check matrix of a type-B extended LDPC code for (69k,14/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-B extended check matrix of a type-B extended LDPC code for (69k,14/16). FIG. 13 is a diagram showing an example of a check matrix initial value table representing a type-B extended check matrix of a type-B extended LDPC code for (69k,14/16). FIG. 11 is a diagram for explaining column weights of a type-A extended parity check matrix represented by a parity check matrix initial value table of the type-A method. FIG. 13 is a diagram showing parameters of a type-A extended parity check matrix represented by a parity check matrix initial value table of the type-A method. FIG. 11 is a diagram for explaining column weights of a type-B extended parity check matrix represented by a parity check matrix initial value table of the type-B method. FIG. 13 is a diagram showing parameters of a type-B extended parity check matrix represented by a parity check matrix initial value table of the type-B method. FIG. 1 is a block diagram showing an example of the configuration of an embodiment of a computer to which the present technology is applied.

Below, we will explain the embodiment of this technology, but first we will explain LDPC codes.

<LDPC code>

Note that LDPC codes are linear codes and do not necessarily have to be binary, but here we will explain them as being binary.

The most distinctive feature of LDPC codes is that the parity check matrix that defines them is sparse. Here, a sparse matrix is a matrix with an extremely small number of "1" elements (a matrix with most elements being 0).

Figure 1 shows an example of a check matrix H for an LDPC code.

In the check matrix H in Figure 1, the weight of each column (column weight) (number of "1s") is "3", and the weight of each row (row weight) is "6".

In coding using LDPC codes (LDPC coding), for example, a generator matrix G is generated based on a check matrix H, and then a codeword (LDPC code) is generated by multiplying binary information bits by this generator matrix G.

Specifically, an encoding device that performs LDPC encoding first calculates a generator matrix G such that the equation GH ^T =0 holds between the generator matrix G and a transposed matrix H ^T of a check matrix H. Here, when the generator matrix G is a K×N matrix, the encoding device multiplies the generator matrix G by a bit string (vector u) of K information bits to generate a codeword c (=uG) consisting of N bits. The codeword (LDPC code) generated by this encoding device is received at the receiving side via a predetermined communication path.

Decoding of LDPC codes is an algorithm proposed by Gallager called Probabilistic Decoding, and can be performed by a message passing algorithm using belief propagation on a Tanner graph consisting of variable nodes (also called message nodes) and check nodes. Hereinafter, variable nodes and check nodes will be referred to simply as nodes where appropriate.

Figure 2 is a flowchart showing the procedure for decoding an LDPC code.

In the following description, the real value (received LLR) representing the likelihood of the value of the i-th code bit of the LDPC code (one code word) received by the receiving side being "0" using the log likelihood ratio is also referred to as the received value u _0i . Also, the message output from the check node is u _j , and the message output from the variable node is v _i .

First, in decoding an LDPC code, as shown in Fig. 2, in step S11, an LDPC code is received, a message (check node message) _uj is initialized to "0", and a variable k, which is an integer and serves as a counter for repeated processing, is initialized to "0", and the process proceeds to step S12. In step S12, a message (variable node message) _vj is obtained by performing an operation (variable node operation) shown in formula (1) based on a received value _u0i obtained by receiving the LDPC code, and further, a message _uj is obtained by performing an operation (check node operation) shown in formula (2) based on this message _vj .

・・・（１）

...(1)

・・・（２）

... (2)

Here, _dv and _dc in formula (1) and formula (2) are arbitrarily selectable parameters indicating the number of "1"s in the vertical direction (columns) and horizontal direction (rows), respectively, of the check matrix H. For example, in the case of an LDPC code ((3,6) LDPC code) for a check matrix H having a column _weight of 3 and a _row weight of 6 as shown in FIG.

In the variable node operation of formula (1) and the check node operation of formula (2), messages input from edges (lines connecting variable nodes and check nodes) that are to output messages are not included in the operation, so the operation range is 1 to _dv -1 or 1 to _dc -1. In reality, the check node operation of formula (2) is performed by creating in advance a table of function R( _v1 , _v2 ) shown in formula (3), which is defined as one output for two inputs _v1 and _v2 , and using this continuously (recursively) as shown in formula (4).

・・・（３）

...(3)

・・・（４）

...(4)

In step S12, the variable k is further incremented by "1" and the process proceeds to step S13. In step S13, it is determined whether the variable k is greater than a predetermined number of iterative decoding cycles C. If it is determined in step S13 that the variable k is not greater than C, the process returns to step S12 and the same process is repeated.

Also, if it is determined in step S13 that the variable k is greater than C, the process proceeds to step S14, where the message v _i is calculated as the final decoded result by performing the calculation shown in equation (5) and output, and the decoding process of the LDPC code is completed.

・・・（５）

...(5)

Here, the calculation of equation (5) differs from the variable node calculation of equation (1) in that it is performed using messages u _j from all edges connected to the variable node.

Figure 3 shows an example of a check matrix H for a (3,6) LDPC code (coding rate 1/2, code length 12).

In the check matrix H in Figure 3, the column weight is 3 and the row weight is 6, just like in Figure 1.

Figure 4 shows the Tanner graph of the check matrix H in Figure 3.

In Figure 4, a plus sign "+" indicates a check node, and an equal sign "=" indicates a variable node. The check nodes and variable nodes correspond to the rows and columns of the parity check matrix H, respectively. The connection between the check nodes and variable nodes is an edge, which corresponds to the element "1" of the parity check matrix.

In other words, if the element in the jth row and ith column of the parity check matrix is 1, then in FIG. 4, the i-th variable node from the top (the "=" node) and the j-th check node from the top (the "+" node) are connected by a branch. The branch indicates that the code bit corresponding to the variable node has a constraint corresponding to the check node.

The Sum Product Algorithm, a method for decoding LDPC codes, involves repeated variable node calculations and check node calculations.

Figure 5 shows the variable node calculations performed at the variable node.

In the variable node, the message v _i corresponding to the branch to be calculated is calculated by the variable node calculation of formula (1) using the messages u ₁ and u ₂ from the remaining branches connected to the variable node and the received value u _{0 i} . Messages corresponding to other branches are calculated in the same manner.

Figure 6 shows the check node operations performed at a check node.

The check node operation in formula (2) can be rewritten as formula (6) using the relationship of the formula a×b＝exp{ln(|a|)+ln(|b|)}×sign(a)×sign(b). Note that sign(x) is 1 when x≧0 and -1 when x＜0.

・・・（６）

...(6)

If the function φ(x) is defined as φ(x) = ln(tanh(x/2)) for x≧0, then the equation φ ^-1 (x) = 2tanh ^-1 (e ^-x ) holds, so equation (6) can be transformed into equation (7).

・・・（７）

...(7)

At the check node, the check node operation of equation (2) is performed according to equation (7).

That is, in the check node, as shown in Fig. 6, the message _uj corresponding to the edge to be calculated is obtained by the check node calculation of formula (7) using the messages _v1 , _v2 , _v3 , _v4 , and _v5 from the remaining edges connected to the check node. Messages corresponding to other edges are obtained in the same manner.

The function φ(x) in equation (7) can be expressed as φ(x) = ln((e ^x +1)/(e ^x -1)), where φ(x) = φ ^-1 (x) for x > 0. When implementing the functions φ(x) and φ ^-1 (x) in hardware, they may be implemented using a Look Up Table (LUT), but both of them use the same LUT.

<Example of a transmission system configuration using this technology>

Figure 7 shows an example of the configuration of one embodiment of a transmission system to which the present technology is applied (a system refers to a logical collection of multiple devices, and it does not matter whether the devices are in the same housing or not).

In FIG. 7, the transmission system is composed of a transmitting device 11 and a receiving device 12.

The transmitting device 11 transmits (broadcasts) (transmits), for example, television broadcast programs. That is, the transmitting device 11 encodes the target data to be transmitted, such as image data and audio data as a program, into an LDPC code, and transmits it via a communication path 13, such as a satellite line, terrestrial wave, or cable (wired line).

The receiving device 12 receives the LDPC code transmitted from the transmitting device 11 via the communication path 13, decodes it into the target data, and outputs it.

The LDPC code used in the transmission system in Figure 7 is known to have extremely high performance in AWGN (Additive White Gaussian Noise) communication channels.

On the other hand, burst errors and erasures may occur in the communication path 13. For example, in an OFDM (Orthogonal Frequency Division Multiplexing) system, particularly when the communication path 13 is terrestrial, in a multipath environment where the D/U (Desired to Undesired Ratio) is 0 dB (Undesired = echo power is equal to Desired = main path power), the power of a particular symbol may become 0 (erasure) depending on the delay of the echo (path other than the main path).

Even in a flutter channel (a channel with zero delay and an echo with a Doppler frequency added), if the D/U is 0 dB, the power of the entire OFDM symbol at a specific time may be eradicated due to the Doppler frequency.

Furthermore, burst errors may occur due to the condition of the wiring from a receiving section (not shown) such as an antenna that receives signals from the transmitting device 11 to the receiving device 12, or due to instability in the power supply of the receiving device 12.

On the other hand, in decoding an LDPC code, in the variable nodes corresponding to the columns of the check matrix H, and in turn to the code bits of the LDPC code, as shown in FIG. 5, a variable node operation of the formula (1) involving the addition of the code bits of the LDPC code (received value u _0i ) is performed. Therefore, if an error occurs in the code bits used in the variable node operation, the accuracy of the required message decreases.

In decoding an LDPC code, the check node calculation of equation (7) is performed at a check node using the message obtained at the variable node connected to that check node. Therefore, if there are a large number of check nodes where multiple connected variable nodes (corresponding code bits of the LDPC code) have errors (including erasures) at the same time, the decoding performance deteriorates.

That is, for example, when two or more variable nodes connected to a check node are simultaneously erased, the check node returns to all variable nodes a message with equal probability of the value being 0 and the value being 1. In this case, the check node returning the equally probable message does not contribute to one decoding process (one set of variable node calculations and check node calculations), and as a result, the decoding process needs to be repeated many times, degrading the decoding performance and increasing the power consumption of the receiving device 12 that decodes the LDPC code.

Therefore, the transmission system in Figure 7 is capable of improving tolerance to burst errors and erasures while maintaining performance on an AWGN communication path (AWGN channel).

<Example of the configuration of the transmitting device 11>

Figure 8 is a block diagram showing an example configuration of the transmitting device 11 in Figure 7.

In the transmitting device 11, one or more input streams as target data are supplied to a mode adaptation/multiplexer 111.

The mode adaptation/multiplexer 111 performs processing such as mode selection and multiplexing of one or more input streams supplied to it as necessary, and supplies the resulting data to the padder 112.

The padder 112 performs the necessary zero padding (insertion of nulls) on the data from the mode adaptation/multiplexer 111 and supplies the resulting data to the BB scrambler 113.

The BB scrambler 113 performs BB scrambling (Base-Band Scrambling) on the data from the padder 112 and supplies the resulting data to the BCH encoder 114.

The BCH encoder 114 BCH-encodes the data from the BB scrambler 113 and supplies the resulting data to the LDPC encoder 115 as LDPC target data to be LDPC-encoded.

The LDPC encoder 115 performs LDPC encoding on the LDPC target data from the BCH encoder 114, for example, according to a check matrix in which the parity matrix, which is the part corresponding to the parity bits of the LDPC code, has a dual diagonal structure, and outputs an LDPC code in which the LDPC target data is information bits.

That is, the LDPC encoder 115 performs LDPC encoding to encode the LDPC target data into an LDPC code (corresponding to a parity check matrix) specified in a specific standard such as DVB-S.2, DVB-T.2, DVB-C.2, or ATSC3.0, or into another LDPC code, and outputs the resulting LDPC code.

The LDPC codes specified in the DVB-S.2 and ATSC3.0 standards, and the LDPC codes planned for adoption in ATSC3.0, are IRA (Irregular Repeat Accumulate) codes, and the parity matrix (part or all) in the check matrix of the LDPC code has a staircase structure. The parity matrix and the staircase structure will be described later. The IRA codes are described, for example, in "Irregular Repeat-Accumulate Codes," H. Jin, A. Khandekar, and R. J. McEliece, in Proceedings of 2nd International Symposium on Turbo codes and Related Topics, pp. 1-8, Sept. 2000.

The LDPC code output by the LDPC encoder 115 is supplied to the bit interleaver 116.

The bit interleaver 116 performs bit interleaving (described below) on the LDPC code from the LDPC encoder 115, and supplies the bit-interleaved LDPC code to the mapper 117.

The mapper 117 performs orthogonal modulation (multi-level modulation) by mapping the LDPC code from the bit interleaver 116 to a signal point representing one symbol of orthogonal modulation in units of one or more code bits (symbol units) of the LDPC code.

That is, the mapper 117 performs orthogonal modulation by mapping the LDPC code from the bit interleaver 116 to a signal point determined by a modulation method that performs orthogonal modulation of the LDPC code on a constellation that is an IQ plane defined by an I axis representing an I component that is in phase with the carrier wave and a Q axis representing a Q component that is orthogonal to the carrier wave.

When the number of signal points of a constellation used in the modulation method of orthogonal modulation performed in mapper 117 is ^2m , m code bits of the LDPC code are regarded as a symbol (1 symbol), and mapper 117 maps the LDPC code from bit interleaver 116 to a signal point representing a symbol among the ^2m signal points on a symbol-by-symbol basis.

The modulation method of the orthogonal modulation performed by the mapper 117 may be, for example, the modulation method defined in the DVB-S.2 or ATSC3.0 standard, or other modulation methods, such as BPSK (Binary Phase Shift Keying), QPSK (Quadrature Phase Shift Keying), 8PSK (Phase-Shift Keying), 16APSK (Amplitude Phase-Shift Keying), 32APSK, 16QAM (Quadrature Amplitude Modulation), 16QAM, 64QAM, 256QAM, 1024QAM, 4096QAM, 4PAM (Pulse Amplitude Modulation), etc. The modulation method used for the orthogonal modulation in the mapper 117 is preset, for example, according to the operation of the operator of the transmitting device 11.

The data obtained by processing in the mapper 117 (the mapping result of mapping symbols to signal points) is supplied to the time interleaver 118.

The time interleaver 118 performs time interleaving (interleaving in the time direction) on a symbol-by-symbol basis on the data from the mapper 117, and supplies the resulting data to a SISO/MISO (Single Input Single Output/Multiple Input Single Output) encoder 119.

The SISO/MISO encoder 119 performs space-time coding on the data from the time interleaver 118 and supplies it to the frequency interleaver 120.

The frequency interleaver 120 performs frequency interleaving (interleaving in the frequency direction) on a symbol-by-symbol basis on the data from the SISO/MISO encoder 119 and supplies it to the frame builder/resource allocation unit (Frame Builder & Resource Allocation) 131.

On the other hand, the BCH encoder 121 is supplied with control data (signalling) for transmission control, such as BB signaling (Base Band Signalling) (BB Header).

The BCH encoder 121 BCH-encodes the control data supplied thereto in the same manner as the BCH encoder 114, and supplies the resulting data to the LDPC encoder 122.

The LDPC encoder 122 LDPC-encodes the data from the BCH encoder 121 as LDPC target data in the same manner as the LDPC encoder 115, and supplies the resulting LDPC code to the mapper 123.

Similar to mapper 117, mapper 123 performs orthogonal modulation by mapping the LDPC code from LDPC encoder 122 to a signal point representing one symbol of orthogonal modulation in units of one or more code bits (symbol units) of the LDPC code, and supplies the resulting data to frequency interleaver 124.

Similar to the frequency interleaver 120, the frequency interleaver 124 performs frequency interleaving on a symbol-by-symbol basis on the data from the mapper 123 and supplies it to the frame builder/resource allocation unit 131.

The frame builder/resource allocation unit 131 inserts pilot symbols into the necessary positions of the data (symbols) from the frequency interleavers 120 and 124, and constructs a frame (e.g., a PL (Physical Layer) frame, a T2 frame, a C2 frame, etc.) consisting of a predetermined number of symbols from the resulting data (symbols), and supplies it to the OFDM generation unit (OFDM generation) 132.

The OFDM generation unit 132 generates an OFDM signal corresponding to the frame from the frame builder/resource allocation unit 131 and transmits it via the communication path 13 (Figure 7).

The transmitting device 11 can be configured without some of the blocks shown in FIG. 8, such as the time interleaver 118, the SISO/MISO encoder 119, the frequency interleaver 120, and the frequency interleaver 124.

<Example of the configuration of bit interleaver 116>

Figure 9 is a block diagram showing an example configuration of the bit interleaver 116 in Figure 8.

The bit interleaver 116 has the function of interleaving data, and is composed of a parity interleaver 23, a group-wise interleaver 24, and a block interleaver 25.

The parity interleaver 23 performs parity interleaving to interleave the parity bits of the LDPC code from the LDPC encoder 115 into the positions of other parity bits, and supplies the LDPC code after the parity interleaving to the group-wise interleaver 24.

The group-wise interleaver 24 performs group-wise interleaving on the LDPC code from the parity interleaver 23, and supplies the LDPC code after group-wise interleaving to the block interleaver 25.

In group-wise interleaving, one LDPC code is divided into 360-bit units, equal to the parallel factor P described later, from the beginning of the code, and the 360 bits of each division are treated as bit groups, and the LDPC code from the parity interleaver 23 is interleaved in bit group units.

When group-wise interleaving is performed, the error rate can be improved compared to when group-wise interleaving is not performed, and as a result, good communication quality can be ensured in data transmission.

The block interleaver 25 performs block interleaving to demultiplex the LDPC code from the group-wise interleaver 24, thereby symbolizing, for example, one code's worth of LDPC code into m-bit symbols, which are the unit of mapping, and supplies them to the mapper 117 (Figure 8).

Here, in block interleaving, for example, columns serving as memory areas for storing a predetermined number of bits in the column (vertical) direction are arranged in a number of rows (horizontal) direction equal to the number of bits m of a symbol. The LDPC code from the group-wise interleaver 24 is written in the column direction and read out in the row direction to symbolize the LDPC code into an m-bit symbol.

<LDPC code check matrix>

Figure 10 is a diagram showing an example of a check matrix H used for LDPC encoding in the LDPC encoder 115 of Figure 8.

The check matrix H has an LDGM (Low-Density Generation Matrix) structure, and can be expressed by the equation H = [H _A |H _T ] (a matrix with the elements of the information matrix H _A as the left elements and the elements of the parity matrix H _T as the right elements) using an information matrix H _A of the part of the code bits of the LDPC code corresponding to the information bits and a parity matrix H _T corresponding to the parity bits.

Here, the number of information bits and the number of parity bits among the code bits of one LDPC code (one code word) are called the information length K and the parity length M, respectively, and the number of code bits of one LDPC code (one code word) is called the code length N (= K + M).

The information length K and parity length M for an LDPC code with a certain code length N are determined by the coding rate. Also, the check matrix H is a matrix with M×N rows and N columns. The information matrix H _A is an M×K matrix, and the parity matrix H _T is an M×M matrix.

FIG. 11 is a diagram showing an example of a parity matrix H _T of the check matrix H used for LDPC encoding in the LDPC encoder 115 in FIG.

As the parity matrix H _T of the check matrix H used for LDPC encoding in the LDPC encoder 115, for example, a parity matrix H _T similar to the check matrix H of the LDPC code defined in standards such as DVB-T.2 can be adopted.

The parity matrix H _T of the check matrix H of the LDPC code defined in the standards such as DVB-T.2 is a staircase-structured matrix (lower bidiagonal matrix) in which elements of 1 are arranged in a staircase-like manner, as shown in Fig. 11. The row weight of the parity matrix H _T is 1 for the first row, and 2 for all the remaining rows. The column weight is 1 for the last column, and 2 for all the remaining columns.

As described above, an LDPC code for a check matrix H in which the parity matrix H _T has a staircase structure can be easily generated by using that check matrix H.

That is, an LDPC code (one code word) is represented by row vector c, and the column vector obtained by transposing the row vector is represented by c ^T. In addition, the information bit portion of row vector c, which is the LDPC code, is represented by row vector A, and the parity bit portion is represented by row vector T.

In this case, row vector c can be expressed as c = [A|T] (a row vector with the elements of row vector A as the left elements and row vector T as the right elements) with row vector A as the information bits and row vector T as the parity bits.

Check matrix H and the row vector c=[A|T] as LDPC code must satisfy the formula ^HcT =0. When the parity matrix HT of check matrix H=[H _A |H T] is the staircase structure shown in Fig. 11, the row vector _T as ^the parity bit of the row vector c=[A| _T ] that satisfies this formula ^HcT =0 can be obtained sequentially (in order) by setting the elements of each row to 0 in order from the element of the first row of the column vector ^HcT in formula HcT=0.

Figure 12 is a diagram explaining the check matrix H of the LDPC code defined in standards such as DVB-T.2.

The first KX columns of the check matrix H of the LDPC code defined in standards such as DVB-T.2 have a column weight of X, the next K3 columns have a column weight of 3, the next M-1 columns have a column weight of 2, and the last column has a column weight of 1.

Here, KX+K3+M-1+1 is equal to the code length N.

Figure 13 shows the column numbers KX, K3, and M, as well as the column weight X, for each coding rate r of the LDPC code defined in standards such as DVB-T.2.

Standards such as DVB-T.2 prescribe LDPC codes with code lengths N of 64,800 bits and 16,200 bits.

For an LDPC code with a code length N of 64,800 bits, eleven nominal rates are specified: 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10. For an LDPC code with a code length N of 16,200 bits, ten nominal rates are specified: 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, and 8/9.

Hereinafter, a code length N of 64,800 bits will also be referred to as 64k bits, and a code length N of 16,200 bits will also be referred to as 16k bits.

For LDPC codes, the code bits corresponding to columns with larger column weights in the check matrix H tend to have lower error rates.

In the check matrix H defined in standards such as DVB-T.2 and shown in Figures 12 and 13, the columns at the beginning (left side) tend to have larger column weights. Therefore, for the LDPC code corresponding to that check matrix H, the code bits at the beginning tend to be more resistant to errors (more resistant to errors), and the code bits at the end tend to be more vulnerable to errors.

＜Parity interleave＞

With reference to Figures 14 to 16, we will explain parity interleaving by the parity interleaver 23 in Figure 9.

Figure 14 shows an example of a Tanner graph (part of it) of a check matrix for an LDPC code.

As shown in Figure 14, when two or more of the variable nodes (corresponding code bits) connected to a check node simultaneously experience an error such as erasure, a check node returns a message to all variable nodes connected to that check node, with equal probability of the value being 0 and the value being 1. For this reason, when multiple variable nodes connected to the same check node simultaneously experience an erasure, etc., decoding performance deteriorates.

Incidentally, the LDPC code output by the LDPC encoder 115 in FIG. 8 is an IRA code, similar to the LDPC code defined in standards such as DVB-T.2, and the parity matrix H _T of the check matrix H has a staircase structure as shown in FIG. 11.

FIG. 15 is a diagram showing an example of the parity matrix H _T having a staircase structure as shown in FIG. 11 and a Tanner graph corresponding to the parity matrix H _T.

FIG. 15A shows an example of a parity matrix H _T having a staircase structure, and FIG. 15B shows a Tanner graph corresponding to the parity matrix H _T of FIG. 15A.

In the parity matrix H _T having a staircase structure, elements of 1 are adjacent in each row (except the first row). Therefore, in the Tanner graph of the parity matrix H _T , two adjacent variable nodes corresponding to columns of two adjacent elements whose value in the parity matrix H _T is 1 are connected to the same check node.

Therefore, when parity bits corresponding to two adjacent variable nodes mentioned above become erroneous at the same time due to a burst error or erasure, the check nodes connected to the two variable nodes (variable nodes that use the parity bits to find a message) corresponding to the two erroneous parity bits return messages with equal probability of being 0 and 1 to the variable node connected to that check node, degrading decoding performance. And when the burst length (the number of consecutive erroneous parity bits) becomes large, the number of check nodes that return messages with equal probability increases, further degrading decoding performance.

To prevent the above-mentioned degradation of decoding performance, the parity interleaver 23 (Figure 9) performs parity interleaving, which interleaves the parity bits of the LDPC code from the LDPC encoder 115 into the positions of other parity bits.

FIG. 16 is a diagram showing a parity matrix H _T of the check matrix H corresponding to the LDPC code after parity interleaving performed by the parity interleaver 23 in FIG.

Here, the information matrix H _A of the check matrix H corresponding to the LDPC code output by the LDPC encoder 115 has a cyclic structure, similar to the information matrix of the check matrix H corresponding to the LDPC code defined in standards such as DVB-T.2.

A cyclic structure is one in which a column is equal to the cyclic shift of another column. For example, it includes a structure in which the position of 1 in each row of each of P columns is cyclically shifted in the column direction by a predetermined value, such as a value proportional to the value q obtained by dividing the first column of P columns by the parity length M. Hereinafter, P columns in a cyclic structure will be referred to as a parallel factor where appropriate.

As explained in Figures 12 and 13, there are two types of LDPC codes defined in standards such as DVB-T.2, with code lengths N of 64,800 bits and 16,200 bits, and for both types of LDPC codes, the parallel factor P is defined as 360, which is one of the divisors of the parity length M excluding 1 and M.

The parity length M is a value other than a prime number expressed by the formula M = q x P = q x 360, with the value q varying depending on the coding rate. Therefore, like the parallel factor P, the value q is another of the divisors of the parity length M, excluding 1 and M, and is obtained by dividing the parity length M by the parallel factor P (the product of P and q, which are divisors of parity length M, is the parity length M).

As described above, the parity interleaver 23 interleaves the K+qx+y+1-th code bit of the code bits of the N-bit LDPC code into the K+Py+x+1-th code bit position as parity interleaving, where K is the information length, x is an integer greater than or equal to 0 and less than P, and y is an integer greater than or equal to 0 and less than q.

The K+qx+y+1th code bit and the K+Py+x+1th code bit are both parity bits because they are code bits after the K+1th bit. Therefore, according to parity interleaving, the position of the parity bit of the LDPC code is moved.

With this type of parity interleaving, variable nodes (corresponding parity bits) connected to the same check node are separated by the parallel factor P, i.e., 360 bits in this case. Therefore, if the burst length is less than 360 bits, it is possible to avoid a situation in which multiple variable nodes connected to the same check node experience an error at the same time, thereby improving resistance to burst errors.

The LDPC code after parity interleaving, in which the K+qx+y+1th code bit is interleaved at the K+Py+x+1th code bit position, matches the LDPC code of the check matrix (hereinafter also referred to as the transformed check matrix) obtained by performing column permutation, in which the K+qx+y+1th column of the original check matrix H is replaced with the K+Py+x+1th column.

In addition, the parity matrix of the converted check matrix has a quasi-cyclic structure with units of P columns (360 columns in FIG. 16), as shown in FIG. 16.

Here, a pseudo-cyclic structure means a structure in which all but a few parts are cyclic.

The transformed check matrix obtained by performing column permutation equivalent to parity interleaving on the check matrix of the LDPC code defined in standards such as DVB-T.2 is missing one element of 1 (and has an element of 0) in the 360 row x 360 column part in the upper right corner of the transformed check matrix (the shift matrix, described below). In that respect, it is not a (completely) cyclic structure, but rather a pseudo-cyclic structure.

The conversion check matrix for the check matrix of the LDPC code output by the LDPC encoder 115 has a quasi-cyclic structure, similar to the conversion check matrix for the check matrix of the LDPC code specified in standards such as DVB-T.2.

The transformed check matrix in FIG. 16 is a matrix in which, in addition to the column permutation equivalent to parity interleaving, row permutation (row permutation) has also been performed on the original check matrix H so that the transformed check matrix is composed of the constituent matrices described below.

Figure 17 is a flowchart explaining the processing performed by the LDPC encoder 115, bit interleaver 116, and mapper 117 in Figure 8.

The LDPC encoder 115 waits for the LDPC target data to be supplied from the BCH encoder 114, and in step S101, encodes the LDPC target data into an LDPC code and supplies the LDPC code to the bit interleaver 116, after which the process proceeds to step S102.

In step S102, the bit interleaver 116 performs bit interleaving on the LDPC code from the LDPC encoder 115, supplies the symbols obtained by the bit interleaving to the mapper 117, and the process proceeds to step S103.

That is, in step S102, in the bit interleaver 116 (FIG. 9), the parity interleaver 23 performs parity interleaving on the LDPC code from the LDPC encoder 115, and supplies the LDPC code after the parity interleaving to the group-wise interleaver 24.

The group-wise interleaver 24 performs group-wise interleaving on the LDPC code from the parity interleaver 23 and supplies it to the block interleaver 25.

The block interleaver 25 performs block interleaving on the LDPC code after group-wise interleaving by the group-wise interleaver 24, and supplies the resulting m-bit symbol to the mapper 117.

In step S103, the mapper 117 performs orthogonal modulation by mapping the symbols from the block interleaver 25 to any of 2 ^m signal points determined by the modulation method of the orthogonal modulation performed by the mapper 117, and supplies the resulting data to the time interleaver 118.

As described above, by performing parity interleaving or group-wise interleaving, it is possible to improve the error rate when multiple code bits of an LDPC code are transmitted as one symbol.

Here, in FIG. 9, for ease of explanation, the parity interleaver 23, which is a block that performs parity interleaving, and the groupwise interleaver 24, which is a block that performs groupwise interleaving, are configured separately, but the parity interleaver 23 and the groupwise interleaver 24 can be configured as an integrated unit.

In other words, both parity interleaving and group-wise interleaving can be performed by writing and reading code bits to memory, and can be represented by a matrix that converts the address at which the code bits are written (write address) into the address at which the code bits are read (read address).

Therefore, if you obtain a matrix by multiplying a matrix representing parity interleaving by a matrix representing group-wise interleaving, you can perform parity interleaving by converting the code bits using these matrices, and then obtain the result of group-wise interleaving the LDPC code after the parity interleaving.

In addition to the parity interleaver 23 and group-wise interleaver 24, the block interleaver 25 can also be configured integrally.

In other words, the block interleaving performed by the block interleaver 25 can also be represented by a matrix that converts the write addresses of the memory that stores the LDPC code into read addresses.

Therefore, if you obtain a matrix by multiplying a matrix representing parity interleaving, a matrix representing group-wise interleaving, and a matrix representing block interleaving, you can use these matrices to perform parity interleaving, group-wise interleaving, and block interleaving all at once.

Note that one or the amount of parity interleaving and group-wise interleaving may not be performed.

<Example of the configuration of the LDPC encoder 115>

Figure 18 is a block diagram showing an example configuration of the LDPC encoder 115 in Figure 8.

The LDPC encoder 122 in FIG. 8 is configured in a similar manner.

As explained in Figures 12 and 13, standards such as DVB-T.2 prescribe LDPC codes with two code lengths N: 64,800 bits and 16,200 bits.

For an LDPC code with a code length N of 64,800 bits, eleven coding rates are specified: 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10. For an LDPC code with a code length N of 16,200 bits, ten coding rates are specified: 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, and 8/9 (Figures 12 and 13).

The LDPC encoder 115 can perform, for example, encoding (error correction encoding) using LDPC codes with code lengths N of 64,800 bits and 16,200 bits and various coding rates, according to a check matrix H prepared for each code length N and each coding rate.

In addition, the LDPC encoder 115 can perform LDPC encoding according to a check matrix H of an LDPC code with an arbitrary code length N and an arbitrary coding rate r.

The LDPC encoder 115 is composed of an encoding processing unit 601 and a memory unit 602.

The encoding processing unit 601 is composed of an encoding rate setting unit 611, an initial value table reading unit 612, a check matrix generation unit 613, an information bit reading unit 614, an encoding parity calculation unit 615, and a control unit 616, and performs LDPC encoding of the LDPC target data supplied to the LDPC encoder 115, and supplies the resulting LDPC code to the bit interleaver 116 (Figure 8).

That is, the coding rate setting unit 611 sets the code length N and coding rate r of the LDPC code, and other specific information that identifies the LDPC code, for example, in response to an operation by an operator.

The initial value table reading unit 612 reads from the memory unit 602 the check matrix initial value table described below, which represents the check matrix of the LDPC code specified by the specific information set by the coding rate setting unit 611.

The check matrix generating unit 613 generates a check matrix H based on the check matrix initial value table read by the initial value table reading unit 612, and stores the check matrix H in the storage unit 602. For example, the check matrix generating unit 613 generates the check matrix H by arranging one element of the information matrix H _A corresponding to the information length K (=code length N-parity length M) according to the code length N and the coding rate r set by the coding rate setting unit 611 in a period of 360 columns (parallel factor P) in the column direction, and stores the check matrix H in the storage unit 602.

The information bit reading unit 614 reads (extracts) information bits of information length K from the LDPC target data supplied to the LDPC encoder 115.

The encoding parity calculation unit 615 reads the check matrix H generated by the check matrix generation unit 613 from the storage unit 602, and uses the check matrix H to calculate parity bits for the information bits read by the information bit reading unit 614 based on a predetermined formula, thereby generating a codeword (LDPC code).

The control unit 616 controls each block that makes up the encoding processing unit 601.

The storage unit 602 stores a plurality of check matrix initial value tables and the like corresponding to the plurality of coding rates and the like shown in FIG. 12 and FIG. 13 for each code length N, such as 64800 bits and 16200 bits. The storage unit 602 also temporarily stores data necessary for the processing of the encoding processing unit 601.

Figure 19 is a flowchart that explains an example of the processing of the LDPC encoder 115 in Figure 18.

In step S201, the coding rate setting unit 611 sets the code length N and coding rate r for LDPC coding, as well as other specific information that identifies the LDPC code.

In step S202, the initial value table reading unit 612 reads from the storage unit 602 a predetermined check matrix initial value table that is specified by the code length N and the coding rate r, etc., as specific information set by the coding rate setting unit 611.

In step S203, the check matrix generation unit 613 uses the check matrix initial value table read from the storage unit 602 by the initial value table reading unit 612 to determine (generate) the check matrix H of the LDPC code having the code length N and coding rate r set by the coding rate setting unit 611, and supplies it to the storage unit 602 for storage.

In step S204, the information bit reading unit 614 reads information bits of information length K (=N×r) corresponding to the code length N and coding rate r set by the coding rate setting unit 611 from the LDPC target data supplied to the LDPC encoder 115, and also reads the check matrix H calculated by the check matrix generation unit 613 from the storage unit 602 and supplies it to the encoding parity calculation unit 615.

In step S205, the encoding parity calculation unit 615 uses the information bits from the information bit reading unit 614 and the check matrix H to sequentially calculate the parity bits of the codeword c that satisfies equation (8).

^HcT = 0
...(8)

In equation (8), c represents a row vector as a codeword (LDPC code), and ^cT represents the transpose of row vector c.

As described above, if the information bit portion of row vector c as an LDPC code (one code word) is represented by row vector A and the parity bit portion is represented by row vector T, row vector c can be expressed as c = [A|T] with row vector A as the information bits and row vector T as the parity bits.

The check matrix H and the row vector c=[A|T] as LDPC code must satisfy the formula ^HcT =0. When the parity matrix HT of the check matrix H=[H _A |H _T ] is the staircase structure shown in Fig. 11, the row vector T as ^the parity bit that constitutes the row vector c=[A| _T ] that satisfies this formula ^HcT =0 can be obtained sequentially by setting the elements of each row to 0, starting from the element of the first row of the column vector ^HcT in the formula HcT=0.

The encoding parity calculation unit 615 calculates the parity bit T for the information bit A from the information bit reading unit 614, and outputs the codeword c = [A | T] represented by the information bit A and the parity bit T as the LDPC encoding result of the information bit A.

Then, in step S206, the control unit 616 determines whether or not to end the LDPC encoding. If it is determined in step S206 that the LDPC encoding is not to end, that is, for example, if there is still LDPC target data to be LDPC encoded, the process returns to step S201 (or step S204), and the processes of steps S201 (or step S204) to S206 are repeated.

Also, if it is determined in step S206 that the LDPC encoding is to be terminated, that is, for example, if there is no LDPC target data to be LDPC encoded, the LDPC encoder 115 terminates the process.

For the LDPC encoder 115, a check matrix initial value table (representing a check matrix) for LDPC codes of various code lengths N and coding rates r can be prepared in advance. The LDPC encoder 115 can perform LDPC encoding for LDPC codes of various code lengths N and coding rates r using a check matrix H generated from a check matrix initial value table prepared in advance. Note that since the check matrix H can be generated from the check matrix initial value table, the check matrix H and the check matrix initial value table are equivalent information. In the implementation of the LDPC encoder 115, the check matrix H is generated from the check matrix initial value table, and LDPC encoding is performed using the check matrix H, and LDPC encoding can also be performed using the check matrix initial value table as is.

<Example of check matrix initial value table>

For example, the check matrix initial value table is a table that represents the position of element 1 of information matrix H _A (Fig. 10) corresponding to the code length N of LDPC code (LDPC code defined by check matrix H) and the information length K according to the coding rate r of check matrix H for each of 360 columns (parallel factor P), and is created in advance for each check matrix H of each code length N and each coding rate r.

That is, the check matrix initial value table indicates at least the positions of elements of 1 in the information matrix H _A for every 360 columns (parallel factor P).

In addition, the parity check matrix H may be a parity check matrix in which the entire parity matrix H _T has a staircase structure, or a parity check matrix in which a part of the parity matrix H _T has a staircase structure and the remaining part is a diagonal matrix (unit matrix).

Hereinafter, the expression method of the parity check matrix initial value table representing the parity check matrix in which a part of the parity matrix H _T has a staircase structure and the remaining part is a diagonal matrix is also referred to as Type A method. Also, the expression method of the parity check matrix initial value table representing the parity check matrix in which the entire parity matrix H _T has a staircase structure is also referred to as Type B method.

In addition, an LDPC code for a check matrix represented by a Type A check matrix initial value table is also called a Type A code, and an LDPC code for a check matrix represented by a Type B check matrix initial value table is also called a Type B code.

The designations "Type A" and "Type B" conform to the ATSC 3.0 standard. For example, ATSC 3.0 uses both Type A and Type B codes.

Note that DVB-T.2 and other formats use Type B coding.

Figure 20 shows an example of a check matrix initial value table for the Type B method.

That is, FIG. 20 shows a check matrix initial value table (representing check matrix H) for a type B code with a code length N of 16200 bits and a coding rate (the coding rate in DVB-T.2 notation) r of 1/4, as specified in the DVB-T.2 standard.

The check matrix generation unit 613 (FIG. 18) uses the check matrix initial value table for the Type B method to find the check matrix H as follows:

Figure 21 is a diagram explaining how to find the check matrix H from the check matrix initial value table for the Type B method.

That is, Figure 21 shows a check matrix initial value table for a Type B code with a code length N of 16200 bits and a coding rate r of 2/3, as specified in the DVB-T.2 standard.

The check matrix initial value table of the Type B method is a table that represents the positions of all elements of 1 in the information matrix H _A corresponding to the information length K according to the code length N and the coding rate r of the LDPC code for each of 360 columns (parallel factor P). In the i-th row, the row numbers of the elements of 1 in the 1+360×(i-1)-th column of the check matrix H (the row numbers of the 1st row of the check matrix H being 0) are arranged in the same number as the column weight of the 1+360×(i-1)-th column.

Here, the parity matrix H _T (FIG. 10) corresponding to the parity length M of the check matrix H of the type B method is determined to have a staircase structure as shown in FIG. 15, so if the information matrix H _A (FIG. 10) corresponding to the information length K can be obtained using the check matrix initial value table, the check matrix H can be obtained.

The number of rows k+1 in the check matrix initial value table for Type B method varies depending on the information length K.

The relationship between the information length K and the number of rows in the check matrix initial value table (k+1) satisfies the following formula (9).

K = (k + 1) x 360
... (9)

Here, 360 in equation (9) is the parallel factor P explained in Figure 16.

In the check matrix initial value table in Figure 21, 13 values are listed from the first row to the third row, and 3 values are listed from the fourth row to the k+1th row (the 30th row in Figure 21).

Therefore, the column weight of the check matrix H obtained from the check matrix initial value table in FIG. 21 is 13 from the 1st column to the 1+360×(3-1)-1th column, and 3 from the 1+360×(3-1)th column to the Kth column.

The first row of the parity check matrix initial value table in Figure 21 is 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622, which indicates that in the first column of parity check matrix H, the elements of the rows with row numbers 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622 are 1 (and the other elements are 0).

In addition, the second row of the parity check matrix initial value table in FIG. 21 is 1,122,1516,3448,2880,1407,1847,3799,3529,373,971,4358,3108, which indicates that in the 361st (=1+360×(2-1))th column of parity check matrix H, the elements of the rows with row numbers 1,122,1516,3448,2880,1407,1847,3799,3529,373,971,4358,3108 are 1.

As described above, the parity check matrix initial value table indicates the positions of elements of 1 in the information matrix H _A of the parity check matrix H for every 360 columns.

Columns other than the 1+360×(i-1)th column of the parity check matrix H, that is, each column from the 2+360×(i-1)th column to the 360×ith column, are arranged by periodically cyclically shifting the element 1 in the 1+360×(i-1)th column determined by the parity check matrix initial value table downward (downward in the column) according to the parity length M.

For example, the 2+360×(i-1)th column is the 1+360×(i-1)th column cyclically shifted downward by M/360(=q), and the next 3+360×(i-1)th column is the 1+360×(i-1)th column cyclically shifted downward by 2×M/360(=2×q) (the 2+360×(i-1)th column cyclically shifted downward by M/360(=q)).

Now, assuming that the numerical value in the i-th row (i-th from the top) and j-th column (j-th from the left) of the parity check matrix initial value table is represented as h _i,j and the row index of the j-th element of 1 in the w-th column of the parity check matrix H is represented as H _wj , the row index H _wj of the element of 1 in the w-th column, which is a column other than the 1+360×(i−1)-th column of the parity check matrix H, can be obtained by equation (10).

H _wj ＝mod{h _i,j ＋mod((w-1),P)×q,M)
...(10)

Here, mod(x, y) means the remainder when x is divided by y.

P is the parallel factor described above, and in this embodiment, it is 360, similar to the standards such as DVB-T.2 and ATSC3.0. Furthermore, q is the value M/360 obtained by dividing the parity length M by the parallel factor P (=360).

The check matrix generation unit 613 (Figure 18) identifies the row number of the element that is 1 in the 1+360×(i-1)th column of the check matrix H using the check matrix initial value table.

Furthermore, the check matrix generation unit 613 (FIG. 18) obtains the row index _Hwj of the element of 1 in the w-th column, which is a column other than the 1+360×(i−1)-th column of the check matrix H, in accordance with equation (10), and generates the check matrix H in which the elements of the row indexes obtained above are set to 1.

Figure 22 shows the structure of check matrix H for Type A.

The check matrix for Type A is composed of matrix A, matrix B, matrix C, matrix D, and matrix Z.

Matrix A is the upper left matrix of check matrix H, with M1 rows and K columns, represented by a predetermined value M1 and the information length K of the LDPC code = code length N × coding rate r.

Matrix B is a step-structured matrix adjacent to the right of matrix A, with M1 rows and M1 columns.

Matrix C is the matrix adjacent to and below matrix A and matrix B, with N-K-M1 rows and K+M1 columns.

The D matrix is an identity matrix with N-K-M1 rows and N-K-M1 columns, adjacent to the right of the C matrix.

The Z matrix is the zero matrix adjacent to the right of the B matrix, with M1 rows and N-K-M1 columns.

In the type A check matrix H, which is composed of the above-mentioned A matrix, D matrix, and Z matrix, the A matrix and a part of the C matrix form the information matrix, and the remaining parts of the B matrix, the C matrix, the D matrix, and the Z matrix form the parity matrix.

Note that matrix B is a staircase-structured matrix and matrix D is a unit matrix, so part of the parity matrix of check matrix H in Type A method (matrix B) has a staircase-structured matrix, and the remaining part (matrix D) is a diagonal matrix (unit matrix).

The A and C matrices, like the information matrix of the parity check matrix H of the Type B method, have a cyclic structure for each column of the parallel factor P (e.g., 360 columns), and the parity check matrix initial value table of the Type A method represents the positions of elements of 1 in the A and C matrices for every 360 columns.

As described above, the A matrix and a part of the C matrix constitute an information matrix, so the Type A method parity check matrix initial value table, which represents the positions of elements of 1 in the A matrix and the C matrix every 360 columns, can be said to at least represent the positions of elements of 1 in the information matrix every 360 columns.

In addition, since the Type A method's parity check matrix initial value table represents the positions of elements that are 1 in the A and C matrices every 360 columns, it can also be said that it represents the positions of elements that are 1 in a part of the parity check matrix (the remaining part of the C matrix) every 360 columns.

Figure 23 shows an example of a check matrix initial value table for the Type A method.

In other words, FIG. 23 shows an example of a check matrix initial value table that represents a check matrix H with a code length N of 35 bits and a coding rate r of 2/7.

The Type A method check matrix initial value table is a table that indicates the positions of elements of 1 in the A and C matrices for each parallel factor P, and in the i-th row, the row numbers of elements of 1 in the 1+P×(i-1)th column of check matrix H (row numbers assuming that the row number of the first row of check matrix H is 0) are listed for the same number of column weights as the 1+P×(i-1)th column.

For simplicity's sake, let's assume that the parallel factor P is, for example, 5.

The parameters of the check matrix H for the Type A method are M1, M2, Q1, and Q2.

M1 (Figure 22) is a parameter that determines the size of the B matrix, and takes a value that is a multiple of the parallel factor P. By adjusting M1, the performance of the LDPC code changes, and it is adjusted to a predetermined value when the check matrix H is determined. Here, it is assumed that M1 is set to 15, which is three times the parallel factor P = 5.

M2 (Figure 22) is the value M-M1 obtained by subtracting M1 from the parity length M.

Here, the information length K is N×r＝35×2/7＝10, and the parity length M is N-K＝35-10＝25, so M2 is M-M1＝25-15＝10.

Q1 is calculated according to the formula Q1 = M1/P and represents the number of cyclic shifts (number of rows) in the A matrix.

In other words, columns other than the 1+P×(i-1)th column of the A matrix of the Type A method check matrix H, that is, each column from the 2+P×(i-1)th column to the P×ith column, are arranged by periodically cyclically shifting the element 1 in the 1+P×(i-1)th column determined by the check matrix initial value table downward (downward in the column), and Q1 represents the number of cyclic shifts in the A matrix.

Q2 is calculated according to the formula Q2 = M2/P and represents the number of cyclic shifts (number of rows) in the C matrix.

In other words, columns other than the 1+P×(i-1)th column of the C matrix of the Type A method check matrix H, that is, each column from the 2+P×(i-1)th column to the P×ith column, are arranged by periodically cyclically shifting the element 1 in the 1+P×(i-1)th column determined by the check matrix initial value table downward (downward in the column), and Q2 represents the number of cyclic shifts in the C matrix.

Here, Q1 is M1/P = 15/5 = 3, and Q2 is M2/P = 10/5 = 2.

In the parity check matrix initial value table of FIG. 23, three numerical values are listed in the first and second rows, and one numerical value is listed in the third to fifth rows. According to this arrangement of numerical values, the column weights of the A and C matrices of the parity check matrix H obtained from the parity check matrix initial value table of FIG. 23 are 3 from the 1=1+5×(1-1)th column to the 10=5×2nd column, and 1 from the 11=1+5×(3-1)th column to the 25=5×5th column.

In other words, the first row of the parity check matrix initial value table in FIG. 23 is 2,6,18, which indicates that in the first column of parity check matrix H, the elements in the row numbers 2,6,18 are 1 (and the other elements are 0).

In this case, the A matrix (Figure 22) is a matrix with 15 rows and 10 columns (M1 rows and K columns), and the C matrix (Figure 22) is a matrix with 10 rows and 25 columns (N-K-M1 rows and K+M1 columns), so the rows with row numbers 0 to 14 of the check matrix H are the rows of the A matrix, and the rows with row numbers 15 to 24 of the check matrix H are the rows of the C matrix.

Therefore, of the rows with row numbers 2, 6, and 18 (hereafter referred to as rows #2, #6, #18, etc.), rows #2 and #6 are rows of the A matrix, and row #18 is a row of the C matrix.

The second row of the parity check matrix initial value table in FIG. 23 is 2, 10, 19, which indicates that the elements of rows #2, #10, and #19 in the 6th (= 1 + 5 × (2-1)) column of parity check matrix H are 1.

Here, in the 6th (=1+5×(2-1)) column of the check matrix H, among rows #2, #10, and #19, rows #2 and #10 are rows of the A matrix, and row #19 is a row of the C matrix.

The third row of the parity check matrix initial value table in Figure 23 is 22, which indicates that the element in row #22 in the 11th (= 1 + 5 × (3-1)) column of parity check matrix H is 1.

Here, in the 11th (= 1 + 5 × (3 - 1)) column of the check matrix H, row #22 is a row of the C matrix.

Similarly, the 19 in the 4th row of the parity check matrix initial value table in FIG. 23 indicates that the element in row #19 in the 16th (= 1 + 5 × (4-1)) column of parity check matrix H is 1, and the 15 in the 5th row of the parity check matrix initial value table in FIG. 23 indicates that the element in row #15 in the 21st (= 1 + 5 × (5-1)) column of parity check matrix H is 1.

As described above, the check matrix initial value table represents the positions of elements of 1 in the A matrix and C matrix of the check matrix H for each parallel factor P = 5 columns.

Columns other than the 1+5×(i-1)th column of the A matrix and C matrix of the parity check matrix H, that is, each column from the 2+5×(i-1)th column to the 5×ith column, are arranged by periodically cyclically shifting the element of 1 in the 1+5×(i-1)th column determined by the parity check matrix initial value table downward (downward in the column direction) according to the parameters Q1 and Q2.

For example, the 2+5×(i-1)th column of matrix A is the 1+5×(i-1)th column cyclically shifted down by Q1 (=3), and the next 3+5×(i-1)th column is the 1+5×(i-1)th column cyclically shifted down by 2×Q1 (=2×3) (the 2+5×(i-1)th column cyclically shifted down by Q1).

For example, the 2+5×(i-1)th column of matrix C is the 1+5×(i-1)th column cyclically shifted down by Q2 (=2), and the next 3+5×(i-1)th column is the 1+5×(i-1)th column cyclically shifted down by 2×Q2 (=2×2) (the 2+5×(i-1)th column cyclically shifted down by Q2).

Figure 24 shows the A matrix generated from the check matrix initial value table in Figure 23.

In matrix A in FIG. 24, the elements in rows #2 and #6 of the 1st (= 1 + 5 × (1-1)) column are 1, in accordance with the 1st row of the parity check matrix initial value table in FIG. 23.

And each column from the 2nd (=2+5×(1-1)) to the 5th (=5+5×(1-1)) columns is a cyclic shift of Q1=3 downwards from the previous column.

Furthermore, in matrix A in FIG. 24, the elements in rows #2 and #10 of the 6th (= 1 + 5 × (2-1)) column are 1, in accordance with the second row of the parity check matrix initial value table in FIG. 23.

And each column from the 7th (= 2 + 5 × (2-1)) to the 10th (= 5 + 5 × (2-1)) columns is a cyclic shift of Q1 = 3 downwards from the previous column.

Figure 25 shows the parity interleaving of the B matrix.

The check matrix generation unit 613 (Figure 18) uses the check matrix initial value table to generate matrix A, and places matrix B of a staircase structure to the immediate right of matrix A. Then, the check matrix generation unit 613 regards matrix B as a parity matrix, and performs parity interleaving so that adjacent elements of 1 in matrix B of the staircase structure are separated in the row direction by a parallel factor P = 5.

Figure 25 shows the A and B matrices after parity interleaving of the B matrix in Figure 24.

Figure 26 shows the C matrix generated from the check matrix initial value table in Figure 23.

In matrix C in FIG. 26, the element in row #18 of the 1st (= 1 + 5 × (1 - 1))th column of parity check matrix H is 1, in accordance with the 1st row of the parity check matrix initial value table in FIG. 23.

And each column from the 2nd (=2+5×(1-1)) to the 5th (=5+5×(1-1)) of the C matrix is a cyclic shift of the previous column downwards by Q2=2.

Furthermore, in matrix C of FIG. 26, in accordance with the second to fifth rows of the parity check matrix initial value table of FIG. 23, the elements of row #19 in the 6th (=1+5×(2-1)) column, row #22 in the 11th (=1+5×(3-1)) column, row #19 in the 16th (=1+5×(4-1)) column, and row #15 in the 21st (=1+5×(5-1)) column of parity check matrix H are set to 1.

And each column from 7 (=2+5×(2-1)) to 10 (=5+5×(2-1)), each column from 12 (=2+5×(3-1)) to 15 (=5+5×(3-1)), each column from 17 (=2+5×(4-1)) to 20 (=5+5×(4-1)), and each column from 22 (=2+5×(5-1)) to 25 (=5+5×(5-1)) are cyclically shifted downwards by Q2=2 from the previous column.

The check matrix generation unit 613 (Figure 18) uses the check matrix initial value table to generate matrix C, and places matrix C below matrix A and matrix B (after parity interleaving).

Furthermore, the check matrix generation unit 613 places the Z matrix to the right of the B matrix, and places the D matrix to the right of the C matrix, generating the check matrix H shown in FIG. 26.

Figure 27 shows the parity interleaving of the D matrix.

After generating the check matrix H in FIG. 26, the check matrix generation unit 613 regards the D matrix as a parity matrix and performs parity interleaving (only on the D matrix) so that elements with a value of 1 in an odd row and the next even row of the unit matrix D matrix are separated in the row direction by a parallel factor P = 5.

Figure 27 shows the check matrix H after performing parity interleaving of the D matrix on the check matrix H in Figure 26.

The LDPC encoder 115 (the encoding parity calculation unit 615 (Figure 18)) performs LDPC encoding (generation of LDPC code) using, for example, the check matrix H in Figure 27.

The LDPC code generated using the check matrix H in FIG. 27 is an LDPC code that has been parity interleaved, and therefore, for the LDPC code generated using the check matrix H in FIG. 27, there is no need to perform parity interleaving in the parity interleaver 23 (FIG. 9). In other words, the LDPC code generated using the check matrix H after parity interleaving of the D matrix is an LDPC code that has been parity interleaved, and therefore, for such an LDPC code, the parity interleaving in the parity interleaver 23 is skipped.

Figure 28 shows the parity check matrix H in Figure 27, where column permutation has been performed on the B matrix, part of the C matrix (the part of the C matrix that is placed under the B matrix), and the D matrix as parity deinterleaving to restore the parity interleaving.

The LDPC encoder 115 can perform LDPC encoding (generation of an LDPC code) using the check matrix H in FIG. 28.

When LDPC coding is performed using the check matrix H in FIG. 28, an LDPC code that does not undergo parity interleaving is obtained. Therefore, when LDPC coding is performed using the check matrix H in FIG. 28, parity interleaving is performed in the parity interleaver 23 (FIG. 9).

Figure 29 shows the converted check matrix obtained by performing row permutation on the check matrix H in Figure 27.

As described below, the conversion check matrix is a matrix that is expressed by a combination of a P×P unit matrix, a quasi-unit matrix in which one or more of the 1's in the unit matrix are replaced with 0, a shift matrix obtained by cyclically shifting a unit matrix or a quasi-unit matrix, a sum matrix that is the sum of two or more of the unit matrix, the quasi-unit matrix, or the shift matrix, and a P×P 0 matrix.

By using the conversion check matrix for decoding the LDPC code, it is possible to adopt an architecture for simultaneously performing P check node operations and variable node operations in the decoding of the LDPC code, as described below.

One way to ensure good communication quality in data transmission using LDPC codes is to use high-performance LDPC codes.

Here, a high-performance LDPC code is one that is obtained from an appropriate check matrix H.

An appropriate check matrix H is, for example, a check matrix that satisfies a predetermined condition and reduces the bit error rate ( _BER ) (and frame error rate (FER)) when the LDPC code obtained from the check matrix H is transmitted at a low E s /N ₀ or E _b /N _o (signal power to noise power ratio per bit).

An appropriate check matrix H can be found, for example, by performing a simulation to measure the BER when LDPC codes obtained from various check matrices that satisfy predetermined conditions are transmitted at a low E _s /N _o .

The predetermined conditions that an appropriate check matrix H must satisfy include, for example, good analytical results obtained by a method for analyzing the performance of the code called Density Evolution, and the absence of a loop of elements of 1, called cycle 4.

Here, it is known that if elements of 1 are concentrated in the information matrix H _A , such as in cycle 4, the decoding performance of the LDPC code deteriorates. For this reason, it is desirable that cycle 4 does not exist in the check matrix H.

In the check matrix H, the minimum length of a loop made up of elements of 1 is called the girth. The absence of cycle 4 means that the girth is greater than 4.

The predetermined conditions that an appropriate check matrix H must satisfy can be determined appropriately from the viewpoint of improving the decoding performance of the LDPC code, facilitating (simplifying) the decoding process of the LDPC code, etc.

Figures 30 and 31 are diagrams explaining density evolution that obtain analysis results as predetermined conditions that an appropriate check matrix H must satisfy.

Density evolution is a code analysis method that calculates the expected error probability for an ensemble of LDPC codes with code length N of ∞, characterized by a degree sequence (described below).

For example, in an AWGN channel, if the noise variance is increased from 0, the expected error probability of a certain ensemble is initially 0, but once the noise variance exceeds a certain threshold, it is no longer 0.

According to density evolution, the performance of the ensemble (the appropriateness of the check matrix) can be determined by comparing the noise variance threshold (hereafter referred to as the performance threshold) at which the expected value of the error probability is no longer zero.

For a specific LDPC code, by determining the ensemble to which the LDPC code belongs and performing density evolution on that ensemble, it is possible to predict the rough performance of the LDPC code.

Therefore, if you find an ensemble with good performance, you can find a good LDPC code among the LDPC codes that belong to that ensemble.

The degree sequence mentioned above indicates the proportion of variable nodes and check nodes with each weight value for the code length N of the LDPC code.

For example, a regular(3,6) LDPC code with a code rate of 1/2 belongs to an ensemble characterized by a degree sequence in which all variable nodes have a weight (column weight) of 3 and all check nodes have a weight (row weight) of 6.

Figure 30 shows the Tanner graph of such an ensemble.

In the Tanner Bluff of Figure 30, there are N variable nodes, indicated by circles (○) in the figure, which is equal to the code length N, and there are N/2 check nodes, indicated by squares (□) in the figure, which is equal to the product of the code length N and the coding rate 1/2.

Each variable node has three edges connected to it, equal to the column weight, so there are a total of 3N edges connecting the N variable nodes.

Also, each check node has 6 edges connected to it, equal to the row weight, so there are a total of 3N edges connecting to the N/2 check nodes.

Furthermore, in the Tanner graph of Figure 30, there is one interleaver.

The interleaver randomly rearranges the 3N branches connected to the N variable nodes, and then connects each rearranged branch to one of the 3N branches connected to the N/2 check nodes.

There are only (3N)! (= (3N) x (3N-1) x ... x 1) possible permutations for the 3N branches connected to N variable nodes in an interleaver. Therefore, an ensemble characterized by a degree sequence in which all variable nodes have a weight of 3 and all check nodes have a weight of 6 is a set of (3N)! LDPC codes.

In simulations to find high-performance LDPC codes (suitable check matrices), a multi-edge type ensemble can be used in density evolution.

In the multi-edge type, the interleaver through which the branches connected to the variable nodes and the branches connected to the check nodes pass is divided into multiple (multi-edge), which allows for more precise characterization of the ensemble.

Figure 31 shows an example of a Tanner graph for a multi-edge type ensemble.

In the Tanner graph of Figure 31, there are two interleavers: a first interleaver and a second interleaver.

In addition, in the Tanner graph of Figure 31, there are only v1 variable nodes with one edge connected to the first interleaver and zero edges connected to the second interleaver, only v2 variable nodes with one edge connected to the first interleaver and two edges connected to the second interleaver, and only v3 variable nodes with zero edges connected to the first interleaver and two edges connected to the second interleaver.

Furthermore, in the Tanner graph of Figure 31, there are c1 check nodes with 2 edges connected to the first interleaver and 0 edges connected to the second interleaver, c2 check nodes with 2 edges connected to the first interleaver and 2 edges connected to the second interleaver, and c3 check nodes with 0 edges connected to the first interleaver and 3 edges connected to the second interleaver.

Here, density evolution and its implementation are described, for example, in "On the Design of Low-Density Parity-Check Codes within 0.0045 dB of the Shannon Limit", S.Y.Chung, G.D.Forney, T.J.Richardson,R.Urbanke, IEEE Communications Leggers, VOL.5, NO.2, Feb 2001.

In a simulation to find an LDPC code (its check matrix), an ensemble is found where the performance threshold, which is E _b /N ₀ (signal power to noise power ratio per bit) at which the BER starts to drop (become smaller) by multi-edge type density evolution, is below a predetermined value, and from the LDPC codes belonging to that ensemble, the LDPC code that reduces the BER when one or more orthogonal modulations such as QPSK are used can be selected as the LDPC code with good performance.

For data transmission in the transmission system of Figure 7, for example, a type A code or type B code corresponding to a cyclic check matrix H with a parallel factor P of 360, the same as that of DVB-T.2, ATSC3.0, etc., obtained by the above simulation can be used.

For data transmission in the transmission system of FIG. 7, an LDPC code with a code length N longer than that of DVB-T.2 or ATSC3.0 can be used, i.e., for example, an LDPC code with a code length N of 69120 bits and coding rates r of 2/16, 3/16, 4/16, 5/16, 6/16, 7/16, 8/16, 9/16, 10/16, 11/16, 12/16, 13/16, or 14/16.

<Constellation>

Figures 32 to 56 are diagrams showing examples of constellations that can be used in the transmission system of Figure 7.

In the transmission system of Figure 7, for example, for MODCOD, which is a combination of a modulation method (MODulation) and an LDPC code (CODe), it is possible to set a constellation to be used for that MODCOD.

For a MODCOD of 1, one or more constellations can be set.

There are two types of constellations: UC (Uniform Constellation), in which the signal points are arranged uniformly, and NUC (Non Uniform Constellation), in which the signal points are not arranged uniformly.

Furthermore, NUC includes, for example, a constellation called 1D-NUC (1-dimensional (M ² -QAM) non-uniform constellation) and a constellation called 2D-NUC (2-dimensional (QQAM) non-uniform constellation).

In general, BER is improved with 1D-NUC compared to UC, and BER is further improved with 2D-NUC compared to 1D-NUC.

When the modulation method is QPSK, UC can be used as a constellation. When the modulation method is 16QAM, 64QAM, 256QAM, etc., UC or 2D-NUC can be used as a constellation, and when the modulation method is 1024QAM, 4096QAM, etc., UC or 1D-NUC can be used as a constellation.

The transmission system in Figure 7 can use various constellations that improve error rates, such as those specified in ATSC3.0 and DVB-C.2.

That is, when the modulation method is QPSK, for example, the same UC can be used for each coding rate r of the LDPC code.

In addition, when the modulation method is 16QAM, 64QAM, or 256QAM, for example, the same UC can be used for each coding rate r of the LDPC code. Furthermore, when the modulation method is 16QAM, 64QAM, or 256QAM, for example, a different 2D-NUC can be used for each coding rate r of the LDPC code.

In addition, when the modulation method is 1024QAM or 4096QAM, for example, the same UC can be used for each coding rate r of the LDPC code. Furthermore, when the modulation method is 1024QAM or 4096QAM, for example, a different 1D-NUC can be used for each coding rate r of the LDPC code.

Here, UC of QPSK is also referred to as QPSK-UC, UC of 2 ^{m QAM is also referred to as 2 m QAM-UC, and 1D-NUC and 2D-NUC of 2 m QAM} are also referred to as 2 ^m QAM-1D-NUC and 2 ^m QAM-2D-NUC, respectively.

Below, we will explain some of the constellations defined in ATSC3.0.

Figure 32 shows the coordinates of QPSK-UC signal points used for all coding rates of LDPC codes specified in ATSC3.0 when the modulation method is QPSK.

In Fig.32, "Input Data cell y" represents a 2-bit symbol to be mapped to QPSK-UC, and "Constellation point _zs " represents the coordinates of constellation point _zs . Note that index s of constellation point _zs (as well as index q of constellation point _zq , described later) represents the discrete time of the symbol (the time interval between one symbol and the next symbol).

In FIG. 32, the coordinates of the signal point _zs are expressed in the form of complex numbers, and j represents the imaginary unit (√(-1)).

Figure 33 shows the coordinates of the signal points of 16QAM-2D-NUC used for the coding rates r(CR) = 2/15, 3/15, 4/15, 5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12,15, 13/15 of the LDPC code specified in ATSC3.0 when the modulation method is 16QAM.

In FIG. 33, similarly to FIG. 32, the coordinates of signal point _zs are expressed in the form of complex numbers, with j representing the imaginary unit.

In Figure 33, w#k represents the coordinates of the signal point in the first quadrant of the constellation.

In 2D-NUC, the signal points in the second quadrant of the constellation are placed at positions obtained by moving the signal points in the first quadrant symmetrically with respect to the Q axis, and the signal points in the third quadrant of the constellation are placed at positions obtained by moving the signal points in the first quadrant symmetrically with respect to the origin. And the signal points in the fourth quadrant of the constellation are placed at positions obtained by moving the signal points in the first quadrant symmetrically with respect to the I axis.

Here, when the modulation method is 2 ^m QAM, m bits are treated as one symbol, and the one symbol is mapped to a signal point corresponding to that symbol.

An m-bit symbol can be expressed, for example, by integer values from 0 to 2 ^m -1. If we now let b = 2 ^m /4, then the symbols y(0), y(1), ..., y(2 ^m -1), which are expressed by integer values from 0 to 2 ^m -1, can be classified into four symbols: y(0) to y(b-1), y(b) to y(2b-1), y(2b) to y(3b-1), and y(3b) to y(4b-1).

In Figure 33, the suffix k of w#k takes an integer value ranging from 0 to b-1, and w#k represents the coordinates of the signal point corresponding to symbol y(k) ranging from symbol y(0) to y(b-1).

The coordinates of the signal point corresponding to symbol y(k+b) in the range of symbols y(b) to y(2b-1) are represented by -conj(w#k), and the coordinates of the signal point corresponding to symbol y(k+2b) in the range of symbols y(2b) to y(3b-1) are represented by conj(w#k). Also, the coordinates of the signal point corresponding to symbol y(k+3b) in the range of symbols y(3b) to y(4b-1) are represented by -w#k.

Here, conj(w#k) represents the complex conjugate of w#k.

For example, when the modulation method is 16QAM, the m = 4-bit symbols y(0), y(1), ..., y(15) are classified into four ^symbols , y(0) through y(3), y(4) through y(7), y(8) through y(11), and y(12) through y(15), with b = 2/4 = 4.

For example, among the symbols y(0) to y(15), the symbol y(12) is a symbol y(k+3b) = y(0+3×4) in the range of symbols y(3b) to y(4b-1), where k = 0, so the coordinates of the signal point corresponding to the symbol y(12) are -w#k = -w0.

Now, if the coding rate r(CR) of the LDPC code is, for example, 9/15, then according to FIG. 33, when the modulation method is 16QAM and the coding rate r is 9/15, w0 is 0.2386+j0.5296, so the coordinate -w0 of the signal point corresponding to the symbol y(12) is -(0.2386+j0.5296).

Figure 34 shows an example of the coordinates of signal points of 1024QAM-1D-NUC used for the coding rates r(CR) = 2/15, 3/15, 4/15, 5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12/15, 13/15 of the LDPC code specified in ATSC3.0 when the modulation method is 1024QAM.

In Fig. 34, u#k represents the real part Re( _zs ) and the imaginary part Im( _zs ) of a complex number as the coordinates of the signal point _zs of the 1D-NUC, and is a component of a vector u=(u0, u1,..., u#V-1) called a position vector. The number V of components u#k of the position vector u is given by the formula V=√(2 ^m )/2.

Figure 35 shows the relationship between the 1024QAM symbol y and the position vector u (its components u#k).

Now, let us represent the 10-bit symbol y of 1024QAM as _y0,s , _y1,s , _y2,s , y3 _{,s, y4, s} , _y5,s , _y6,s , _y7,s , _y8,s , _y9,s, from its first bit (most significant bit).

A in FIG. 35 shows the correspondence between the even-numbered five bits _y1,s , y3 _,s , _y5,s , y7 _,s , and y9 _,s of a symbol y and u#k representing the real part Re( _zs ) (in coordinates) of a signal point _zs corresponding to the symbol y.

FIG. 35B shows the correspondence between the odd-numbered five bits _y0,s , y2 _,s , _y4,s , _y6,s , and _y8,s of a symbol y and u#k representing the imaginary part Im( _zs ) of a signal point _zs corresponding to that symbol y.

If the 10-bit symbol y = ( _y0,s , _y1,s , _y2,s , _y3,s , _y4,s , _y5,s , _y6,s , _y7,s , _y8,s , _y9,s ) of 1024QAM is, for example, (0,0,1,0,0,1,1,1,0,0), then the odd-numbered five bits ( _y0,s , _y2,s , _y4,s , _y6,s , _y8,s ) are (0,1,0,1,0), and the even-numbered five bits ( _y1,s , _y3, s, _y5,s , _y7,s , _y9,s ) are (0,0,1,1,0).

In A of FIG. 35, the even-numbered five bits (0,0,1,1,0) are associated with u11, and therefore the real part Re(z _s ) of the signal point z _s corresponding to the symbol y=(0,0,1,0,0,1,1,1,0,0) is u11.

In FIG. 35B, the odd-numbered five bits (0,1,0,1,0) are associated with u3, and therefore the imaginary part Im(z _s ) of the signal point z _s corresponding to the symbol y=(0,0,1,0,0,1,1,1,0,0) is u3.

On the other hand, if the coding rate r of the LDPC code is, for example, 6/15, then according to FIG. 34 above, for a 1D-NUC used when the modulation method is 1024QAM and the coding rate of the LDPC code r(CR) = 6/15, u3 is 0.1295 and u11 is 0.7196.

Therefore, the real part Re( _zs ) of the signal point _zs corresponding to the symbol y = (0,0,1,0,0,1,1,1,0,0) is u11 = 0.7196, and the imaginary part Im( _zs ) is u3 = 0.1295. As a result, the coordinates of the signal point _zs corresponding to the symbol y = (0,0,1,0,0,1,1,1,0,0) are expressed as 0.7196 + j0.1295.

In addition, the signal points of 1D-NUC are arranged in a grid pattern on a line parallel to the I axis or on a line parallel to the Q axis in the constellation. However, the interval between signal points is not constant. In addition, when transmitting the signal points (the data mapped to them), the average power of the signal points on the constellation can be normalized. If the mean square value of the absolute values of all the signal points (the coordinates of the signal points) on the constellation is expressed as P _ave , normalization can be _{performed by multiplying each signal point zs on the constellation by the reciprocal 1/(√P ave )} , which is the square root of the mean square value P _ave , by the signal point _zs on the constellation.

The transmission system in Figure 7 can use the constellations defined in ATSC3.0 as described above.

Figures 36 to 47 show the coordinates of UC signal points as specified in DVB-C.2.

That is, Fig. 36 is a diagram showing the real part Re( _zq ) of the coordinate _zq of a signal point of QPSK-UC (UC of QPSK) defined in DVB-C.2. Fig. 37 is a diagram showing the imaginary part Im( _zq ) of the coordinate _zq of a signal point of QPSK-UC defined in DVB-C.2.

Fig. 38 is a diagram showing a real part Re( _zq ) of a signal point coordinate _zq of 16QAM-UC (UC of 16QAM) defined in DVB-C.2. Fig. 39 is a diagram showing an imaginary part Im( _zq ) of a signal point coordinate _zq of 16QAM-UC defined in DVB-C.2.

Fig. 40 is a diagram showing the real part Re( _zq ) of the coordinate _zq of a signal point of 64QAM-UC (UC of 64QAM) defined in DVB-C.2. Fig. 41 is a diagram showing the imaginary part Im( _zq ) of the coordinate _zq of a signal point of 64QAM-UC defined in DVB-C.2.

Fig. 42 is a diagram showing a real part Re( _zq ) of a signal point coordinate _zq of 256QAM-UC (UC of 256QAM) defined in DVB-C.2. Fig. 43 is a diagram showing an imaginary part Im( _zq ) of a signal point coordinate _zq of 256QAM-UC defined in DVB-C.2.

Fig. 44 is a diagram showing a real part Re( _zq ) of a signal point coordinate _zq of 1024QAM-UC (UC of 1024QAM) defined in DVB-C.2. Fig. 45 is a diagram showing an imaginary part Im( _zq ) of a signal point coordinate _zq of 1024QAM-UC defined in DVB-C.2.

Fig. 46 is a diagram showing a real part Re( _zq ) of a signal point coordinate _zq of 4096QAM-UC (UC of 4096QAM) defined in DVB-C.2. Fig. 47 is a diagram showing an imaginary part Im( _zq ) of a signal point coordinate _zq of 4096QAM-UC defined in DVB-C.2.

In Fig. 36 to Fig. 47, y _i,q represents the (i+1)th bit from the beginning of the m-bit (e.g., 2 bits in QPSK) symbol of 2 ^m QAM. In addition, when transmitting (data mapped to) a UC signal point, the average power of the signal points on the constellation can be normalized. If the mean square value of the absolute values of all the signal points (coordinates of the signal points) on the constellation is represented as P _ave , normalization can be performed by multiplying each signal point z _q on the constellation by the reciprocal 1/(√P _ave ), which is the square root of the _mean square value P _ave .

The transmission system in Figure 7 can use the UCs specified in DVB-C.2 as described above.

Figures 48 to 56 show examples of the coordinates of signal points of other NUCs.

That is, Figure 48 shows an example of the coordinates of signal points for 16QAM-2D-NUC.

Figure 49 shows an example of the coordinates of signal points for 64QAM-2D-NUC.

Figures 50 and 51 show examples of the coordinates of signal points for 256QAM-2D-NUC.

Note that Figure 51 is a sequel to Figure 50.

In Figures 48 to 51, similarly to Figure 33, the coordinates of signal points _zs are expressed in the form of complex numbers, with j representing the imaginary unit.

In Figures 48 to 51, w#k represents the coordinates of the signal point in the first quadrant of the constellation, as in Figure 33.

Here, as explained in Figure 33, if an m-bit symbol is represented by integer values from 0 to ^2m -1 and b = ^2m /4, then the symbols y(0), y(1), ..., y( ^2m -1) represented by integer values from 0 to ^2m -1 can be classified into four symbols: y(0) to y(b-1), y(b) to y(2b-1), y(2b) to y(3b-1), and y(3b) to y(4b-1).

In Figures 48 to 51, as in Figure 33, the suffix k of w#k takes an integer value in the range of 0 to b-1, and w#k represents the coordinates of the signal point corresponding to symbol y(k) in the range of symbols y(0) to y(b-1).

Furthermore, in Figures 48 to 51, as in Figure 33, the coordinates of the signal point corresponding to symbol y(k+3b) in the range of symbols y(3b) to y(4b-1) are represented by -w#k.

However, in Figure 33, the coordinates of the signal point corresponding to symbol y(k+b) in the range of symbols y(b) to y(2b-1) are represented by -conj(w#k), and the coordinates of the signal point corresponding to symbol y(k+2b) in the range of symbols y(2b) to y(3b-1) are represented by conj(w#k), but in Figures 48 to 51, the sign of conj is reversed.

That is, in Figures 48 to 51, the coordinates of the signal point corresponding to symbol y(k+b) in the range of symbols y(b) to y(2b-1) are represented by conj(w#k), and the coordinates of the signal point corresponding to symbol y(k+2b) in the range of symbols y(2b) to y(3b-1) are represented by -conj(w#k).

Figure 52 shows an example of the coordinates of signal points for 1024QAM-1D-NUC.

That is, FIG. 52 is a diagram showing the relationship between the real part Re(z _s ) and imaginary part Im(z _s ) of a complex number as the coordinates of a signal point z _s of 1024QAM-1D-NUC, and the position vector u (component u_k of the vector).

Figure 53 shows the relationship between the 1024QAM symbol y and the position vector u (component u#k) in Figure 52.

That is, let us now represent the 10-bit symbol y of 1024QAM, from its first bit (most significant bit), as _y0,s , _y1,s , _y2,s , _y3,s , _{y4,s ,} y5,s, _y6,s , _y7,s , _y8,s , _y9,s .

A in FIG. 53 shows the correspondence between the odd-numbered five bits _y0,s , y2 _,s , _y4,s , _y6,s , _y8,s of a 10-bit symbol y and a position vector u#k representing the real part Re( _zs ) of (the coordinates of) a signal point _zs corresponding to that symbol y.

FIG. 53B shows the correspondence between the even-numbered five bits _y1,s , y3 _,s , _y5,s , _y7,s , and _y9,s of a 10-bit symbol y and a position vector u#k representing the imaginary part Im( _zs ) of the signal point _zs corresponding to that symbol y.

When a 10-bit symbol y of 1024QAM is mapped to a signal point _zs of 1024QAM-1D-NUC defined in Figs. 52 and 53, the method of finding the coordinates of the signal point _zs is the same as that described in Figs. 34 and 35, and therefore the description thereof will be omitted.

Figure 54 shows an example of the coordinates of signal points for 4096QAM-1D-NUC.

That is, FIG. 54 is a diagram showing the relationship between the real part Re(z _s ) and imaginary part Im(z _s ) of a complex number as the coordinates of a signal point z _s of 4096QAM-1D-NUC, and the position vector u(u#k).

Figures 55 and 56 show the relationship between the 4096QAM symbol y and the position vector u (component u#k) in Figure 54.

That is, let us represent the 12-bit symbol y of 4096QAM, from its first bit (most significant bit), as _y0,s , _y1,s , _y2,s , _y3,s , _y4,s , y5, _s , _y6,s , _y7,s , _{y8 ,s, y9 ,s, y10,s} , _y11,s .

FIG. 55 shows the correspondence between the odd-numbered 6 bits _y0,s , _y2,s , _y4,s , _y6,s , _y8,s , _y10,s of a 12-bit symbol y and a position vector u#k representing the real part Re( _zs ) of the signal point _zs corresponding to that symbol y.

FIG. 56 shows the correspondence between the even-numbered 6 bits _y1,s , _y3,s , _y5,s , _y7,s , _y9,s , and _y11,s of a 12-bit symbol y and a position vector u#k representing the imaginary part Im( _zs ) of the signal point _zs corresponding to that symbol y.

When a 12-bit symbol y of 4096QAM is mapped to a signal point _zs of 4096QAM-1D-NUC defined in Figs. 54 to 56, the method of finding the coordinates of the signal point _zs is the same as that described in Figs. 34 and 35, and therefore the description thereof will be omitted.

In transmitting (data mapped to) the NUC constellation points in Figures 48 to 56, the average power of the constellation points on the constellation can be normalized. If the mean square value of the absolute values of all (the coordinates of) the constellation points on the constellation is represented as P _ave , normalization can be performed by multiplying each constellation point _zs on the constellation by the reciprocal 1/(√P _ave ), which is the square root of the mean square value _{P ave} . In addition, in the above-mentioned FIG. 35 , the odd-numbered bits of the symbol y are associated with the position vector u#k representing the imaginary part Im( _zs ) of the signal point _zs , and the even-numbered bits of the symbol y are associated with the position vector u#k representing the real part Re( _zs ) of the signal point _zs . However, in FIG. 53 , FIG. 55 and FIG. 56 , on the other hand, the odd-numbered bits of the symbol y are associated with the position vector u#k representing the real part Re( _zs ) of the signal point _zs , and the even-numbered bits of the symbol y are associated with the position vector u#k representing the imaginary part Im( _zs ) of the signal point _zs .

<Block interleaver 25>

Figure 57 is a diagram explaining the block interleaving performed by the block interleaver 25 in Figure 9.

Block interleaving is performed by dividing one codeword of an LDPC code into a part called part 1 and a part called part 2, starting from the beginning.

If the length of part 1 (number of bits) is represented as Npart1 and the length of part 2 is represented as Npart2, then Npart1 + Npart2 is equal to the code length N.

Conceptually, in block interleaving, columns serving as storage areas for storing Npart1/m bits are arranged in one direction, the column (vertical) direction, and a number m, equal to the number of bits in the symbol, are arranged in the row direction perpendicular to the column direction, and each column is divided from the top into small units of 360 bits, which is the parallel factor P. These small column units are also called column units.

In block interleaving, as shown in Figure 57, part 1 of an LDPC code for one codeword is written from top to bottom (column direction) in the first column unit of a column, moving from left to right columns.

Then, when writing to the first column unit in the rightmost column is completed, as shown in FIG. 57, the process returns to the leftmost column, and writing is performed from top to bottom in the second column unit of the column, proceeding from left to right, and so on until part 1 of the LDPC code for one codeword is written.

When writing of part 1 of the LDPC code for one code word is completed, part 1 of the LDPC code is read out in m-bit units in the row direction from the first row of all m columns, as shown in Figure 57.

The m-bit units of part 1 are supplied as m-bit symbols from the block interleaver 25 to the mapper 117 (Figure 8).

The reading of part 1 in m-bit units is performed sequentially from the bottom row of m columns, and when the reading of part 1 is completed, part 2 is divided into m-bit units from the beginning and supplied from the block interleaver 25 to the mapper 117 as an m-bit symbol.

Therefore, part 1 is symbolized while being interleaved, and part 2 is symbolized sequentially, divided into m bits, without being interleaved.

The length of the column, Npart1/m, is a multiple of the parallel factor P, 360, and so that Npart1/m is a multiple of 360, an LDPC code for one codeword is divided into part 1 and part 2.

Figure 58 shows examples of part 1 and part 2 of an LDPC code with a code length N of 69120 bits when the modulation methods are QPSK, 16QAM, 64QAM, 256QAM, 1024QAM, and 4096QAM.

In Figure 58, when the modulation method is 1024QAM, part 1 is 68400 bits and part 2 is 720 bits, and when the modulation method is QPSK, 16QAM, 64QAM, 256QAM, or 4096QAM, part 1 is 69120 bits and part 2 is 0 bits in all cases. The number of columns required for block interleaving is equal to the number of bits in a symbol, m.

<Group-wise interleaving>

Figure 59 is a diagram explaining the group-wise interleaving performed by the group-wise interleaver 24 in Figure 9.

As shown in FIG. 59, in group-wise interleaving, the LDPC code of one codeword is divided into 360-bit units, which is equal to the parallel factor P, from the beginning of the codeword. The 360 bits of each unit are treated as bit groups, and the LDPC code of one codeword is interleaved in bit group units according to a predetermined pattern (hereinafter also referred to as the GW pattern).

Here, when an LDPC code of one codeword is divided into bit groups, the (i+1)th bit group from the beginning is hereinafter also referred to as bit group i.

When the parallel factor P is 360, for example, an LDPC code with a code length N of 1800 bits is divided into 5 (=1800/360) bit groups, namely, bit groups 0, 1, 2, 3, and 4. Furthermore, for example, an LDPC code with a code length N of 69120 bits is divided into 192 (=69120/360) bit groups, namely, bit groups 0, 1, ..., 191.

In the following, GW patterns will be represented by a sequence of numbers that represent bit groups. For example, for an LDPC code with a code length N of 1800 bits, a GW pattern of 4,2,0,3,1 represents interleaving (rearranging) the sequence of bit groups 0,1,2,3,4 into the sequence of bit groups 4,2,0,3,1.

For example, let x _i represent the (i+1)th code bit from the beginning of an LDPC code whose code length N is 1800 bits.

In this case, according to the group-wise interleaving of GW patterns 4, 2, 0, 3, 1, the 1800-bit LDPC code {x ₀ , x ₁ , ..., x ₁₇₉₉ } is interleaved in the order {x ₁₄₄₀ , x ₁₄₄₁ , ..., x ₁₇₉₉ }, {x ₇₂₀ , x ₇₂₁ , ..., x ₁₀₇₉ }, {x ₀ , x ₁ , ..., x ₃₅₉ }, {x ₁₀₈₀ , x ₁₀₈₁ , ..., x ₁₄₃₉ }, {x ₃₆₀ , x ₃₆₁ , ..., x ₇₁₉ }.

GW patterns can be set for each code length N of the LDPC code, each coding rate r, each modulation method, each constellation, and even for combinations of two or more of code length N, coding rate r, modulation method, and constellation.

<Example of GW pattern for LDPC code>

Figure 60 shows an example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in FIG. 60, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is
12, 8, 132, 26, 3, 18, 19, 98, 37, 190, 123, 81, 95, 167, 76, 66, 27, 46, 105, 28, 29, 170, 20, 96, 35, 177, 24, 86, 114, 63, 52, 80, 119, 153, 121, 107, 97, 129, 57, 38, 15, 91, 122, 14, 104, 175, 150, 1, 124, 72, 90, 32, 161, 78, 44, 73, 162, 5, 11, 179, 93, 6, 152, 180, 68, 36, 103, 160, 100, 138, 146, 9, 82, 187, 147, 7, 87, 17, 102, 69, 110, 130, 42, 16, 71, 2, 169, 58, 33, 136, 106, 140, 84, 79, 143, 156, 139, 55, 116, 4, 21, 144, 64, 70, 158, 48, 118, 184, 50, 181, 120, 174, 133, 115, 53, 127, 74, 25, 49, 88, 22, 89, 34, 126, 61, 94, 172, 131, 39, 99, 183, 163, 111, 155, 51, 191, 31, 128, 1 49, 56, 85, 109, 10, 151, 188, 40, 83, 41, 47, 178, 186, 43, 54, 164, 13, 142, 117, 92, 113, 182, 168, 165, 101, 171, 60, 166, 77, 30, 67, 23, 0, 65, 141, 185, 112, 145, 135, 108, 176, 45, 148, 137, 125, 62, 75, 189, 59, 173, 154, 157
are interleaved in the sequence.

<Example of the configuration of the receiving device 12>

Figure 61 is a block diagram showing an example configuration of the receiving device 12 in Figure 7.

The OFDM operation unit 151 receives an OFDM signal from the transmitting device 11 (FIG. 7) and performs signal processing on the OFDM signal. The data obtained by the signal processing performed by the OFDM operation unit 151 is supplied to the frame management unit 152.

The frame management unit 152 processes (interprets) the frames composed of data supplied from the OFDM processing unit 151, and supplies the resulting target data signal and control data signal to frequency deinterleavers 161 and 153, respectively.

The frequency deinterleaver 153 performs frequency deinterleaving on the data from the frame management unit 152 on a symbol-by-symbol basis and supplies the data to the demapper 154.

The demapper 154 performs orthogonal demodulation by demapping (signal point arrangement decoding) the data (constellation data) from the frequency deinterleaver 153 based on the signal point arrangement (constellation) determined by the orthogonal modulation performed on the transmitting device 11 side, and supplies the resulting data (LDPC code (likelihood)) to the LDPC decoder 155.

The LDPC decoder 155 performs LDPC decoding of the LDPC code from the demapper 154, and supplies the resulting LDPC target data (here, the BCH code) to the BCH decoder 156.

The BCH decoder 156 performs BCH decoding on the LDPC target data from the LDPC decoder 155, and outputs the resulting control data (signaling).

On the other hand, the frequency deinterleaver 161 performs frequency deinterleaving on the data from the frame management unit 152 on a symbol-by-symbol basis and supplies the data to a SISO/MISO decoder 162.

The SISO/MISO decoder 162 performs space-time decoding of the data from the frequency deinterleaver 161 and supplies it to the time deinterleaver 163.

The time deinterleaver 163 performs time deinterleaving on the data from the SISO/MISO decoder 162 on a symbol-by-symbol basis and supplies the data to the demapper 164.

The demapper 164 performs orthogonal demodulation by demapping (signal point arrangement decoding) the data (constellation data) from the time deinterleaver 163 based on the signal point arrangement (constellation) determined by the orthogonal modulation performed on the transmitting device 11 side, and supplies the resulting data to the bit deinterleaver 165.

The bit deinterleaver 165 performs bit deinterleaving of the data from the demapper 164, and supplies the LDPC code (likelihood), which is the bit deinterleaved data, to the LDPC decoder 166.

The LDPC decoder 166 performs LDPC decoding on the LDPC code from the bit deinterleaver 165, and supplies the resulting LDPC target data (here, the BCH code) to the BCH decoder 167.

The BCH decoder 167 performs BCH decoding on the LDPC target data from the LDPC decoder 155, and supplies the resulting data to the BB DeScrambler 168.

The BB descrambler 168 performs BB descrambling on the data from the BCH decoder 167 and supplies the resulting data to the null deletion unit (Null Deletion) 169.

The null deletion unit 169 deletes the nulls inserted by the padder 112 in FIG. 8 from the data from the BB descrambler 168 and supplies the data to the demultiplexer 170.

The demultiplexer 170 separates one or more streams (target data) multiplexed into the data from the null deletion unit 169, performs the necessary processing, and outputs them as an output stream.

The receiving device 12 can be configured without some of the blocks shown in FIG. 61. That is, for example, when the transmitting device 11 (FIG. 8) is configured without the time interleaver 118, the SISO/MISO encoder 119, the frequency interleaver 120, and the frequency interleaver 124, the receiving device 12 can be configured without the time deinterleaver 163, the SISO/MISO decoder 162, the frequency deinterleaver 161, and the frequency deinterleaver 153, which are blocks corresponding to the time interleaver 118, the SISO/MISO encoder 119, the frequency interleaver 120, and the frequency interleaver 124 of the transmitting device 11, respectively.

<Example of the configuration of bit deinterleaver 165>

Figure 62 is a block diagram showing an example configuration of the bit deinterleaver 165 in Figure 61.

The bit deinterleaver 165 is composed of a block deinterleaver 54 and a group-wise deinterleaver 55, and performs (bit) deinterleaving of the symbol bits of the symbols, which are the data from the demapper 164 (Figure 61).

That is, the block deinterleaver 54 performs block deinterleaving (the reverse process of block interleaving) corresponding to the block interleaving performed by the block interleaver 25 in FIG. 9 on the symbol bits of the symbol from the demapper 164, that is, block deinterleaving that returns the positions of the code bits (of the likelihoods) of the LDPC code rearranged by the block interleaving to their original positions, and supplies the resulting LDPC code to the group-wise deinterleaver 55.

The group-wise deinterleaver 55 performs group-wise deinterleaving (the inverse process of group-wise interleaving) on the LDPC code from the block deinterleaver 54, which corresponds to the group-wise interleaving performed by the group-wise interleaver 24 in FIG. 9. In other words, the group-wise deinterleaver 55 performs group-wise deinterleaving to return the code bits of the LDPC code, whose order has been changed on a bit-group basis by the group-wise interleaving described in FIG. 59, to their original order by rearranging them on a bit-group basis.

Here, when the LDPC code supplied from the demapper 164 to the bit deinterleaver 165 has been subjected to parity interleaving, group-wise interleaving, and block interleaving, the bit deinterleaver 165 can perform all of the following: parity deinterleaving corresponding to parity interleaving (the inverse process of parity interleaving, i.e., parity deinterleaving that returns the code bits of the LDPC code whose order has been changed by parity interleaving to their original order), block deinterleaving corresponding to block interleaving, and group-wise deinterleaving corresponding to group-wise interleaving.

However, in the bit deinterleaver 165 of FIG. 62, a block deinterleaver 54 that performs block deinterleaving corresponding to block interleaving and a group-wise deinterleaver 55 that performs group-wise deinterleaving corresponding to group-wise interleaving are provided, but a block that performs parity deinterleaving corresponding to parity interleaving is not provided, and parity deinterleaving is not performed.

Therefore, the bit deinterleaver 165 (group-wise deinterleaver 55) supplies the LDPC decoder 166 with an LDPC code that has been block deinterleaved and group-wise deinterleaved, but has not been parity deinterleaved.

The LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 using a transformed check matrix obtained by performing at least column permutation equivalent to parity interleaving on the type B check matrix H used for LDPC encoding by the LDPC encoder 115 in FIG. 8, or a transformed check matrix (FIG. 29) obtained by performing row permutation on the type A check matrix (FIG. 27), and outputs the resulting data as the decoded result of the LDPC target data.

Figure 63 is a flowchart explaining the processing performed by the demapper 164, bit deinterleaver 165, and LDPC decoder 166 in Figure 62.

In step S111, the demapper 164 demaps and orthogonally demodulates the data from the time deinterleaver 163 (data on the constellation mapped to the signal points) and supplies it to the bit deinterleaver 165, and the process proceeds to step S112.

In step S112, the bit deinterleaver 165 deinterleaves (bit deinterleaves) the data from the demapper 164, and processing proceeds to step S113.

That is, in step S112, in the bit deinterleaver 165, the block deinterleaver 54 performs block deinterleaving on the data (symbols) from the demapper 164, and supplies the resulting code bits of the LDPC code to the group-wise deinterleaver 55.

The group-wise deinterleaver 55 performs group-wise deinterleaving on the LDPC code from the block deinterleaver 54, and supplies the resulting LDPC code (the likelihood of the LDPC code) to the LDPC decoder 166.

In step S113, the LDPC decoder 166 performs LDPC decoding of the LDPC code from the group-wise deinterleaver 55 using the check matrix H used for LDPC encoding by the LDPC encoder 115 in FIG. 8, that is, using, for example, a converted check matrix obtained from the check matrix H, and outputs the resulting data to the BCH decoder 167 as the decoded result of the LDPC target data.

In FIG. 62, as in the case of FIG. 9, for ease of explanation, the block deinterleaver 54 that performs block deinterleaving and the group-wise deinterleaver 55 that performs group-wise deinterleaving are configured separately, but the block deinterleaver 54 and the group-wise deinterleaver 55 can be configured as an integrated unit.

In addition, if group-wise interleaving is not performed in the transmitting device 11, the receiving device 12 can be configured without providing a group-wise deinterleaver 55 that performs group-wise deinterleaving.

<LDPC Decoding>

The LDPC decoding performed by the LDPC decoder 166 in Figure 61 will now be explained in further detail.

As described above, in the LDPC decoder 166 in FIG. 61, LDPC decoding of an LDPC code that has been subjected to block deinterleaving and group-wise deinterleaving from the group-wise deinterleaver 55 and has not been subjected to parity deinterleaving is performed using a transformed check matrix obtained by performing at least column permutation equivalent to parity interleaving on the type B check matrix H used for LDPC encoding by the LDPC encoder 115 in FIG. 8, or a transformed check matrix (FIG. 29) obtained by performing row permutation on the type A check matrix (FIG. 27).

Here, a method of LDPC decoding has been proposed that uses a conversion check matrix to perform LDPC decoding, making it possible to suppress the circuit size while keeping the operating frequency within a fully feasible range (see, for example, Patent No. 4224777).

First, we will explain the previously proposed LDPC decoding using a conversion check matrix with reference to Figures 64 to 67.

Figure 64 shows an example of a check matrix H for an LDPC code with a code length N of 90 and a coding rate of 2/3.

Note that in Figure 64 (as well as Figures 65 and 66 described below), 0 is represented by a period (.).

In the check matrix H in Figure 64, the parity matrix has a staircase structure.

Figure 65 shows the check matrix H' obtained by applying the row permutation of equation (11) and the column permutation of equation (12) to the check matrix H in Figure 64.

Line replacement: 6s+t+1st line → 5t+s+1st line
...(11)

Column permutation: 6x+y+column 61 → 5y+x+column 61
...(12)

However, in formulas (11) and (12), s, t, x, and y are integers in the ranges 0≦s<5, 0≦t<6, 0≦x<5, and 0≦t<6, respectively.

According to the row permutation of equation (11), the 1st, 7th, 13th, 19th, and 25th lines, which have a remainder of 1 when divided by 6, are substituted with the 1st, 2nd, 3rd, 4th, and 5th lines, respectively, and the 2nd, 8th, 14th, 20th, and 26th lines, which have a remainder of 2 when divided by 6, are substituted with the 6th, 7th, 8th, 9th, and 10th lines, respectively.

In addition, according to the column permutation of equation (12), for columns 61 and onwards (parity matrix), columns 61, 67, 73, 79, and 85, which have a remainder of 1 when divided by 6, are permuted to columns 61, 62, 63, 64, and 65, respectively, and columns 62, 68, 74, 80, and 86, which have a remainder of 2 when divided by 6, are permuted to columns 66, 67, 68, 69, and 70, respectively.

In this way, the matrix obtained by permuting rows and columns on the check matrix H in Figure 64 is the check matrix H' in Figure 65.

Here, even if row permutation is performed on the check matrix H, it does not affect the arrangement of the code bits of the LDPC code.

The column permutation in equation (12) corresponds to the parity interleaving described above, in which the K+qx+y+1th code bit is interleaved at the K+Py+x+1th code bit position, when the information length K is 60, the parallel factor P is 5, and the divisor q (=M/P) of the parity length M (30 in this case) is 6.

Therefore, the check matrix H' in Figure 65 is a transformed check matrix obtained by at least performing column permutation to replace the K+qx+y+1-th column of the check matrix H in Figure 64 (hereinafter referred to as the original check matrix, as appropriate) with the K+Py+x+1-th column.

For the conversion check matrix H' of Figure 65, when the LDPC code of the original check matrix H of Figure 64 is multiplied by the same permutation as that of formula (12), a zero vector is output.That is, when the row vector c of the LDPC code (one codeword) of the original check matrix H is obtained by carrying out the column permutation of formula (12) as the row vector c', according to the nature of check matrix, Hc ^T becomes a zero vector, so naturally H'c' ^T also becomes a zero vector.

From the above, the converted check matrix H' in Figure 65 is the check matrix of the LDPC code c' obtained by performing the column permutation of equation (12) on the LDPC code c of the original check matrix H.

Therefore, by performing the column permutation of equation (12) on the LDPC code c of the original check matrix H, and then decoding (LDPC decoding) the LDPC code c' after the column permutation using the converted check matrix H' in FIG. 65, and then performing the inverse permutation of the column permutation of equation (12) on the decoded result, it is possible to obtain the same decoding result as when the LDPC code of the original check matrix H is decoded using that check matrix H.

Figure 66 shows the conversion check matrix H' in Figure 65, with spacing between 5x5 (5 rows and 5 columns) matrix units.

In FIG. 66, the conversion check matrix H' is expressed as a combination of a 5x5 (=PxP) unit matrix, which is the parallel factor P; a matrix in which one or more of the units in the unit matrix have been changed to zero (hereinafter, appropriately referred to as a quasi-unit matrix); a matrix in which a unit matrix or a quasi-unit matrix has been cyclically shifted (hereinafter, appropriately referred to as a shift matrix); a sum of two or more of a unit matrix, a quasi-unit matrix, or a shift matrix (hereinafter, appropriately referred to as a sum matrix); and a 5x5 zero matrix.

The conversion check matrix H' in FIG. 66 can be said to be composed of a 5x5 unit matrix, quasi-unit matrix, shift matrix, sum matrix, and 0 matrix. Therefore, these 5x5 matrices (unit matrix, quasi-unit matrix, shift matrix, sum matrix, and 0 matrix) that compose the conversion check matrix H' will be referred to as constituent matrices below, where appropriate.

To decode an LDPC code of a check matrix represented by a P×P constituent matrix, an architecture that simultaneously performs P check node operations and variable node operations can be used.

Figure 67 is a block diagram showing an example of the configuration of a decoding device that performs such decoding.

In other words, FIG. 67 shows an example of the configuration of a decoding device that decodes an LDPC code using the transformed check matrix H' in FIG. 66 obtained by performing at least the column permutation of equation (12) on the original check matrix H in FIG. 64.

The decoding device of FIG. 67 comprises an edge data storage memory 300 consisting of six FIFOs ₃₀₀₁ to ₃₀₀₆ , a selector 301 which selects the FIFOs ₃₀₀₁ to ₃₀₀₆ , a check node calculation unit 302, two cyclic shift circuits 303 and 308, an edge data storage memory 304 consisting of ₁₈ FIFOs ₃₀₄₁ to 30418, a selector ₃₀₅ which selects the FIFOs 3041 to ₃₀₄₁₈ , a received data memory 306 which stores received data, a variable node calculation unit 307, a decoded word calculation unit 309, a received data rearrangement unit 310, and a decoded data rearrangement unit 311.

First, we will explain how data is stored in edge data storage memories 300 and 304.

The edge data storage memory 300 is composed of six FIFOs ₃₀₀₁ to ₃₀₀₆ , which is the number of rows of the conversion check matrix H' in Fig. 66, 30, divided by the number of rows of the constituent matrix (parallel factor P), 5. The FIFO _300y (y = 1, 2, ..., 6) is composed of a storage area with a plurality of stages, and the storage area of each stage is capable of simultaneously reading and writing messages corresponding to five edges, which are the number of rows and columns (parallel factor P) of the constituent matrix. The number of stages of the storage area of the FIFO _300y is 9, which is the maximum number of 1s (Hamming weight) in the row direction of the conversion check matrix in Fig. 66.

In FIFO 300 ₁ , data (message v _i from variable node) corresponding to the position of 1 from the first row to the fifth row of conversion check matrix H' in Fig. 66 is stored in a form in which each row is packed horizontally (ignoring 0). That is, if the jth row and the ith column are represented as (j, i), the first-stage storage area of FIFO 300 ₁ stores data corresponding to the position of 1 in the 5x5 unit matrix (1,1) to (5,5) of conversion check matrix H'. The second-stage storage area stores data corresponding to the position of 1 in the shift matrix (the shift matrix that cyclically shifts the 5x5 unit matrix to the right by three) from (1,21) to (5,25) of conversion check matrix H'. Similarly, data is stored in the third to eighth-stage storage areas in association with conversion check matrix H'. Then, in the memory area of the 9th stage, data corresponding to the positions of 1 in the shift matrix from (1,86) to (5,90) of the conversion check matrix H' (a shift matrix in which the 1 in the first row of a 5 x 5 unit matrix is replaced with 0 and cyclically shifted by one position to the left) is stored.

_FIFO3002 stores data corresponding to the position of 1 from the 6th row to the 10th row of the conversion check matrix H' in Fig. 66. That is, the first-stage storage area of _FIFO3002 stores data corresponding to the position of 1 of the first shift matrix that constitutes the sum matrix (the first shift matrix that cyclically shifts a 5x5 unit matrix to the right by one place and the second shift matrix that cyclically shifts to the right by two places) of the conversion check matrix H'.In addition, the second-stage storage area stores data corresponding to the position of 1 of the second shift matrix that constitutes the sum matrix (6,1) to (10,5) of the conversion check matrix H'.

That is, for a constituent matrix with a weight of 2 or more, when the constituent matrix is expressed as a sum of a P×P unit matrix with a weight of 1, a quasi-unit matrix in which one or more of the 1 elements of the unit matrix have become 0, or a shift matrix obtained by cyclically shifting a unit matrix or a quasi-unit matrix, data corresponding to the position of 1 in the unit matrix, quasi-unit matrix, or shift matrix with a weight of 1 (messages corresponding to branches belonging to the unit matrix, quasi-unit matrix, or shift matrix) is stored at the same address (the same FIFO among FIFOs ₃₀₀₁ to ₃₀₀₆ ).

Then, data is stored in the memory areas from the third to ninth rows in association with the conversion check matrix H'.

Similarly, FIFOs ₃₀₀₃ to ₃₀₀₆ store data in association with the conversion check matrix H'.

The edge data storage memory 304 is composed of 18 FIFOs ₃₀₄₁ to ₃₀₄₁₈ , which is obtained by dividing the number of columns of the conversion check matrix H', 90, by the number of columns of the constituent matrix (parallel factor P), 5. The FIFOs _304x (x=1, 2, ..., 18) are composed of storage areas with a plurality of stages, and the storage area of each stage is capable of simultaneously reading and writing messages corresponding to five edges, which are the number of rows and columns of the constituent matrix (parallel factor P).

In FIFO 304 ₁ , data corresponding to the positions of 1 from the first column to the fifth column of the conversion check matrix H' in FIG.66 (message u _j from check node) is stored in a form in which each column is packed vertically (ignoring 0). That is, in the first-stage storage area of FIFO 304 ₁ , data corresponding to the positions of 1 of the 5×5 unit matrix from (1,1) to (5,5) of the conversion check matrix H' is stored. In the second-stage storage area, data corresponding to the positions of 1 of the first shift matrix constituting the sum matrix from (6,1) to (10,5) of the conversion check matrix H' (the sum matrix being the sum of the first shift matrix obtained by cyclically shifting the 5×5 unit matrix to the right by one place and the second shift matrix obtained by cyclically shifting the 5×5 unit matrix to the right by two places) is stored. In addition, in the third-stage storage area, data corresponding to the positions of 1 of the second shift matrix constituting the sum matrix from (6,1) to (10,5) of the conversion check matrix H' is stored.

That is, for a constituent matrix with a weight of 2 or more, when the constituent matrix is expressed as a sum of a P×P unit matrix with a weight of 1, a quasi-unit matrix in which one or more of the 1 elements of the unit matrix have become 0, or a shift matrix obtained by cyclically shifting a unit matrix or a quasi-unit matrix, data corresponding to the position of 1 in the unit matrix, quasi-unit matrix, or shift matrix with a weight of 1 (messages corresponding to branches belonging to the unit matrix, quasi-unit matrix, or shift matrix) is stored at the same address (the same FIFO among FIFOs _304-1 to _304-18 ).

Similarly, data is stored in the fourth and fifth storage areas in association with the transformed check matrix H'. The number of storage areas in the FIFO ₃₀₄₁ is five, which is the maximum number of 1's (Hamming weights) in the row direction in the first to fifth columns of the transformed check matrix H'.

FIFOs ₃₀₄₂ and ₃₀₄₃ similarly store data in association with the conversion check matrix H', and each has a length (number of stages) of 5. FIFOs ₃₀₄₄ to ₃₀₄₁₂ similarly store data in association with the conversion check matrix H', and each has a length of 3. _{FIFOs 30413} to ₃₀₄₁₈ similarly store data in association with the conversion check matrix H', and each has a length of 2.

Next, we will explain the operation of the decoding device in Figure 67.

The edge data storage memory 300 is composed of six FIFOs ₃₀₀₁ to ₃₀₀₆ , and selects a FIFO from the FIFOs ₃₀₀₁ to ₃₀₀₆ to store data according to information (Matrix data) D312 indicating which row of the conversion check matrix H' in Fig. 66 the five messages D311 supplied from the cyclic shift circuit 308 in the previous stage belong to, and stores the five messages D311 in the selected FIFO in order. When reading data, the edge data storage memory 300 reads the five messages _D3001 in order from the FIFO ₃₀₀₁ and supplies them to the selector 301 in the next stage. After finishing reading the messages from the FIFO ₃₀₀₁ , the edge data storage memory 300 also reads messages in order from the FIFOs ₃₀₀₂ to ₃₀₀₆ and supplies them to the selector 301.

The selector 301 selects five messages from the FIFO from which data is currently being read out of the FIFOs 300 ₁ to 300 ₆ in accordance with the select signal D 301 , and supplies them to the check node calculation unit 302 as message D 302 .

The check node calculation unit 302 is made up of five check node calculators _302-1 to _302-5 , and performs check node calculation according to equation ( ₇ ) using messages D302 ( _D302-1 to D302-5) (messages v _i in equation (7)) supplied via the selector 301. The check node calculation unit 302 supplies five messages D303 ( _D303-1 to _D303-5 ) (messages u _j in equation (7)) obtained as a result of the check node calculation to the cyclic shift circuit 303.

The cyclic shift circuit 303 cyclically shifts the five messages _D303-1 to _D303-5 calculated by the check node calculation unit 302, based on information (Matrix data) D305 indicating how many cyclic shifts the original unit matrix (or quasi-unit matrix) of the corresponding edge in the converted parity check matrix H' has been performed, and supplies the result to the edge data storage memory 304 as a message D304.

The edge data storage memory 304 is made up of 18 FIFOs ₃₀₄₁ to ₃₀₄₁₈ , and selects a FIFO from FIFOs ₃₀₄₁ to ₃₀₄₁₈ to store data according to information D305 indicating which row of the conversion check matrix H' the five messages D304 supplied from the previous stage cyclic shift circuit 303 belong to, and stores the five messages D304 in the selected FIFO in sequence. When reading data, the edge data storage memory 304 reads five messages _D3061 from FIFO 3041 in sequence and supplies them to the selector 305 in the next stage. After finishing reading data from _{FIFO 3041 ,} the edge data storage memory 304 also reads messages from FIFOs ₃₀₄₂ to ₃₀₄₁₈ in sequence and supplies them to the selector 305.

The selector 305 selects five messages from the FIFO from which data is currently being read out of the FIFOs 304 ₁ to 304 ₁₈ in accordance with the select signal D 307 , and supplies them to the variable node calculation unit 307 and the decoded word calculation unit 309 as message D 308 .

Meanwhile, the received data rearrangement unit 310 rearranges the LDPC code D313 corresponding to the check matrix H in FIG. 64 received through the communication path 13 by performing column permutation according to equation (12), and supplies the result as received data D314 to the received data memory 306. The received data memory 306 calculates and stores the received LLR (log-likelihood ratio) from the received data D314 supplied from the received data rearrangement unit 310, and supplies the received LLR in groups of five as received values D309 to the variable node calculation unit 307 and the decoded word calculation unit 309.

The variable node calculation unit 307 consists of five variable node calculators ₃₀₇₁ to ₃₀₇₅ , and performs variable node calculations in accordance with equation (1) using messages D308 ( _D3081 to _D3085 ) (messages _uj in equation (1)) supplied through the selector 305 and five received values D309 (received values _u0i in equation (1)) supplied from the received data memory 306, and supplies messages D310 ( _D3101 to _D3105 ) (messages _vi in equation (1)) obtained as a result of the calculation to the cyclic shift circuit 308.

The cyclic shift circuit 308 cyclically shifts the messages _D3101 to _D3105 calculated by the variable node calculation unit 307 based on information indicating how many cyclic shifts the original unit matrix (or quasi-unit matrix) in the converted parity check matrix H' that the corresponding edge is obtained by, and supplies the result to the edge data storage memory 300 as a message D311.

By performing one cycle of the above operations, one decoding of the LDPC code (variable node calculation and check node calculation) can be performed. After the decoding device in FIG. 67 decodes the LDPC code a predetermined number of times, the decoded word calculation unit 309 and the decoded data rearrangement unit 311 calculate and output the final decoding result.

That is, the decoded word calculation unit 309 is made up of five decoded word calculators ₃₀₉₁ to ₃₀₉₅ , and uses the five messages D308 ( _D3081 to D3085) (messages _uj in equation ( ₅ )) output by the selector 305 and five received values D309 (received values _u0i in equation (5)) supplied from the received data memory 306 to calculate a decoding result (decoded word) based on equation (5) as the final stage of multiple decoding operations, and supplies the resulting decoded data D315 to the decoded data rearrangement unit 311.

The decoded data rearrangement unit 311 rearranges the order of the decoded data D315 supplied from the decoded word calculation unit 309 by performing the inverse permutation of the column permutation in equation (12), and outputs the final decoded result D316.

As described above, by performing row permutation or column permutation or both on the parity check matrix (original parity check matrix) and converting it into a P×P unit matrix, a quasi-unit matrix in which one or more of the 1s in its elements are changed to 0, a shift matrix in which a unit matrix or a quasi-unit matrix is cyclically shifted, a unit matrix, a quasi-unit matrix, or a sum matrix which is the sum of multiple shift matrices, and a combination of P×P 0 matrices, that is, a parity check matrix (converted parity check matrix) that can be expressed as a combination of constituent matrices, it becomes possible to adopt an architecture for decoding LDPC codes in which check node operations and variable node operations are performed simultaneously on P nodes, the number of which is smaller than the number of rows and columns of the parity check matrix. When adopting an architecture in which node operations (check node operations and variable node operations) are performed simultaneously on P nodes, the number of which is smaller than the number of rows and columns of the parity check matrix, it is possible to suppress the operating frequency to a feasible range and perform a large number of repeated decodings, compared to when node operations are performed simultaneously on a number equal to the number of rows and columns of the parity check matrix.

The LDPC decoder 166 constituting the receiving device 12 in FIG. 61 performs LDPC decoding by simultaneously performing P check node operations and variable node operations, similar to the decoding device in FIG. 67, for example.

In other words, for the sake of simplicity, if the check matrix of the LDPC code output by the LDPC encoder 115 constituting the transmitting device 11 in FIG. 8 is, for example, the check matrix H shown in FIG. 64, in which the parity matrix has a staircase structure, the parity interleaver 23 of the transmitting device 11 performs parity interleaving to interleave the K+qx+y+1th code bit at the K+Py+x+1th code bit position, with the information length K set to 60, the parallel factor P set to 5, and the divisor q (=M/P) of the parity length M set to 6.

As described above, this parity interleaving corresponds to the column permutation in equation (12), so the LDPC decoder 166 does not need to perform the column permutation in equation (12).

For this reason, in the receiving device 12 of FIG. 61, as described above, the group-wise deinterleaver 55 supplies the LDPC decoder 166 with an LDPC code that has not been subjected to parity deinterleaving, that is, an LDPC code that has been subjected to the column permutation of equation (12), and the LDPC decoder 166 performs processing similar to that of the decoding device of FIG. 67, except that the column permutation of equation (12) is not performed.

That is, FIG. 68 is a diagram showing an example configuration of the LDPC decoder 166 in FIG. 61.

In FIG. 68, the LDPC decoder 166 is configured in the same manner as the decoding device in FIG. 67, except that the received data rearrangement unit 310 in FIG. 67 is not provided, and performs the same processing as the decoding device in FIG. 67, except that the column permutation in equation (12) is not performed, so a description thereof will be omitted.

As described above, the LDPC decoder 166 can be configured without the received data rearrangement unit 310, so the size can be reduced compared to the decoding device in FIG. 67.

In addition, in Figures 64 to 68, for simplicity of explanation, the code length N of the LDPC code is set to 90, the information length K is set to 60, the parallel factor (number of rows and columns of the constituent matrix) P is set to 5, and the divisor q (= M/P) of the parity length M is set to 6, but the code length N, information length K, parallel factor P, and divisor q (= M/P) are not limited to the values mentioned above.

In other words, in the transmitting device 11 of FIG. 8, the LDPC encoder 115 outputs an LDPC code with, for example, a code length N of 64800, 16200, 69120, etc., an information length K of N-Pq (=N-M), a parallel factor P of 360, and a divisor q of M/P. The LDPC decoder 166 of FIG. 68 is applicable to LDPC decoding of such an LDPC code by simultaneously performing P check node operations and variable node operations.

In addition, if the parity portion of the decoded result is not required after the LDPC decoder 166 decodes the LDPC code and only the information bits of the decoded result are output, the LDPC decoder 166 can be configured without the decoded data rearrangement unit 311.

<Example of the configuration of block deinterleaver 54>

Figure 69 is a diagram explaining the block deinterleaving performed by the block deinterleaver 54 in Figure 62.

In block deinterleaving, the reverse process of the block interleaving performed by the block interleaver 25 described in FIG. 57 is performed, and the order of the code bits of the LDPC code is returned (restored) to the original order.

In other words, in block deinterleaving, for example, like block interleaving, the arrangement of the LDPC code bits is restored to the original arrangement by writing and reading the LDPC code into m columns, which is equal to the number of bits in the symbol m.

However, in block deinterleaving, the LDPC codes are written in the same order as the LDPC codes are read in block interleaving. Furthermore, in block deinterleaving, the LDPC codes are read in the same order as the LDPC codes are written in block interleaving.

That is, for part 1 of the LDPC code, as shown in FIG. 69, part 1 of the LDPC code, which is an m-bit symbol unit, is written in the row direction from the first row of all m columns. That is, the code bits of the LDPC code, which is an m-bit symbol, are written in the row direction.

The writing of part 1 in m-bit units is performed sequentially from the top to the bottom row of m columns, and when the writing of part 1 is completed, part 1 is read from the top to the bottom of the first column unit of the column, from left to right, as shown in Figure 69.

When reading out to the rightmost column is complete, as shown in FIG. 69, the process returns to the leftmost column, and part 1 of the second column unit is read out from the top to the bottom, proceeding from left to right toward the columns, and so on until part 1 of the LDPC code for one codeword is read out.

When reading of part 1 of the LDPC code of one code word is completed, for part 2, which is an m-bit symbol unit, the m-bit symbol unit is sequentially concatenated after part 1, and the symbol-based LDPC code is returned to the code bit arrangement of the original LDPC code of one code word (the LDPC code before block interleaving).

<Other configuration examples of bit deinterleaver 165>

Figure 70 is a block diagram showing another example configuration of the bit deinterleaver 165 in Figure 61.

In the figure, parts corresponding to those in Figure 62 are given the same reference numerals, and their explanation will be omitted below as appropriate.

In other words, the bit deinterleaver 165 in FIG. 70 is configured in the same way as in FIG. 62, except that a parity deinterleaver 1011 is newly provided.

In FIG. 70, the bit deinterleaver 165 is composed of a block deinterleaver 54, a group-wise deinterleaver 55, and a parity deinterleaver 1011, and performs bit deinterleaving of the code bits of the LDPC code from the demapper 164.

That is, the block deinterleaver 54 performs block deinterleaving (the reverse process of block interleaving) on the LDPC code from the demapper 164, which corresponds to the block interleaving performed by the block interleaver 25 of the transmitting device 11, that is, block deinterleaving that returns the positions of the code bits that have been swapped by the block interleaving to their original positions, and supplies the resulting LDPC code to the group-wise deinterleaver 55.

The group-wise deinterleaver 55 performs group-wise deinterleaving on the LDPC code from the block deinterleaver 54, which corresponds to the group-wise interleaving performed as a rearrangement process by the group-wise interleaver 24 of the transmitting device 11.

The LDPC code resulting from group-wise deinterleaving is supplied from group-wise deinterleaver 55 to parity deinterleaver 1011.

The parity deinterleaver 1011 performs parity deinterleaving (the inverse process of parity interleaving) on the code bits after group-wise deinterleaving in the group-wise deinterleaver 55, which corresponds to the parity interleaving performed by the parity interleaver 23 of the transmitting device 11, i.e., performs parity deinterleaving to return the code bits of the LDPC code whose order has been changed by parity interleaving to their original order.

The LDPC code obtained as a result of the parity deinterleaving is supplied from the parity deinterleaver 1011 to the LDPC decoder 166.

Therefore, in the bit deinterleaver 165 of FIG. 70, the LDPC decoder 166 is supplied with an LDPC code that has been block deinterleaved, group-wise deinterleaved, and parity deinterleaved, i.e., an LDPC code obtained by LDPC encoding according to the check matrix H.

The LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 using the check matrix H used for LDPC encoding by the LDPC encoder 115 of the transmitting device 11.

That is, for the Type B method, the LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 using the check matrix H (of the Type B method) used for LDPC encoding by the LDPC encoder 115 of the transmitting device 11, or using a transformed check matrix obtained by performing at least column permutation equivalent to parity interleaving on the check matrix H. For the Type A method, the LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 using a check matrix (FIG. 28) obtained by performing column permutation on the check matrix (FIG. 27) (of the Type A method) used for LDPC encoding by the LDPC encoder 115 of the transmitting device 11, or a transformed check matrix (FIG. 29) obtained by performing row permutation on the check matrix (FIG. 27) used for LDPC encoding.

In FIG. 70, the LDPC decoder 166 is supplied with an LDPC code obtained by LDPC encoding according to the check matrix H from the bit deinterleaver 165 (the parity deinterleaver 1011). When the LDPC code is decoded using the check matrix H of the type B method used for LDPC encoding by the LDPC encoder 115 of the transmitting device 11, or the check matrix (FIG. 28) obtained by performing column permutation on the check matrix (FIG. 27) of the type A method used for LDPC encoding, the LDPC decoder 166 can be configured, for example, as a decoding device that performs LDPC decoding using a full serial decoding method in which message (check node message, variable node message) calculations are performed sequentially for each node, or a decoding device that performs LDPC decoding using a full parallel decoding method in which message calculations are performed simultaneously (in parallel) for all nodes.

In the LDPC decoder 166, when LDPC decoding of the LDPC code is performed using a conversion check matrix obtained by performing at least column permutation equivalent to parity interleaving on the check matrix H of the type B method used for LDPC encoding by the LDPC encoder 115 of the transmitting device 11, or a conversion check matrix (FIG. 29) obtained by performing row permutation on the check matrix H of the type A method used for LDPC encoding (FIG. 27), the LDPC decoder 166 is a decoding device with an architecture that simultaneously performs P (or a divisor of P other than 1) check node operations and variable node operations, and can be configured as a decoding device (FIG. 67) having a received data rearrangement unit 310 that rearranges the code bits of the LDPC code by performing column permutation similar to the column permutation (parity interleaving) for obtaining the conversion check matrix on the LDPC code.

In FIG. 70, for ease of explanation, the block deinterleaver 54 that performs block deinterleaving, the groupwise deinterleaver 55 that performs groupwise deinterleaving, and the parity deinterleaver 1011 that performs parity deinterleaving are configured separately, but two or more of the block deinterleaver 54, groupwise deinterleaver 55, and parity deinterleaver 1011 can be configured integrally, similar to the parity interleaver 23, groupwise interleaver 24, and block interleaver 25 of the transmitting device 11.

<Example of receiving system configuration>

Figure 71 is a block diagram showing a first example configuration of a receiving system to which the receiving device 12 can be applied.

In FIG. 71, the receiving system is composed of an acquisition unit 1101, a transmission path decoding processing unit 1102, and an information source decoding processing unit 1103.

The acquisition unit 1101 acquires a signal including an LDPC code obtained by LDPC-encoding at least LDPC target data such as program image data and audio data via a transmission path (communication path) (not shown), such as terrestrial digital broadcasting, satellite digital broadcasting, a CATV network, the Internet, or other networks, and supplies the signal to the transmission path decoding processing unit 1102.

Here, when the signal acquired by the acquisition unit 1101 is broadcast from a broadcasting station via terrestrial waves, satellite waves, a CATV (Cable Television) network, or the like, the acquisition unit 1101 is configured with a tuner, an STB (Set Top Box), or the like. Also, when the signal acquired by the acquisition unit 1101 is transmitted by multicast from a web server, such as IPTV (Internet Protocol Television), the acquisition unit 1101 is configured with a network I/F (Interface) such as a NIC (Network Interface Card), for example.

The transmission path decoding processing unit 1102 corresponds to the receiving device 12. The transmission path decoding processing unit 1102 performs a transmission path decoding process, which includes at least a process for correcting errors that occur in the transmission path, on the signal acquired by the acquisition unit 1101 via the transmission path, and supplies the resulting signal to the information source decoding processing unit 1103.

In other words, the signal acquired by the acquisition unit 1101 via the transmission path is a signal obtained by at least performing error correction coding to correct errors that occur on the transmission path, and the transmission path decoding processing unit 1102 performs transmission path decoding processing such as error correction processing on such a signal.

Here, examples of error correction coding include LDPC coding and BCH coding. Here, at least LDPC coding is used as the error correction coding.

In addition, the transmission path decoding process may include demodulation of modulated signals.

The information source decoding processing unit 1103 performs information source decoding processing on the signal that has been subjected to transmission path decoding processing, which includes at least a process of expanding compressed information to the original information.

In other words, the signal acquired by the acquisition unit 1101 via the transmission path may have undergone compression encoding to compress the information in order to reduce the amount of data such as images and audio. In such a case, the information source decoding processing unit 1103 performs information source decoding processing, such as a process of expanding the compressed information to the original information (expansion processing), on the signal that has undergone transmission path decoding processing.

Note that if the signal acquired by the acquisition unit 1101 via the transmission path has not been compression-encoded, the information source decoding processing unit 1103 does not perform processing to expand the compressed information back to the original information.

Here, the decompression process includes, for example, MPEG decoding. In addition to the decompression process, the transmission path decoding process may also include descrambling, etc.

In the receiving system configured as described above, the acquisition unit 1101 performs compression encoding such as MPEG encoding on data such as images and audio, and the signal that has been further subjected to error correction encoding such as LDPC encoding is acquired via the transmission path and supplied to the transmission path decoding processing unit 1102.

In the transmission path decoding processing unit 1102, the signal from the acquisition unit 1101 is subjected to a transmission path decoding process, for example, a process similar to that performed by the receiving device 12, and the resulting signal is supplied to the information source decoding processing unit 1103.

The information source decoding processing unit 1103 performs information source decoding processing such as MPEG decoding on the signal from the transmission path decoding processing unit 1102, and outputs the resulting image or sound.

The receiving system shown in Figure 71 above can be applied, for example, to a television tuner that receives television broadcasts as digital broadcasts.

The acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103 can each be configured as an independent device (hardware (such as an IC (Integrated Circuit)) or a software module).

Furthermore, with regard to the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103, it is possible to configure a set of the acquisition unit 1101 and the transmission path decoding processing unit 1102, a set of the transmission path decoding processing unit 1102 and the information source decoding processing unit 1103, or a set of the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103 as a single independent device.

Figure 72 is a block diagram showing a second example configuration of a receiving system to which the receiving device 12 can be applied.

In the figure, parts corresponding to those in Figure 71 are given the same reference numerals, and their explanation will be omitted below as appropriate.

The receiving system in FIG. 72 is the same as that in FIG. 71 in that it has an acquisition unit 1101, a transmission path decoding processing unit 1102, and an information source decoding processing unit 1103, but differs from that in FIG. 71 in that an output unit 1111 is newly provided.

The output unit 1111 is, for example, a display device that displays images or a speaker that outputs audio, and outputs images, audio, etc. as signals output from the information source decoding processing unit 1103. That is, the output unit 1111 displays images or outputs audio.

The receiving system of Figure 72 as described above can be applied to, for example, a TV (television receiver) that receives television broadcasts as digital broadcasts, or a radio receiver that receives radio broadcasts.

If the signal acquired by the acquisition unit 1101 has not been subjected to compression encoding, the signal output by the transmission path decoding processing unit 1102 is supplied to the output unit 1111.

Figure 73 is a block diagram showing a third example configuration of a receiving system to which the receiving device 12 can be applied.

In the figure, parts corresponding to those in Figure 71 are given the same reference numerals, and their explanation will be omitted below as appropriate.

The receiving system in FIG. 73 is the same as that in FIG. 71 in that it has an acquisition unit 1101 and a transmission path decoding processing unit 1102.

However, the receiving system in FIG. 73 differs from that in FIG. 71 in that it does not include an information source decoding processing unit 1103 and instead includes a new recording unit 1121.

The recording unit 1121 records (stores) the signal (e.g., TS packets of MPEG TS) output by the transmission path decoding processing unit 1102 onto a recording (storage) medium such as an optical disk, a hard disk (magnetic disk), or a flash memory.

The receiving system shown in Figure 73 can be applied to recorders that record television broadcasts.

In FIG. 73, the receiving system is configured to include an information source decoding processing unit 1103, and the signal after information source decoding processing is performed by the information source decoding processing unit 1103, i.e., the image and sound obtained by decoding, can be recorded by the recording unit 1121.

<Punctured LDPC Code>

Figure 74 is a diagram explaining punctured LDPC codes.

For data transmission in the transmission system of Figure 7, in addition to using an LDPC code obtained by LDPC encoding information bits based on a check matrix, it is also possible to use a punctured LDPC code obtained by puncturing (deleting) some of the bits of the LDPC code obtained by LDPC encoding.

In the following, the code length of the punctured LDPC code is represented as N, for example, N = 69120 (bits).

Let K denote the information bit length, and r denote the coding rate of the punctured LDPC code. The coding rate r is expressed by the formula r=K/N.

In punctured LDPC coding, which encodes information bits of information length K into a punctured LDPC code with a coding rate of r, as shown in FIG. 74, an extended LDPC code with parity bits of parity length M = N + L-K is generated by LDPC coding information bits of information length K = N × r based on an extended check matrix in which the rows and columns of the check matrix of an LDPC code with code length N and coding rate r are each extended by a predetermined puncture length L.

In punctured LDPC coding, the beginning of the information bits of the extended LDPC code is punctured by a puncture length of L to generate a punctured LDPC code with a code length of N and a coding rate of r.

The code length of an extended LDPC code is N+L bits, and bits of puncture length L are punctured from these N+L bits, so that an N-bit punctured LDPC code is obtained by puncturing the N+L-bit extended LDPC code.

A punctured LDPC code contains only K-L bits as information bits, not K bits, but the information bits that are the subject of the punctured LDPC coding are K bits, and the punctured LDPC code obtained by punctured LDPC coding of those information bits is N bits, so the coding rate r of the punctured LDPC code is K/N.

Figure 75 is a diagram explaining the structure of the extended check matrix of the Type A method, which encodes K information bits into an extended LDPC code of N+L bits.

A in Figure 75 shows the structure of a check matrix for a type A code with code length N and coding rate r (hereinafter also referred to as a type A regular check matrix).

The structure of a type A regular check matrix is as described in Figure 22.

In other words, a type A regular check matrix is a matrix with N-K rows and N columns, consisting of matrix A, matrix B, matrix C, matrix D, and matrix Z.

Then, the A matrix is a matrix with M1 rows and K columns, the B matrix is a matrix with M1 rows and M1 columns, the C matrix is a matrix with N-K-M1 (=M2) rows and K+M1 columns, the D matrix is a unit matrix with N-K-M1 (=M2) rows and N-K-M1 (=M2) columns, and the Z matrix is a zero matrix with M1 rows and N-K-M1 (=M2) columns.

B of Figure 75 shows the structure of an extended parity check matrix (hereinafter also referred to as a type-A extended parity check matrix) in which the rows and columns of the type-A regular parity check matrix in A of Figure 75 are each extended by a predetermined puncture length L.

The type A extended parity check matrix, like the type A regular parity check matrix, is composed of the A matrix, B matrix, C matrix, D matrix, and Z matrix.

However, the type A extended parity check matrix is a matrix with N+L-K rows and N+L columns, with the rows and columns both extended by the puncture length L compared to the type A regular parity check matrix.

Then, the A matrix is a matrix with M1 rows and K columns, the B matrix is a matrix with M1 rows and M1 columns, the C matrix is a matrix with N+L-K-M1 rows and K+M1 columns, the D matrix is a unit matrix with M2 (=N+L-K-M1) rows and M2 columns, and the Z matrix is a zero matrix with M1 rows and M2 (=N+L-K-M1) columns.

Here, the parity length M of the type-A regular check matrix is expressed by the formula M=N-K, and the parity length M of the type-A extended check matrix is expressed by the formula M=N+L-K. Therefore, the parity length M of the type-A extended check matrix is longer than that of the type-A regular check matrix by the puncture length L.

If the parity length M is expressed by the formula M=M1+M2 using parameter M1, then M2 of the type A regular parity check matrix is expressed by the formula M2=N-K-M1, and M2 of the type A extended parity check matrix is expressed by the formula M2=N+L-K-M1.

In a type A extended check matrix, one or both of M1 and M2 are larger than in a type A regular check matrix.

Figure 76 is a diagram explaining the structure of the extended check matrix of the Type B method, which encodes K information bits into an extended LDPC code of N+L bits.

A in Figure 76 shows the structure of a check matrix for a type B code with code length N and coding rate r (hereinafter also referred to as a type B regular check matrix).

The structure of the type B regular check matrix is as described in Figure 10.

That is, the type-B regular parity check matrix is a matrix of M (=NK) rows and N columns in which an information matrix H _A corresponding to information bits and a parity matrix H _T corresponding to parity bits are arranged in the horizontal direction.

The information matrix H _A has M rows and K (=N×r) columns, and the parity matrix H _T has M rows and M columns. The parity matrix H _T has a staircase structure as described in FIG. 11.

B of Figure 76 shows the structure of an extended parity check matrix (hereinafter also referred to as a type B extended parity check matrix) in which the rows and columns of the type B regular parity check matrix in A of Figure 76 are each extended by a predetermined puncture length L.

Like the regular parity check matrix of type B, the extended parity check matrix of type B is a matrix in which an information matrix H _A and a parity matrix H _T are arranged in the horizontal direction.

However, the type B extended parity check matrix is a matrix with M+L rows and N+L columns, with the rows and columns both extended by the puncture length L compared to the type B regular parity check matrix.

The information matrix H _A is a matrix of M+L rows and K columns, and the parity matrix H _T is a matrix of M+L rows and M+L columns.

Therefore, the parity length M+L (=N+LK) of the type-B extended parity check matrix is longer than that of the type-B regular parity check matrix by the puncture length L. As a result, in the type-B extended parity check matrix, the number of rows of the information matrix H _A is greater than that of the type-B regular parity check matrix by the puncture length L, and the number of rows and columns of the parity matrix H _T are greater than that of the type-B regular parity check matrix by the puncture length L.

Figure 77 is a flowchart that explains an example of the processing (encoding processing) of the LDPC encoder 115 ( Figure 8 ) when a punctured LDPC code with code length N = 69120 is used for data transmission.

In step S311, the LDPC encoder 115 selects a coding rate r of a punctured LDPC code with a code length N = 69120. For example, the LDPC encoder 115 selects a predetermined coding rate or a coding rate specified by an operator of the transmitting device 11 as the selected coding rate.

In step S312, the LDPC encoder 115 performs LDPC encoding of information bits of information length K = N x r based on an extended check matrix in which the rows and columns are each extended by a predetermined puncture length L for a check matrix with a coding rate N of 69120 bits and a coding rate r of the selected coding rate, thereby generating (finding) an extended LDPC code having parity bits of parity length M = N + L - K and a code length of N + L.

In step S313, the LDPC encoder 115 punctures the beginning of the information bits of the extended LDPC code by the puncture length L to generate (obtain) a punctured LDPC code with a code length of N and a coding rate of r, and supplies it to the downstream bit interleaver 116 (Figure 8).

Figure 78 is a flowchart that explains an example of the processing (decoding processing) of the LDPC decoder 166 ( Figure 61 ) when a punctured LDPC code with code length N = 69120 is used for data transmission.

In step S321, the LDPC decoder 166 obtains the received LLR of the punctured LDPC code from the bit deinterleaver 165, and obtains the received LLR of the extended LDPC code by adding to the received LLR an LLR indicating that the likelihood that the information bits are 0 and the likelihood that they are 1 are the same as the received LLR of the first L bits of the information bits punctured by the LDPC encoder 115.

In step S322, the LDPC decoder 166 decodes the extended LDPC code (information bits) using the received LLR of the extended LDPC code based on an extended check matrix in which the rows and columns are extended for a check matrix with a code length N of 69120 bits and a coding rate r of the selected coding rate.

Here, the extended LDPC code may be, for example, a type A code or type B code with a parallel factor P of 360, the same as in DVB-T.2, ATSC3.0, etc., and corresponding to a check matrix H with a cyclic structure.

Furthermore, as the extended LDPC code, for example, an LDPC code can be used that has a code length N of, for example, 69120 bits, which is longer than the 64 kbits of DVB-T.2, ATSC3.0, etc., and that can obtain punctured LDPC codes with coding rates r of, for example, 2/16, 3/16, 4/16, 5/16, 6/16, 7/16, 8/16, 9/16, 10/16, 11/16, 12/16, 13/16, 14/16, etc.

As the extended LDPC code, for example, an LDPC code that can obtain a punctured LDPC code with a good BER can be adopted by the simulation described in Figures 30 and 31. In the simulation, for example, the BER can be used as an index to determine the extended LDPC code (its check matrix) and the puncture length L for puncturing the extended LDPC code.

The punctured LDPC code obtained by puncturing the extended LDPC code obtained in the above manner by the puncture length L obtained in the same manner can ensure good communication quality in data transmission.

Below is an example of a check matrix initial value table representing the extended check matrix of an extended LDPC code obtained by simulation, and a puncture length L.

Figures 79 and 80 are diagrams showing examples of a check matrix initial value table (code table) that represents the type-A extended check matrix of the type-A extended LDPC code (before puncturing) (hereinafter also referred to as the type-A extended LDPC code for (69k, 2/16)) used when obtaining a punctured LDPC code with a code length N of 69120 (69k) bits and a coding rate r (Rate) of 2/16.

Note that Figure 80 is a sequel to Figure 79.

For the type A extended LDPC code for (69k, 2/16), puncturing is performed with a puncture length of L = 0. Therefore, the punctured LDPC code obtained by puncturing the type A extended LDPC code for (69k, 2/16) is identical to the type A extended LDPC code for (69k, 2/16) before puncturing.

Figures 81 and 82 are diagrams showing examples of check matrix initial value tables that represent the type-A extended check matrix of the type-A extended LDPC code (hereinafter also referred to as the type-A extended LDPC code for (69k, 3/16)) used when obtaining a punctured LDPC code with a code length N of 69120 bits and a coding rate r of 3/16.

Note that Figure 82 is a sequel to Figure 81.

For the type A extended LDPC code for (69k, 3/16), puncturing is performed with a puncture length of L = 0. Therefore, the punctured LDPC code obtained by puncturing the type A extended LDPC code for (69k, 3/16) is identical to the type A extended LDPC code for (69k, 3/16) before puncturing.

Figures 83 and 84 are diagrams showing examples of check matrix initial value tables that represent the type-A extended check matrix of the type-A extended LDPC code (hereinafter also referred to as the type-A extended LDPC code for (69k, 4/16)) used when obtaining a punctured LDPC code with a code length N of 69120 bits and a coding rate r of 4/16.

Note that Figure 84 is a sequel to Figure 83.

For the (69k,4/16) type A extended LDPC code, puncturing is performed with a puncture length of L = 0. Therefore, the punctured LDPC code obtained by puncturing the (69k,4/16) type A extended LDPC code is identical to the (69k,4/16) type A extended LDPC code before puncturing.

Figures 85 and 86 are diagrams showing examples of check matrix initial value tables that represent the type-A extended check matrix of the type-A extended LDPC code (hereinafter also referred to as the type-A extended LDPC code for (69k, 5/16)) used when obtaining a punctured LDPC code with a code length N of 69120 bits and a coding rate r of 5/16.

Note that Figure 86 is a sequel to Figure 85.

For the type A extended LDPC code for (69k,5/16), puncturing is performed with a puncture length L = 1800. Therefore, the punctured LDPC code obtained by puncturing the type A extended LDPC code for (69k,5/16) is shorter by the puncture length L = 1800 than the type A extended LDPC code for (69k,5/16) before puncturing.

Figures 87 and 88 are diagrams showing examples of check matrix initial value tables that represent the type-A extended check matrix of the type-A extended LDPC code (hereinafter also referred to as the type-A extended LDPC code for (69k, 6/16)) used when obtaining a punctured LDPC code with a code length N of 69120 bits and a coding rate r of 6/16.

Note that Figure 88 is a sequel to Figure 87.

For the type A extended LDPC code for (69k, 6/16), puncturing is performed with a puncture length L = 1800. Therefore, the punctured LDPC code obtained by puncturing the type A extended LDPC code for (69k, 6/16) is shorter by the puncture length L = 1800 than the type A extended LDPC code for (69k, 6/16) before puncturing.

Figures 89, 90, and 91 are diagrams showing examples of check matrix initial value tables that represent the type-A extended check matrix of the type-A extended LDPC code (hereinafter also referred to as the type-A extended LDPC code for (69k, 7/16)) used when obtaining a punctured LDPC code with a code length N of 69120 bits and a coding rate r of 7/16.

Note that Figure 90 is a continuation of Figure 89, and Figure 91 is a continuation of Figure 90.

For the type A extended LDPC code for (69k, 7/16), puncturing is performed with a puncture length L = 2160. Therefore, the punctured LDPC code obtained by puncturing the type A extended LDPC code for (69k, 7/16) is shorter by the puncture length L = 2160 than the type A extended LDPC code for (69k, 7/16) before puncturing.

Figures 92, 93, and 94 are diagrams showing examples of check matrix initial value tables that represent the type-A extended check matrix of the type-A extended LDPC code (hereinafter also referred to as the type-A extended LDPC code for (69k, 8/16)) used when obtaining a punctured LDPC code with a code length N of 69120 bits and a coding rate r of 8/16.

Note that Figure 93 is a continuation of Figure 92, and Figure 94 is a continuation of Figure 93.

For the type A extended LDPC code for (69k, 8/16), puncturing is performed with a puncture length L = 2520. Therefore, the punctured LDPC code obtained by puncturing the type A extended LDPC code for (69k, 8/16) is shorter by the puncture length L = 2520 than the type A extended LDPC code for (69k, 8/16) before puncturing.

Figures 95, 96, 97, and 98 are diagrams showing examples of check matrix initial value tables representing the type-A extended check matrix of the type-A extended LDPC code (hereinafter also referred to as the type-A extended LDPC code for (69k, 9/16)) used when obtaining a punctured LDPC code with a code length N of 69120 bits and a coding rate r of 9/16.

Note that Figure 96 is a continuation of Figure 95, and Figure 97 is a continuation of Figure 96. Figure 98 is a continuation of Figure 97.

For the type A extended LDPC code for (69k, 9/16), puncturing is performed with a puncture length L = 1800. Therefore, the punctured LDPC code obtained by puncturing the type A extended LDPC code for (69k, 9/16) is shorter by the puncture length L = 1800 than the type A extended LDPC code for (69k, 9/16) before puncturing.

Figures 99, 100, and 101 are diagrams showing examples of check matrix initial value tables that represent the type-B extended check matrix of the type-B extended LDPC code (hereinafter also referred to as the type-B extended LDPC code for (69k, 9/16)) used when obtaining a punctured LDPC code with a code length N of 69120 bits and a coding rate r of 9/16.

Note that Figure 100 is a continuation of Figure 99, and Figure 101 is a continuation of Figure 100.

For the type B extended LDPC code for (69k, 9/16), puncturing is performed with a puncture length L = 1080. Therefore, the punctured LDPC code obtained by puncturing the type B extended LDPC code for (69k, 9/16) is shorter by the puncture length L = 1080 than the type B extended LDPC code for (69k, 9/16) before puncturing.

Figures 102, 103, 104, and 105 are diagrams showing examples of check matrix initial value tables representing the type B extended check matrix of the type B extended LDPC code (hereinafter also referred to as the type B extended LDPC code for (69k,10/16)) used when obtaining a punctured LDPC code with a code length N of 69120 bits and a coding rate r of 10/16.

Note that FIG. 103 is a continuation of FIG. 102, and FIG. 104 is a continuation of FIG. 103. FIG. 105 is a continuation of FIG. 104.

For the type B extended LDPC code for (69k,10/16), puncturing is performed with a puncture length L = 360. Therefore, the punctured LDPC code obtained by puncturing the type B extended LDPC code for (69k,10/16) is shorter by the puncture length L = 360 than the type B extended LDPC code for (69k,10/16) before puncturing.

Figures 106, 107, 108, and 109 are diagrams showing examples of check matrix initial value tables representing the type B extended check matrix of the type B extended LDPC code (hereinafter also referred to as the type B extended LDPC code for (69k,11/16)) used when obtaining a punctured LDPC code with a code length N of 69120 bits and a coding rate r of 11/16.

Note that FIG. 107 is a continuation of FIG. 106, and FIG. 108 is a continuation of FIG. 107. FIG. 109 is a continuation of FIG. 108.

For the type B extended LDPC code for (69k,11/16), puncturing is performed with a puncture length L = 1440. Therefore, the punctured LDPC code obtained by puncturing the type B extended LDPC code for (69k,11/16) is shorter by the puncture length L = 1440 than the type B extended LDPC code for (69k,11/16) before puncturing.

Figures 110, 111, 112, and 113 are diagrams showing examples of check matrix initial value tables representing the type B extended check matrix of the type B extended LDPC code (hereinafter also referred to as the type B extended LDPC code for (69k,12/16)) used when obtaining a punctured LDPC code with a code length N of 69120 bits and a coding rate r of 12/16.

Note that FIG. 111 is a continuation of FIG. 110, and FIG. 112 is a continuation of FIG. 111. FIG. 113 is a continuation of FIG. 112.

For the type B extended LDPC code for (69k,12/16), puncturing is performed with a puncture length L = 1440. Therefore, the punctured LDPC code obtained by puncturing the type B extended LDPC code for (69k,12/16) is shorter by the puncture length L = 1440 than the type B extended LDPC code for (69k,12/16) before puncturing.

Figures 114, 115, 116, and 117 are diagrams showing examples of check matrix initial value tables representing the type B extended check matrix of the type B extended LDPC code (hereinafter also referred to as the type B extended LDPC code for (69k,13/16)) used when obtaining a punctured LDPC code with a code length N of 69120 bits and a coding rate r of 13/16.

Note that Figure 115 is a continuation of Figure 114, and Figure 116 is a continuation of Figure 115. Figure 117 is a continuation of Figure 116.

For the (69k,13/16) type B extended LDPC code, puncturing is performed with a puncture length of L = 720. Therefore, the punctured LDPC code obtained by puncturing the (69k,13/16) type B extended LDPC code is shorter by a puncture length of L = 720 than the (69k,13/16) type B extended LDPC code before puncturing.

Figures 118, 119, 120, and 121 are diagrams showing examples of check matrix initial value tables representing the type B extended check matrix of the type B extended LDPC code (hereinafter also referred to as the type B extended LDPC code for (69k,14/16)) used when obtaining a punctured LDPC code with a code length N of 69120 bits and a coding rate r of 14/16.

Note that Figure 119 is a continuation of Figure 118, and Figure 120 is a continuation of Figure 119. Figure 121 is a continuation of Figure 120.

For the (69k,14/16) type B extended LDPC code, puncturing is performed with a puncture length of L = 720. Therefore, the punctured LDPC code obtained by puncturing the (69k,14/16) type B extended LDPC code is shorter by the puncture length L = 720 than the (69k,14/16) type B extended LDPC code before puncturing.

Figure 122 is a diagram explaining the column weights of the type A extended check matrix represented by the type A method check matrix initial value tables of Figures 79 to 98.

As shown in FIG. 122, for the type A extended check matrix, the column weight of the first K1 columns of the A and C matrices is represented as X1, the column weight of the subsequent K2 columns of the A and C matrices is represented as X2, the column weight of the subsequent K3 columns of the A and C matrices is represented as X3, the column weight of the subsequent K4 columns of the A and C matrices is represented as X4, and the column weight of the subsequent K5 columns of the A and C matrices is represented as X5.

Here, the number of columns of matrix A is equal to the information length K=K1+K2+K3+K4+K5, and the number of columns of matrix C is K+M1, which is greater than the information length K=K1+K2+K3+K4+K5.

For the type A extended check matrix, the column weight of the K+1th to M1st columns of the C matrix is represented as XM1.

In a type A extended check matrix, the parity length M=N+L-K is equal to the sum M1+M2 of the number of columns in the B matrix M1 and the number of columns in the Z matrix M2.

The code length N+L of the Type A extended check matrix is the sum of the code length N=69120 of the punctured LDPC code and the puncture length L, 69120+L, and can be expressed as K1+K2+K3+K4+K5+M1+M2.

For the type-A extended parity check matrix, the column weight of the 1st to M1-1th columns of the B matrix is 2, and the column weight of the M1th column (the last column) of the B matrix is 1. Furthermore, the column weight of the D matrix is 1, and the column weight of the Z matrix is 0.

Figure 123 is a diagram showing the parameters of the type A extended check matrix represented by the check matrix initial value tables of the type A method in Figures 79 to 98.

The parameters X1 to X5, K1 to K5, XM1, M1, and M2 in FIG. 122 as well as the information length K and puncture length L of the Type-A extended check matrix of the Type-A extended LDPC code used when obtaining punctured LDPC codes with r=2/16, 3/16, 4/16, 5/16, 6/16, 7/16, 8/16, and 9/16 are as shown in FIG. 123.

In other words, for the Type A extended check matrix of the Type A extended LDPC code used to obtain a punctured LDPC code with r=2/16, the information length K, puncture length L, (X1,K1), (X2,K2), (X3,K3), (X4,K4), (X5,K5), XM1, M1, and M2 are 8640, 0, (21,1440), (20,7200), (0,0), (0,0), (0,0), 16, 1800, and 58680.

For the Type A extended check matrix of the Type A extended LDPC code used to obtain a punctured LDPC code with r=3/16, the information length K, puncture length L, (X1,K1), (X2,K2), (X3,K3), (X4,K4), (X5,K5), XM1, M1, and M2 are 12960, 0, (16,11520), (15,1440), (0,0), (0,0), (0,0), 11, 1800, and 54360.

For the Type A extended parity check matrix of the Type A extended LDPC code used to obtain a punctured LDPC code with r=4/16, the information length K, puncture length L, (X1,K1), (X2,K2), (X3,K3), (X4,K4), (X5,K5), XM1, M1, and M2 are 17280, 0, (13,16200), (12,720), (45,360), (0,0), (0,0), 9, 1800, and 50040.

For the Type A extended parity check matrix of the Type A extended LDPC code used to obtain a punctured LDPC code with r=5/16, the information length K, puncture length L, (X1,K1), (X2,K2), (X3,K3), (X4,K4), (X5,K5), XM1, M1, and M2 are 21600, 1800, (28,720), (27,1080), (9,7560), (8,3960), (10,8280), 4, 3600, and 45720.

For the Type A extended parity check matrix of the Type A extended LDPC code used to obtain a punctured LDPC code with r=6/16, the information length K, puncture length L, (X1,K1), (X2,K2), (X3,K3), (X4,K4), (X5,K5), XM1, M1, and M2 are 25920, 1800, (25,1800), (9,13680), (8,8640), (10,1800), (0,0), 2, 3600, and 41400.

For the Type A extended parity check matrix of the Type A extended LDPC code used to obtain a punctured LDPC code with r=7/16, the information length K, puncture length L, (X1,K1), (X2,K2), (X3,K3), (X4,K4), (X5,K5), XM1, M1, and M2 are 30240, 2160, (19,2160), (8,26280), (7,360), (3,1440), (0,0), 2, 3960, and 37080.

For the Type A extended parity check matrix of the Type A extended LDPC code used to obtain a punctured LDPC code with r=8/16, the information length K, puncture length L, (X1,K1), (X2,K2), (X3,K3), (X4,K4), (X5,K5), XM1, M1, and M2 are 34560, 2520, (15,1800), (14,720), (8,20880), (7,5040), (4,6120), 1,5040, and 32040.

For the Type A extended parity check matrix of the Type A extended LDPC code used to obtain a punctured LDPC code with r=9/16, the information length K, puncture length L, (X1,K1), (X2,K2), (X3,K3), (X4,K4), (X5,K5), XM1, M1, and M2 are 38880, 1800, (18,1440), (17,360), (10,3240), (9,12240), (4,21600), 1, 9000, and 23040.

The parameters X1 through X5, K1 through K5, XM1, M1 (M2), and the puncture length L are set to further improve the performance (e.g., BER, etc.) of the punctured LDPC code.

Figure 124 is a diagram explaining the column weights of the type B extended check matrix represented by the check matrix initial value table of the type B method in Figures 99 to 121.

For the Type B extended check matrix, as shown in FIG. 124, the column weight of the first through KX1 columns is represented as X1, the column weight of the subsequent KX2 column is represented as X2, the column weight of the subsequent KX3 column is represented as X3, and the column weight of the subsequent KY1 column is represented as Y1.

Note that KX1+KX2+KX3+KY1 is equal to the information length K, and KX1+KX2+KX3+KY1+M is equal to the code length N+L=69120+L of the extended LDPC code.

In addition, for the type-B extended parity check matrix, the column weight of the last M columns, ie, the column weight of the M−1 columns excluding the last column of the parity matrix H _T is 2, and the column weight of the last column is 1.

Figure 125 is a diagram showing the parameters of the type B extended check matrix represented by the check matrix initial value table of the type B method in Figures 99 to 121.

The parameters of the Type B extended check matrix of the Type B extended LDPC code used to obtain punctured LDPC codes with r=9/16, 10/16, 11/16, 12/16, 13/16, and 14/16, X1, KX1, and M in FIG. 124, as well as the information length K and puncture length L, are as shown in FIG. 125.

In other words, for the Type B extended check matrix of the Type B extended LDPC code used to obtain a punctured LDPC code with r=9/16, the information length K, puncture length L, X1, KX1, X2, KX2, X3, KX3, Y1, KY1, and M are 38880, 1080, 29, 1080, 17, 3240, 12, 3240, 3, 31320, and 31320.

For the Type B extended check matrix of the Type B extended LDPC code used to obtain a punctured LDPC code with r=10/16, the information length K, puncture length L, X1, KX1, X2, KX2, X3, KX3, Y1, KY1, and M are 43200, 360, 73, 360, 38, 360, 14, 8280, 3, 34200, and 26280.

For the Type B extended check matrix of the Type B extended LDPC code used to obtain a punctured LDPC code with r=11/16, the information length K, puncture length L, X1, KX1, X2, KX2, X3, KX3, Y1, KY1, and M are 47520, 1440, 29, 1440, 8, 1800, 9, 5760, 3, 38520, and 23040.

For the Type B extended check matrix of the Type B extended LDPC code used to obtain a punctured LDPC code with r=12/16, the information length K, puncture length L, X1, KX1, X2, KX2, X3, KX3, Y1, KY1, and M are 51840, 1440, 24, 1440, 9, 4680, 8, 1440, 3, 44280, and 18720.

For the Type B extended check matrix of the Type B extended LDPC code used to obtain a punctured LDPC code with r=13/16, the information length K, puncture length L, X1, KX1, X2, KX2, X3, KX3, Y1, KY1, and M are 56160, 720, 34, 720, 10, 3600, 11, 4320, 3, 47520, and 13680.

For the Type B extended check matrix of the Type B extended LDPC code used to obtain a punctured LDPC code with r=14/16, the information length K, puncture length L, X1, KX1, X2, KX2, X3, KX3, Y1, KY1, and M are 60480, 720, 24, 720, 12, 1080, 10, 4680, 3, 54000, and 9360.

The parameters X1, KX1, X2, KX2, X3, KX3, Y1, KY1, and the puncture length L (parity length M=N+L-K) are set to further improve the performance (e.g., BER, etc.) of the punctured LDPC code.

The above punctured LDPC code achieves good BER/FER and capacity (channel capacity).

Here, in the extended check matrix, as shown in Figures 123 and 125, the weight of the left column (e.g., X1) tends to be larger than the weight of the right column (e.g., X3).

Therefore, in an extended LDPC code, the further to the left (leading) a bit is, the more nodes (check nodes) it is connected to in the Tanner graph of the extended parity check matrix. As a result, in an extended LDPC code, if an error occurs in a bit on the left, the effect of that error propagates to many nodes, which can hinder improvement of the BER.

Therefore, for extended LDPC codes, by puncturing the left bits, i.e., the bits at the beginning of the information bits, it is possible to prevent the effects of errors from propagating to many nodes and hindering the improvement of the BER.

Note that, here, the first bits of the extended LDPC code (the first part of the information bits) are punctured, but the bits to be punctured are not limited to the first bits of the extended LDPC code.

In other words, puncturing of an extended LDPC code can be performed on any bit, such as a portion of the parity bits of the extended LDPC code.

<An embodiment of a computer>

Next, the above-mentioned series of processes can be performed by hardware or software. When the series of processes is performed by software, the program that constitutes the software is installed on a general-purpose computer or the like.

Figure 126 shows an example of the configuration of one embodiment of a computer on which a program that executes the above-mentioned series of processes is installed.

The program can be pre-recorded on a hard disk 705 or ROM 703 as a recording medium built into the computer.

Alternatively, the program can be temporarily or permanently stored (recorded) on a removable recording medium 711 such as a flexible disk, a CD-ROM (Compact Disc Read Only Memory), an MO (Magneto Optical) disk, a DVD (Digital Versatile Disc), a magnetic disk, or a semiconductor memory. Such a removable recording medium 711 can be provided as a so-called package software.

The program can be installed on the computer from the removable recording medium 711 as described above, or it can be transferred wirelessly from a download site to the computer via an artificial satellite for digital satellite broadcasting, or transferred wired to the computer via a network such as a LAN (Local Area Network) or the Internet, and the computer can receive the program transferred in this way via the communication unit 708 and install it on the built-in hard disk 705.

The computer includes a built-in CPU (Central Processing Unit) 702. An input/output interface 710 is connected to the CPU 702 via a bus 701. When a command is input by a user through the input/output interface 710 by operating an input unit 707 consisting of a keyboard, mouse, microphone, etc., the CPU 702 executes a program stored in a ROM (Read Only Memory) 703 in accordance with the command. Alternatively, the CPU 702 loads into a RAM (Random Access Memory) 704 a program stored in a hard disk 705, a program transferred from a satellite or a network, received by a communication unit 708, and installed on the hard disk 705, or a program read from a removable recording medium 711 attached to a drive 709 and installed on the hard disk 705. As a result, the CPU 702 performs processing according to the above-mentioned flowchart or processing performed by the configuration of the above-mentioned block diagram. Then, the CPU 702 outputs the processing results from the output unit 706, which is composed of an LCD (Liquid Crystal Display) and a speaker, via the input/output interface 710, or transmits the results from the communication unit 708, or records the results on the hard disk 705, as necessary.

In this specification, the processing steps that describe a program for causing a computer to perform various processes do not necessarily have to be processed chronologically in the order described in the flowchart, and also include processes that are executed in parallel or individually (for example, parallel processing or object-based processing).

The program may be processed by one computer, or may be distributed among multiple computers. Furthermore, the program may be transferred to a remote computer for execution.

The embodiment of this technology is not limited to the above-mentioned embodiment, and various modifications are possible without departing from the spirit of this technology.

For example, the new LDPC code (its check matrix initial value table) and GW pattern described above can be used for satellite lines, terrestrial waves, cables (wired lines), and other communication paths 13 (FIG. 7). Furthermore, the new LDPC code and GW pattern can also be used for data transmission other than digital broadcasting.

Note that the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

11 transmitter, 12 receiver, 23 parity interleaver, 24 group-wise interleaver, 25 block interleaver, 54 block deinterleaver, 55 group-wise deinterleaver, 111 mode adaptation/multiplexer, 112 padder, 113 BB scrambler, 114 BCH encoder, 115 LDPC encoder, 116 bit interleaver, 117 mapper, 118 time interleaver, 119 SISO/MISO encoder, 120 frequency interleaver, 121 BCH encoder, 122 LDPC encoder, 123 mapper, 124 frequency interleaver, 131 frame builder/resource allocation unit, 132 OFDM generation unit, 151 OFDM processing unit, 152 frame management unit, 153 frequency deinterleaver, 154 Demapper, 155 LDPC decoder, 156 BCH decoder, 161 Frequency deinterleaver, 162 SISO/MISO decoder, 163 Time deinterleaver, 164 Demapper, 165 Bit deinterleaver, 166 LDPC decoder, 167 BCH decoder, 168 BB descrambler, 169 Null deletion unit, 170 Demultiplexer, 300 Edge data storage memory, 301 Selector, 302 Check node calculation unit, 303 Cyclic shift circuit, 304 Edge data storage memory, 305 Selector, 306 Received data memory, 307 Variable node calculation unit, 308 Cyclic shift circuit, 309 Decoded word calculation unit, 310 Received data rearrangement unit, 311 Decoded data rearrangement unit, 601 Encoding processing unit, 602 storage unit, 611 encoding rate setting unit, 612 initial value table reading unit, 613 check matrix generation unit, 614 information bit reading unit, 615 encoding parity calculation unit, 616 control unit, 701 bus, 702 CPU, 703 ROM, 704 RAM, 705 hard disk, 706 output unit, 707 input unit, 708 communication unit, 709 drive, 710 input/output interface, 711, removable recording medium, 1001 reverse exchange unit, 1002 memory, 1011 parity deinterleaver, 1101 acquisition unit, 1101 transmission path decoding processing unit, 1103 information source decoding processing unit, 1111 output unit, 1121 recording unit

Claims (2)

Based on an extended parity check matrix in which the rows and columns of an LDPC code having a code length N of 69120 bits and a coding rate r of 9/16 are each extended by a predetermined puncture length L, LDPC coding is performed on information bits of information length K=N×r to generate an extended LDPC code having parity bits of parity length M=N+LK;
an encoding unit that punctures a leading portion of the information bits of the extended LDPC code by the puncture length L to generate a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 9/16;
The extended check matrix is
A matrix A in the upper left corner of the extended parity check matrix having M1 rows and K columns represented by a predetermined value M1 and the information length K=N×r;
A B matrix having a step structure adjacent to the right of the A matrix, the B matrix having M1 rows and M1 columns;
A Z matrix, which is a zero matrix adjacent to the right of the B matrix and has M1 rows and N+LK-M1 columns;
a C matrix adjacent below the A matrix and the B matrix, the C matrix having N+LK-M1 rows and K+M1 columns;
and a D matrix which is an identity matrix adjacent to the right of the C matrix and has N+LK-M1 rows and N+LK-M1 columns,
The puncture length L is 1800;
The predetermined value M1 is 9000,
The A matrix and the C matrix are represented by a check matrix initial value table,
The parity check matrix initial value table is a table representing positions of elements of 1 in the A matrix and the C matrix for every 360 columns,
3681 3750 3985 4255 8583 9468 12078 12353 15700 16492 17127 18174 18264 22392 23070 25263 29195 32034
804 4119 5315 5489 8261 9514 10099 10268 14359 16861 21050 21439 23880 24274 26637 30518 30944 31195
3684 4224 4412 7772 8017 10100 12529 15888 16518 18089 19685 28054 28297 28345 28897 29827 30402 31794
2013 2073 4993 6278 6716 10271 13971 14141 14727 17892 21649 22734 24394 25979 26485 30156 30617 31322
671 4057 4827 6795 8726 11791 15912 16773 16823 21296 24678 28589 29419 30212 30976 31701 32035
2831 3625 4812 9421 10678 11313 11919 13859 24185 26543
105 197 4569 12767 18835 20708 21307 21922 29762 30542
1939 3334 7927 12368 22520 24007 25355 26414 27639 30526
935 4228 7324 10281 10930 14811 20832 21012 24721 31868
451 1279 6541 9174 9524 23917 24447 24765 27400 30105
596 3093 7695 12690 12805 20513 26844 26874 27238 30238
3165 4948 8257 13864 15261 19334 23340 27303 29834 30592
4311 6608 8867 12314 17011 19562 29621 29653 29867 31831
246 1043 4063 9880 12133 14403 17673 21772 26756 28865
3800 4310 7891 9005 17892 22752 29776 30960 31922
169 3202 6707 9267 19608 21494 24264 27783 30896
2756 3526 5061 14144 15208 17722 19974 23683 25622
5640 6672 8062 10253 14587 17029 23586 29354 30935
1780 6399 7013 13407 14129 26025 27047 27302 28430
3867 8295 8448 11173 12961 16355 23417 30645 30840
114 2303 5658 10578 12954 19396 23278 26133 29150
4205 6484 8154 9468 9855 17738 25225 28855 29327
4064 5671 6785 11073 12684 17900 18543 24915 25278
4591 6432 6812 9172 9497 10443 11612 15805 26385
3429 5317 5699 11875 12763 19252 24194 28715 31645
2334 5348 8140 15322 16398 18377 22674 23119 27452
5806 8178 8750 18695 19361 20500 21337 23747 26594
868 5108 7470 12695 12827 13362 17150 30388 32036
1401 3377 6069 13887 15223 16423 20548 26114 31525
2388 2511 6647 15288 20979 21546 22893 25768 26293
5918 7740 8309 16069 17648 21533 21638 30421 30592
4531 6710 7575 10870 14321 15801 22289 27422 29206
282 2349 2823 16122 18235 22889 30845 31790 32028
1028 3364 7170 9696 10463 13676 21633 22408 22987
4747 5376 7037 11344 18790 18904 23562 26963 29547
2666 4221 8779 12684 15548 16845 19631 27773 32000
3277 3636 6417 15359 20686 23258 23607 28911 31760
1394 1613 4705 10030 14240 20469 21907 25971 28392
2428 3334 6308 9823 14969 16081 20361 21680 27204
870 4539 5033 11210 11227 12757 13164 16363 18278
519 8424 8966 11266 12282 15631 17138 25283 27009
562 4648 7031 9367 9769 17258 17524 18469 23544
2607 4017 4276 12525 16477 21617 28004 29179 31638
1311 1705 6279 19425 20643 21524 21927 26759 30022
2440 5160 8827 19724 20470 21579 22088 25426 26076
247 1718 3238 15685 16926 26381 27070 28504 31522
1646 3308 3325 12196 13145 18495 22879 25613 31074
2777 6991 7582 12852 15441 16518 19845 27107 31491
24 1098 6964 10014
3834 7138 8104 27290
2467 2695 6985 23538
597 1655 2786 26365
3412 3568 3869 22313
1378 3631 7350 30759
396 2426 3965 30636
294 5276 6622 28723
889 5479 5831 13814
1355 5011 7082 24636
1737 5683 7638 12279
4248 4328 7871 13506
1867 5466 7068 23531
1400 5020 7410 9775
2727 3409 6324 21177
4027 4240 7262 16737
1442 7380 7650 24201
601 6169 6278 26698
1070 3198 6038 11626
616 3835 8339 28168
4424 5809 6656 26638
3857 4561 4879 27896
2696 2722 4665 17776
643 2333 3072 10579
232 4876 4956 18710
3486 3535 6104 29906
774 5073 6030 23656
4617 6194 7445 31653
4163 5489 8227 28295
3675 3991 4940 18635
496 2003 4758 20333
1062 2059 4493 25301
1380 7374 8642 28926
1294 1639 8662 30961
5866 6147 7653 11713
5458 7184 7361 20695
2463 4602 6018 16857
320 4682 8140 19724
4410 6923 8975 26037
306 1921 7301 11104
57 1768 5604 17338
2839 3153 5912 28608
1091 6051 7495 31918
1681 2099 2259 16924
4490 5186 6994 25446
3188 4252 6208 25437
1342 5660 7305 21071
1048 3204 7421 15675
2197 3412 5125 22484
5721 6143 6479 22800
2531 4216 4794 17691
628 3665 5783 26756
2660 5527 7289 14552
3432 4895 6255 20101
288 2324 2375 27024
3898 7386 8459 10265
301 4717 4972 10844
1895 7065 8334 22255
331 1779 7214 22726
3202 4096 7467 27090
27017
29554
30755
30289
14496
29460
27770
9663
12310
11707
30095
30852
20107
23269
22090
12537
23969
13527
10911
20907
15272
23822
31661
13732
21787
A transmitting device. Based on an extended parity check matrix in which the rows and columns of an LDPC code having a code length N of 69120 bits and a coding rate r of 9/16 are each extended by a predetermined puncture length L, LDPC coding is performed on information bits of information length K=N×r to generate an extended LDPC code having parity bits of parity length M=N+LK;
a coding step of puncturing a leading portion of the information bits of the extended LDPC code by the puncture length L to generate a punctured LDPC code having a code length N of 69120 bits and a coding rate r of 9/16;
The extended check matrix is
A matrix A in the upper left corner of the extended parity check matrix having M1 rows and K columns represented by a predetermined value M1 and the information length K=N×r;
A B matrix having a step structure adjacent to the right of the A matrix, the B matrix having M1 rows and M1 columns;
A Z matrix, which is a zero matrix adjacent to the right of the B matrix and has M1 rows and N+LK-M1 columns;
a C matrix adjacent below the A matrix and the B matrix, the C matrix having N+LK-M1 rows and K+M1 columns;
and a D matrix which is an identity matrix adjacent to the right of the C matrix and has N+LK-M1 rows and N+LK-M1 columns,
The puncture length L is 1800;
The predetermined value M1 is 9000,
The A matrix and the C matrix are represented by a check matrix initial value table,
The parity check matrix initial value table is a table representing positions of elements of 1 in the A matrix and the C matrix for every 360 columns,
3681 3750 3985 4255 8583 9468 12078 12353 15700 16492 17127 18174 18264 22392 23070 25263 29195 32034
804 4119 5315 5489 8261 9514 10099 10268 14359 16861 21050 21439 23880 24274 26637 30518 30944 31195
3684 4224 4412 7772 8017 10100 12529 15888 16518 18089 19685 28054 28297 28345 28897 29827 30402 31794
2013 2073 4993 6278 6716 10271 13971 14141 14727 17892 21649 22734 24394 25979 26485 30156 30617 31322
671 4057 4827 6795 8726 11791 15912 16773 16823 21296 24678 28589 29419 30212 30976 31701 32035
2831 3625 4812 9421 10678 11313 11919 13859 24185 26543
105 197 4569 12767 18835 20708 21307 21922 29762 30542
1939 3334 7927 12368 22520 24007 25355 26414 27639 30526
935 4228 7324 10281 10930 14811 20832 21012 24721 31868
451 1279 6541 9174 9524 23917 24447 24765 27400 30105
596 3093 7695 12690 12805 20513 26844 26874 27238 30238
3165 4948 8257 13864 15261 19334 23340 27303 29834 30592
4311 6608 8867 12314 17011 19562 29621 29653 29867 31831
246 1043 4063 9880 12133 14403 17673 21772 26756 28865
3800 4310 7891 9005 17892 22752 29776 30960 31922
169 3202 6707 9267 19608 21494 24264 27783 30896
2756 3526 5061 14144 15208 17722 19974 23683 25622
5640 6672 8062 10253 14587 17029 23586 29354 30935
1780 6399 7013 13407 14129 26025 27047 27302 28430
3867 8295 8448 11173 12961 16355 23417 30645 30840
114 2303 5658 10578 12954 19396 23278 26133 29150
4205 6484 8154 9468 9855 17738 25225 28855 29327
4064 5671 6785 11073 12684 17900 18543 24915 25278
4591 6432 6812 9172 9497 10443 11612 15805 26385
3429 5317 5699 11875 12763 19252 24194 28715 31645
2334 5348 8140 15322 16398 18377 22674 23119 27452
5806 8178 8750 18695 19361 20500 21337 23747 26594
868 5108 7470 12695 12827 13362 17150 30388 32036
1401 3377 6069 13887 15223 16423 20548 26114 31525
2388 2511 6647 15288 20979 21546 22893 25768 26293
5918 7740 8309 16069 17648 21533 21638 30421 30592
4531 6710 7575 10870 14321 15801 22289 27422 29206
282 2349 2823 16122 18235 22889 30845 31790 32028
1028 3364 7170 9696 10463 13676 21633 22408 22987
4747 5376 7037 11344 18790 18904 23562 26963 29547
2666 4221 8779 12684 15548 16845 19631 27773 32000
3277 3636 6417 15359 20686 23258 23607 28911 31760
1394 1613 4705 10030 14240 20469 21907 25971 28392
2428 3334 6308 9823 14969 16081 20361 21680 27204
870 4539 5033 11210 11227 12757 13164 16363 18278
519 8424 8966 11266 12282 15631 17138 25283 27009
562 4648 7031 9367 9769 17258 17524 18469 23544
2607 4017 4276 12525 16477 21617 28004 29179 31638
1311 1705 6279 19425 20643 21524 21927 26759 30022
2440 5160 8827 19724 20470 21579 22088 25426 26076
247 1718 3238 15685 16926 26381 27070 28504 31522
1646 3308 3325 12196 13145 18495 22879 25613 31074
2777 6991 7582 12852 15441 16518 19845 27107 31491
24 1098 6964 10014
3834 7138 8104 27290
2467 2695 6985 23538
597 1655 2786 26365
3412 3568 3869 22313
1378 3631 7350 30759
396 2426 3965 30636
294 5276 6622 28723
889 5479 5831 13814
1355 5011 7082 24636
1737 5683 7638 12279
4248 4328 7871 13506
1867 5466 7068 23531
1400 5020 7410 9775
2727 3409 6324 21177
4027 4240 7262 16737
1442 7380 7650 24201
601 6169 6278 26698
1070 3198 6038 11626
616 3835 8339 28168
4424 5809 6656 26638
3857 4561 4879 27896
2696 2722 4665 17776
643 2333 3072 10579
232 4876 4956 18710
3486 3535 6104 29906
774 5073 6030 23656
4617 6194 7445 31653
4163 5489 8227 28295
3675 3991 4940 18635
496 2003 4758 20333
1062 2059 4493 25301
1380 7374 8642 28926
1294 1639 8662 30961
5866 6147 7653 11713
5458 7184 7361 20695
2463 4602 6018 16857
320 4682 8140 19724
4410 6923 8975 26037
306 1921 7301 11104
57 1768 5604 17338
2839 3153 5912 28608
1091 6051 7495 31918
1681 2099 2259 16924
4490 5186 6994 25446
3188 4252 6208 25437
1342 5660 7305 21071
1048 3204 7421 15675
2197 3412 5125 22484
5721 6143 6479 22800
2531 4216 4794 17691
628 3665 5783 26756
2660 5527 7289 14552
3432 4895 6255 20101
288 2324 2375 27024
3898 7386 8459 10265
301 4717 4972 10844
1895 7065 8334 22255
331 1779 7214 22726
3202 4096 7467 27090
27017
29554
30755
30289
14496
29460
27770
9663
12310
11707
30095
30852
20107
23269
22090
12537
23969
13527
10911
20907
15272
23822
31661
13732
21787
This is the transmission method.

Images