JP7530007B2 - A/D Converter - Google Patents

Description

The present invention relates to an AD converter.

The AD converter is composed of a DA converter section that outputs a known voltage, a sample-and-hold section that holds the voltage value of the analog input, and a comparator. The output value of the DA converter section is changed sequentially, and the digital value at the minimum DA converter section output value at which the comparator output changes from a low output voltage to a high output voltage is set, and used as the conversion value of the AD converter (Non-Patent Document 1).

Overview and mechanism of A/D conversion - MEMEs support page [Retrieved May 25, 2020], Internet (http://memes.sakura.ne.jp/memes/?page_id=1120)

When an integrator circuit consisting of a current source and capacitance that sequentially increases the output voltage over time or the number of processing steps is used in the DA converter section to achieve high linearity, there is an issue that linearity is degraded due to parasitic capacitance.

The present invention has been made in consideration of this problem, and aims to provide an AD converter that prevents degradation of linearity due to parasitic capacitance and reduces conversion errors.

The AD converter according to one embodiment of the present invention is an AD converter that repeats an operation of accumulating a unit voltage by an input voltage as an initial value, and is provided with a current source that generates the unit voltage, a capacitance that holds the initial value and accumulates the unit voltage, a first switch that connects the current source to the capacitance, and an error suppression unit that connects the current source to the capacitance when the first switch is disconnected, thereby suppressing the movement of charge accumulated in the parasitic capacitance of the current source and the first switch.

The present invention provides an AD converter that prevents degradation of linearity due to parasitic capacitance and reduces conversion errors.

1 is a block diagram showing an example of a functional configuration of an AD converter according to a first embodiment of the present invention; FIG. 13 is a diagram showing a circuit model of an integrator taking into account parasitic capacitance. 3 is a diagram illustrating an example of a change in terminal voltage of the parasitic capacitance illustrated in FIG. 2 . FIG. 2 is a diagram showing a circuit model of an integrating section and an error suppressing section shown in FIG. 1 . 5 is a diagram illustrating an example of a change in terminal voltage of the parasitic capacitance illustrated in FIG. 4 . FIG. 11 is a block diagram showing an example of a functional configuration of an AD converter according to a second embodiment of the present invention. FIG. 7 is a diagram showing a circuit model of an integrator and an error suppressor shown in FIG. 6 .

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The same reference symbols are used for the same parts in the drawings, and the description will not be repeated.

First Embodiment
A block diagram of an AD converter according to a first embodiment of the present invention is shown in Fig. 1. The AD converter 100 shown in Fig. 1 converts an input voltage into a digital value based on the number of times that an integrated voltage, which is accumulated by holding the input voltage in a capacitance _C0 and integrating it with a unit voltage as an initial value, becomes equal to a threshold voltage.

The AD converter 100 is composed of a control unit and an integrating conversion unit 20, and the integrating conversion unit is composed of a third switch SW3, a threshold voltage unit 21, a comparator 22, an integrating unit 23, and an error suppression unit 24. The integrating unit 23 is composed of a current source 230, a first switch SW1, and a capacitance _C0 .

During conversion, the first switch SW1 is disconnected and the third switch SW3 is once connected and then disconnected, and the input voltage input to the input terminal is held in the capacitance _C0 . After this, the first switch SW1 is repeatedly connected and disconnected, and the number of integrations ki is measured when the integrated voltage _V0 , which is the integration of the unit voltage VG, becomes equal to the threshold voltage Vth. When the integrated voltage _V0 and the threshold voltage Vth at this time are equal, the following formula is established.

(Errors occur due to switching on and off of the integration section)
2 shows a circuit model of the integrator that takes into account the parasitic capacitance of the current source and the switch. In the figure, Cp represents the parasitic capacitance. When the switch SW1 is in the connected state, the charge output from the current source 230 is accumulated in Co and Cp, and if the integration time for one time is Δt, the unit voltage VG is expressed by the following formula.

Figure 3 shows the behavior of the output voltage Vio of the current source 230 in the circuit model of Figure 2 with respect to the connection state of SW1. When the switch SW1 is in the disconnected state, the charge output from the current source 230 is stored only in the parasitic capacitance Cp. Normally, the parasitic capacitance Cp is orders of magnitude smaller than the capacitance Co, so the voltage rises rapidly due to the current from the current source 230. If the output voltage of the current source 230 rises excessively, the current stops flowing from the current source 230, and the output voltage of the current source 230, i.e., the voltage of the parasitic capacitance Cp, becomes saturated. The charge is held for the capacitance Co, so the voltage is also held. When the switch SW1 is again connected in this state, not only the charge from the current source 230 but also the charge stored in the parasitic capacitance Cp flows into the capacitance Co, so an error occurs in the unit voltage represented by equation (2). In addition, when the disconnected state is changed to the connected state, the charge flowing from the parasitic capacitance Cp changes with the voltage of the capacitance Co, so the integration characteristics become nonlinear. The degradation of linearity due to this parasitic capacitance causes conversion errors in the AD converter.

(Error Suppression Unit)
4 shows a circuit model of the integrator 23 and the error suppressor 24 according to the first embodiment. The relationship between the connection states of the first switch SW1 and the second switch SW2 is such that when the first switch SW1 is in the connection state, the second switch SW2 is in the disconnection state, and when the first switch SW1 is in the disconnection state, the second switch SW2 is in the connection state. When the first switch SW1 is in the disconnection state and the second switch SW2 is in the connection state, the output voltage Vio of the current source 230 is expressed by the following equation, where A1 is the gain of the OP amplifier in the error suppressor 24 and Vof is the offset voltage.

In equation (3), Vo,0 represents the voltage of the capacitance Co. If the gain is large enough, Vio ≈ Vo,0. In this embodiment, the charge from the current source 230 does not accumulate in the parasitic capacitance Cp but flows to the OP amplifier of the error suppression unit 24, so the voltage of the output of the current source 230 does not increase and becomes the same as Vo. Figure 5 shows the behavior of Vio in this embodiment with respect to the connection state of SW1a. Even if the first switch SW1 is in the disconnected state and the second switch SW2 is in the connected state, Vio does not become the saturation voltage of the output of the current source 230 and is held at Vo. Next, when the first switch SW1 is in the connected state and the second switch SW2 is in the disconnected state, the voltage of the parasitic capacitance Cp is the same as Vo, so there is no movement of charge. Therefore, in this embodiment, no integration error occurs due to the parasitic capacitance Cp.

As described above, this embodiment provides an AD converter that prevents degradation of linearity due to parasitic capacitance Cp and reduces conversion errors.

Second Embodiment
6 shows a block diagram of an AD converter 200 according to a second embodiment of the present invention. The configuration of the error suppression unit 34 is different from that of the first embodiment. The relationship of the connection states of the first switch SW1, the second switch SW2, and the error correction switch SW4 is such that when the first switch SW1 is in a connected state, the second switch SW2 is in a disconnected state, and a1 and c1 of the error correction switch SW4 are connected, and when the first switch SW1 is in a disconnected state, the second switch SW2 is in a connected state, and a1 and b1 of the error correction switch SW4 are connected.

Figure 7 shows a circuit model of this embodiment. When the first switch SW1 is in the disconnected state, the second switch SW2 is in the connected state, and a1 and b1 of the error correction switch SW4 are connected, the output voltage Vio of the current source 230 is expressed by the following equation.

In equation (4), A and Vof are the gain and offset voltage, respectively, of the buffer amplifier (op-amp) 250. Vo,0 represents the voltage of Co in this switch state. The charges Qs,0 and Qp,0 stored in the error suppression capacitance Cs and the parasitic capacitance Cp are expressed by the following equations.

In the circuit model, the electrode of the error suppression capacitance Cs connected to the output of the buffer amplifier 250 is the positive pole. Next, we consider the transfer of charge when the first switch SW1 is connected, the second switch SW2 is disconnected, and a1 and c1 of the error correction switch SW4 are connected. If the voltage of the capacitance Co in this switch state is Vo,1, the law of conservation of charge holds before and after the change in switch state, and the following equation holds.

In equation (7), the second term on the right hand side represents the effect of the charge stored in the parasitic capacitance Cp on Vo,1. By setting the size of the error suppression capacitance Cs to be approximately the same as the parasitic capacitance Cp in advance, the second term on the right hand side of equation (7) becomes zero, and the effect of the charge stored in the parasitic capacitance Cp can be eliminated. Therefore, in this embodiment, no integration error occurs due to the parasitic capacitance Cp.

The error suppression unit 25 of the AD converter 200 according to the present embodiment described above includes an error suppression capacitance Cs having a capacitance value similar to the parasitic capacitance Cp of the current source 230 and the first switch SW1, a buffer amplifier 250 that generates an integrated voltage that replicates the voltage held by the capacitance Co, an error correction switch SW4 that connects the error suppression capacitance Cs between the current source 230 and a common potential when the first switch SW1 is connected, and subtracts the error suppression voltage charged in the error suppression capacitance Cs from the integrated voltage when the first switch SW1 is disconnected, and a second switch SW2 that subtracts the error suppression voltage from the integrated voltage and connects the voltage to the output of the current source when the first switch SW1 is disconnected. This makes it possible to provide an AD converter that prevents degradation of linearity due to the parasitic capacitance Cp and reduces conversion errors.

The present invention is not limited to the above-described embodiments, and modifications are possible within the scope of the gist of the invention. The present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is determined only by the invention-specific matters related to the scope of the claims that are appropriate from the above description.

10: Control unit 20: Integration conversion unit 21: Threshold voltage unit 22: Comparator 23: Integration unit 24: Error suppression unit 240: First operational amplifier 241: Second operational amplifier
SW1: First switch
SW2: Second switch
SW3: Third switch
SW4: Error correction switch

Claims (3)

In an AD converter that repeats an operation of multiplying an input voltage by a unit voltage using the input voltage as an initial value,
A current source that generates the unit voltage;
a capacitance for holding the initial value and integrating the unit voltage;
a first switch connecting the current source to the capacitance;
an error suppression unit that connects the current source and the capacitance when the first switch is disconnected, and suppresses movement of charge accumulated in the parasitic capacitance of the current source and the first switch. The error suppression unit is
a first operational amplifier having a non-inverting input terminal connected to the unit voltage;
a second operational amplifier having an output terminal connected to a non-inverting input terminal and an inverting input terminal connected to an output terminal and an inverting input terminal of the first operational amplifier;
2. The AD converter according to claim 1, further comprising: a second switch for connecting the output terminal of the first operational amplifier to the current source. The error suppression unit is
An error suppression capacitance having the same capacitance value as the parasitic capacitance;
a buffer amplifier that generates an integrated voltage that is a copy of the voltage held by the capacitor;
an error correction switch that connects the error suppression capacitance between the current source and a common potential when the first switch is connected, and subtracts an error suppression voltage charged in the error suppression capacitance from the integrated voltage when the first switch is disconnected;
2. The AD converter according to claim 1, further comprising: a second switch that connects a voltage obtained by subtracting the error suppression voltage from the integrated voltage to an output of the current source when the first switch is turned off.

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