JP7531352B2 - PWM modulated wave abnormality detection method and PWM modulated wave abnormality detection device - Google Patents

Description

The present invention relates to a PWM-modulated wave anomaly detection method and a PWM-modulated wave anomaly detection device.
In more detail, the present invention relates to a PWM modulated wave anomaly detection method and a PWM modulated wave anomaly detection device that can accurately determine and detect anomalies in the carrier frequency and in the signal wave in a PWM modulated wave obtained by PWM-modulating a signal wave from a signal wave generator with a carrier wave, and transmit the detected anomaly detection signal to a calculator that outputs data that is the source of the signal wave, or to a calculator for abnormality processing.

In the railway field, PWM modulated waves are used for motor drive control, and for amplifying train detection signals (TD signals) and automatic train control signals (ATC signals) output to track circuits. In order to ensure the safety of trains, when an abnormality occurs in the PWM modulated waves, the function is provided to detect the abnormality and safely stop the train.
Furthermore, to improve maintainability, there is a demand for a function to accurately determine and record the circumstances under which an abnormality occurred and the location of the abnormality when it is detected so that the cause of the abnormality can be easily analyzed.

Patent Publication No. 4767211 (Patent Document 1) describes a technology that focuses on the carrier frequency of the carrier component contained in a PWM modulated wave and detects abnormalities in the carrier frequency by detecting when the number of carrier changes per unit time deviates from a predetermined range.

Patent No. 4767211

The technology described in Patent Document 1 has the effect of enabling detection of carrier frequency anomalies in a modulated wave generator to be configured with a simple circuit. However, the number of carrier changes per unit time, which is the criterion for detecting an anomaly in the carrier frequency, may erroneously detect that an anomaly has occurred in the carrier frequency even when the carrier frequency is normal. In other words, if the carrier frequency is abnormal, the number of carrier changes per unit time will necessarily deviate from a predetermined range, but just because the number of carrier changes per unit time deviates from a predetermined range does not necessarily mean that the carrier frequency is abnormal.

In other words, there are cases where the number of carrier wave changes per unit time is the same in two states: a state where the signal wave is normal and the carrier frequency is abnormal (see FIG. 2(b)), and a state where the carrier frequency is normal and the signal wave is abnormal (see FIGS. 2(c) and (d)). In such cases, it has been found that the conventional technology described in Patent Document 1 has a problem in that it is not possible to distinguish between these two states. Furthermore, Patent Document 1 does not particularly consider detecting abnormalities in the signal wave. Details will be described later with reference to FIG. 2.

In order to solve the above problem, one of the representative PWM modulation wave abnormality detection methods and devices of the present invention measures the modulation wave change time, which is the time from when the modulation wave exceeds a reference value until it exceeds the reference value again, or the time from when the modulation wave falls below the reference value until it falls below the reference value again, and detects deviations of the modulation wave change time from a predetermined range to detect abnormalities in the signal wave or carrier wave. In this method and device, if the modulation wave change time continues to be below the lower limit of the predetermined range for a predetermined time or more, it is determined that there is an abnormality in the carrier upper limit frequency, which is an abnormality in which the carrier frequency exceeds the upper limit frequency that can be tolerated, and if the modulation wave change time continues to be above the upper limit value of the predetermined range for a predetermined time or more, it is determined that there is an abnormality in the carrier lower limit frequency, which is an abnormality in which the carrier frequency exceeds the lower limit frequency that can be tolerated, and if the modulation wave change time repeats a state in which it exceeds and does not exceed the upper limit value of the predetermined range a predetermined number of times or more within a predetermined time, it is determined that there is an abnormality in the signal wave.

In addition, one of the simplified versions of the representative PWM modulated wave anomaly detection method and device of the present invention measures the modulation wave change time, which is the time from when the modulated wave exceeds a reference value until it exceeds the reference value again, or the time from when the modulated wave falls below the reference value until it falls below the reference value again, and detects deviations of the modulation wave change time from a predetermined range to detect anomalies in the signal wave or carrier wave. In this method and device, if the modulation wave change time remains below the lower limit of the predetermined range for a predetermined period of time or more, or if the modulation wave change time remains above the upper limit of the predetermined range for a predetermined period of time or more, it is determined that there is an anomaly in the carrier wave frequency, and if the modulation wave change time alternates between exceeding and not exceeding the upper limit of the predetermined range a predetermined number of times or more within a predetermined period of time, it is determined that there is an anomaly in the signal wave.

The above-mentioned reference value 56 (see Figures 2 and 4) refers to the threshold voltage of the low level (OFF) and high level (ON) of the modulated wave. Furthermore, the time from when the modulated wave exceeds the reference value until it exceeds the reference value again refers to the interval between two consecutive rising edges of the modulated wave (Tpwm) (see Figures 2 and 4), and the time from when the modulated wave falls below the reference value until it falls below the reference value again refers to the interval between two falling edges of the modulated wave. Furthermore, the above-mentioned specified range refers to the range between the lower limit judgment value and the upper limit judgment value that are considered to be normal.

According to the present invention, it is possible to detect and distinguish between two abnormal states in a modulated wave, namely, a state in which the signal wave is normal but the carrier frequency of the carrier wave is abnormal, and a state in which the carrier frequency is normal but the signal wave is abnormal, thereby making it possible to identify abnormal states and abnormal parts in the system.
Problems, configurations and effects other than those described above will become apparent from the following description of the embodiments.

1 is a diagram showing an example of a system configuration to which a PWM modulated wave anomaly detection device according to the present invention is applied; 1A is a waveform diagram illustrating the normal state of a signal wave, a carrier wave, and a modulated wave (PWM); FIG. 1B is a waveform diagram illustrating a state where the signal wave is normal and the carrier wave frequency is abnormal; FIG. 1C is a waveform diagram illustrating a state where the carrier wave frequency is normal and the signal wave is abnormal (amplitude abnormality); and FIG. 1D is a waveform diagram illustrating a state where the carrier wave frequency is normal and the signal wave is abnormal (DC bias abnormality). FIG. 1 is a block diagram showing an example of a PWM modulated wave abnormality detection device according to the present invention (first embodiment); 6 is a diagram for explaining, using a time chart, the operation of the modulated wave rising edge detection circuit and the PWM_EDG signal falling edge detection circuit in the PWM modulated wave abnormality detection devices of FIG. 3 and FIG. 5 . FIG. 11 is a block diagram showing another example of a PWM modulated wave abnormality detection device according to the present invention (Embodiment 2). 5 is a flowchart showing a process of detecting an abnormality in a carrier frequency and an abnormality in a signal wave by the PWM modulated wave abnormality detection device when applied to a system using PWM modulation according to the first embodiment of the present invention. 10 is a flowchart showing a process of detecting an abnormality in a carrier frequency and an abnormality in a signal wave by a PWM-modulated wave abnormality detection device when the device is applied to a system using PWM modulation according to a second embodiment of the present invention.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is an example of a system configuration diagram to which a PWM modulated wave abnormality detection device 80 of the present invention is applied, and is a block diagram showing an embodiment for detecting an abnormality in the carrier frequency of a signal wave 35 and a carrier wave 45 in a modulated wave (PWM) 55 output by a modulator 50 after modulating a signal wave 35 from a signal wave generator 20 with a carrier wave 45 from a carrier wave generator 40.

The above system has a computing unit (CPU) 10, a signal wave generator (D/A) 20, a pre-amplifier (PRE) 30, a carrier wave generator (CAR GEN) 40, a modulator (MOD) 50, a post-amplifier (AMP) 60, a load (LOAD) 70, a PWM modulated wave abnormality detection device (LOGIC) 80 of the present invention, and a reference clock generator (CLK GEN) 90.

In this example, we are assuming a system that has a pre-amplifier (PRE) 30 and a post-amplifier (AMP) 60, but the invention can also be applied to systems that do not require either or both of these.

The calculator 10, which may be a CPU, generates digital data 15 that is the source of the signal wave 35 and outputs it to the signal wave generator 20.

The signal wave generator 20 is made up of a digital/analog converter (D/A) that converts the digital data 15 output from the calculator 10 into an analog waveform and outputs it to the preamplifier 30.

The preamplifier 30 amplifies the analog waveform converted by the digital/analog converter (D/A) and outputs it to the modulator 50 as a signal wave 35.

The modulator 50 PWM-modulates the signal wave 35 from the front-stage amplifier 30 using the carrier wave 45 from the carrier wave generator 40, and outputs the modulated wave (PWM) 55 to the rear-stage amplifier 60.

The post-stage amplifier 60 amplifies the modulated wave (PWM) 55 and outputs it to the load (LOAD) 70. The load (LOAD) 70 can take various forms, such as a speaker, a motor, or a track circuit.

The reference clock generator 90 generates a reference clock signal (CLK) 95 having a frequency higher than the frequency of the carrier wave 45.

The PWM modulated wave abnormality detection device (LOGIC) 80 of the present invention accurately distinguishes and detects abnormalities in the signal wave 35 component contained in the modulated wave 55 and abnormalities in the carrier frequency of the carrier wave component, and transmits an abnormality detection signal 85 to notify the abnormal state to the calculator 10 and/or an abnormality processing calculator (not shown in FIG. 1). The circuit configuration and operating principle of the PWM modulated wave abnormality detection device (LOGIC) 80 of the present invention will be described in detail in the following Examples 1 and 2.

The abnormality detection signal 85 has the form of a carrier frequency upper limit frequency exceeding abnormality detection signal (ERR_FH) 86, a carrier frequency lower limit frequency exceeding abnormality detection signal (ERR_FL) 87, and a signal wave abnormality detection signal (ERR_SIG) 89 in Example 1 described below, and has the form of a carrier frequency abnormality detection signal (ERR_FRQ) 88 and a signal wave abnormality detection signal (ERR_SIG) 89 in Example 2.

The calculator 10 and/or an anomaly processing calculator (not shown in FIG. 1) receives the anomaly detection signal 85 output from the PWM modulated wave anomaly detection device 80, judges whether the anomaly detection signal 85 is normal or abnormal based on the High/Low logic level, and if an anomaly is detected, safely stops the system and records the abnormal state.

One of the PWM modulated wave abnormality detection devices 80 of the present invention is
a measurement unit 801 for measuring a modulated wave change time, which is a time from when a modulated wave 55 obtained by PWM-modulating a signal wave 35 with a carrier wave 45 exceeds a reference value 56 until the modulated wave 55 exceeds the reference value 56 again, i.e., an interval between two successive rising edges of the modulated wave 55, or a time from when the modulated wave 55 falls below the reference value 56 until the modulated wave 55 falls below the reference value 56 again, i.e., an interval between two successive rising edges of the modulated wave 55;
When the state where the modulated wave change time measured by the measurement unit is below the lower limit of a predetermined range continues for a first predetermined time or more, it is determined that the carrier wave frequency is an abnormality exceeding an upper limit frequency that is permissible, and
When the state in which the modulated wave change time exceeds the upper limit value of the predetermined range continues for a second predetermined time or more, it is determined that a carrier wave lower limit frequency abnormality has occurred, which is an abnormality in which the frequency of the carrier wave has fallen below a lower limit frequency that is permissible, and
The device has an abnormality determination unit 802 that determines that the signal wave is abnormal if the state in which the modulated wave change time exceeds the upper limit value of a predetermined range and the state in which it does not exceed the upper limit value are repeated a predetermined number of times or more within a third predetermined time.

The following will be explained in detail with reference to FIG. 3. The measurement unit 801 of the PWM modulated wave abnormality detection device 80 of the present invention is composed of a rising edge detection circuit 810 of the modulated wave 55, a falling edge detection circuit 815 of the PWM_EDG signal, a counter 821, a latch 841, and a reset circuit 881 for the counter 821.

The abnormality determination unit 802 of the PWM modulated wave abnormality detection device 80 of the present invention is composed of a comparator 861, a comparator 871, a counter 822, a comparator 862, a latch 842, a reset circuit 882 of counter 822, a counter 823, a comparator 863, a latch 843, a reset circuit 883 of counter 823, a counter 824, a comparator 864, a comparator 874, a reset circuit 884 of counter 824, a counter 825, a comparator 865, a latch 845, and a reset circuit 885 of counter 825.
The operating principles of each part constituting the measuring section 801 and the abnormality determining section 802 will be described in detail below.

First, the operating principle of the measuring unit 801 will be described in detail.
The counter 821 is a timer for measuring the interval (Tpwm) between two successive rising edges of the modulated wave 55 .
After being reset, the counter 821 counts the number of rising edges of the reference clock signal (CLK) 95 of the reference clock generator 90, and outputs the count value CNT1.

The rising edge detection circuit 810 of the modulated wave 55 generates an edge detection signal (PWM_EDG) of the modulated wave 55 that has a logic level of High ('H') only between the rising edge of the modulated wave 55 ((A) in FIG. 4) and the rising edge of the CLK signal 95 that appears immediately thereafter ((B) in FIG. 4), and has a logic level of Low ('L') otherwise.

The latch 841 captures the count number CNT1 at the rising edge of the PWM_EDG signal ((A) in Figure 4), holds it as CNT1_L, and outputs it to the comparators 861 and 871.

On the other hand, the PWM_EDG signal falling edge detection circuit 815 generates a signal C_RST1 having a logic level of High ('H') only between the falling edge of the PWM_EDG signal (Figure 4(C)) and the rising edge of the CLK signal 95 that appears immediately thereafter (Figure 4(D)), and a logic level of Low ('L') otherwise.

The reset circuit 881 of the counter 821 is composed of a logical OR gate that receives the reset signal (RST) 81 and the signal C_RST1 as inputs, and generates a reset signal CNT1_R for the counter 821. That is, when either the RST signal 81 or the signal C_RST1, or both, are at a logical level High ('H'), the level of CNT1_R becomes High ('H'), and the count value CNT1 of the counter 821 is reset to 0.

By the operation of the measuring unit 801 described above, the interval (Tpwm) between two consecutive rising edges of the modulated wave 55 can be measured and converted into a proportional count value CNT1_L of the CLK signal 95. In other words, CNT1_L can be read as Tpwm in the following explanation.

The CLK signal 95 measures the interval between two successive rising edges of the modulated wave 55, so a clock with an interval shorter than that interval is required, which means that a CLK signal with a higher frequency than the modulated wave 55 is required. The higher the CLK signal frequency, the higher the measurement accuracy. These are well known, so a detailed explanation will be omitted.

Next, the operation principle of the abnormality determination unit 802 will be described in detail.
The comparator 861 compares the count value CNT1_L (B) output from the measurement unit 801 with a preset upper limit value MAX (A), and outputs a comparison result CR1a having a logic level High ('H') if the count value CNT1_L is smaller than MAX (B < A), and a logic level Low ('L') otherwise.
The upper limit value MAX is the largest integer smaller than the value obtained by dividing the frequency of the CLK signal 95 by the lower limit normal frequency of the carrier wave 45 .

The comparator 871 compares the count value CNT1_L (A) output from the measurement unit 801 with a preset lower limit value MIN (B), and outputs a comparison result CR1b having a logic level High ('H') if the count value CNT1_L is greater than MIN (A>B), and a logic level Low ('L') otherwise.
The lower limit value MIN is the smallest integer greater than the value obtained by dividing the frequency of the CLK signal 95 by the upper limit normal frequency of the carrier wave 45 .

A method of detecting an abnormality in which the carrier frequency of the carrier wave 45 exceeds the upper limit frequency will be described.
The counter 822 is a timer for measuring the above-mentioned first predetermined time period.
After being reset, the counter 822 counts the number of rising edges of the CLK signal 95 and outputs the count value CNT2.

The reset circuit 882 of the counter 822 is composed of a logical OR gate that receives the reset signal (RST) 81 and the comparison result CR1b of the comparator 871 as inputs, and generates a reset signal CNT2_R for the counter 822. That is, when either or both of the RST signal 81 and CR1b are at a logical level High ('H'), the level of CNT2_R becomes High ('H'), and the count value CNT2 of the counter 822 is reset to 0.

The comparator 862 compares the count value CNT2 (A) of the counter 822 with a preset judgment value N2 (B), and outputs a comparison result CR2 having a logic level of High ('H') if the count value CNT2 is greater than the judgment value N2 (A>B), and a logic level of Low ('L') otherwise.

When the carrier frequency of the carrier component contained in the modulated wave 55 does not exceed the upper limit frequency (normal state, see Figure 2(a)), CNT1_L>MIN and CR1b='H', so the timer constituted by counter 822 always maintains a reset state. However, when the carrier frequency exceeds the upper limit frequency (abnormal state), the timer starts, and when the abnormal state continues for a predetermined time, CNT2>N2 and CR2 changes from 'L' to 'H'.

When CR2 changes from 'L' to 'H', the latch 842 changes the logic level of the carrier frequency upper limit frequency exceedance abnormality detection signal (ERR_FH) 86 from 'L' to 'H' and maintains the 'H' state (abnormal state).

The same effect can be achieved by inputting the most significant bit of counter 822 to latch 842 instead of the comparison result CR2 of comparator 862.

Next, a method of detecting an abnormality in which the carrier frequency of the carrier wave 45 falls below the lower limit frequency will be described.
The counter 823 is a timer for measuring the above-mentioned second predetermined time period.
After being reset, the counter 823 counts the number of rising edges of the CLK signal 95 and outputs the count value CNT3.

The reset circuit 883 of the counter 823 is composed of a logical OR gate that receives the reset signal (RST) 81 and the comparison result CR1a of the comparator 861 as inputs, and generates a reset signal CNT3_R for the counter 823. That is, when either or both of the RST signal 81 and CR1a are at a logical level High ('H'), the level of CNT3_R becomes High ('H'), and the count value CNT3 of the counter 823 is reset to 0.

The comparator 863 compares the count value CNT3 (A) of the counter 823 with a preset judgment value N3 (B), and outputs a comparison result CR3 having a logic level High ('H') if the count value CNT3 is greater than the judgment value N3 (A>B), and a logic level Low ('L') otherwise.
The judgment value N3 may be a value different from the above-mentioned N2 (N2≠N3) or may be the same value (N2=N3).

When the carrier frequency of the carrier component contained in modulated wave 55 does not exceed the lower limit frequency (normal state, see Figure 2(a)), CNT1_L < MAX and CR1a = 'H', so the timer formed by counter 823 always maintains a reset state. However, when the carrier frequency exceeds the lower limit frequency (abnormal state, see Figure 2(b)), the timer starts, and when the abnormal state continues for a predetermined time, CNT3 > N3 and CR3 changes from 'L' to 'H'.

When CR3 changes from 'L' to 'H', the latch 843 changes the logic level of the carrier frequency lower limit frequency exceedance abnormality detection signal (ERR_FL) 87 from 'L' to 'H' and maintains the 'H' state (abnormal state).

The same effect can be achieved by inputting the most significant bit of counter 823 to latch 843 instead of the comparison result CR3 of comparator 863.

Finally, a method for detecting an abnormality in the signal wave 35 will be described.
The counter 825 is a counter for measuring the above-mentioned predetermined number of times.
After being reset, the counter 825 counts the number of rising edges of the comparison result CR1a of the comparator 861, and outputs the count value CNT5 to the comparator 865.

The comparator 865 compares the count value CNT5 (A) of the counter 825 with a preset judgment value N5 (B), and outputs a comparison result CR5 having a logic level of High ('H') if the count value CNT5 is greater than the judgment value N5 (A>B), and a logic level of Low ('L') otherwise.

When the signal wave component contained in the modulated wave 55 is normal (see Figure 2 (a)), CNT1_L < MAX, and CR1a is always 'H' (it does not alternate between 'H' and 'L'), so the count value CNT5 does not increase. However, when there is an abnormality in the signal wave (see Figures 2 (c) and (d)), CR1a alternates between 'H' and 'L', and the count value CNT5 increases each time CR1a changes (rises) from 'L' to 'H', and when it exceeds a certain number of times N5 (CNT5 > N5), CR5 changes from 'L' to 'H'.

The latch 845 changes the logic level of the signal wave abnormality detection signal (ERR_SIG) 89 from 'L' to 'H' when CR5 changes from 'L' to 'H', and holds the 'H' state (abnormal state).

The same effect can be obtained by inputting the most significant bit of counter 825 to latch 845 instead of the comparison result CR5 of comparator 865.

Furthermore, in order to prevent the count value CNT5 of the counter 825 from being incorrectly accumulated due to a temporary erroneous detection, the counter 825 is periodically reset by a reset timer consisting of the counter 824, comparator 864, comparator 874, reset circuit 884 of the counter 824, and reset circuit 885 of the counter 825, and the count value CNT5 within a predetermined period of time is used to determine an abnormality. The operation is explained below.

The counter 824 is a timer for measuring the third predetermined time period mentioned above.
After being reset, the counter 824 counts the number of rising edges of the CLK signal 95 and outputs the count value CNT4.

The comparator 864 compares the count value CNT4 (A) of the counter 824 with a preset judgment value N4 (B), and outputs a signal C_RST5 having a logic level of High ('H') if the count value CNT4 is equal to the judgment value N4 (A=B), and a logic level of Low ('L') otherwise.

The reset circuit 885 of the counter 825 is composed of a logical OR gate that receives the reset signal (RST) 81 and the comparison result C_RST5 of the comparator 864 as inputs, and generates a reset signal CNT5_R for the counter 825. That is, when either or both of the RST signal 81 and C_RST5 are at a logical level High ('H'), the level of CNT5_R becomes High ('H') and the count value CNT5 of the counter 825 is reset to 0.

The comparator 874 also compares the count value CNT4 (A) of the counter 824 with a preset judgment value N4+1 (B), and outputs a signal C_RST4 having a logic level of High ('H') if the count number CNT4 is equal to N4+1 (A=B), and a logic level of Low ('L') otherwise.

The reset circuit 884 of the counter 824 is composed of a logical OR gate that receives the reset signal (RST) 81 and the comparison result C_RST4 of the comparator 874 as inputs, and generates a reset signal CNT4_R for the counter 824. That is, when either or both of the RST signal 81 and C_RST4 are at a logical level High ('H'), the level of CNT4_R becomes High ('H') and the count value CNT4 of the counter 824 is reset to 0.

Figure 6 is a flowchart showing the process of detecting carrier frequency anomalies and signal wave anomalies in the PWM modulated wave anomaly detection device when the present invention of Example 1 is applied to a system using PWM modulation.

The operation based on the flowchart in FIG. 6 is as follows.
Step S801:
The measurement unit 801 in the PWM modulated wave abnormality detection device 80 measures (counts) the number of rising edges (or falling edges) of the reference clock signal CLK detected between each rising edge (or falling edge) of the modulated wave 55, i.e., the modulated wave change time.

Step S802′:
The abnormality determination unit 802 in the PWM modulated wave abnormality detection device 80 determines whether or not a state in which the modulated wave change time falls below a predetermined lower limit number of times (MIN reference value) continues for a predetermined time.
As a result, if the modulation wave change time falls below a predetermined lower limit number of times (MIN reference value) and this state continues for a predetermined time (Yes), proceed to step S803', and if it has not continued for the predetermined time (No), return to step S801.

Step S803′:
The anomaly determination unit 802 in the PWM modulated wave anomaly detection device 80 determines that the carrier frequency of the carrier wave 45 has an upper limit frequency exceeding anomaly, transmits the result to the calculator 10 as a carrier frequency upper limit frequency exceeding anomaly detection signal 86 (ERR_FH), and terminates the anomaly detection process.

Step S802″:
The abnormality determination unit 802 in the PWM modulated wave abnormality detection device 80 determines whether or not a state in which the modulated wave change time exceeds a predetermined upper limit number of times (MAX reference value) continues for a predetermined time.
As a result, if the modulation wave change time exceeds a predetermined upper limit number of times (MAX reference value) and this state continues for a predetermined time (Yes), proceed to step S803'', and if it has not continued for the predetermined time (No), return to step S801.

Step S803″:
The anomaly determination unit 802 in the PWM modulated wave anomaly detection device 80 determines that the carrier wave 45 has a lower limit frequency exceedance anomaly, transmits the result as a carrier frequency lower limit frequency exceedance anomaly detection signal 87 (ERR_FL) to the calculator 10, and terminates the anomaly detection process.

Step S804:
The abnormality determination unit 802 in the PWM modulated wave abnormality detection device 80 determines whether the state in which the modulated wave change time of the carrier wave 45 exceeds a predetermined upper limit number (MAX) and the state in which it does not exceed the upper limit number (MAX) are repeated a predetermined number of times or more within a predetermined time.
As a result, if the state in which the modulated wave change time exceeds a predetermined upper limit number (MAX) and the state in which the modulated wave change time does not exceed the upper limit number (MAX) are repeated a predetermined number of times or more within a predetermined time (Yes), proceed to step S805, and if the state is not repeated a predetermined number of times or more (No), return to step S801.

Step S805:
The anomaly determination unit 802 in the PWM modulated wave anomaly detection device 80 determines that the signal wave is abnormal, transmits the result as a signal wave anomaly detection signal 89 (ERR_SIG) to the calculator 10, and terminates the anomaly detection process.
In FIG. 6, steps S802', S802'', and S804 are executed in parallel (parallel processing), but they may be executed in serial (sequential processing).

As a result, it is possible to distinguish and detect an abnormal state in which the carrier frequency of carrier wave 45 exceeds the upper normal frequency limit, an abnormal state in which the carrier frequency falls below the lower normal frequency limit, and an abnormal state of the signal.

One of the PWM modulated wave abnormality detection devices 80 of the present invention is
a measurement unit 801 for measuring a modulated wave change time, which is a time from when a modulated wave 55 obtained by PWM-modulating a signal wave 35 with a carrier wave 45 exceeds a reference value 56 until the modulated wave 55 exceeds the reference value 56 again, i.e., an interval between two successive rising edges of the modulated wave 55, or a time from when the modulated wave 55 falls below the reference value 56 until the modulated wave 55 falls below the reference value 56 again, i.e., an interval between two successive rising edges of the modulated wave 55;
When the state where the modulated wave change time measured by the measurement unit is below the lower limit of a predetermined range or the state where the modulated wave change time exceeds the upper limit of the predetermined range continues for a first predetermined time or more, it is determined that a carrier lower limit frequency abnormality has occurred, which is an abnormality in which the frequency of the carrier wave is below a permissible lower limit frequency,
The signal wave is determined to be abnormal when the modulation wave change time alternates between exceeding and not exceeding the upper limit of a predetermined range a predetermined number of times or more within a third predetermined time.

A detailed explanation will be given using FIG. 5. The measurement unit 801 of the PWM modulated wave anomaly detection device 80 in the second embodiment is exactly the same as that in the first embodiment, so the explanation will be omitted.

The anomaly determination unit 802' of the PWM modulated wave anomaly detection device 80 of the present invention is composed of a comparator 861, a comparator 871, a counter 826, a comparator 866, a latch 846, a reset circuit 886 for the counter 826, a counter 824, a comparator 864, a comparator 874, a reset circuit 884 for the counter 824, a counter 825, a comparator 865, a latch 845, and a reset circuit 885 for the counter 825.

Comparator 861, comparator 871, and the signal wave abnormality detection circuit are exactly the same as in Example 1, so their explanation is omitted.

A method of detecting an abnormality in the carrier frequency of the carrier wave 45, which is different from that in the first embodiment, will be described below.
The counter 826 is a timer for measuring the first predetermined time period mentioned above.
After being reset, the counter 826 counts the number of rising edges of the CLK signal 95 and outputs the count value CNT6.

The reset circuit 886 of the counter 826 is composed of a logic gate OR that receives as inputs the reset signal (RST) 81 and the output C_RST6 of a logic AND gate that receives as inputs the comparison result CR1a of the comparator 861 and the comparison result CR1b of the comparator 871, and generates a reset signal CNT6_R for the counter 826. That is, when either or both of the RST signal 81 and C_RST6 are at a logic level High ('H'), the level of CNT6_R becomes High ('H') and the count value CNT6 of the counter 826 is reset to 0. Note that the logic level of C_RST6 becomes High ('H') only when both CR1a and CR1b are at a logic level High ('H').

The comparator 866 compares the count value CNT6 (A) of the counter 826 with a preset judgment value N6 (B), and outputs a comparison result CR6 having a logic level of High ('H') if the count value CNT6 is greater than the judgment value N6 (A>B), and a logic level of Low ('L') otherwise.

When the carrier frequency of the carrier component contained in modulated wave 55 does not exceed the upper limit frequency and does not exceed the lower limit frequency (normal state, see Figure 2 (a)), MAX > CNT1_L > MIN, CR1a = 'H' and CR1b = 'H', so the timer always remains in the reset state. However, when the carrier frequency exceeds the upper limit frequency or the lower limit frequency (abnormal state), the timer composed of counter 826 starts, and when the abnormal state continues for a predetermined time, CNT6 > N6 and CR6 changes from 'L' to 'H'.

When CR6 changes from 'L' to 'H', the latch 846 changes the logic level of the carrier frequency anomaly detection signal (ERR_FRQ) 88 from 'L' to 'H' and holds the 'H' state (abnormal state).

The same effect can be achieved by inputting the most significant bit of counter 826 to latch 846 instead of the comparison result CR6 of comparator 866.

Figure 7 is a flowchart showing the process of detecting carrier frequency anomalies and signal wave anomalies in the PWM modulated wave anomaly detection device when applied to a system using PWM modulation according to the second embodiment of the present invention.

The operation based on the flowchart in FIG.
Step S801:
The measurement unit 801 in the PWM modulated wave abnormality detection device 80 measures (counts) the number of rising edges (or falling edges) of the reference clock signal CLK detected between each rising edge (or falling edge) of the modulated wave 55, i.e., the modulated wave change time.

Step S802:
The abnormality determination unit 802' in the PWM modulated wave abnormality detection device 80 determines whether the state in which the modulated wave change time falls below a predetermined lower limit number of times (MIN reference value) or exceeds a predetermined upper limit number of times (MAX reference value) continues for a predetermined period of time.
As a result, if the state in which the modulation wave change time falls below a predetermined lower limit number of times (MIN reference value) or exceeds a predetermined upper limit number of times (MAX reference value) continues for a predetermined period of time (Yes), proceed to step S803, and if it has not continued for the predetermined period of time or more (No), return to step S801.

Step S803:
The abnormality determination section 802' in the PWM modulated wave abnormality detection device 80 determines that the carrier wave 45 has an abnormality in its carrier frequency, transmits the result as a carrier wave frequency abnormality detection signal 88 (ERR_FRQ) to the calculator 10, and terminates the abnormality detection process.

Step S804:
The abnormality determination unit 802' in the PWM modulated wave abnormality detection device 80 determines whether the state in which the modulated wave change time exceeds a predetermined upper limit number (MAX) and the state in which it does not exceed the upper limit number (MAX) have been repeated a predetermined number of times or more.
As a result, if the modulated wave change time has been repeated the predetermined number of times or more (Yes), the process proceeds to step S805, and if it has not been repeated the predetermined number of times or more (No), the process returns to step S801.

Step S805:
The anomaly determination unit 802 in the PWM modulated wave anomaly detection device 80 determines that the signal wave 35 is abnormal, transmits the result as a signal wave anomaly detection signal 89 (ERR_SIG) to the calculator 10, and terminates the anomaly detection process.

As a result, it is possible to distinguish between an abnormal carrier frequency state of the carrier wave 45 and an abnormal signal state and detect it.

The above is a typical configuration and operating principle of the PWM modulated wave abnormality detection device (LOGIC) 80 of the present invention. Note that the present invention is not limited to the above-mentioned Examples 1 and 2, and also includes configurations with minor changes that can obtain equivalent results.

For example, the measurement unit 801 measures the interval between two consecutive rising edges of the modulated wave 55, but may be reconfigured to measure the interval between two consecutive falling edges of the modulated wave 55.

In this embodiment, the carrier frequency upper limit over frequency abnormality detection signal (ERR_FH) 86, the carrier frequency lower limit over frequency abnormality detection signal (ERR_FL) 87, the carrier frequency abnormality detection signal 88 (ERR_FRQ), and the signal wave abnormality detection signal (ERR_SIG) 89 are designed so that a logic level of Low ('L') indicates a "normal state" and a logic level of High ('H') indicates an "abnormal state." If you want to reverse the relationship between the logic levels Low ('L')/High ('H') and the normal state/abnormal state, you can simply change the D terminal input level of latches 842, 843, 845, and 846 to Low ('L').

In addition, although the comparator output and internal signals such as the reset signal of the present invention are designed in positive logic, they may also be designed in negative logic.

The present invention is not limited to the above-mentioned embodiment, and various modified examples are included. For example, the above-mentioned embodiment has been described in detail to explain the present invention in an easy-to-understand manner, and is not necessarily limited to those having all the configurations described. In addition, it is possible to replace a part of the configuration of a certain embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of a certain embodiment. In addition, it is possible to add, delete, or replace a part of the configuration of each embodiment with another configuration. In addition, each configuration, function, etc. of the above-mentioned PWM modulated wave detection device may be realized by software by a processor interpreting and executing a program that realizes each function. Information such as programs, tables, files, etc. that realize each function can be placed in a memory, a recording device such as a hard disk or SSD (Solid State Drive), or a recording medium such as an IC card, SD card, or DVD.

10 Calculator 20 Signal wave generator 30 Preamplifier 40 Carrier wave generator 50 Modulator 60 Postamplifier 70 Load 80 PWM modulated wave abnormality detection device 90 Reference clock generator 15 Digital data 35 Signal wave 45 Carrier wave 55 Modulated wave (PWM)
56 Reference value 81 Reset signal (RST)
85 Abnormality detection signal 86 Carrier frequency upper limit frequency exceeding abnormality detection signal (ERR_FH)
87 Carrier frequency lower limit excess abnormality detection signal (ERR_FL)
88 Carrier frequency abnormality detection signal (ERR_FRQ)
89 Signal wave abnormality detection signal (ERR_SIG)
95 Reference clock signal (CLK)
801: Measurement unit of PWM modulated wave abnormality detection device 80 802: Abnormality determination unit of PWM modulated wave abnormality detection device 80 (Example 1)
802' Abnormality determination unit of the PWM modulated wave abnormality detection device 80 (Example 2)
810 Rising edge detection circuit of modulated wave 55 815 Falling edge detection circuit of PWM_EDG signal 821 Counter 822 Counter 823 Counter 824 Counter 825 Counter 826 Counter 841 Latch 842 Latch 843 Latch 845 Latch 846 Latch 861 Comparator 862 Comparator 863 Comparator 873 Comparator 864 Comparator 865 Comparator 866 Comparator 871 Comparator 874 Comparator 881 Reset circuit of counter 821 882 Reset circuit of counter 822 883 Reset circuit of counter 823 884 Reset circuit of counter 824 885 Reset circuit of counter 825 886 Reset circuit of counter 826

Claims (4)

measuring a modulated wave change time, which is a time from when a modulated wave obtained by PWM-modulating a signal wave with a carrier wave exceeds a reference value until the modulated wave exceeds the reference value again, or a time from when the modulated wave falls below the reference value until the modulated wave falls below the reference value again;
A PWM modulated wave anomaly detection method for detecting an anomaly in the signal wave or the carrier wave by detecting deviation of the modulated wave change time from a predetermined range,
When the state where the modulated wave change time is below the lower limit of the predetermined range continues for a first predetermined time or more,
A carrier upper limit frequency abnormality is determined to be an abnormality in which the frequency of the carrier exceeds an upper limit frequency that is permissible,
When the state in which the modulated wave change time exceeds the upper limit value of the predetermined range continues for a second predetermined time or more,
A carrier lower limit frequency abnormality is determined to be an abnormality in which the frequency of the carrier is below a lower limit frequency that is permissible,
When the state in which the modulated wave change time exceeds the upper limit value of the predetermined range and the state in which the modulated wave change time does not exceed the upper limit value are repeated a predetermined number of times or more within a third predetermined time,
and determining whether the signal wave is abnormal. 2. The PWM modulated wave abnormality detection method according to claim 1,
When the state where the modulated wave change time is below the lower limit of the predetermined range or the state where the modulated wave change time is above the upper limit of the predetermined range continues for a first predetermined time or more,
The carrier frequency of the carrier is determined to be abnormal,
When the state in which the modulated wave change time exceeds the upper limit value of the predetermined range and the state in which the modulated wave change time does not exceed the upper limit value are repeated a predetermined number of times or more within a third predetermined time,
and determining whether the signal wave is abnormal. A PWM modulated wave abnormality detection device that detects an abnormality in a carrier wave frequency in a modulated wave obtained by PWM modulating a signal wave with a carrier wave and an abnormality in the signal wave,
The PWM modulated wave abnormality detection device is
a measurement unit that measures a modulation wave change time, which is a time from when the modulated wave exceeds a reference value until it exceeds the reference value again, or a time from when the modulated wave falls below the reference value until it falls below the reference value again;
an abnormality determination unit that determines an abnormality in a carrier frequency of the carrier wave and an abnormality in the signal wave,
The abnormality determination unit is
When the state where the modulated wave change time measured by the measurement unit is below the lower limit of a predetermined range continues for a first predetermined time or more,
A carrier upper limit frequency abnormality is determined to be an abnormality in which the frequency of the carrier exceeds an upper limit frequency that is permissible,
When the state in which the modulated wave change time exceeds the upper limit value of the predetermined range continues for a second predetermined time or more,
A carrier lower limit frequency abnormality is determined to be an abnormality in which the frequency of the carrier is below a lower limit frequency that is permissible,
When the state in which the modulated wave change time exceeds the upper limit value of the predetermined range and the state in which it does not exceed the upper limit value are repeated a predetermined number of times or more within a third predetermined time,
A PWM modulated wave abnormality detection device having a function of determining whether the signal wave is abnormal. In the PWM modulated wave abnormality detection device according to claim 3,
The abnormality determination unit is
When the state where the modulated wave change time measured by the measurement unit is below the lower limit of a predetermined range or the state where the modulated wave change time is above the upper limit of a predetermined range continues for a first predetermined time or more,
The carrier frequency of the carrier is determined to be abnormal,
When the state in which the modulated wave change time exceeds the upper limit value of the predetermined range and the state in which it does not exceed the upper limit value are repeated a predetermined number of times or more within a third predetermined time,
A PWM modulated wave abnormality detection device having a function of determining whether the signal wave is abnormal.

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