JP7532902B2 - Display devices and electronic devices - Google Patents

Description

The present invention relates to a display device and an electronic device.

Display devices using, for example, OLEDs or liquid crystal elements as display elements are known. OLED is an abbreviation for Organic Light Emitting Diode. There is a strong demand for low power consumption in this type of display device. For this reason, a technology has been proposed that provides a mode for achieving low power consumption in addition to a mode for performing normal display operation (see, for example, Patent Document 1).
Specifically, in a normal display mode, an image is displayed across the entire display area, and in a low power consumption mode, a reduced version of the image displayed across the entire display area is displayed in part of the display area, and a black image is displayed in the remainder of the display area.

JP 2018-159819 A

However, in the mode that aims to reduce power consumption in the above technology, a special configuration such as image processing is required to obtain a reduced image, which makes the image more complicated.

A display device according to one aspect of the present disclosure includes a display area in which pixel circuits are arranged in a matrix at the intersections of multiple rows of scanning lines and multiple columns of data lines, a scanning line driving circuit capable of driving the multiple rows of scanning lines in any order, and a data signal output circuit capable of supplying a data signal obtained by converting one row of video data out of an entire image corresponding to input video data to the multiple columns of data lines in any order. In a mode in which a reduced image obtained by thinning out the entire image by rows and columns is assigned to a partial area of the display area and displayed, the scanning line driving circuit drives the scanning line of the row when the row specified by the video data corresponds to the row assigned to the partial area, and drives a scanning line of a row other than the row specified by the video data when the row specified by the video data corresponds to an area other than the partial area, and the data signal output circuit supplies a data signal corresponding to the scanning line of the row driven by the scanning line driving circuit to the data line assigned to the partial area.

1 is a perspective view showing a configuration of a display device according to an embodiment. FIG. 2 is a block diagram showing a configuration of a display device. FIG. 2 is a diagram showing an example of a display area in a display device. FIG. 2 is a diagram illustrating an example of an amplifier circuit in a display device. FIG. 2 is a diagram illustrating an example of a pixel circuit in a display device. 11 is a timing chart showing an example of an operation in a normal image display mode. 10 is a timing chart showing an example of an operation in a reduced image display mode. FIG. 11 is a diagram showing an example of gradation data assigned in a display area. FIG. 11 is a diagram showing an example of gradation data assigned in a display area. FIG. 13 is a diagram showing a display example of a reduced image. FIG. 11 is a diagram showing another display example of a reduced image. 13 is a timing chart showing another example of the reduced image display mode. FIG. 11 is a diagram showing an example of gradation data assigned in a display area. FIG. 11 is a diagram showing an example of gradation data assigned in a display area. FIG. 13 is a diagram showing a display example of a reduced image. FIG. 11 is a diagram showing another display example of a reduced image. FIG. 11 is a block diagram showing a configuration of a display device according to a first application example. 13A and 13B are diagrams for explaining the operation of the display device according to the second application example. FIG. 1 is a perspective view showing a head mounted display using a display device. FIG. 2 is a diagram showing an optical configuration of a head mounted display.

The display device according to the embodiment of the present invention will be described below with reference to the drawings. Note that in each drawing, the dimensions and scale of each part are appropriately different from the actual ones. In addition, the embodiments described below are preferred examples, and therefore various technically preferable limitations are applied, but the scope of the present invention is not limited to these forms unless otherwise specified in the following description to the effect that the present invention is limited.

Figure 1 is a perspective view showing the configuration of a display device 10 according to an embodiment. The display device 10 is, for example, a micro display panel that displays color images in a head-mounted display or the like. In the display device 10, a plurality of pixel circuits and a drive circuit for driving the pixel circuits are formed on a semiconductor substrate. The semiconductor substrate is typically a silicon substrate, but may be another type of semiconductor substrate.

The display device 10 is housed in a frame-shaped case 192 that opens in the display area. One end of an FPC (Flexible Printed Circuits) board 194 is connected to the display device 10. The other end of the FPC board 194 is provided with a plurality of terminals 196 for connection to an external host device. The multiple terminals 196 are connected to a host device (not shown). Video data, synchronization signals, and the like are supplied to the display device 10 from the host device via the multiple terminals 196 and the FPC board 194.

FIG. 2 is a block diagram showing the configuration of the display device 10, and FIG.
As shown in FIG. 2, the display device 10 is roughly divided into a control circuit 20 , a display area 100 , a scanning line driving circuit 120 , and a data signal output circuit 140 .
In the display area 100, m rows of scanning lines 12 are provided along the left-right direction in FIG. 3, and n columns of data lines 14 are provided along the top-bottom direction while being electrically insulated from each other.
Here, m and n are integers of 2 or more.

3, pixel circuits 110 are provided in the display region 100 corresponding to the intersections of m rows of scanning lines 12 and n columns of data lines 14. Therefore, the pixel circuits 110 are arranged in a matrix of m rows and n columns in the figure. In order to distinguish the rows of the matrix arrangement, they may be referred to as 1, 2, 3, ..., (m-1), mth row from the top in the figure. Similarly, in order to distinguish the columns of the matrix, they may be referred to as 1, 2, 3, ..., (n-1), nth column from the left in the figure.
An integer i between 1 and m is used to generally describe the scan lines 12. Similarly, an integer j between 1 and n is used to generally describe the data lines 14.

In this embodiment, the following two operation modes are prepared as modes for displaying images. In detail, there are two modes: a normal image display mode in which an image of video data Vid supplied from a higher-level device is displayed in the entire display area 100, and a reduced image display mode in which an image obtained by reducing the image of the video data Vid is displayed in a part of the display area 100.
In either mode, the video data Vid specifies the gradation level of pixels in the image to be displayed, for example, in 8 bits.
The video data Vid specifies the gradation levels of pixels in the order of row 1, column 1 to row 1 n, row 2, column 1 to row 2 n, row 3, column 1 to row 3 n, ..., row m, column 1 to row m n, in accordance with vertical scanning and horizontal scanning. In addition, in this description, the pixel circuit 110 includes an OLED, and the pixel is expressed by the light emission of the OLED.

The control circuit 20 controls each part based on the video data Vid and the synchronization signal Sync supplied from the higher-level device. The synchronization signal Sync includes a vertical synchronization signal that instructs the start of vertical scanning of the video data Vid, a horizontal synchronization signal that instructs the start of horizontal scanning, and a dot clock signal that indicates the timing of one pixel of the video data.
Control information Wip is supplied to the control circuit 20. The control information Wip includes information for specifying an operation mode, and when a reduced image display mode is specified as the operation mode, information indicating a reduction ratio of a reduced image, information indicating a position in the display area 100 where the reduced image should be displayed, and the like.
The control information Wip may be supplied from the higher-level device, or may be supplied in accordance with the operation of an operator of the electronic device in which the display device 10 is incorporated.

The scanning line driving circuit 120 supplies scanning signals /Gwr(1), /Gwr(2), ..., /Gwr(m-1), /Gwr(m) to the 1st, 2nd, 3rd, ..., (m-1), and mth rows of scanning lines 12 in accordance with the control by the control circuit 20. In general, the scanning signal supplied to the i-th row of scanning line 12 is represented as /Gwr(i).
The scanning line driving circuit 120 sets the scanning signal to the selected scanning line 12 among the 1st to mth scanning lines 12 to an L level, and sets the scanning signal to the other scanning lines 12 to an H level. The selection order of the scanning lines 12 differs between the normal image display mode and the reduced image display mode.

The data signal output circuit 140 is a circuit for applying a voltage according to a gray scale level to the pixel circuits 110 located in the row selected by the scanning line driving circuit 120 .
In detail, the data signal output circuit 140 includes latch circuits 41 and 42 , a DAC group 43 , an amplifier group 44 , and a data controller 142 .

The latch circuit group 41 is a collection of latch circuits L1 provided in each column. Similarly, the latch circuit group 42 is a collection of latch circuits L2 provided in each column.

The data controller 142 sets the video data Vid supplied from the higher-level device via the control circuit 20 in the latch circuits L1 of columns 1 to n depending on the mode.
The latch circuits L2 of each column in the latch circuit group 42 simultaneously output the video data Vid set in the latch circuits L1 under the control of the control circuit 20.

The DAC group 43 includes a DA conversion circuit C and a voltage generation circuit G provided in each column. The voltage generation circuit G generates an analog voltage of 256 gradations from the power supply voltage, and the DA conversion circuit C of each column selects and outputs a voltage corresponding to the video data output from the latch circuit L2 from the 256 gradations of analog voltages. Note that the voltage generation circuit G does not generate an analog voltage if the control signal Pw1 from the control circuit 20 is at L level. Therefore, if the control signal Pw1 is at L level, the DA conversion circuit C in each column stops converting the analog voltage.

The amplifier group 44 is a collection of amplifier circuits A(1) to A(n) provided corresponding to each column.
Of the amplifier circuits A(1) to A(n), a configuration example of the amplifier circuit A(j) in the jth column will be described with reference to FIG.
The amplifier circuit A(j) includes switches Sw1 to Sw3 and an operational amplifier amp. The switch Sw1 is provided between a power supply line 116 of a high potential power supply voltage Vel and a high potential power supply node of the operational amplifier amp. The switch Sw2 is provided between a ground potential Gnd and a low potential power supply node of the operational amplifier amp. The switch Sw3 is provided between the power supply line 116 and an output node Out.
The output node Out is connected to the data line 14 in the j-th column.

The on/off of the switches Sw1 to Sw3 is controlled by a control signal Pw2(j) from the control circuit 20. In detail, when the control signal Pw2(j) is at an H level, the switches Sw1 and Sw2 are turned on and the switch Sw3 is turned off, and when the control signal Pw2(j) is at an L level, the switches Sw1 and Sw2 are turned off and the switch Sw3 is turned on.
When the switches Sw1 and Sw2 are on, the operational amplifier amp amplifies the signal supplied to the input node In, i.e., the output signal of the j-th column DA converter circuit C, and outputs the amplified signal to the output node Out. When the switches Sw1 and Sw2 are off, the operational amplifier amp puts the output terminal of the operational amplifier amp into a high impedance state. However, since the switch Sw3 is on, the output node Out becomes the voltage Vel.
The amplifier circuits other than the j-th column have the same configuration. Control signals Pw2(1) to Pw2(n) are supplied from the control circuit 20 to the amplifier circuits A(1) to A(n) in order.

In addition, in FIG. 3, the voltages of the data lines 14 in the 1st, 2nd, ..., (n-1), nth columns are represented in order as Vd(1), Vd(2), ..., Vd(n-1), Vd(n). In general, the voltage of the data line 14 in the jth column is represented as Vd(j).

Figure 5 is a diagram showing the configuration of a pixel circuit 110. The pixel circuits 110 arranged in a matrix of m rows and n columns are electrically identical to each other. For this reason, the pixel circuits 110 will be described by taking as a representative one the pixel circuit 110 corresponding to the i-th row and j-th column.

As shown in FIG. 5, the pixel circuit 110 includes an OLED 130, p-channel transistors 121 and 122, and a capacitance element 129.

The OLED 130 is an example of a display element, and has a light-emitting functional layer 216 sandwiched between a pixel electrode 213 and a common electrode 218. The pixel electrode 213 functions as an anode, and the common electrode 218 functions as a cathode. The common electrode 218 is optically transparent.
In the OLED 130, when a current flows from the anode to the cathode, holes injected from the anode and electrons injected from the cathode recombine in the light-emitting functional layer 216 to generate excitons, thereby generating white light.

The source node of the transistor 121 is connected to the power supply line 116 of the voltage Vel, and the drain node of the transistor 121 is connected to the pixel electrode 213 which is the anode of the OLED 130 .
The gate node of the transistor 121 is connected to the drain node of the transistor 122 and one end of a capacitance element 129. The other end of the capacitance element 129 is connected to the power supply line 116 of the voltage Vel. Therefore, the capacitance element 129 holds the voltage between the gate and source nodes of the transistor 121.
Note that the capacitance element 129 may be a capacitance parasitic to the gate node of the transistor 121, or a capacitance formed by sandwiching an insulating layer between different conductive layers on a silicon substrate.
In the pixel circuit 110 in the i-th row and j-th column, the gate node of the transistor 122 is connected to the i-th row scanning line 12, and the source node is connected to the j-th column data line 14.

In the pixel circuit 110 configured in this way, when the i-th row of scanning line 12 is selected and the scanning signal /Gwr(i) goes to the L level, the transistor 122 turns on. As a result, the voltage Vd(j) of the data line 14 is applied to the gate node of the transistor 121, and the voltage Vd(j) is held by the capacitance element 129. In detail, the voltage between the gate and source nodes of the transistor 121 when the transistor 122 is turned on is held by the capacitance element 129.

When the selection of the i-th scanning line 12 is completed and the scanning signal /Gwr(i) becomes H level, the transistor 122 turns off, but the capacitance element 129 continues to hold the voltage when the transistor 122 was on. Therefore, in the pixel circuit 110 of the i-th row and j-th column, the transistor 121 supplies a current to the OLED 130 according to the voltage between the gate and source nodes held in the capacitance element 129. Therefore, the OLED 130 emits light with a brightness according to the current.

Note that, although the pixel circuit 110 in the i-th row and j-th column has been described here, this operation is similarly performed for the pixel circuits 110 in the i-th row other than the j-th column. Also, for the pixel circuits 110 in the other than the i-th row, the same operation is performed when the scanning line 12 is selected and the scanning signal supplied to the scanning line 12 becomes the L level.

Next, the operation of the display device 10 will be described. For the sake of simplicity, this operation will be described assuming that the number of rows m of the scanning lines 12 is 8, the number of columns n of the data lines 14 is 8, and further that the OLED 130 emits, for example, white light to display a monochrome image in the display area 100.

First, the operation in the normal image display mode will be described.
Fig. 6 is a timing chart showing the operation of the display device 10 in the normal image display mode. Fig. 8 is a diagram showing the video data Vid assigned to the pixel circuits 110 in the normal image display mode.

8, each square frame indicates a pixel circuit 110 in the display device 10, and the number inside the square frame indicates the pixel position of the video data Vid assigned to the pixel circuit 110. The number before the hyphen "-" indicates the row of the pixel position, and the number after the hyphen indicates the column. For example, in FIG. 8, "4-2" is written in the square frame indicating the pixel circuit 110 with 4 rows and 2 columns, so the data in the 4th row and 2nd column of the video data Vid is assigned as is.
In FIG. 8, of the video data Vid, data allocated to odd-numbered rows constituting the reduced image is hatched to distinguish it from data of even-numbered rows.

6, in the normal image display mode, the control signals Pw1 and Pw2(1) to Pw2(8) are at H level. Therefore, in the DAC group 43, the DA conversion circuit C of each column outputs an analog voltage, and in the amplifier group 44, the amplifier circuits A(1) to A(n) perform an amplification operation.
8, in the normal image display mode, the pixel position indicated by the video data Vid coincides with the position of the pixel circuit 110 in the display area 100. Therefore, in the normal image display mode, the control circuit 20 controls the scanning line driving circuit 120 in accordance with the vertical scanning, and controls the data signal output circuit 140 in accordance with the horizontal scanning.

In detail, as shown in FIG. 6, in accordance with this control, the scanning line driving circuit 120 sequentially and exclusively sets the scanning signals /Gwr(1) to /Gwr(8) to the L level for each horizontal scanning period (H) during one frame (F).
In this description, the period of one frame (F) refers to the period required to display one frame of an image specified by the video data Vid. If the length of the period of one frame is the same as the vertical synchronization period, for example, if the frequency of the vertical synchronization signal included in the synchronization signal Sync is 60 Hz, then the period of one frame is 16.7 milliseconds, which corresponds to one cycle of the vertical synchronization signal.

In the normal image display mode, when the video data Vid supplied from the higher-level device via the control circuit 20 is the i-th row, the data controller 142 sets columns 1 to 8 of the i-th row in the latch circuits L1 of columns 1 to 8 in that order.
When the 1st to 8th columns of the i-th row are set in the latch circuits L1 of the 1st to nth columns, the control circuit 20 sets the i-th row video data Vid set in the latch circuits L1 in the latch circuits L2 and outputs them all at once. The i-th row video data Vid output from the latch circuits L2 is converted to an analog voltage in the DAC group 43, amplified in the amplifier group 44, and output as voltages Vd(1) to Vd(8) to the 1st to 8th column data lines 14.
In addition, during the period in which the video data Vid of the i-th row is output from the latch circuit L2, the video data Vid of the (i+1)th row is supplied, so the data controller 142 sets columns 1 to 8 of the (i+1)th row in the latch circuits L1 of columns 1 to 8 in that order.
Therefore, the period during which the video data Vid for the i-th row is supplied from the host device and the period during which the scanning line driving circuit 120 selects the i-th scanning line 12 are shifted by approximately one horizontal scanning period.

In addition, the control circuit 20 causes the scanning line driving circuit 120 to select the i-th scanning line 12 in synchronization with the output of the i-th row video data Vid from the latch circuit L2. For this reason, the scanning line driving circuit 120 sets the scanning signal /Gwr(i) to the L level.
As a result, the pixel circuits 110 in the i-th row and 1st to 8th columns emit light with luminance according to the voltages Vd(1) to Vd(8).
In the normal image display mode, such an operation is executed for the first to eighth rows in order.
Therefore, in the normal image display mode, the OLED 130 of the pixel circuit 110 emits light with a luminance corresponding to the gradation specified by the video data Vid, and an image as specified by the video data Vid is displayed in the display area 100.
In FIG. 6, the voltages Vd(1) to Vd(8) indicate the pixel arrangement specified by the video data Vid, and are actually analog voltages according to the gradation levels specified by the video data Vid.

Next, the operation of the display device 10 in the reduced image display mode will be described.
The reduced image display mode is a mode in which an image supplied from a higher-level device is reduced and displayed in the display area 100. In the display area 100, pixel circuits 110 are turned off in areas other than the area in which the reduced image is displayed.

Note that the off state of the pixel circuit 110 refers to a state in which no current flows in the display element. In this embodiment, since the display element is the OLED 130, the off state refers to a dark state in which no current flows. If the display element is a normally white mode liquid crystal element, the off state refers to a bright state.
A reduced image is an image in which the vertical and horizontal sizes of an image supplied from a higher-level device are each reduced to 1/k times the size of the image, where k is an integer equal to or greater than 2.
This reduced image is produced by selecting and using only one row out of k rows in the vertical size and one column out of k columns in the horizontal size from the image specified by the video data Vid.
Specifically, if k=2, then only one row out of two rows and only one column out of two columns are selected from the image specified by the video data Vid, and if k=4, then only one row out of four rows and only one column out of four columns are selected from the image specified by the video data Vid.
For the sake of simplicity, the vertical and horizontal reduction rates are set to the same value, but they may be different. Furthermore, k, which indicates the magnification of the reduced image, is included in the control information Wip.

In this embodiment, in the reduced image display mode, the reduced image can be allocated to any position in the display area 100. For convenience of explanation, a case will be described in which, for example, when k is "2", the reduced image is allocated to the upper left corner of the display area 100.
In this case, since k is "2", the reduced image is realized by thinning out one row at a time horizontally and one column at a time vertically from the image supplied from the upper device.

Specifically, from the image of the video data Vid supplied from a higher-level device, either the odd rows or the even rows are thinned out, and either the odd columns or the even columns are thinned out, and the pixel array after the thinning is assigned to the desired position in the display area 100.
FIG. 10 shows an example in which even-numbered rows and even-numbered columns are thinned out to create a reduced image and allocated to the upper left corner of the display area 100. In FIG.

Of the video data Vid, data of pixels that do not constitute the reduced image do not contribute to display. Therefore, in this embodiment, as shown in the figure, pixels that do not constitute the reduced image are replaced with black (Bk) display.
In this embodiment, black display is achieved by not causing the OLED 130 to emit light, that is, by not allowing current to flow.

Now, a configuration can be considered in which scanning lines 12 in the display area 100 are selected in the order of 1, 2, 3, 4, ..., and the video data Vid in the 1st, 3rd, 5th, 7th, ... rows is converted and supplied to data lines 14 in the 1st, 2nd, 3rd and 4th columns, thereby displaying a reduced image such as that shown in Figure 10 on the display device 10.
However, the video data Vid supplied from the higher-level device is supplied in the order of pixels from row 1, column 1 to row 1, column 8, row 2, column 1 to row 2, column 8, row 3, column 1 to row 3, column 8, ..., row 1 to row 8, column 8. Therefore, when the second scanning line 12 is selected, for example, the video data Vid for the third row has not yet been supplied from the higher-level device. Therefore, in order to obtain the video data Vin for the third row when the second scanning line 12 is selected, a configuration is required in which the video data Vid is stored for one frame in a display memory or the like and then read out. Such a configuration not only requires a large storage capacity in the display memory, but also causes a delay in display.

10 in the reduced image display mode, the scanning line driving circuit 120 selects the scanning line 12 in the first row according to the control of the control circuit 20 when the video data Vid supplied from the higher-level device is the first row, and when the video data Vid is the second row, the scanning line driving circuit 120 selects the scanning line 12 in the fifth row, which is different from the second row. Similarly, when the video data Vid is the third, fourth, fifth, sixth, seventh, and eighth rows, the scanning line driving circuit 120 selects the scanning lines 12 in the second, sixth, third, seventh, fourth, and eighth rows in order.
In detail, as shown in FIG. 7 , the scanning line drive circuit 120 sequentially and exclusively sets the scanning signals /Gwr(1), /Gwr(5), /Gwr(2), /Gwr(6), /Gwr(3), /Gwr(7), /Gwr(4), and /Gwr(8) to the L level for each horizontal scanning period (H).
In reality, the period during which the video data Vid for one row is supplied from the higher-level device and the period during which the scanning line driving circuit 120 selects the scanning line 12 for that row are shifted by approximately one horizontal scanning period.

In the reduced image display mode, when the video data Vid supplied from the higher-level device via the control circuit 20 is for the first row, the data controller 142 sets the video data Vid for the first, third, fifth, and seventh columns in the latch circuits L1 for the first, second, third, and fourth columns, and converts the video data Vid for the second, fourth, sixth, and eighth columns into black data and sets it in the latch circuits L1 for the fifth, sixth, seventh, and eighth columns. Note that the black data here is data that puts the OLED 130 in a dark state, and is data that corresponds to the lowest grayscale level.
When the image data Vid is set in the latch circuit L1, the control circuit 20 sets the image data Vid set in the latch circuit L1 in the latch circuit L2 and causes them to be output all at once.
In response to this output, the control circuit 20 causes the scanning line driving circuit 120 to select the first scanning line 12. For this reason, the scanning line driving circuit 120 sets the scanning signal /Gwr(1) to the L level.
Furthermore, control circuit 20 sets control signals Pw1 and Pw2(1) through Pw2(4) to an H level and control signals Pw2(5) through Pw2(8) to an L level in accordance with the period in which scanning signal /Gwr(1) is at an L level.
Therefore, during the period when the scanning signal /Gwr(1) is at the L level, the signal is converted into an analog voltage in the DA conversion circuits C of the DAC group 43 for the first to fourth columns, amplified in the amplifier group 44, and output to the data lines 14 for the first to fourth columns.
In addition, during the period when the scanning signal /Gwr(1) is at the L level, the control signals Pw2(5) to Pw2(8) are at the L level, so that the voltages Vd(5) to Vd(8) of the data lines 14 in the fifth to eighth columns are at the voltage Vel.

Therefore, when the scanning signal /Gwr(1) becomes L level, the pixel circuits 110 in the first row, first column to the fourth row display the first row, third row, fifth row, and seventh row of the video data Vid, while the pixel circuits 110 in the fifth row to the eighth row display black, with no current flowing through the OLED 130.

Next, when the video data Vid supplied from the higher-level device is for the second row, the data controller 142 converts the video data Vid to black data and sets it in the latch circuit L1.
Therefore, the black data set in latch circuit L1 is set in latch circuit L2 and output all at once. Furthermore, during the period corresponding to the output period from latch circuit L2, control circuit 20 causes scanning line drive circuit 120 to select scanning line 12 in the fifth row, and sets control signals Pw1 and Pw2(1) to Pw2(8) to the L level. As a result, voltages Vd(1) to Vd(8) of data lines 14 in the first to eighth columns become voltage Vel.
Therefore, when the scanning signal /Gwr(5) goes to the L level, the pixel circuits 110 in the 5th row, 1st column to the 5th row, 8th column display black.

Next, the video data Vid in the third row is supplied from the higher-level device. The operation at this time is the same as when the scanning signal /Gwr(1) is at the L level, except that the data controller 142 sets the video data Vid in the first, third, fifth, and seventh columns in the third row to the latch circuits L1 in the first, second, third, and fourth columns, and after setting, the control circuit 20 causes the scanning line driving circuit 120 to select the scanning line 12 in the second row.
For this reason, when the scanning signal /Gwr(2) becomes an L level, the pixel circuits 110 in the 2nd row, 1st column to the 2nd row, 4th column display the 3rd row, 1st column, the 3rd row, 3rd column, the 3rd row, 5th column, and the 3rd row, 7th column of the video data Vid, while the pixel circuits 110 in the 2nd row, 5th column to the 2nd row, 8th column display black.

Next, the video data Vid for the fourth row is supplied from the higher-level device, and the operation at this time is the same as when the video data Vid for the second row is supplied. Therefore, when the scanning signal /Gwr(6) becomes L level, the pixel circuits 110 in the first column of the sixth row to the eighth column of the sixth row display black.

The same operation is repeated when the video data Vid for the 5th, 6th, 7th, and 8th rows are supplied from the higher-level device. In detail, when the video data Vid for the 5th, 6th, 7th, and 8th rows are supplied, the scanning signals /Gwr(3), /Gwr(7), /Gwr(4), and /Gwr(8) go to L level in order. As a result, a reduced image is displayed in the display area 100 as shown in FIG. 10.

In addition, when displaying a reduced image as shown in Fig. 10, once the pixel circuits 110 in the 5th to 8th rows display black, there is no need to select the scanning lines 12 in the 5th to 8th rows thereafter. Therefore, the scanning signals /Gwr(5) to /Gwr(8) may be maintained at the H level as shown by the thick dashed lines in Fig. 7. In other words, when transitioning from the normal image display mode to the reduced image display mode, the scanning signals may be changed in the order of the solid lines and the thick dashed lines in Figs. 6 and 7.
Alternatively, when transitioning from the normal image display mode to the reduced image display mode, the transition may be made in the order of the thick dashed line in FIG. 7 after all the pixel circuits 110 have been set to black display.

According to this embodiment, in the reduced image display mode, when all pixel circuits 110 related to the scanning line 12 should display black, the DA conversion circuit C of the DAC group 43 and the amplifier circuits A(1) to A(n) of the amplifier group 44 are stopped. Also, if some of the pixel circuits 110 related to the scanning line 12 are displaying black, the operation of the amplifier circuit of the data line 14 related to the black display, among the amplifier circuits A(1) to A(n), is stopped. Therefore, in this embodiment, low power consumption is achieved.
In this embodiment, in the reduced image display mode, the order of selecting the scanning lines 12 is changed according to the row of the video data Vid supplied from the upper device, and the storage destination of the latch circuit L1 for each column of the video data Vid is changed. In the reduced image display mode, since there is no need to store video data, the configuration can be simplified and the delay in displaying the video data Vid can be reduced.
Furthermore, in this embodiment, since image processing for creating a reduced image and a dedicated circuit are not required, the configuration can be simplified.

In the present embodiment, the reduced image is displayed at the upper left corner of the display area 100, but the reduced image may be displayed at any position.
However, if the display position of the reduced image is arbitrary, the setting of the display position becomes complicated, so for example, control information Wip corresponding to a plurality of types of positions may be preset in advance, and one of them may be selected when the reduced image is displayed. As an example of a plurality of types of positions, as shown in Fig. 11, in addition to the upper left end, there are nine types, namely, the upper center end, the upper right end, the center left, the center, the center right, the lower left end, the lower center end, and the lower right end.

In FIG. 11, a right-pointing triangle indicates the starting row of a reduced image, and a downward-pointing triangle indicates the starting column of a reduced image.
Once the starting row and starting column of the reduced image are determined, it will be easy to infer in what order the scanning lines 12 should be selected and which column of video data Vid should be set in which column of latch circuit L1.

Although the above is an example in which k=2 and the magnification of the reduced image is 1/2, other magnifications are also possible. For example, k=4 and the magnification of the reduced image may be 1/4.
In the reduced image display mode, when the reduced image is displayed positioned at the upper left corner of display area 100, as shown in FIG. 15, the order in which scanning lines 12 are selected, which column of video data Vid is set in which column of latch circuit L1, and the levels of control signals Pw1, Pw2(1), Pw2(2), Pw2(3) through Pw2(8) are, for example, as shown in FIG. 12.
Moreover, the video data Vid allocated to the pixel circuit 110 in the normal image display mode is as shown in Fig. 13. How the video data Vid selected in the reduced image display mode is allocated to the pixel circuit 110 is as shown in Fig. 14.
In this example, the reduced image is composed of rows 1 and 5. In Fig. 13 and Fig. 14, the data assigned to rows 1 and 5 is hatched to distinguish it from the data of the other rows.
12 to 15 can be easily understood by analogy with FIGS. 7 to 10.

In addition, when the magnification of the reduced image is set to 1/4, an example of how to position the reduced image in the display area 100 is shown in FIG. 16. This explanation should also be able to be inferred from FIG. 11.

Although the embodiment has been described as displaying a monochromatic image in the display region 100, a color image may be displayed by additive color mixing of three colors, for example, RGB (red, green, blue).
To make the OLED 130 R, G or B, an optical resonator and a color filter may be provided. In detail, the white light generated from the OLED 130 resonates in an optical resonator composed of a reflective film and a half mirror, and is emitted at a resonant wavelength set corresponding to any one of the colors R, G or B. The light is colored by a color filter corresponding to the color provided on the light emission side from the optical resonator, and is visually recognized by an observer.

In addition, the data signal output circuit 140 may drive the data lines 14 in a so-called scanner mode or in a so-called block sequential mode.

17 is a block diagram showing the configuration of a display device 10 according to the first application example. The display device 10 displays a color image in a display area 100, and a data signal output circuit 140 drives the data lines 14 in a scanner mode.
Specifically, m rows of scanning lines 12 and n columns of data lines 14 are provided in the display area 100. In the first application example, n, which is the number of columns of the data lines 14, is 3p, that is, a multiple of 3.
In the first application example, pixel circuits 110 are arranged in m rows (3p) columns. Of the pixel circuits 110 arranged in m rows (3p) columns, for example, the pixel circuits 110 in the 1st, 4th, 7th, 10th, ..., (3p-2)th columns correspond to R, the pixel circuits 110 in the 2nd, 5th, 8th, 11th, ..., (3p-1)th columns correspond to G, and the pixel circuits 110 in the 3rd, 6th, 9th, 12th, ..., (3p)th columns correspond to B. Three adjacent RGB pixel circuits 110 represent one color pixel.
Moreover, the video data Vid specifies the gradation of one color pixel with, for example, 8 bits for each of RGB.

In this example, one pixel circuit expresses one of the three color components of one color pixel, and therefore should be called a sub-pixel circuit, but since the explanation extends beyond the embodiment, it is referred to as a pixel circuit.

17, the data signal output circuit 140 drives the data lines 14 in a three-phase scanner manner. In particular, switches 45 are provided in a one-to-one correspondence with (3p) columns of data lines 14, and the data lines 14 are grouped in groups of three columns. That is, in the first application example, the number of groups is "p", and the number of columns (number of phases) of data lines 14 constituting one group is "3".
In the first application example, the latch circuits L1 of the latch circuit group 41 and the latch circuits L2 of the latch circuit group 42 are provided in a number corresponding to the number of columns of the data lines 14 constituting one group. Therefore, the number of the latch circuits L1 and the number of the latch circuits L2 are "3".

In the first application example, the DAC group 43 includes three DA conversion circuits C and a voltage generation circuit G, and the amplifier group 44 includes three amplifier circuits A(1) to A(3). Note that, in order to distinguish the latch circuit L2 and the DA conversion circuit C, they may be expressed as the first phase, the second phase, and the third phase from the left.
The output nodes in the amplifier circuits A(1) to A(3) are each branched into p columns and connected to one end of a switch 45. The other end of the switch 45 is connected to the data line 14. The on/off of the switches 45 is controlled for each group. For example, the three switches 45 belonging to the first group counting from the left in the figure are turned on when the control signal Sel(1) is at H level and turned off when it is at L level. The three switches 45 belonging to the second group are similarly turned on and off in accordance with the control signal Sel(2). The three switches 45 belonging to the pth group are similarly turned on and off in accordance with the control signal Sel(p). The control signals Sel(1) to Sel(p) are supplied from the control circuit 20.

Next, the operation of the first application example will be described. For the sake of simplicity, it is assumed that the number of rows m of the scanning lines 12 is "8" and the number of columns n of the data lines 14 is "24", that is, the number of groups p is "8".
In addition, in the first application example, one square frame in Fig. 8 to Fig. 10 indicates one color pixel. Therefore, as in the embodiment, the number before the hyphen "-" indicates the row, but the number after the hyphen indicates the group number. For example, in Fig. 8, "4-2" indicates a color pixel in four rows and two columns, more specifically, a color pixel in the fourth row represented by the R pixel circuit 110 in the fourth column, the G pixel circuit 110 in the fifth column, and the B pixel circuit 110 in the sixth column.
For the sake of simplicity, the video data Vid will be described in units of one color pixel, rather than in units of RGB.

In this example, in the normal image display mode, in one horizontal scanning period (H) in which the video data Vid for the first row is supplied, the control circuit 20 causes the scanning line driving circuit 120 to select the scanning line 12 for the first row. Therefore, the scanning signal /Gwr(1) becomes the L level.
Moreover, the control circuit 20 sequentially and exclusively sets the control signals Sel(1) to Sel(8) to the H level.
In detail, when video data Vid of a color pixel "1-1" corresponding to the first group in the first row is supplied from a higher-level device, the data controller 142 sets the RGB components of the video data in the first to third phase latch circuits L1. After setting the video data Vid in the three latch circuits L1, the control circuit 20 transfers the set video data to the latch circuit L2. As a result, the RGB of the video data corresponding to the color pixel in the first row and first column is output from the three latch circuits L2. The control circuit 20 sets the control signal Sel(1) to the H level in accordance with the transfer to the latch circuit L2.
As a result, the three columns of data lines 14 corresponding to the first group are supplied with a voltage obtained by converting and amplifying the R, G, and B component video data Vid of the color pixel corresponding to the intersection with the scanning line 12.

Next, when the video data Vid of the color pixels "1-2" corresponding to the second group is supplied from the higher-level device, the data controller 142 sets the RGB components of the video data in the first to third phase latch circuits L1. After setting the video data Vid in the latch circuit L1, the control circuit 20 transfers the set video data to the latch circuit L2. As a result, the video data corresponding to the color pixel in the first row and second column is output from the three latch circuits L2. The control circuit 20 sets the control signal Sel(2) to the H level in accordance with the transfer to the latch circuit L2. As a result, the three data lines 14 corresponding to the second group are supplied with a voltage obtained by converting and amplifying the video data Vid of the R, G, and B components of the color pixel corresponding to the intersection with the scanning line 12.

Similar operations are repeated until the control signal Sel(8) goes to H level and a voltage obtained by converting and amplifying the R, G, and B component video data Vid of the color pixel corresponding to the intersection with the scanning line 12 is supplied to the three data lines 14 corresponding to the color pixel in the first row and eighth column.
This completes the display of line 1. Similar operations are then carried out for lines 2 to 8.

10 in the reduced image display mode, first, if the video data Vid supplied from the host device via the control circuit 20 is for the first row, the video data Vid corresponding to the color pixels in the first column is adopted and written using the control signal Sel(1), the video data Vid corresponding to the color pixels in the second column is converted to black data and written using the control signal Sel(5), the video data corresponding to the color pixels in the third column is adopted and written using the control signal Sel(2), the video data Vid corresponding to the color pixels in the fourth column is converted to black data and written using the control signal Sel(6), and similar operations are repeated thereafter. In detail, the control signals Sel(1), Sel(5), Sel(2), Sel(6), Sel(3), Sel(7), Sel(4), and Sel(8) are turned to H level in this order and writing is performed.
During the periods in which the control signals Sel are at H level in the above order, the control circuit 20 causes the scanning line driving circuit 120 to select the first scanning line 12 .

Next, when the video data Vid supplied from the higher-level device is for the second row, the data controller 142 converts the video data Vid to black data and outputs it. During the period in which the black data is written by the control signal Sel, the control circuit 20 causes the scanning line driving circuit 120 to select the scanning line 12 for the fifth row, and sets the control signals Pw1 and Pw2(1) to Pw2(8) to the L level. As a result, the data lines 14 for the first to eighth columns are at the voltage Vel.
In addition, when the video data Vid supplied from the higher-level device is the 3rd, 5th, or 7th row, an operation similar to that of the 1st row is executed, and when the video data Vid supplied from the higher-level device is the 4th, 6th, or 8th row, an operation similar to that of the 2nd row is executed.

In the first application example, the number of columns of data lines 14 constituting one group is "3", but it may be a multiple of 3 other than "3", and the number of groups p may be an integer of 2 or more other than "8". In addition, when the data lines 14 are grouped into multiples of 3, the group may be used as a unit when adopting the video data Vid in the horizontal (column) direction for the reduced image.

Next, we will explain a second application example in which the number of columns of data lines 14 that make up one group is "240" and the number of groups p is "24".

In the second application example, the number of columns of data lines 14 constituting one group, "240", is converted into the number of color pixels arranged, which is "80" (=240÷3). Also, in the second application example, the number of columns of data lines 14 is 5760 (=240×24), and the color pixels are arranged in 1920 columns (=5760÷3) per row.
Although the specific configuration of the second application example is not particularly shown, in FIG. 17, the number of latch circuits L1 in the latch circuit group 41, the number of latch circuits L2 in the latch circuit group 42, the number of DA conversion circuits C in the DAC group 43, and the number of amplifier circuits in the amplifier group 44 are all set to "240."

In the second application example, the number of color pixels arranged in one row is "1920", which is "5760" in terms of RGB, so the amount of data in the video data Vid is enormous. For this reason, in the second application example, the video data Vid is supplied from a higher-level device in parallel, for example, over 12 channels. Specifically, the RGB components of four color pixels are supplied over a total of 12 channels.
The video data Vid for RGB of the four color pixels is collectively referred to as 4RGB. For simplicity, the video data Vid will be described in units of one color pixel, not for each of RGB. Specifically, the video data Vid will be described as the color pixels in columns 1 to 1920 for one row.

In the second application example, in the normal image display mode, the data controller 142 repeatedly sets the 4RGB video data Vid in the latch circuit L1 20 times, and when all the data is ready, it transfers it to the latch circuit L2, outputs analog voltages from the 240 DA conversion circuits C and 240 amplifier circuits, and applies (scans) the analog voltages to the 240 data lines 14 selected in the order of the control signals Sel(1) to Sel(24). This operation is repeated 24 times in one horizontal synchronization period, and is written to all 5,760 data lines 14.

On the other hand, in this configuration, when a 1/2 reduced image is displayed in the reduced image display mode by using, for example, odd rows and odd columns, if the video data Vid supplied from the higher-level device is an odd row, the data controller 142 excludes the video data of the even columns from the video data Vid supplied twice for 4 RGB, and arranges (rearranges) only the 4 RGB in the odd columns in order, and sets them in order in the latch circuit L1.
That is, half (odd-numbered columns) of the video data supplied from the higher-level device is set in the latch circuit L1. Conversely, to set odd-numbered columns of video data in all latch circuits L1, video data Vid for two scans, which is double the amount, needs to be supplied from the higher-level device.
For this reason, until one scan's worth of video data Vid is supplied from the higher-level device, the control circuit 20 writes in a black display area using one of the control signals Sel(1)-Sel(24) with the output of the latch circuit L2 as black data, and then, when two scans' worth of video data Vid is supplied and all of the odd-numbered column video data Vid is set in the latch circuit L1, the control circuit 20 transfers the data to the latch circuit L2 and applies the analog voltage to the 240 columns of data lines 14 selected by one of the control signals Sel(1)-Sel(24). This operation is repeated in one horizontal synchronization period to write in all of the data lines 14 for one row.

This operation will be described with reference to Fig. 18. Fig. 18 is a diagram showing the relationship between the video data Vid for two scans of columns 1 to 160 supplied from a higher-level device and the video data Vid output from the latch circuit L2. In detail, the upper part of Fig. 18 shows the video data Vid supplied from the higher-level device, and the lower part of Fig. 18 shows the video data Vid output from the latch circuit L2.
As shown in the upper part of FIG. 18, for a certain odd-numbered row, the color pixels (RGB) in columns 1 to 80 are supplied in this order, and then the color pixels (RGB) in columns 81 to 160 are supplied in this order.
In reality, the video data Vid is supplied from a higher-level device in parallel over 12 channels as described above, but for the sake of convenience, it is represented here as if the video data Vid of color pixels is supplied in time series starting from the first column.

During the period in which the color pixels in the 1st to 80th columns are supplied, the control circuit 20 resets the 240 latch circuits L2 to output black data. At this time, the control circuit 20 sets the control signal Sel (41) to the H level.
Therefore, in the right half of the display area 100, a voltage corresponding to black data is written to the data lines 14 of the 240th column belonging to the 41st group on the leftmost side.

Furthermore, the data controller 142 selects only the video data on odd-numbered columns from the video data Vid on the 1st to 160th columns, and sets them in order in the latch circuit L1.
When all the video data for the odd-numbered columns among the 1st to 160th columns are set in the latch circuit L1, the control circuit 20 transfers the video data for the odd-numbered columns to the latch circuit L2. At this time, the control circuit 20 sets the control signal Sel(1) to the H level. As a result, a voltage equivalent to the video data for the odd-numbered columns is written to the data lines 14 of the 240th column belonging to the first group at the leftmost end in the left half area of the display area 100.

In the odd rows, this operation of writing black data and selecting odd columns is performed each time video data Vid for columns 161 to 320, 321 to 640, ..., 1761 to 1920 is supplied, that is, each time two scans' worth of video data Vid is supplied.

Furthermore, in this configuration, when a 1/4 reduced image is displayed in reduced image display mode by adopting the video data Vid in rows 1, 5, 9, 13, ... and columns 1, 5, 9, 13, ..., if the video data Vid supplied from the higher-level device is for the adopted row, the data controller 142, for example, excludes the video data for the non-adopted columns from the video data Vid supplied four times for 4 RGB, and arranges only the 4 RGB for the adopted column in order and sets it in the latch circuit L1.
To set the video data of the adopted column in all latch circuits L1, video data Vid for four scans, which is four times the amount, must be supplied from the upper device. Therefore, during the period when the video data Vid for the first, second, and third scans is supplied from the upper device, the control circuit 20 writes the black display area using the output of the latch circuit L2 as black data by one of the control signals Sel(1) to Sel(24). Next, when the video data Vid for the fourth scan is supplied and all the video data Vid of the adopted example is set in the latch circuit L1, the control circuit 20 transfers the data to the latch circuit L2 and applies the analog voltage to the data lines 14 of the 240 columns selected by one of the control signals Sel(1) to Sel(24). This operation is repeated in one horizontal synchronization period to write all the data lines 14 for one row.

In the selected row, this operation of writing three scans of black data and selecting the selected column for writing is performed every time video data Vid for columns 1 to 320, 321 to 640, ..., 1601 to 1920 is supplied, that is, every time video data Vid for four scans is supplied.

This operation is easy to understand from the analogy of FIG. 18, so illustration is omitted. Also, in the second application example, the operation when displaying a 1/2 or 1/4 reduced image in the reduced image display mode is almost the same as the embodiment and its application examples already described, so explanation is omitted.

5 has been described as an example of pixel circuit 110, but the present invention is not limited to this configuration. For example, an element for compensating for the threshold voltage of transistor 121, an element for controlling the light emission period of OLED 130, an element for clearing the charge held in the capacitance of OLED 130, etc. may be provided.
In the embodiment and the like, the OLED 130 has been described as an example of a display element, but as described above, other display elements may be used. For example, an LED or a liquid crystal element may be used as the display element.
In addition, in the embodiments and the like, the channel type of the transistor in the pixel circuit 110 is not limited to the embodiments. When changing the channel type of a transistor, the logic level of the control signal supplied to the gate node of the transistor is appropriately inverted.
It should be noted that if the transistor 121 is changed to an n-channel transistor, the voltage that turns off the pixel circuit 110 becomes a low voltage at which the transistor 121 turns off.

<Electronic devices>
Next, an electronic device to which the display device 10 according to the embodiment is applied will be described. As described above, the display device 10 is suitable for applications requiring small-sized pixels and high-definition display. Therefore, a head-mounted display will be taken as an example of the electronic device.

FIG. 19 is a diagram showing the appearance of a head mounted display, and FIG. 20 is a diagram showing its optical configuration.
First, as shown in Fig. 19, the head mounted display 300 has temples 310, a bridge 320, and lenses 301L and 301R, similar to general eyeglasses. As shown in Fig. 20, the head mounted display 300 is provided with a display device 10L for the left eye and a display device 10R for the right eye near the bridge 320 and on the rear side of the lenses 301L and 301R (the lower side in the figure).
The image display surface of the display device 10L is disposed to the left in FIG. 20. As a result, the image displayed by the display device 10L is output in the direction of 9 o'clock in the figure via the optical lens 302L. The half mirror 303L reflects the image displayed by the display device 10L in the direction of 6 o'clock, while transmitting light incident from the direction of 12 o'clock. The image display surface of the display device 10R is disposed to the right, opposite the display device 10L. As a result, the image displayed by the display device 10R is output in the direction of 3 o'clock in the figure via the optical lens 302R. The half mirror 303R reflects the image displayed by the display device 10R in the direction of 6 o'clock, while transmitting light incident from the direction of 12 o'clock.

In this configuration, a person wearing the head mounted display 300 can observe the images displayed by the display devices 10L and 10R in a see-through state in which the images are superimposed on the outside world.
When the wearer walks, in the normal image display mode, the field of view is blocked by the images displayed by the display devices 10L and 10R. In such a case, by switching to the reduced image display mode, a reduced image is displayed, and a space is created in the display area 100, so that the field of view can be secured.
can be done.

In addition, electronic devices including the display device 10 can be applied to electronic viewfinders in video cameras and digital cameras with interchangeable lenses, in addition to the head-mounted display 300.

<Additional Notes>
A display device according to one aspect (aspect 1) includes a display area in which pixel circuits are arranged in a matrix, the pixel circuits being provided at the intersections of a plurality of rows of scanning lines and a plurality of columns of data lines; a scanning line driving circuit capable of driving the plurality of rows of scanning lines in any order; and a data signal output circuit capable of supplying, to the plurality of columns of data lines, a data signal obtained by converting one row of video data of an entire image corresponding to input video data, in any order. In a mode in which a reduced image obtained by thinning out the entire image by rows and columns is assigned to a partial region of the display area and displayed, the scanning line driving circuit drives a scanning line of the row when a row specified by the video data corresponds to the row assigned to the partial region, and drives a scanning line of a row other than the row specified by the video data when the row specified by the video data corresponds to an area other than the partial region, and the data signal output circuit supplies a data signal corresponding to the scanning line of the row driven by the scanning line driving circuit to the data line assigned to the partial region.
According to this aspect, since no special configuration such as image processing is required to obtain a reduced image, the configuration can be simplified.

In a display device according to a specific aspect (aspect 2) of aspect 1, the reduced image is assigned to a position in the display area specified by the control information. According to this aspect, by assigning the reduced image to a position specified by the control information, free space is generated in the display area 100, making it easier to ensure visibility.

In a display device according to a specific aspect (aspect 3) of aspect 1 or aspect 2, in the mode, the data signal output circuit supplies a signal that turns off the pixel circuit to data lines other than the data lines assigned to the partial region. According to this aspect, it is possible to reduce power consumption when displaying a reduced image.

In a display device according to a specific aspect (aspect 4) of aspect 3, the data signal output circuit includes an amplifier circuit that amplifies a signal based on the video data and supplies the signal to the data line as the data signal, and in the mode, the amplifier circuit supplies a signal of a voltage that turns off the pixel circuit to data lines other than the data lines assigned to the partial region.

In addition, in a display device according to a specific aspect (aspect 5) of aspect 4, the data signal output circuit has a DA conversion circuit corresponding to the data line, which converts the video data into an analog signal and supplies it to the amplifier circuit, and in the mode, if the row specified by the video data does not correspond to the row assigned to the partial area, the DA conversion circuit stops the conversion operation.

An electronic device according to a specific aspect (aspect 6) of aspects 1 to 5 has a display device according to any of the above aspects. According to this aspect, an electronic device with a simplified configuration is realized.

10: display device, 12: scanning line, 14: data line, 20: control circuit, 100: display area, 110: pixel circuit, 120: scanning line drive circuit, 130: OLED, 140: data signal output circuit, 300: head mounted display.

Claims (6)

a display area in which pixel circuits are arranged in a matrix, the pixel circuits being provided at the intersections of a plurality of rows of scanning lines and a plurality of columns of data lines;
a scanning line driving circuit capable of driving the plurality of scanning lines in any order;
a data signal output circuit capable of supplying a data signal obtained by converting one row of video data out of an entire image corresponding to input video data to the data lines of the plurality of columns;
Including,
A mode in which a reduced image obtained by thinning out the entire image by rows and columns is allocated to a part of the display area and displayed,
The scanning line driving circuit includes:
If a row designated by the image data corresponds to a row assigned to the partial region, driving the scan line of the row;
When the row specified by the video data corresponds to a thinned row in the reduced image , driving the scanning lines of the row not included in the partial area ;
The data signal output circuit includes:
the data signal corresponding to the scanning line of the row driven by the scanning line driving circuit is supplied to the data line assigned to the partial region. The display device according to claim 1 , wherein the reduced image is allocated to a position in the display area that is designated by control information. The data signal output circuit includes:
In said mode,
The display device according to claim 1 , further comprising: a signal for turning off the pixel circuit being supplied to a data line other than the data line assigned to the partial region. The data signal output circuit includes:
an amplifier circuit that amplifies a signal based on the video data and supplies the signal to the data line as the data signal;
The amplifier circuit includes:
In said mode,
The display device according to claim 3 , wherein a signal having a voltage for turning off the pixel circuit is supplied to data lines other than the data lines assigned to the partial region. The data signal output circuit includes:
a DA conversion circuit for converting the video data into an analog signal and supplying the analog signal to the amplifier circuit, the DA conversion circuit being provided in correspondence with the data line;
In the mode, if a line designated by the image data does not correspond to a line assigned to the partial region,
The display device according to claim 4 , wherein the DA conversion circuit stops a conversion operation. 6. An electronic device comprising the display device according to claim 1.

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