JP7535866B2 - Semiconductor Device - Google Patents

Description

The present invention relates to a semiconductor device .

In order to prevent damage caused by abnormal increases in junction temperature during operation of semiconductor power elements such as power MOS transistors, there is a technology that controls the semiconductor power elements to protect them from thermal damage according to the temperature detected by a heat-sensitive element placed near the semiconductor power elements.

Specifically, a semiconductor device has been proposed in which a heat-sensing element that detects the heat generation state of a semiconductor power element is disposed in a region between the semiconductor power element formation regions of a semiconductor chip in which a semiconductor power element that generates high heat when a current flows in the conductive state is formed (see, for example, Patent Document 1).

Japanese Patent Application Publication No. 10-116987

In one aspect, the objective is to provide a semiconductor device that can suppress the occurrence of stress migration in metal wiring arranged between semiconductor element formation regions.

In one embodiment, the semiconductor device comprises:
A semiconductor device having a semiconductor substrate, a plurality of semiconductor element forming regions spaced apart from each other, and a gap region sandwiched between the semiconductor element forming regions,
a plurality of metal wiring layers each disposed above the semiconductor element in the semiconductor element forming region and electrically connected to the semiconductor element;
a plurality of interlayer insulating films which insulate the plurality of metal wiring layers from one another and are disposed in the semiconductor element forming region and the gap region;
a first group of plugs that are embedded through the interlayer insulating film and are electrically connected to the metal wiring layers;
an inter-region metal wiring extending across the gap region between the semiconductor element forming regions;
a second plug group embedded in the gap region of the interlayer insulating film below the uppermost layer of the metal wiring layer.

In one aspect, a semiconductor device can be provided that can suppress the occurrence of stress migration in metal wiring arranged between semiconductor element formation regions.

FIG. 1 is a circuit diagram showing a semiconductor device according to the first embodiment. FIG. 2 is a schematic top view of the transistor shown in FIG. FIG. 3 is an enlarged perspective view of the transistor formation region shown in FIG. FIG. 4 is a schematic diagram showing a cross section taken along line AA shown in FIG. FIG. 5 is an enlarged perspective view of the transistor formation region and the gap region shown in FIG. FIG. 6 is an enlarged perspective view of a transistor formation region and a gap region shown for comparison. FIG. 7 is a schematic diagram showing a cross section of the transistor formation region and the gap region shown in FIG. FIG. 8 is an explanatory diagram showing a method for manufacturing the semiconductor device according to the first embodiment. FIG. 9 is an explanatory diagram showing a method for manufacturing the semiconductor device according to the first embodiment. FIG. 10 is an explanatory diagram showing a method for manufacturing the semiconductor device according to the first embodiment. FIG. 11 is an explanatory diagram showing a method for manufacturing the semiconductor device according to the first embodiment. FIG. 12 is an explanatory diagram showing a method for manufacturing the semiconductor device according to the first embodiment. FIG. 13 is an explanatory diagram showing a method for manufacturing the semiconductor device according to the first embodiment. FIG. 14 is an explanatory diagram showing a method for manufacturing the semiconductor device according to the first embodiment. FIG. 15 is an explanatory diagram showing a method for manufacturing the semiconductor device according to the first embodiment. FIG. 16 is an explanatory diagram showing a method for manufacturing the semiconductor device according to the first embodiment. FIG. 17 is an explanatory diagram showing a method for manufacturing the semiconductor device according to the first embodiment. FIG. 18 is an enlarged perspective view of a transistor formation region and a gap region in a semiconductor device according to the second embodiment. FIG. 19 is a schematic top view of a transistor according to the third embodiment.

A semiconductor device according to one embodiment of the present invention is a semiconductor device having a plurality of semiconductor element formation regions, each of which has a semiconductor element formed therein and spaced apart from one another, and a gap region sandwiched between the semiconductor element formation regions, and is equipped with: a plurality of metal wiring layers, each of which is disposed above the semiconductor elements in the semiconductor element formation regions and electrically connected to the semiconductor elements; a plurality of interlayer insulating films which insulate the plurality of metal wiring layers and are disposed in the semiconductor element formation regions and the gap region; a plurality of first plug groups which are embedded through the interlayer insulating films and are electrically connected to the plurality of metal wiring layers; inter-region metal wiring which is provided in the gap region between the semiconductor element formation regions; and a second plug group which is embedded in the gap region of the interlayer insulating film below the topmost layer of the metal wiring layers.
Alternatively, the semiconductor element formation region may have a recess in plan view, and the inside of this recess may be the gap region.

The semiconductor device according to one embodiment of the present invention is based on the following findings:

In the semiconductor device described in Patent Document 1, in order to ensure electrical conduction to the source and drain of the power MOS transistor formed in the bottom layer, multi-layer wiring is formed above them. In addition, in order to prevent the power MOS transistor from being thermally destroyed, a thermal element that detects heat from the power MOS transistor is provided in the bottom layer of the gap region sandwiched between the transistor formation regions in order to accurately detect the heat. In this case, if the source and drain metal wiring is routed in the top layer above the thermal element to narrow the layout, voids due to stress migration may occur locally in this metal wiring, reducing the allowable current of the wiring and making it impossible to flow the desired amount of current. This is thought to be because thermal stress occurs in the plugs and metal wiring that form the multi-layer wiring in the transistor formation region, and large thermal stress is concentrated in the gap region sandwiched between the transistor formation regions. Therefore, with such a structure, defects may occur during high-temperature storage tests and temperature cycle tests.

Therefore, in the semiconductor device according to one embodiment of the present invention, a second group of plugs is embedded as a plurality of dummy plugs in the interlayer insulating film in the gap region.
As a result, in the gap region of the semiconductor device according to the embodiment of the present invention, plug groups are embedded in the gap region in the same manner as in the semiconductor element formation regions on both sides thereof, so that the structure of the gap region becomes similar to that of the semiconductor element formation region, and it is considered that thermal stress from the semiconductor element formation region is less likely to concentrate on the metal wiring in the gap region due to the anchor effect of the plug groups. Therefore, in the gap region, it is possible to suppress the occurrence of stress migration in the inter-region metal wiring that electrically connects the semiconductor element formation regions.

In the above embodiment, the second plug group, which is a dummy plug group, is embedded in the gap region, but this is not limited to the above. From the viewpoint of making the structure of the gap region closer to the structure of the semiconductor element formation region, metal wiring may be formed in the gap region, or both the second plug group and metal wiring may be formed.

Moreover, a manufacturing method of a semiconductor device according to one embodiment of the present invention is a manufacturing method of a semiconductor device having a plurality of semiconductor element formation regions, each of which has a semiconductor element formed therein and spaced apart from one another, and a gap region sandwiched between the semiconductor element formation regions, the manufacturing method including the steps of: forming the semiconductor elements in each of the semiconductor element formation regions; repeatedly forming, in this order, a metal wiring layer that is stacked above the semiconductor elements and electrically connects them to the semiconductor elements; an interlayer insulating film that is stacked in the semiconductor element formation regions and the gap region and provides electrical insulation between the metal wiring layer; and a first group of plugs that are embedded through the interlayer insulating film and electrically connect them to the metal wiring layer; and repeatedly forming the metal wiring layer, the interlayer insulating film, and the first group of plugs, and embedding a second group of plugs in the gap region in an interlayer insulating film that is lower than the topmost layer of the metal wiring layer, to bridge inter-region metal wiring between the semiconductor element formation regions.
As a result, the semiconductor device according to one embodiment of the present invention can be manufactured by the method for manufacturing a semiconductor device according to one embodiment of the present invention.

Next, embodiments of the semiconductor device of the present invention will be described with reference to the drawings.
The dimensions, materials, shapes, and relative positions of each of the components illustrated in the embodiments may be appropriately changed depending on the configuration of the device to which the present invention is applied, various conditions, and the like.

In each drawing, the same components are given the same reference numerals, and duplicated explanations may be omitted.
In the drawings, the X, Y, and Z directions are perpendicular to one another. A direction including the X direction and the opposite direction to the X direction (-X direction) is referred to as the "X-axis direction", a direction including the Y direction (upward) and the opposite direction to the Y direction (-Y direction, downward) is referred to as the "Y-axis direction", and a direction including the Z direction and the opposite direction to the Z direction (-Z direction) is referred to as the "Z-axis direction" (height direction, thickness direction).
Furthermore, a plane including the X-axis and Y-axis directions is sometimes referred to as the "XY plane," a plane including the X-axis and Z-axis directions is sometimes referred to as the "XZ plane," and a plane including the Y-axis and Z-axis directions is sometimes referred to as the "YZ plane."

First Embodiment
(Semiconductor device)
FIG. 1 is a circuit diagram showing a semiconductor device according to the first embodiment.
1, the circuits formed in the semiconductor device 100 include a transistor 110, an input terminal 120, an output terminal 130, a resistive voltage divider circuit 140, a comparator 150, a reference voltage circuit 160, and a thermal shutdown circuit 170. The semiconductor device 100 steps down an input voltage and outputs a constant voltage.

The transistor 110, which serves as a semiconductor element, is a power MOS transistor and is sometimes referred to as a driver. The transistor 110 has a source S connected to an input terminal 120, and a drain D connected to an output terminal 130 and a resistive voltage divider circuit 140. A comparator 150 and a thermal shutdown circuit 170 are connected to a gate G of the transistor 110.

The resistive voltage divider circuit 140 is connected between the output terminal 130 and the ground terminal.
The comparator 150 receives the divided voltage obtained by the resistive voltage divider circuit 140 at its non-inverting input terminal, and receives the reference voltage of the reference voltage circuit 160 at its inverting input terminal.

The semiconductor device 100 controls the gate G of the transistor 110 based on the voltage output from the comparator 150 to which a divided voltage based on the output voltage of the output terminal 130 and a reference voltage of a reference voltage circuit 160 are input. This allows the semiconductor device 100 to output to the output terminal 130 a constant output voltage _Vout that is lower than the input _voltage Vin applied to the input terminal 120.

In order to prevent the transistor 110 from being thermally destroyed, the thermal shutdown circuit 170 turns off the gate of the transistor 110 when the detected temperature of a heat sensitive element 171 arranged near the transistor 110 reaches or exceeds a predetermined value.
The heat-sensitive element 171 may be, for example, a diode.

Figure 2 is a schematic top view of the transistor shown in Figure 1. Figure 2 shows the vicinity of the transistor 110 when the semiconductor device 100 formed on the semiconductor substrate is viewed from above.

As shown in FIG. 2, the source wiring S3 and drain wiring D3 of the transistor 110 are formed on the upper surface of the semiconductor device 100, and the comb-shaped wiring arranged in parallel in the X-axis direction is arranged so as to interdigitate. The interdigitated region is divided into two transistor formation regions 111 and 112, where the transistors 110 are respectively formed on the semiconductor substrate, and a gap region 113 between them where no transistors are formed.

On the semiconductor substrate in this gap region 113, a heat sensitive element 171 of the thermal shutdown circuit 170 shown in FIG.
It should be noted that the thermal element 171 is not shown in FIG.

Furthermore, for convenience, the wiring that is part of the comb-shaped wiring of the source wiring S3 and the drain wiring D3 in the gap region 113 and electrically connects the transistor formation regions 111 and 112 is referred to as the inter-region metal wiring 114.

In this embodiment, the comb-shaped wiring has the same thickness from the base to the tip of the comb, but this is not limited to this and the thickness may be made thinner toward the tip. The number of combs can also be selected appropriately depending on the purpose.

In the transistor formation regions 111, 112 and the gap region 113, a plurality of plugs 111P, 112P, 113P are formed which are electrically connected to the underlying metal wiring layer.
Hereinafter, the multiple plugs formed in the transistor formation regions 111, 112 will be referred to as wiring plug groups 111P, 112P (first plug group), and the multiple plugs formed in the gap region 113 will be referred to as a dummy plug group 113P (second plug group).

In this embodiment, the plug groups are arranged in groups of four adjacent small plug groups in the Y-axis direction, and are arranged alternately on the source wiring S3 and the drain wiring D3, but this is not limited to this. For example, the small plug groups may be arranged in two rows of three, etc., to match the thickness of the comb portion.

Figure 3 is an enlarged perspective view of the transistor formation region shown in Figure 2. Figure 3 shows an enlarged view of the transistor formation region 111, and shows not only the metal wiring layer M3, which corresponds to the top layer of the metal wiring, but also the metal wiring layer M2 underneath it.

As shown in FIG. 3, in the metal wiring layer M3, source wiring S3a and drain wiring D3a are arranged parallel to the X-axis direction. In the metal wiring layer M2 below, source wiring S2a, S2b, S2c and drain wiring D2a, D2b, D2c are arranged parallel to the Y-axis direction. The source wiring S3a is electrically connected to the source wiring S2a, S2b, S2c, and the drain wiring D3a is electrically connected to the drain wiring D2a, D2b, D2c by wiring plug groups 111P.

In this embodiment, the source wiring S3a and the drain wiring D3a are arranged so as to intersect at right angles with the source wiring S2a, S2b, and S2c and the drain wiring D2a, D2b, and D2c, but this is not limited to the above.

Figure 4 is a schematic diagram showing a cross section taken along line A-A in Figure 3. Figure 4 shows a cross section of the semiconductor device 100 on the source wiring S3a.

4, a transistor 110 is formed on a semiconductor wafer W, and interlayer insulating films L1, L2, L3, and L4 and a passivation film P are laminated thereon. Metal wiring layers M1, M2, and M3 are laminated on the upper surfaces of the interlayer insulating films L1, L2, and L3, respectively, and are electrically connected to the transistor 110 by a wiring plug group 111P. In other words, the metal wiring layers M1, M2, and M3 are electrically insulated from each other by the interlayer insulating films L1, L2, and L3, and are electrically connected to each other by the wiring plug group 111P. The wiring plug group 111P is embedded through the interlayer insulating films L1, L2, and L3, and electrically connects the metal wiring layers M1, M2, and M3.
Moreover, a Ti/TiN film is formed as an anti-reflection film and a barrier metal film on the upper and lower surfaces of the combination of the metal wiring layer and the wiring plug.

The transistor 110 has a structure in which a plurality of combinations of a source region, a drain region, and a gate electrode are formed.
For example, the source region S0a is electrically connected to a source wiring S3a provided in the uppermost metal wiring layer M3 through metal wirings S1a, S2a and a wiring plug group 111P. Although not shown, the drain region D0a is electrically connected to a drain wiring D3a provided in the metal wiring layer M3 through drain wirings D1a, D2a and a wiring plug group 111P.

Figure 5 is an enlarged perspective view of the transistor formation region and gap region shown in Figure 1. Figure 5 shows an enlarged view of the transistor formation regions 111, 112 and gap region 113, and shows not only the metal wiring layer M3, which is the top layer of the metal wiring, but also the metal wiring layer M2 underneath it.

As shown in FIG. 5, in the transistor formation regions 111 and 112, source wirings S3a and S3b and drain wirings D3a and D3b are formed in the metal wiring layer M3. Source wirings S2a to S2h and drain wirings D2a to D2h are formed in the metal wiring layer M2. Furthermore, wiring plug groups 111P and 112P for electrical connection are arranged between the metal wiring layer M2 and the metal wiring layer M3.

On the other hand, in the gap region 113, an inter-region metal wiring 114 is formed in the metal wiring layer M3. Also, in the metal wiring layer M2, a dummy wiring DM is formed instead of the source wiring and the drain wiring. Furthermore, between the metal wiring layer M2 and the metal wiring layer M3, a dummy plug group 113P is arranged instead of the wiring plug groups 111P and 112P.

The dummy wiring DM is formed with the same shape, structure, size, material and arrangement pattern as the metal wiring layer M2 (D2a, S2a, ..., S2h) in the transistor formation regions 111, 112. In addition, the dummy plug group 113P is formed with the same shape, structure, size, material and arrangement pattern as the wiring plug groups 111P, 112P.

Normally, since no transistors are formed in the gap region 113, the dummy wiring DM and dummy plug group 113P of the metal wiring layer M2 are not required in the gap region 113, and therefore, for example, a structure as shown in FIG. 6 can be used.
However, in the structure shown in FIG. 6, as indicated by the arrows in FIG. 6, stress from wiring plug groups 111P, 112P is concentrated in gap region 113, which causes a problem that stress migration is likely to occur in inter-region metal wiring 114.
5, by providing dummy wiring DM and a dummy plug group 113P in the gap region 113, the structure of the gap region 113 becomes similar to the structure of the transistor formation regions 111, 112, so that it is possible to prevent the stress from the transistor formation regions 111, 112 from concentrating in the gap region 113. In addition, due to the anchor effect of the dummy plug group 113P, the thermal stress from the transistor formation regions 111, 112 is less likely to concentrate on the metal wiring in the gap region 113.
Therefore, the semiconductor device 100 of this embodiment can suppress the occurrence of stress migration that manifests itself as voids, hillocks, and the like in the inter-region metal wiring 114 in the gap region 113 .

Moreover, the shortest pitch between adjacent plugs in the wiring plug groups 111P and 112P is substantially the same as the shortest pitch between adjacent plugs in the dummy plug group 113P.
As a result, the density of the wiring plug groups 111P, 112P on both sides of the gap region 113 and the density of the dummy plug group 113P in the gap region 113 become close to each other, making it easier to balance the stress from the wiring plug groups 111P, 112P on both sides in the gap region 113.

Furthermore, the wiring plug groups 111P and 112P and the dummy plug group 113P are made of tungsten.
This makes it easier to obtain an anchor effect due to the contraction of tungsten with respect to the interlayer insulating film L3, making it easier to balance the stress from the wiring plug groups 111P and 112P on both sides.

Furthermore, since the metal wiring layer M2 is disposed below the dummy plug group 113P, etching is facilitated, and the dummy plug group 113P can be easily manufactured. Moreover, not only the stress caused by the plug group in the gap region 113 but also the stress caused by the metal wiring layer can be relieved.
The metal wiring layers M1, M2, and M3 in the transistor formation regions 111 and 112 are sometimes referred to as the first metal wiring layer, and the metal wiring layer M2 in the gap region 113, i.e., the metal wiring layer M2 located below the dummy plug group 113P, is sometimes referred to as the second metal wiring layer.

FIG. 7 is a schematic diagram showing a cross section of the transistor formation region and the gap region shown in FIG.
As shown in FIG. 7, a thermal sensor 171 is formed on the semiconductor wafer W in the gap region 113 .
As a result, the semiconductor device 100 can control the transistors according to the temperature detected by the thermal element 171 to protect them from thermal destruction in order to avoid destruction due to abnormal increases in junction temperature during operation of the transistors formed in the adjacent transistor formation regions 111, 112.
The wiring of the heat sensitive element 171 is routed in the Y-axis direction of the metal wiring layer M1 for electrical connection.

(Method of manufacturing a semiconductor device)
Next, a method for manufacturing the semiconductor device according to the first embodiment will be described.
The method for manufacturing the semiconductor device 100 according to the first embodiment includes an element forming step and a wiring step.

<Element Formation Process>
In the element forming process, transistors 110 are formed in two transistor forming regions 111 and 112 spaced apart from each other on the semiconductor wafer W. In this embodiment, in addition to the transistors 110, a heat-sensitive element 171 is also formed on the semiconductor wafer W.

Specifically, as shown in FIG. 8, a plurality of transistors 110 in two transistor formation regions 111, 112 are formed by structurally combining a P-type substrate region 1, an N-type well region 2, a gate oxide film 3, a gate electrode 4, and source/drain regions 5.
To form these transistors 110, an N-type well region 2 is formed in a portion of the surface of a P-type substrate region 1, and a gate oxide film 3 is formed on this well region 2. Next, a high concentration of impurities is implanted into the polysilicon film formed on the gate oxide film 3 to form a gate electrode 4. Next, high concentration P-type source/drain regions 5 are formed on the surface of the N-type well region 2 at positions sandwiching the channel region below the gate oxide film 3.
Furthermore, in order to form the thermal element 171, an N-type well region 2, a high-concentration P-type region 6, and a high-concentration N-type region 7 are formed.
These are formed by photolithography, in which a photomask process is performed on the necessary parts.

<Wiring process>
In the wiring process, metal wiring layers M1, M2, M3 are stacked above the transistor 110 and electrically connected to the transistor 110, interlayer insulating films L1, L2, L3, L4 are stacked in the transistor formation regions 111, 112 and the gap region 113 and provide electrical insulation between the metal wiring layers M1, M2, M3, and wiring plug groups 111P, 112P are embedded through the interlayer insulating films L1, L2, L3 and electrically connect the metal wiring layers M1, M2, M3, and are formed by repeatedly stacking and embedding the layers in this order.
In addition, in the wiring process, metal wiring layers, interlayer insulating films, and wiring plug groups are repeatedly formed, and in the gap region 113, dummy plug groups 113P are embedded in interlayer insulating films L1, L2, and L3 lower than the top layer M3 of the metal wiring layers M1, M2, and M3, and an inter-region metal wiring 114 is bridged between the transistor formation regions 111 and 112.

Specifically, first, an interlayer insulating film L1, which is a BPSG (Boro-Phospho Silicate Glass) film, is formed over the entire semiconductor wafer W. Then, via holes V are formed at predetermined positions on the upper surface of the interlayer insulating film L1 by selective etching using photolithography (see FIG. 9), and then a barrier metal film BM, which is a Ti/TiN film, is formed over the entire wafer (see FIG. 10).

Next, tungsten BL is deposited on the barrier metal film BM (see FIG. 11), and then planarized so that the barrier metal film BM remains on the upper surface of the interlayer insulating film L1, thereby forming a tungsten plug in the via hole V (see FIG. 12).

Next, an Al-Cu metal wiring layer M1 is formed on the planarized surface, i.e., on the barrier metal film BM and the upper surface of the plug, and then an anti-reflective film AR, which is a Ti/TiN film, is formed over the entire wafer (see Figure 13).

Then, in the transistor formation regions 111, 112 and the gap region 113, the anti-reflection film AR, the metal wiring layer M1, and the barrier metal film BM are selectively etched and removed by photolithography to form the shape of the metal wiring that wires the transistor 110 and the thermal element 171 (see FIG. 14).

Next, as shown in FIG. 15, after forming an interlayer insulating film L2, which is a BPSG film, over the entire wafer, via holes are provided at predetermined positions on the upper surface of the interlayer insulating film L2 only in the transistor formation regions 111 and 112, and a process for forming tungsten plugs in the via holes is performed as described above. A barrier metal film, a metal wiring layer M2, and an anti-reflective film AR are then formed over the entire wafer, and the wafer is etched into the shape of the metal wiring.

Next, as shown in FIG. 16, an interlayer insulating film L3 which is a BPSG film is formed over the entire wafer, and then via holes are provided at predetermined positions on the upper surface of the interlayer insulating film L3. A barrier metal film, a metal wiring layer M3, and an anti-reflection film AR are formed over the entire wafer, and then etched into the shape of the metal wiring.
The metal wiring layer M3 is formed thick so as to allow a relatively large current to flow therethrough.

Finally, as shown in FIG. 17, an interlayer insulating film L4 made of a BPSG film is formed over the entire wafer, and then a passivation film P made of a silicon nitride film is formed over the entire wafer.
In this manner, the semiconductor device 100 according to the first embodiment can be manufactured by the method for manufacturing the semiconductor device according to the first embodiment.

Thus, the semiconductor device 100 of the first embodiment has transistors 110 formed on a semiconductor wafer W, transistor formation regions 111, 112 that are spaced apart from each other, and a gap region 113 sandwiched between the transistor formation regions 111, 112. This semiconductor device 100 includes a plurality of metal wiring layers M1, M2, and M3 that are disposed above the transistor 110 in the transistor formation regions 111 and 112 and electrically connected to the transistor 110, a plurality of interlayer insulating films L1, L2, L3, and L4 that insulate the plurality of metal wiring layers M1, M2, and M3 and are disposed in the transistor formation regions 111 and 112 and the gap region 113, a plurality of wiring plug groups 111P and 112P that are embedded through the interlayer insulating films L1, L2, and L3 and are electrically connected to the plurality of metal wiring layers M1, M2, and M3, an inter-region metal wiring 114 that is bridged in the gap region 113 between the transistor formation regions 111 and 112, and a dummy plug group 113P that is embedded in the gap region 113 of the interlayer insulating films L1, L2, and L3 that are lower than the top layer M3 of the metal wiring layer.

As a result, in the semiconductor device 100, the structure of the gap region 113 becomes similar to the structure of the transistor formation regions 111, 112, so that stress from the transistor formation regions 111, 112 can be prevented from concentrating on the gap region 113. In addition, due to the anchor effect of the dummy plug group 113P, thermal stress from the transistor formation regions 111, 112 is less likely to concentrate on the metal wiring in the gap region 113.
Therefore, the semiconductor device 100 can suppress the occurrence of stress migration in the inter-region metal wiring 114 disposed between the two transistor formation regions 111 and 112 .

In this embodiment, the number of transistor forming regions is two, but the present invention is not limited to this, and three or more transistor forming regions may be used.
In addition, in this embodiment, the heat-sensitive element is disposed in the gap region between the two transistor forming regions, but this is not limiting, and another element may be disposed, or no element may be disposed at all.

Second Embodiment
The second embodiment is similar to the first embodiment, except that the shape of the dummy wirings DM in the gap region 113 in the first embodiment is changed.
Specifically, as shown in FIG. 18, the shape of the dummy wiring DM2 in the second embodiment is such that it exists only in the vicinity of the dummy plug group 113P and does not extend in the Y-axis direction.
In this way, if the stress on the gap region 113 from the transistor formation regions 111, 112 can be alleviated, the shape of the dummy wiring as well as the structure, size and material of the dummy wiring, and the shape, structure, size and material of the plug can be selected appropriately.

Third Embodiment
The third embodiment is similar to the first embodiment, except that, as shown in FIG. 19 , the two spaced apart transistor formation regions 111, 112 in the first embodiment are replaced by a transistor formation region 115 having a recess, and accordingly, the inside of the recess is formed as a gap region 116.
In this way, if there are not multiple transistor formation regions, but for example, the transistor formation region has a shape having a recess in a planar view, and a gap region is formed, the same effect as that of the semiconductor device 100 of the first embodiment can be obtained.

As described above, a semiconductor device according to an embodiment of the present invention has a semiconductor substrate, a plurality of semiconductor element forming regions each having a semiconductor element formed therein and spaced apart from one another, and a gap region sandwiched between the semiconductor element forming regions. This semiconductor device includes a plurality of metal wiring layers disposed above the semiconductor elements in the semiconductor element forming regions and electrically connected to the semiconductor elements, a plurality of interlayer insulating films that insulate the plurality of metal wiring layers and are disposed in the semiconductor element forming regions and the gap region, a plurality of first plug groups that are embedded through the interlayer insulating films and electrically connected to the plurality of metal wiring layers, inter-region metal wirings that are provided in the gap region between the semiconductor element forming regions, and a second plug group that is embedded in the gap region of an interlayer insulating film that is lower than the uppermost layer of the metal wiring layers.
As a result, the semiconductor device according to one embodiment of the present invention can suppress the occurrence of stress migration in metal wiring arranged between semiconductor element formation regions.

In each embodiment, the semiconductor element is a transistor from the viewpoint of suppressing stress migration, which is likely to occur due to self-heating. However, the semiconductor element is not limited to this and may be, for example, a resistor, a capacitor, a fuse, or the like.
In addition, in each embodiment, the metal wiring layer is three layers and the interlayer insulating film is four layers, but this is not limited thereto, and it is sufficient that there are a plurality of metal wiring layers and a plurality of interlayer insulating films.
Furthermore, in each embodiment, the inter-region metal wiring is the uppermost layer of the metal wiring layer, but this is not limiting.
In each embodiment, one transistor is used, but the present invention is not limited to this, and a plurality of transistors may be provided in parallel.

100 Semiconductor device 110 Transistor 111, 112, 115 Transistor formation region 111P, 112P, 115P Wiring plug group (first plug group)
113, 116 Gap region 113P Dummy plug group (second plug group)
114 Inter-area metal wiring 170 Thermal shutdown circuit 171 Heat-sensitive element
D2a to D2h, D3a, D3b Drain wiring
DM, DM2 Dummy wiring
L1, L2, L3, L4 Interlayer insulating film
M1, M2, M3 metal wiring layer
P passivation film
S2a to S2h, S3a, S3b Source wiring
V Via hole
W: Semiconductor wafer (semiconductor substrate)

Claims (9)

A semiconductor device having a plurality of transistor formation regions, each of which has a transistor formed therein and spaced apart from one another, on a semiconductor substrate, and a gap region sandwiched between the transistor formation regions,
a plurality of metal wiring layers each disposed above the transistor in the transistor forming region and each having a common source wiring and a common drain wiring;
a plurality of interlayer insulating films which insulate the plurality of metal wiring layers from one another and are disposed in the transistor forming region and the gap region;
a first group of plugs that are embedded through the interlayer insulating film and are electrically connected to the metal wiring layers;
an inter-region metal wiring formed in the gap region between the transistor forming regions in the same arrangement pattern as the source wiring and the drain wiring;
a second group of plugs embedded in the gap region of the interlayer insulating film below the uppermost layer of the metal wiring layer and formed in a layout pattern similar to that of the first group of plugs. The semiconductor device according to claim 1, characterized in that, when the semiconductor substrate is viewed in plan, the transistor formation region has a recess, and the gap region is inside the recess. 3. The semiconductor device according to claim 1, wherein a minimum pitch between adjacent plugs in the first plug group is the same as a minimum pitch between adjacent plugs in the second plug group. The semiconductor device according to any one of claims 1 to 3, characterized in that the first plug group and the second plug group are made of tungsten. When the metal wiring layer is a first metal wiring layer,
5. The semiconductor device according to claim 1, further comprising a second metal wiring layer disposed below the second group of plugs. The semiconductor device according to any one of claims 1 to 5, characterized in that the source wiring and the drain wiring are arranged so that the comb-shaped wiring interdigitates. The semiconductor device according to any one of claims 1 to 6, characterized in that a heat-sensitive element is formed on the semiconductor substrate in the gap region. The semiconductor device according to claim 7, characterized in that the heat-sensitive element is electrically connected to the inter-region metal wiring and the second plug group. The semiconductor device according to claim 7 or 8, further comprising a thermal shutdown circuit that turns off the transistor when the temperature detected by the thermal element reaches or exceeds a predetermined temperature.