JP7540166B2 - Transmitting device, receiving device, transmitting method, and receiving method - Google Patents

Description

The present invention relates to a transmitting device, a receiving device, a transmitting method, and a receiving method.

In communications between devices, it may be necessary to transmit information of different natures, such as actual data to be sent to other devices and data related to the device's status information, over a single transmission medium. In such cases, there is generally a large difference between the amount of actual data transmitted and the amount of status information transmitted. For this reason, a high transmission speed is required for transmitting actual data, whereas a slower transmission speed than the actual data may be sufficient for transmitting data related to status information.

One method for transmitting these two pieces of information with different characteristics, as high-speed data with a large amount of data and low-speed data with a small amount of data, is to use a high-speed data transmission medium to transmit low-speed data indicating device status information. In this case, when transmitting device status information, the data to be transmitted and the device status information are transmitted in a time-division multiplexed manner. With this transmission method, a dedicated transmission medium is not required for transmitting device status information, but because the device status information is transmitted in a time-division multiplexed manner using a data transmission medium, the data transmission efficiency of the data to be transmitted deteriorates.

Patent Document 1 discloses a method of transmitting low-speed data using the transmission of a Code Mark Inversion (CMI) code, which converts a 1-bit signal into 2 bits and transmits it. In other words, Patent Document 1 discloses a method of changing 1 bit into 2 bits by changing the original CMI according to the bit value of the low-speed data and transmitting it, thereby superimposing low-speed data on high-speed data. Patent Document 1 also discloses that the receiving side identifies the change rule and restores the low-speed data.

Patent Document 2 discloses that when the number of bits that have changed simultaneously in 64-bit wide data exceeds a predetermined threshold, the data is output with the polarity of each bit reversed, and in other cases, the data is output without reversing the polarity. Patent Document 2 also discloses transmitting the output data, an inversion indication signal indicating whether the number of changed bits has exceeded a threshold, and an error correction code. Patent Document 2 further discloses that when an inversion indication signal in which error code correction has been performed indicates that the number of changed bits has exceeded a threshold, the data that has been error code corrected is output with the polarity of each bit reversed, and in other cases, the data that has been error code corrected is output.

Japanese Unexamined Patent Publication No. 4-252633 JP 2012-100210 A

Incidentally, the inversion instruction signal in Patent Document 2 is information regarding polarity inversion of 64-bit data, and is not related to the above-mentioned high-speed data and low-speed data. The transmission method disclosed in Patent Document 1 attempts to transmit the above-mentioned high-speed data by superimposing the low-speed data, but if an error occurs during data transmission, there is a problem that neither the data originally coded by CMI nor the low-speed data can be restored.
SUMMARY OF THE PRESENT DISCLOSURE An object of the present invention is to provide a transmitting device, a receiving device, a transmitting method, and a receiving method that solve the above problems.

According to a first aspect of the present invention, a transmitting device includes a converter that converts data in a transmission unit, the conversion rules being 2 n conversion rules each corresponding to an n-bit bit string of low-speed data, and the 2 n conversion rules are different from each other, and converts data in a transmission unit, in which high-speed data that is a processing unit for error correction includes an error correction code of the high-speed data, based on the conversion rules corresponding to the n-bit bit string of the low-speed data to generate transmission data.

According to a second aspect of the present invention, a receiving device that receives data transmitted from a transmitting device according to the first aspect includes an inverse converter that inversely converts the received data based on each of 2 n inverse conversion rules for inversely converting the received data corresponding to each of the 2 n conversion rules of the transmitting device, and outputs 2 n inverse conversion data, and an error correction processor that performs error correction processing on each of the 2 n inverse conversion data corresponding to the error correction method used by the transmitting device, and outputs 2 n error correction data after the error correction processing, and outputs the results of the 2 n error correction. -corrector; a determiner that identifies an inverse transformation law corresponding to the inverse transformation data that was error correctable from the results of the 2 n error corrections, and outputs the n-bit bit string corresponding to the identified inverse transformation law as low-speed data based on the correspondence relationship of the inverse transformation law to the 2 n transformation laws that correspond to the n-bit bit strings of the low-speed data in the transmitting device; and a selector that outputs error correction data that has been error corrected using the inverse transformation law identified by the determiner from the 2 n error correction data as high-speed data.

According to a third aspect of the present invention, a transmission method includes a conversion rule for converting data in a transmission unit, the conversion rules being 2 n -th power, each of which corresponds to an n-bit bit string of low-speed data, and the 2 n -th power conversion rules are different from each other, and the data in the transmission unit, in which high-speed data that is a processing unit for error correction contains an error correction code of the high-speed data, is converted based on the conversion rule that corresponds to the n-bit bit string of the low-speed data to generate transmission data.

According to a fourth aspect of the present invention, there is provided a receiving method for receiving data transmitted by the transmitting method according to the third aspect, which inversely transforms received data based on each of 2 n inverse transformation rules for inverse transformation corresponding to each of the 2 n transformation rules of the transmitting method, outputs 2 n inverse transformation data, performs error correction processing on each of the 2 n inverse transformation data corresponding to the error correction method used in the transmitting method, outputs 2 n error correction data after error correction processing, and outputs the results of the 2 n error corrections, identifies the inverse transformation rule corresponding to the inverse transformation data that was error correctable from the results of the 2 n error corrections, outputs the n-bit bit string corresponding to the identified inverse transformation rule as low-speed data based on the correspondence relationship of the inverse transformation rule to the 2 n transformation rules corresponding to each of the n-bit bit strings of low-speed data in the transmitting method, and outputs the error correction data that has been error corrected using the inverse transformation rule identified by the judgment from the 2 n error correction data as high-speed data.

According to the present invention, when transmitting, data of a transmission unit in which the high-speed data, which is the processing unit for error correction, contains an error correction code of the high-speed data, is converted based on a conversion rule corresponding to an n-bit bit string of low-speed data to generate transmission data. Also, when receiving, one of 2 n inverse conversion rules is identified based on the processing result of 2 n error correction data, and an n-bit bit string corresponding to the identified inverse conversion rule is output as low-speed data. Also, error correction data that has been error corrected using the identified inverse conversion rule when receiving is output as high-speed data. This has the effect of making it possible to detect errors when transmitting low-speed data without affecting the transmission of high-speed data, and also making it possible to restore both high-speed data and low-speed data to the extent that error correction is possible even if an error occurs during data transmission.

FIG. 2 is a diagram showing an outline of the configuration of a transmitting device according to an embodiment of the present invention. 1 is a diagram showing an outline of the configuration of a receiving device according to an embodiment of the present invention; FIG. 2 is a diagram illustrating the operation of a transmitting device according to an embodiment of the present invention. FIG. 2 is a diagram illustrating an example of processing of transmission data by a transmitting device according to an embodiment of the present invention. FIG. 2 is a diagram illustrating the operation of a receiving device according to an embodiment of the present invention. FIG. 2 is a diagram illustrating an example of processing of received data by a receiving device according to an embodiment of the present invention. FIG. 13 is a diagram showing an outline of the configuration of a transmitting device according to another embodiment of the present invention. FIG. 11 is a diagram illustrating the operation of a transmitting device according to another embodiment of the present invention. FIG. 13 is a diagram showing an outline of the configuration of a receiving device according to another embodiment of the present invention. FIG. 11 is a diagram illustrating the operation of a receiving device according to another embodiment of the present invention. FIG. 2 is a diagram illustrating an example of the hardware configuration of a transmitting device and a receiving device according to an embodiment of the present invention. FIG. 2 is a diagram showing a minimum configuration of a transmitting device according to an embodiment of the present invention. FIG. 2 is a diagram showing a minimum configuration of a receiving device according to an embodiment of the present invention.

Below, a transmitting device and a receiving device according to one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing an outline of the configuration of a transmitting device 1. In the following, data that is originally transmitted at high speed is referred to as high-speed data, and data that is transmitted slower than high-speed data is referred to as low-speed data.

In FIG. 1, the transmitting device 1 receives high-speed data and low-speed data, converts the data, and generates and transmits the transmission data. The transmitting device 1 includes an error correction coder 11 and a converter 12.

The error correction encoder 11 receives high-speed data as input, and generates an error correction code (ECC: Error Correction Code) for error correction for each processing unit of error correction for the input high-speed data. The error correction encoder 11 also outputs transmission unit data in which the error correction code has been added to the high-speed data, which is the processing unit of error correction.

The converter 12 receives the transmission unit data input from the error correction encoder 11, and also receives the low-speed data input. The converter 12 also encodes the transmission unit data in accordance with the low-speed data to generate transmission data. The transmitting device 1 outputs the generated transmission data.

Figure 2 is a diagram showing the outline of the configuration of the receiving device 2. By inputting and processing the received data, the receiving device 2 reconstructs and outputs the high-speed data and low-speed data from the transmitting device 1. The receiving device 2 includes an inverse converter 21, an error corrector 22, a determiner 23, and a selector 24.

The inverse converter 21 receives the transmission data, performs an inverse conversion process to the conversion process performed by the converter 12 of the transmitting device 1, and outputs the data after the conversion process.

The error corrector 22 includes error corrector 0 22-0 and error corrector 1 22-1. Error corrector 0 22-0 and error corrector 1 22-1 have the same functions. Error corrector 0 22-0 and error corrector 1 22-1 delete the error correction code from the input data, and perform error detection and error correction processing using the error correction code, and output the processed data. Error corrector 0 22-0 and error corrector 1 22-1 also output the results of the error correction processing, such as whether an error was detected and corrected or not. Error corrector 0 22-0 performs error correction processing on the received data. Meanwhile, error corrector 1 22-1 performs error correction processing on the output data from the reverse converter 21.

The determiner 23 inputs the results of the error correction process from the error corrector 0 22-0 and the error corrector 1 22-1. The determiner 23 then determines whether the bit value of the low-speed data is "0" or "1" based on the error correction results, and outputs this as the low-speed data. The determiner 23 also outputs the determination result to the selector 24.

Based on the result of the determination by the determiner 23, the selector 24 outputs the output from either the error corrector 0 22-0 or the error corrector 1 22-1 as high-speed data.

The operation of the transmitting device 1 will be explained in more detail with reference to the figures. FIG. 3 is a diagram showing the operation of the transmitting device 1. In the explanation using FIG. 3, an example of data processing by the transmitting device 1 shown in FIG. 4 will be explained.

As an example of the data to be processed, as shown in FIG. 4, the high-speed data is structured as 8 bytes from B0 to B7, and these 8 bytes are used as a processing unit for error correction.
The error correction code is for 1-byte error correction and 2-byte error detection, and the error correction code for error correction is 3 bytes from C0 to C2.
When the converter 12 of the transmitting device 1 transmits "0" as the low-speed data, it outputs as the transmission data data in which all bits of the output from the error correction encoder 11 are not inverted. When the converter 12 transmits "1" as the low-speed data, it outputs as the transmission data data in which all bits of the output from the error correction encoder 11 are not inverted.
In FIG. 4, the transmission data (B0, B1, B2, . . . B7, C0, C1, C2) are non-inverted.

indicates inversion.

When high-speed data and low-speed data are input to the transmitting device 1, the transmitting device 1 starts processing.

The error correction encoder 11 receives input of high-speed data that is the processing unit of the correction encoding, and generates an error correction code according to the error correction and error detection rules of the error correction code. The error correction encoder 11 also adds an error correction code to the high-speed data that is the processing unit, and outputs it as data for a transmission unit (step S11). The data for a transmission unit from the error correction encoder 11 is output to the converter 12.

In the example of FIG. 4, the error correction encoder 11 receives an input of 8 bytes of high-speed data (B0, B1, B2, ..., B7) which is the processing unit of the correction encoding. The error correction encoder 11 generates a 3-byte error correction code (C0, C1, C2) for the input high-speed data according to the error correction code rule of 1-byte error correction and 2-byte error detection. The error correction encoder 11 also adds a 3-byte error correction code to the 8-byte high-speed data, and outputs 11 bytes of data as the transmission unit data (B0, B1, B2, ..., B7, C0, C1, C2).

The converter 12 receives the input of the low-speed data to be transmitted and determines whether the bit value of the input low-speed data is "1" (step S12).

If the bit value of the low-speed data is "1" (step S12: YES), the converter 12 inverts all bits of the data in the transmission unit from the error correction encoder 11 (step S13). The converter 12 also generates the data in the transmission unit in which all bits have been inverted as transmission data. The transmitting device 1 transmits the generated transmission data (step S14).

On the other hand, if the bit value of the low-speed data is not "1" (step S12: NO), the converter 12 generates the data of the transmission unit from the error correction encoder 11 as transmission data without modification. Then, the transmitting device 1 transmits the transmission data generated by the converter 12 (step S14). That is, the converter 12 does not process the data of the transmission unit from the error correction encoder 11 (no inversion of all bits), and uses the data of the transmission unit from the error correction encoder 11 as transmission data without modification.

In the example of Figure 4, if the bit value of the low-speed data is "1",

The 11 bytes of inverted data are output from the transmitting device 1 as transmission data.

In addition, if the bit value of the low-speed data is not "1", 11 bytes of non-inverted data (B0, B1, B2, ..., B7, C0, C1, C2) are output as transmission data from the transmitting device 1.

The transmitting device 1 determines whether there is further data to be transmitted, and if there is data to be transmitted (step S15: YES), the transmitting device 1 returns to step S11. On the other hand, if there is no data to be transmitted (step S15: NO), the transmitting device 1 ends the transmission process.

As explained above, when transmitting a bit "0" as low-speed data, the transmitting device 1 transmits the transmission unit data non-inverted, and when transmitting a bit "1" as low-speed data, it inverts and transmits the transmission unit data. On the receiving side, it is possible to detect low-speed data by identifying whether the received data is non-inverted or inverted.

In the example of FIG. 4, the transmitting device 1 can transmit 1 bit of low-speed data for every 8 bytes of high-speed data. If the transmission speed of the low-speed data can be slower than the transmission speed of the transmission data, conversion processing of the high-speed data that serves as the processing unit for correction encoding may be performed according to a predetermined transmission rule. For example, as an example of a predetermined transmission rule, conversion processing of the high-speed data that serves as the processing unit for correction encoding may be performed in the same bit value state until a change occurs in the transmission bit of the low-speed data. In this case, the transmitting device 1 and the receiving device 2 may exchange transmission rules for high-speed data and low-speed data, such as information regarding the transmission rates of the high-speed data and low-speed data, or the ratio of the transmission rates of the high-speed data and low-speed data, before starting data transmission and reception.

As an example of a predetermined transmission rule, when converting high-speed data, which is the processing unit for correction coding, with the same bit value until the transmission bit of the low-speed data changes, an example is as follows. When transmitting 1 bit of low-speed data while processing 16 bytes of high-speed data with 8 bytes of high-speed data, the converter 12 processes the 1 bit of low-speed data with the same value while processing the 8 bytes of high-speed data, which is the processing unit for correction coding, twice.

Next, the operation of the receiving device 2 will be described in more detail with reference to the drawings. FIG. 5 is a diagram showing the operation of the receiving device 2. In the explanation using FIG. 5, an example of data processing by the receiving device 2 shown in FIG. 6 will be described. In the example in FIG. 6, as in FIG. 4, the high-speed data serving as the processing unit for error correction is 8 bytes, and the code for error correction is 3 bytes. Also, in the example in FIG. 6, the data from the transmitting device 1 is processed as transmission data in units of 11 bytes (8 bytes + 3 bytes). Also, in FIG. 6, an example is shown in which transmission data in units of 11 bytes is sent from the transmitting device from time t ₀ to time t ₁₁ .

The receiving device 2 starts processing by receiving data from the transmitting device 1.

The receiving device 2 branches the received data into two systems. The receiving device 2 processes the received data of the first system, expecting that the bit value of the low-speed data is "0", and processes the received data of the second system, expecting that the bit value of the low-speed data is "1". In other words, the received data of the second system is input to the inverse converter 21, which processes the received data by inverting all bits of the input received data, and outputs it as inversely converted data (step S21).

The first system of received data is a system that expects the bit value of the low-speed data to be "0". When the bit value of the low-speed data is "0", the high-speed data is transmitted non-inverted, so the receiver 2 does not invert the received data, that is, it inputs the received data directly to the error corrector 0.22-0. The error corrector 0.22-0 uses data corresponding to the error correction code contained in the received data to check whether there is an error, and corrects the error if it is possible (step S22).

In Figure 6, error correction processing is performed on the 11 bytes of received data using a 3-byte error correction code, the error correction code is removed, and the remaining 8 bytes of data are output as error corrected data. In the example in Figure 6, the 8 bytes of data output from error corrector 0.22-0 (ECC0) are shown as (D0, D1, D2, ... D6, D7).

Error corrector 0.22-0 outputs the error correction data to selector 24. Error corrector 0.22-0 also outputs error information indicating whether the error was correctable or uncorrectable to determiner 23. Note that "correctable" includes cases where it has been confirmed that error correction is unnecessary by using an error correction code, and cases where the error is correctable and has been corrected. "Uncorrectable" refers to cases where the error cannot be corrected by using an error correction code.

The inversely transformed data output from the inverse transformer 21 is input to the error corrector 1 22-1. The error corrector 1 22-1 checks whether there is an error using data corresponding to the error correction code contained in the inversely transformed data, and corrects the error if it is possible (step S23).

In Figure 6, error correction processing is performed on the 11 bytes of inversely converted data using a 3-byte error correction code, the error correction code is removed, and the remaining 8 bytes of data are output as error corrected data. In the example of Figure 6, the 8 bytes of data output from the error corrector 1.22-1 (ECC1) are shown as (E0, E1, E2, ... E6, E7).

The error corrector 1 22-1 also outputs the error correction data to the selector 24. The error corrector 1 22-1 also outputs error information indicating whether the error was correctable or uncorrectable to the determiner 23.

Based on the error information from error corrector 0 22-0 and error corrector 1 22-1, determiner 23 identifies which error corrector is on the side where no correctable errors have occurred, and outputs information indicating the error corrector on the correctable side to selector 24. Based on the identification result, determiner 23 also outputs the bit value of the low-speed data (step S24). That is, if error corrector 0 22-0 was able to correct the error, determiner 23 outputs "0" as the bit value of the low-speed data, and if error corrector 1 22-1 was able to correct the error, determiner 23 outputs "1" as the bit value of the low-speed data.

6, in the error correction data from the error corrector 0.22-0 (ECC0), 8 bytes of error correction data that could not be corrected are shown in black, and 8 bytes of error correction data where there was no error or where an error was detected but was corrected are shown in white.
Similarly, in the error correction data from the error corrector 1 22-1 (ECC1), 8 bytes of error correction data that could not be corrected are shown in black, and 8 bytes of error correction data in the cases where there was no error or where an error was detected but was corrected are shown in white.

At times t0 and t1 in FIG. 6, the error corrector 0/22-0 was able to correct the error, so the determiner 23 outputs "0" as the bit value of the low-speed data at times t0 and t1. From time t2 to t6, the error corrector 1/22-1 was able to correct the error, so the determiner 23 outputs "1" as the bit value of the low-speed data at times t2 to t6. From time t7 to t11, the error corrector 0/22-0 was able to correct the error, so the determiner 23 outputs "0" as the bit value of the low-speed data at times t7 to t11.

The selector 24 outputs the input from the error corrector that was correctable as high-speed data based on the information on the occurrence status of correctable errors from the determiner (step S25).

The receiving device 2 determines whether further data has been received (step S26), and if no data has been received (step S26: NO), ends the process. On the other hand, if data has been received (step S26: YES), the receiving device 2 returns to step S21 to process the next received data.

In this manner, the receiving device 2 outputs high-speed data and low-speed data.

In FIG. 6, the operation of the receiving device 2 is described as an example in which the transmitting device 1 transmits 8 bytes of high-speed data and 1 bit of low-speed data. If the transmission speed of the low-speed data can be slower than the transmission speed of the transmitted data, the determiner 23 of the receiving device 2 may output bits of the low-speed data according to a predetermined transmission rule. In this case, the transmitting device 1 and the receiving device 2 may exchange transmission rules, such as information regarding the transmission rates of the high-speed data and the low-speed data, or the ratio of the transmission rates of the high-speed data and the low-speed data, before starting to transmit and receive data.

In Figure 6, the operation of the receiving device 2 is described when no errors occur during transmission, or when an error occurs during transmission but is within the range of error correction capabilities, i.e., a 1-byte error.

If an error of two or more bytes occurs during transmission, it becomes an error that cannot be corrected by either error corrector. In this case, the determiner 23 outputs information to the selector 24 to output data from either side as high-speed data, so that high-speed data is obtained. The determiner 23 also outputs either low-speed data. The high-speed data and low-speed data output from the receiving device 2 are erroneous data, but this is not due to the transmission of low-speed data, but is an error that was bound to occur and exceeds the correction capability of the error corrector. Such errors can be processed by a downstream circuit (not shown) included in the receiving device 2, which can process the error data in a normal receiving device, such as processing a retransmission request.

In the transmitting device 1 and receiving device 2 shown in Figures 1 and 2, it has been explained that when the bit value of the low-speed data is "0", all bits of the transmitted data are not inverted, and when the bit value is "1", all bits of the transmitted data are inverted. This is not limited to this, and for example, when the bit value of the low-speed data is "0", all bits of the transmitted data are inverted, and when the bit value is "1", all bits of the transmitted data are non-inverted.

Furthermore, when the bit value of the low-speed data is "0", "conversion rule 0" for converting data may be applied to the transmission data, and when the bit value is "1", "conversion rule 1" for converting data may be applied to the transmission data. In this case, "conversion rule 0" and "conversion rule 1" are different conversion rules. In this case, the converter 12 of the transmitting device 1 performs data conversion processing using "conversion rule 0" or "conversion rule 1" on the data output from the error correction coder 11 according to the bit value of the low-speed data. In this case, the receiving device 2 includes an "inverse converter 0" that performs an inverse conversion of "conversion rule 0" on the received data, and an "inverse converter 1" that performs an inverse conversion of "conversion rule 0" on the received data. Then, the data from "inverse converter 0" is input to the error corrector 0 22-0 for processing, and the data from "inverse converter 1" is input to the error corrector 1 22-1 for processing.

Furthermore, the receiving device 2 has been described as having two error correctors 22, error corrector 0 22-0 and error corrector 1 22-1. However, if the processing speed of the receiving device 2 is sufficiently fast compared to the receiving transmission speed, the error corrector 22 may have a single error corrector. In this case, the error corrector 22 may be configured to process the two systems of transmission data alternately and output the processing results.

In the above embodiment, the conversion process performed on high-speed data is described as being changed based on one bit of low-speed data. This is not limited to this, and when based on n bits of low-speed data ("n" is an integer), processing may be performed using 2n conversion rules. In other words, data containing error correction codes of high-speed data may be converted using a conversion rule corresponding to an n-bit bit string. In this case, the receiving device 2 may also process using 2n inverse converters that perform processing based on 2n inverse conversion rules corresponding to the 2n conversion rules, respectively.

The following describes a transmitting device 1 and a receiving device 2 that use a conversion process based on n bits ("n" is an integer) of low-speed data.

In FIG. 7, the transmitting device 1 receives high-speed data and low-speed data as input, converts the data based on n bits of the low-speed data, and generates transmission data. The transmitting device 1 includes an error correction coder 11 and a converter 12.

The error correction encoder 11 is the same as the error correction encoder 11 described in Figure 1.

Converter 12 receives transmission unit data as input from error correction encoder 11, and also receives low-speed data as input. Converter 12 then encodes the transmission unit data in accordance with the n-bit value of the low-speed data to generate transmission data. Converter 12 includes switch 12a and 2 n converters: converter 1 12-1, converter 2 12-2, ..., converter 2 ⁿ 12-2 ⁿ . Each converter has a different conversion rule.

Switch 12a performs a process of inputting data output from error correction encoder 11 to one of the converters based on the value of n bits of the low-speed data. For example, if n bits is 2 bits, converter 12 has four converters, which is 2^2. Switch 12a also performs a process of connecting (selecting) with error correction encoder 11 to converter 1 12-1 when the value of the 2 bits is "00", to converter 2 12-2 when the value is "01", to converter 3 12-3 when the value is "10", and to converter 4 12-4 when the value is "11".

The operation of the transmitting device 1 shown in FIG. 7 will be described in more detail with reference to the diagram. FIG. 8 is a diagram showing the operation of the transmitting device 1 shown in FIG. 7.

The error correction encoder 11 receives an input of high-speed data that is the processing unit of the correction encoding, and generates an error correction code according to the error correction and error detection rules of the error correction code. The error correction encoder 11 also adds an error correction code to the high-speed data that is the processing unit, and outputs it as data for a transmission unit (step S31). The data for the transmission unit from the error correction encoder 11 is output to the converter 12.

The converter 12 receives the input of the low-speed data to be transmitted, and the switch 12a of the converter 12 connects (selects) the converter so that the converter corresponding to the n-bit bit string of the input low-speed data is connected to the error correction encoder 11 (step S32).

The converter that is connected (selected) and receives input from the error correction coder 11 converts the data in transmission units from the error correction coder 11 according to the conversion rule assigned to that converter, to generate transmission data (step S33).

The transmitting device 1 outputs the output data from the converter 12 as transmission data (step S34).

The transmitting device 1 determines whether there is further data to be transmitted, and if there is data to be transmitted (step S35: YES), the transmitting device 1 returns to step S31. If there is no data to be transmitted (step S35: NO), the transmitting device 1 ends the transmission process.

As explained above, the transmitting device 1 converts high-speed data with an error correction code based on n bits of low-speed data. This makes it possible to send low-speed data even if the transmission speed of the low-speed data is n times faster than that of the transmitting device 1 shown in Figure 1.

For example, the transmitting device 1 can transmit n bits of low-speed data for every 8-byte unit of high-speed data to which an error correction code is added. If the transmission speed of the low-speed data can be slower than the transmission speed of the transmitted data, conversion processing of the high-speed data that serves as the processing unit for correction coding may be performed according to a predetermined transmission rule. In this case, the transmitting device 1 and the receiving device 2 may exchange transmission rules, such as information regarding the transmission rates of the high-speed data and the low-speed data, or the ratio of the transmission rates of the high-speed data and the low-speed data, before starting transmission and reception of data.

Figure 9 shows the outline of the configuration of a receiving device 2 that reconstructs low-speed data in units of n bits. The receiving device 2 inputs and processes the received data, and sequentially reconstructs and outputs high-speed data and n-bit low-speed data. The receiving device 2 includes an inverse converter 21, an error corrector 22, a determiner 23, and a selector 24.

The inverse converter 21 includes 2n inverse converters 1-21-1, 21-2, ..., and ²ⁿ -21-2n. The 2n inverse converters are assigned ²ⁿ inverse conversion rules for performing inverse conversion corresponding to the 2n conversion rules of the transmitting device 1. The 2n inverse converters perform inverse conversion processing of the received data according to the assigned inverse conversion rules. The inverse converter 21 receives input of the received data, and outputs 2n inverse conversion data that have been subjected to different inverse conversions.

The error corrector 22 includes 2^2 error correctors 1-22-1, 2-2-2, ..., ²ⁿ - ^22-2n . Each of the 2^n error correctors has the same function. The 2^2 error correctors are connected to 2^n inverse converters 1-21-1, 2-21-2, ..., ²ⁿ - ^21-2n . Each of the 2^n error correctors deletes the error correction code from the input data, performs error detection and error correction processing using the error correction code, and outputs the processed data. In addition, each of the 2^n error correctors also outputs information regarding the results of the error correction processing, such as whether error detection and error correction are possible, or whether error detection and correction are impossible.

The determiner 23 inputs information on the results of the error correction process from the 2 n error correctors, determines an n-bit bit string of the low-speed data from the error correction results, and outputs the low-speed data.

The selector 24 outputs one of the outputs from the 2 n error correctors as high-speed data based on the result of the judgment by the judger 23.

Next, the operation of the receiving device 2 shown in FIG. 9 will be described in more detail with reference to the diagram. FIG. 10 is a diagram showing the operation of the receiving device 2 shown in FIG. 9.

The receiving device 2 starts processing when it receives the reception data from the transmitting device 1.

The receiving device 2 branches the received data into 2 n systems and inputs them to 2 n inverse converters. The 2 n inverse converters that receive the inputs perform inverse conversion processing on the input received data based on the inverse conversion rules assigned to each inverse converter, and output the data as inverse conversion data (step S41). Each inverse converter also outputs the inverse conversion data to the error corrector connected to it.

The 2 n error correctors that receive the inverse transformation data check whether there is an error using data corresponding to the error correction code contained in the inverse transformation data, and correct the error if possible (step S42).

The determiner 23 identifies the error corrector that was able to correct the error based on information about the results of correcting 2 to the power of n errors from each error corrector, and outputs information indicating the error corrector that was able to correct the error to the selector 24. The determiner 23 also outputs an n-bit bit string of low-speed data based on the identification result (step S43). That is, the determiner 23 outputs an n-bit bit string corresponding to the identified error corrector as low-speed data.

The selector 24 outputs the input from the error corrector that was correctable based on the identification result from the determiner as high-speed data (step S44).

For example, if n bits is 2 bits, in the converter 12 of the transmitting device 1, if the value of the 2 bits is "00", converter 1 12-1 is selected, if the value is "01", converter 2 12-2 is selected, if the value is "10", converter 3 12-3 is selected, and if the value is "11", converter 4 12-4 is selected. The inverse converter 21 of the receiving device 2 is provided with four inverse converters corresponding to the respective converters: inverse converter 1 21-1, inverse converter 2 21-2, inverse converter 3 21-3, and inverse converter 4 21-4. In such a case, when the 2-bit value of the low-speed data transmitted from the transmitting device 1 is "01", the error corrector 2 22-2 outputs information that "correction is possible". As a result, the determiner 23 outputs "01" as the low-speed data (step S43). Furthermore, based on the result of the determiner 23 identifying the error corrector 2 22-2 as an error corrector that was "correctable," the selector 24 outputs the data output by the error corrector 2 22-2 as high-speed data (S44).

The receiving device 2 determines whether further data has been received (step S45), and if no data has been received (step S45: NO), ends the process. On the other hand, if data has been received (step S45: YES), the receiving device 2 returns to step S41 to process the next received data.

In this way, the receiving device 2 outputs high-speed data and low-speed data in response to the input of received data.

The receiving device 2 shown in FIG. 9 has been described as an example of the operation of the receiving device 2 when the transmitting device 1 shown in FIG. 7 transmits n bits of low-speed data in response to 8 bytes of high-speed data. If the transmission speed of the low-speed data can be slower than the transmission speed of the transmitted data, the determiner 23 of the receiving device 2 may output bits of low-speed data according to a predetermined transmission rule. In this case, the transmitting device 1 and the receiving device 2 may exchange transmission rules, such as information regarding the transmission rates of the high-speed data and the low-speed data, or the ratio of the transmission rates of the high-speed data and the low-speed data, before starting data transmission and reception.

9, the receiving device 2 has been described as having an error corrector 22 that includes 2 n error correctors 1 22-1, 2 22-2, and 2 ⁿ 22-2 ⁿ . However, if the processing speed of the receiving device 2 is sufficiently fast compared to the transmission speed of the transmission data from the transmitting device 1, the error corrector 22 may include fewer than 2 n error correctors. In this case, the fewer than 2 n error correctors in the error corrector 22 may process the output from one or more reverse converters.

In the explanation of the operation of the receiving device 2 using Figure 10, the operation of the receiving device 2 was explained in the case where no errors occur during transmission, or where even if an error occurs during transmission, it is within the range of error correction capabilities, i.e., a 1-byte error.

When an error of 2 bytes or more occurs during transmission in the operation of the receiving device 2 using FIG. 10, it becomes an error that cannot be corrected by any of the error correctors. In this case, the determiner 23 outputs information to the selector 24 to output the data of one of the error correctors as high-speed data, thereby obtaining high-speed data. The determiner 23 also outputs any of the n-bit data as low-speed data. The high-speed data and low-speed data output from the receiving device 2 are erroneous data, but this is not due to the transmission of low-speed data, but is an error that was bound to occur and exceeded the correction capability of the error corrector. Such errors can be processed by a later circuit included in the receiving device 2 (not shown), which processes the error data in a normal receiving device, such as processing a retransmission request.

In the above embodiment, the error correction code is described as an example of 1-byte error correction and 2-byte error detection, but this is not limited to this. For example, the error correction code may be any code that is capable of correcting errors, such as a convolutional code.

When considering the processing speed, it is preferable that each processor constituting the transmitting device 1 and the receiving device 2 is configured with a dedicated circuit. However, the functions of the transmitting device 1 and the receiving device 2 may be realized by software using a general-purpose processor, memory, bus, etc. that is sufficiently fast for the data to be transmitted and received. An example of the hardware configuration of the transmitting device 1 and the receiving device 2 in such a case is shown in Figure 11.

Figure 11 illustrates a computer 9 for implementing the transmitting device 1 and the receiving device 2, as well as a network 81. The computer 9 may be any computer. For example, the computer 9 may be a personal computer (PC), a server machine, or a tablet terminal. The computer 9 may be a dedicated computer designed to implement the transmitting device 1 and the receiving device 2, or may be a general-purpose computer.

The computer 9 includes a bus 91, a processor 92, a memory 93, a storage device 94, an input/output interface 95, and an external interface 96. The bus 91 is a data transmission path for the processor 92, the memory 93, the storage device 94, the input/output interface 95, and the external interface 96, which also serves as a network interface, to transmit and receive data to and from each other. However, the method of connecting the processor 92 and the like to each other is not limited to bus connection. The processor 92 is various processors such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or an FPGA (Field-Programmable Gate Array). The memory 93 is a main storage device realized using a RAM (Random Access Memory) or the like. The storage device 94 is an auxiliary storage device realized using a hard disk, an SSD (Solid State Drive), a memory card, or a ROM (Read Only Memory), or the like.

The input/output interface 95 is an interface for connecting the computer 9 to an input/output device. For example, the input/output interface 95 is connected to an input device such as a keyboard and an output device such as a display device.

The external interface 96 is an interface for connecting the computer 9 to a network 81 or the like. FIG. 11 illustrates a case in which the external interface 96 is a network interface and is connected to the network 81, but this is not limited to this. In the illustrated example, the network is, for example, a LAN (Local Area Network) or a WAN (Wide Area Network). The method for connecting the external interface 96 to the network may be a wireless connection or a wired connection.

The external interface 96 may be a network interface or an interface for directly connecting an external device. For example, it may be connected to other devices via a Universal Serial Bus (USB) or IEEE 1394.

The storage device 94 stores program modules that realize each processing unit of the transmitting device 1 and the receiving device 2. The processor 92 reads each of these program modules into the memory 93 and executes them to realize the function corresponding to each program module.

Figure 12 is a diagram showing the minimum configuration of the transmitting device 1. The transmitting device 1 includes a converter 12. The converter 12 includes conversion rules for converting the data of a transmission unit, which are 2 n conversion rules corresponding to the n-bit bit strings of the low-speed data, and each of the 2 n conversion rules is different. The converter 12 converts the data of a transmission unit, in which the high-speed data serving as the processing unit for error correction contains an error correction code of the high-speed data, based on the conversion rules corresponding to the n-bit bit strings of the low-speed data, to generate transmission data.

Fig. 13 is a diagram showing a minimum configuration of a receiving device 2 that receives reception data from the transmitting device 1 shown in Fig. 12. The receiving device 2 includes an inverse converter 21, an error corrector 22, a determiner 23, and a selector 24.
The inverse transformer 21 inverse transforms the received data based on each of 2n inverse transformation rules for performing inverse transformation corresponding to the 2n transformation rules of the transmitting device 1, and outputs 2n inverse transformed data.
The error corrector 22 performs error correction processing on each of the 2 n inverse transformed data corresponding to the error correction method used in the transmitting device 1, and outputs the 2 n error corrected data after the error correction processing, as well as the results regarding the 2 n error correction.
The determiner 23 specifies an inverse transformation rule corresponding to the inverse transformation data for which error correction processing was possible, based on the results of the 2 n error corrections. The determiner 23 outputs an n-bit bit string corresponding to the specified inverse transformation rule as low-speed data, based on the correspondence relationship of the inverse transformation rule to the 2 n transformation rules corresponding to each n-bit bit string of the low-speed data in the transmitting device 1.
The selector 24 selects the error correction data that has been subjected to error correction processing according to the inverse transformation rule specified by the determiner 23 from the 2 n error correction data, and outputs the error correction data as high-speed data.

The above describes an example in which the transmitting device 1 and the receiving device 2 are applied to the exemplary embodiment described above. However, the technical scope of the transmitting device 1 and the receiving device 2 is not limited to the scope described in each of the above-mentioned embodiments. It is clear to those skilled in the art that various modifications or improvements can be made to such embodiments. In such cases, new embodiments incorporating such modifications or improvements may also be included in the technical scope of the transmitting device 1 and the receiving device 2.

1: Transmitter 11: Error correction encoder 12: Converter 2: Receiving device 21: Inverse converter 22: Error corrector 22-0: Error corrector 0
22-1...Error corrector 1
23: Deciding device 24: Selecting device

Claims (9)

a converter for converting data in a transmission unit, the conversion rules being 2 n in number corresponding to n-bit bit strings of low-speed data, and the 2 n conversion rules being different from one another, the converter converting data in a transmission unit, in which high-speed data serving as a processing unit for error correction includes an error correction code of the high-speed data, based on the conversion rules corresponding to the n-bit bit string of the low-speed data to generate transmission data;
exchanging, with a receiving device, a transmission rule for the high-speed data and the low-speed data, which is related to a transmission rate of the high-speed data and the low-speed data, before starting transmission of the transmission data;
Transmitting device. The transmitting device according to claim 1 , wherein in the converter, the n bits are 1 bit, and the converter comprises, as the conversion rules, two conversion rules corresponding to a bit value of the 1 bit. In the converter, one of the two conversion rules is a bit inversion of all bits of the data of the transmission unit, and the other of the two conversion rules is a bit non-inversion of all bits of the data of the transmission unit.
The transmitting device according to claim 2. The error correction coder generates data in units of transmission, the data including an error correction code for the high-speed data, the high-speed data being a unit of error correction processing.
The transmitting device according to claim 1 , wherein the converter generates the transmission data from the data of the transmission unit generated by the error correction encoder. A receiving device for receiving data transmitted from the transmitting device according to claim 1,
an inverse converter that inversely converts received data based on 2 n inverse conversion rules for performing inverse conversion corresponding to the 2 n conversion rules of the transmitting device, and outputs 2 n inverse conversion data;
an error corrector that performs an error correction process on each of the 2 n inverse transformed data in accordance with an error correction method used in the transmitting device, outputs the 2 n error corrected data after the error correction process, and outputs a result of the 2 n error correction;
a decision unit which, based on the result of the 2 n error correction, identifies an inverse transformation law corresponding to the inverse transformation data which has been error-corrected, and outputs the n-bit bit string corresponding to the identified inverse transformation law as low-speed data based on a correspondence relationship between the inverse transformation law and the 2 n transformation laws which respectively correspond to the n-bit bit string of the low-speed data in the transmitting device;
a selector for selecting the error correction data that has been subjected to error correction processing using the inverse transformation rule specified by the determiner, and outputting the error correction data as high-speed data;
Equipped with
exchanging, with a transmitting device, a transmission rule for the high-speed data and the low-speed data, which is related to a transmission rate of the high-speed data and the low-speed data, before starting to receive the transmitted data;
Receiving device. A receiving device for receiving data transmitted from the transmitting device according to claim 2,
an inverse converter that inversely converts received data based on two inverse conversion rules for inverse conversion corresponding to the two conversion rules of the transmitting device, respectively, and outputs two inverse conversion data;
an error corrector that performs an error correction process on each of the two inverse transformed data in accordance with an error correction method used in the transmitting device, and outputs two pieces of error corrected data after the error correction process, and outputs a result of the two error corrections;
a determiner for determining an inverse transformation rule corresponding to the inverse transformation data for which error correction processing has been possible based on the results of the two error corrections, and outputting a bit value corresponding to the determined inverse transformation rule as the low-speed data based on a correspondence relationship between the inverse transformation rule and two transformation rules each corresponding to a bit value of one bit of the low-speed data in the transmitting device;
a selector for selecting the error correction data that has been subjected to error correction processing based on the inverse transformation rule specified by the determiner, and outputting the error correction data as high-speed data;
A receiving device comprising: A receiving device for receiving data transmitted from the transmitting device according to claim 3,
an inverse converter that performs bit inversion of received data;
an error corrector that performs an error correction process corresponding to an error correction method used in the transmitting device on the received data and the received data on which all bits have been inverted, and outputs two pieces of error-corrected data after the error correction process, and outputs results related to the two error corrections;
a determiner for identifying the error-corrected data that has not been subjected to error correction or that has been subjected to error correction from the results of the two error corrections, and outputting a bit value corresponding to the inverse conversion law of the identified error-corrected data as low-speed data based on a correspondence relationship between an inverse conversion law and two conversion laws, namely, full bit inversion and full bit non-inversion, corresponding to a bit value of one bit of the low-speed data in the transmitting device;
a selector for outputting the error correction data identified by the determiner as high-speed data from the two error correction data;
A receiving device comprising: A conversion rule for converting data in a transmission unit includes 2 n conversion rules each corresponding to an n-bit bit string of low-speed data, and the 2 n conversion rules are different from each other;
A transmission method for generating transmission data by converting data of a transmission unit, the data being high-speed data serving as a processing unit for error correction and including an error correction code of the high-speed data, based on the conversion rule corresponding to a bit string of n bits of the low-speed data, the method comprising:
exchanging, with a receiving device, a transmission rule for the high-speed data and the low-speed data, which is related to a transmission rate of the high-speed data and the low-speed data, before starting transmission of the transmission data;
Transmission method. A receiving method for receiving data transmitted by the transmitting method according to claim 8, comprising the steps of:
inversely transforming the received data based on 2n inverse transformation rules for performing inverse transformation corresponding to the 2n transformation rules of the transmission method, respectively, and outputting 2n inverse transformed data;
performing an error correction process corresponding to the error correction method used in the transmission method on each of the 2 n inverse transformed data, outputting the 2 n error corrected data after the error correction process, and outputting the results of the 2 n error correction;
From the result of the 2 n error correction, an inverse transformation rule corresponding to the inverse transformation data for which error correction processing was possible is identified, and based on a correspondence relationship of the inverse transformation rule to the 2 n transformation rules corresponding to each n-bit bit string of the low-speed data in the transmission method, the n-bit bit string corresponding to the identified inverse transformation rule is output as low-speed data;
outputting error-corrected data that has been subjected to error correction processing based on the specified inverse transformation rule from the 2 n error-corrected data as high-speed data;
A receiving method, comprising:
exchanging, with a transmitting device, a transmission rule for the high-speed data and the low-speed data, which is related to a transmission rate of the high-speed data and the low-speed data, before starting to receive the transmitted data;
Receiving method.

Images