JP7543159B2 - Solid-state imaging device - Google Patents

Description

The present invention relates to a solid-state imaging device that performs global shutter operation corresponding to moving images.

Various solid-state imaging devices using global shutter pixels have been developed in the past. A related technology is the invention disclosed in Patent Document 1 below.

Patent Document 1 relates to a solid-state imaging device used when multiple pixels arranged in a diagonal direction share an element such as an FD (floating diffusion). The solid-state imaging device includes a pixel array in which shared pixel pairs, each consisting of multiple pixels that share at least an FD, are arranged in a diagonal direction, and vertical signal lines that are wired in a zigzag pattern to avoid the photoelectric conversion units of each pixel that makes up the shared pixel pair, and the vertical signal lines are arranged so that they are close to other vertical signal lines at the connection points with the shared pixel pairs.

International Publication No. 2018/173793

In the solid-state imaging device disclosed in the above-mentioned Patent Document 1, the pixel pairs that share two pixels are tilted diagonally and then shifted by 1/2 pixel pitch in both the horizontal and vertical directions to improve resolution. Furthermore, by crossing the arrangement of two adjacent signal output lines, a pixel arrangement that is symmetrical and does not impair sensitivity characteristics is realized. However, because the shared pixel pairs are diagonal, there are problems such as a large number of readout lines and a low frame rate.

One aspect of the present invention aims to realize a solid-state imaging device that reduces the number of readout lines and enables a high frame rate.

In order to solve the above problem, a solid-state imaging device according to one embodiment of the present invention is a solid-state imaging device in which a plurality of 2×2 pixel units in which global shutter shared pixels are arranged adjacent to each other are arranged, and the adjacent 2×2 pixel units are arranged at a period of two pixels in the column direction and at a period of one pixel in the row direction, and in each 2×2 pixel unit, a first global shutter shared pixel and a second global shutter shared pixel having the same layout as the first global shutter shared pixel but inverted in the column direction are arranged adjacent to each other with a shift of 1/2 pixel pitch in the row direction and the column direction, and each of the first global shutter shared pixel and the second global shutter shared pixel is arranged in a pair. The unit pixels are arranged opposite each other in the column direction and share a floating diffusion section that accumulates electric charges, a signal charge detection section that generates a pixel signal according to the electric charges accumulated in the floating diffusion section, and a signal charge reset section that discharges the electric charges accumulated in the floating diffusion section. Each of the pair of unit pixels includes a photodiode section that photoelectrically converts an optical signal to accumulate electric charges, a first charge transfer section that transfers the electric charges accumulated in the photodiode section, a charge retention section that retains the electric charges transferred by the first charge transfer section, and a second charge transfer section that transfers the electric charges retained in the charge retention section to the floating diffusion section.

According to one aspect of the present invention, it is possible to provide a solid-state imaging device that reduces the number of readout lines and enables a high frame rate.

1 is a planar layout diagram of a unit pixel of a solid-state imaging device according to an embodiment of the present invention. 2 is a planar layout diagram of a global shutter shared pixel of the solid-state imaging device according to the embodiment of the present invention. FIG. 2 is a diagram showing a circuit configuration of a global shutter shared pixel of a solid-state imaging device according to an embodiment of the present invention. 1 is a planar layout diagram of a global shutter 2×2 pixel unit of a solid-state imaging device according to an embodiment of the present invention. 1 is a planar layout diagram of a solid-state imaging device according to an embodiment of the present invention. 6 is a diagram in which row readout drive wiring connected to a second charge transfer section is added by a thick line to the planar layout of the solid-state imaging device according to the embodiment of the present invention shown in FIG. 5 . 6 is a diagram in which drive wiring connected to row selection transistors and drive wiring connected to reset transistors are added by thick lines to the planar layout of the solid-state imaging device according to the embodiment of the present invention shown in FIG. 5 . 5A to 5C are diagrams for explaining a method for reading out pixel signals of a solid-state imaging device according to an embodiment of the present invention.

One embodiment of the present invention will be described in detail below. For ease of explanation, identical components are given the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions thereof will not be repeated.

<Plane layout of unit pixel of solid-state imaging device>
1 is a planar layout diagram of a unit pixel of a solid-state imaging device according to an embodiment of the present invention. The unit pixel 100 includes a photodiode portion PD, a first charge transfer portion TRX adjacent to the photodiode portion PD and covered with a first gate electrode, a charge retention portion (not shown) adjacent to the first charge transfer portion TRX in a direction different from the photodiode portion PD, and a second charge transfer portion TRG covered with a second gate electrode adjacent to the charge retention portion in a direction different from the first charge transfer portion TRX.

The unit pixel 100 further includes a floating diffusion portion FD of the first conductive type semiconductor region adjacent to the second charge transfer portion TRG in a direction different from the charge holding portion, a third charge transfer portion OFG covered by a third gate electrode adjacent to the photodiode portion PD in a direction different from the first charge transfer portion TRX, and an overflow drain portion adjacent to the third charge transfer portion OFG in a direction different from the photodiode portion PD and connected to the power supply voltage VDD.

<Plane Layout of Global Shutter Shared Pixels in Solid-State Imaging Device>
2 is a planar layout diagram of a global shutter shared pixel of a solid-state imaging device according to an embodiment of the present invention. The connection wiring of the floating diffusion portion FD is indicated by a thick line. As shown in FIG. 2, the global shutter shared pixel is configured such that two unit pixels 100-1 and 100-2 are connected by a floating diffusion portion FD and are arranged opposite each other in the column direction (the vertical direction in the figure).

The signal charge detection section is composed of a source follower transistor SF and a row selection transistor SEL, whose gate electrode is connected to the floating diffusion section FD by wiring in pixel 100-2 shown by a thick line, and a reset transistor (signal charge reset section) RST, whose source section is connected to the floating diffusion section FD via wiring in pixel 100-2 also shown by a thick line, and whose drain section is connected to the power supply voltage VDD, are shared by the two unit pixels 100-1 and 100-2. The pixel pitch between unit pixels 100-1 and 100-2 is a.

FIG. 3 is a diagram showing the circuit configuration of the global shutter shared pixels 100-1 and 100-2 of the solid-state imaging device according to the embodiment of the present invention. The global shutter shared pixels 100-1 and 100-2 include first charge transfer units TRX1 and TRX2, second charge transfer units TRG1 and TRG2, overflow gates (third charge transfer units) OFG1 and OFG2, photodiode units PD1 and PD2, charge holding units MEM1 and MEM2, a floating diffusion unit FD, a reset transistor RST, a source follower transistor SF, and a row selection transistor SEL.

The photodiode unit PD1 functions as a photoelectric conversion unit that converts incident light into electric charge by photoelectric conversion and accumulates the electric charge. The anode terminal of the photodiode unit PD1 is grounded, and the cathode terminal is connected to the first charge transfer unit TRX1 and the third charge transfer unit OFG1.

The first charge transfer unit TRX1 is driven by a first transfer signal (not shown). When the first charge transfer unit TRX1 is turned on, the charge stored in the photodiode unit PD1 is transferred to the charge holding unit MEM1. The transfer of charge from the photodiode unit PD1 to the charge holding unit MEM1 is performed at approximately the same timing for all unit pixels of the solid-state imaging element, and charge is transferred simultaneously for all unit pixels. The charge holding unit MEM1 holds the charge transferred from the photodiode unit PD1.

The second charge transfer unit TRG1 is driven by a row readout drive signal described below. When the second charge transfer unit TRG1 is turned on, the charge stored in the charge holding unit MEM1 is transferred to the floating diffusion unit FD.

The overflow gate OFG1 is driven by a discharge signal (not shown). When the overflow gate OFG1 is turned on, the charge stored in the photodiode portion PD1 is discharged to the power supply wiring VDD. The overflow gate OFG1 also has the function of causing charge to overflow (overflow) from the photodiode portion PD1 to the power supply wiring VDD when charge greater than the saturation charge amount of the photodiode portion PD1 is generated by photoelectric conversion.

Similarly, the photodiode unit PD2 functions as a photoelectric conversion unit that converts incident light into electric charge by photoelectric conversion and accumulates the electric charge. The anode terminal of the photodiode unit PD2 is grounded, and the cathode terminal is connected to the first charge transfer unit TRX2 and the third charge transfer unit OFG2.

The first charge transfer unit TRX2 is driven by a first transfer signal (not shown). When the first charge transfer unit TRX2 is turned on, the charge stored in the photodiode unit PD2 is transferred to the charge holding unit MEM2. The transfer of charge from the photodiode unit PD2 to the charge holding unit MEM2 is performed at approximately the same timing for all unit pixels of the solid-state imaging element, and charge is transferred simultaneously for all unit pixels. The charge holding unit MEM2 holds the charge transferred from the photodiode unit PD2.

The second charge transfer unit TRG2 is driven by a row readout drive signal described below. When the second charge transfer unit TRG2 is turned on, the charge stored in the charge holding unit MEM2 is transferred to the floating diffusion unit FD.

The overflow gate OFG2 is driven by a discharge signal (not shown). When the overflow gate OFG2 is turned on, the charge stored in the photodiode section PD2 is discharged to the power supply wiring VDD. The overflow gate OFG2 also has the function of causing charge to overflow (overflow) from the photodiode section PD2 to the power supply wiring VDD when charge greater than the saturation charge amount of the photodiode section PD2 is generated by photoelectric conversion.

The source follower transistor SF outputs a pixel signal at a level corresponding to the charge stored in the floating diffusion section FD to the vertical signal line VSL via the row selection transistor SEL. In other words, by configuring the floating diffusion section FD to be connected to the gate electrode of the source follower transistor SF, the floating diffusion section FD and the source follower transistor SF function as a conversion section that converts the charge generated in the photodiode section PD1 or PD2 into a pixel signal at a level corresponding to that charge.

The row selection transistor SEL is driven by a row selection signal, which will be described later. When the row selection transistor SEL is turned on, the pixel signal output from the source follower transistor SF can be output to the vertical signal line VSL. The source follower transistor SF and the row selection transistor SEL function as a signal charge detection unit.

The reset transistor RST is driven by a row reset signal (RST signal) described below. When the reset transistor RST is turned on, the charge stored in the floating diffusion portion FD is discharged to the power supply wiring VDD, and the floating diffusion portion FD is reset.

The floating diffusion portion FD is a first conductivity type semiconductor region having a predetermined storage capacitance connected to the gate electrode of the source follower transistor SF, and stores the charge transferred from the charge holding portion. The floating diffusion portion FD, reset transistor RST, source follower transistor SF, and row selection transistor SEL are shared by two unit pixels 100-1 and 100-2.

<Plane Layout of Global Shutter 2×2 Pixel Unit of Solid-State Imaging Device>
4 is a planar layout diagram of a global shutter 2×2 pixel unit of a solid-state imaging device according to an embodiment of the present invention. The connection wiring of the floating diffusion portion FD is indicated by a thick line. Note that unit pixels 100-11 and 100-21 constitute one global shutter shared pixel, and unit pixels 100-12 and 100-22 constitute another global shutter shared pixel.

The global shutter 2×2 pixel unit is arranged adjacent to the global shutter shared pixels (100-1, 100-2) shown in FIG. 2 by inverting the same global shutter shared pixels in the column direction (up and down direction) and shifting them by a/2 with respect to the pixel pitch a in the row and column directions.

As shown in FIG. 4, the VDD of the overflow drain of the overflow gate OFG11 adjacent to the upper photodiode PD11 of the left global shutter shared pixel (100-11, 100-21) is shared with the VDD connected to the drain terminal of the reset transistor RST2 of the right global shutter shared pixel (100-12, 100-22).

<Plane layout of solid-state imaging device>
5 is a planar layout diagram of the solid-state imaging device 1 according to the embodiment of the present invention. The connection wiring of the floating diffusion portion FD is indicated by a thick line. The solid-state imaging device according to the present embodiment is configured by arranging a plurality of global shutter 2×2 units shown in FIG. 3 at a period of two pixels in the column direction and at a period of one pixel in the row direction.

As shown in FIG. 5, for example, the VDD of the overflow gate OFG21 adjacent to the lower photodiode PD21 of the global shutter shared pixel (100-11, 100-21) on the upper left side is shared with the VDD connected to the drain of the source follower transistor SF22 of the global shutter shared pixel (100-32, 100-42) on the lower right side. The other global shutter shared pixels are similarly arranged and connected.

In FIG. 5, the global shutter shared pixel (100-13, 100-23) and the global shutter shared pixel (100-14, 100-24) form one global shutter 2×2 pixel unit. The global shutter shared pixel (100-31, 100-41) and the global shutter shared pixel (100-32, 100-42) form one global shutter 2×2 pixel unit. Similarly, the global shutter shared pixel (100-33, 100-43) and the global shutter shared pixel (100-34, 100-44) form one global shutter 2×2 pixel unit.

<Row readout drive wiring of solid-state imaging device>
Fig. 6 is a diagram in which row readout drive wirings connected to the second charge transfer units TRG are added by thick lines to the planar layout of the solid-state imaging device 1 according to the embodiment of the present invention shown in Fig. 5. The row readout drive wirings TRG1 to TRG4 are wired in a zigzag pattern at the boundaries of the global shutter shared pixels arranged in the column direction, and the second charge transfer units TRG on the upper side of each global shutter shared pixel are connected by the same row readout drive wirings (TRG1, TRG3), and the second charge transfer units TRG on the lower side are connected by the same row readout drive wirings (TRG2, TRG4).

<Drive Wiring Connected to Row Selection Transistor SEL and Drive Wiring Connected to Reset Transistor RST of Solid-State Imaging Device>
FIG. 7 is a diagram in which a drive wiring connected to the row selection transistor SEL and a drive wiring connected to the reset transistor RST are added by bold lines to the planar layout of the solid-state imaging device according to the embodiment of the present invention shown in FIG. 5 .

A drive wiring (row selection signal) SEL1 is connected to row selection transistors SEL11, SEL12, SEL13, and SEL14. Although they are separate wirings within the pixel array, they are connected in the pixel peripheral circuit section (not shown) and the same waveform is supplied.

Drive wiring SEL2 is connected to row selection transistors SEL21, SEL22, SEL23, and SEL24. Although it is a separate wiring within the pixel array, it is connected in the pixel peripheral circuit section (not shown) like row selection signal SEL1, and the same waveform is supplied.

A drive wiring (row reset signal) RST1 is connected to the reset transistors RST11, RST12, RST13, and SEL14. Although it is a separate wiring within the pixel array, it is connected in the pixel peripheral circuit section (not shown) and the same waveform is supplied.

The drive wiring RST2 is connected to the reset transistors RST21, RST22, RST23, and SEL24. Although it is a separate wiring within the pixel array, it is connected in the pixel peripheral circuit section (not shown) in the same way as the row reset signal RST1, and the same waveform is supplied.

The drive wirings SEL1, SEL2, RST1, and RST2 are wired in a zigzag pattern at the boundaries of each global shutter shared pixel. The drive wirings SEL1 and RST1 are connected to each global shutter shared pixel by two wires, but as shown in FIG. 7, the order of arrangement in the column direction is reversed when the drive wirings are wired above the global shutter shared pixel and when they are wired below the global shutter shared pixel.

Figure 8 is a diagram for explaining a method for reading out pixel signals from the solid-state imaging device 1 according to an embodiment of the present invention. As shown in Figure 8, by reading out pixel signals from unit pixels arranged in a zigzag pattern, the number of readouts can be halved compared to the conventional technology. This allows operation at a high frame rate, enabling high-speed readout.

As described above, in the solid-state imaging device of this embodiment, two unit pixels 100-1 and 100-2 are connected by a floating diffusion section FD and arranged opposite each other in the column direction (the vertical direction in the figure) to form a global shutter shared pixel. The second charge transfer section TRG on the upper side of the global shutter shared pixel is connected by a row readout drive wiring, and the second charge transfer section TRG on the lower side is connected by another row readout drive wiring. This makes it possible to reduce the number of readout lines and achieve a high frame rate.

The frame rate (the time required to read one screen) is calculated by multiplying the readout time per line (the AD conversion time per line) by the number of lines read out. Therefore, even if the number of pixels is the same, if the number of lines read out is halved, the frame rate will simply double.

In addition, the VDD of the overflow drain section of the overflow gate OFG11 adjacent to the upper photodiode PD11 of the global shutter shared pixel (100-11, 100-21) is shared with the VDD connected to the drain terminal of the reset transistor RST2 of the global shutter shared pixel (100-12, 100-22). Therefore, the arrangement of the global shutter shared pixel (100-11, 100-21) and the global shutter shared pixel (100-12, 100-22) can be efficiently performed, and the characteristics of the photodiode section and the charge holding section can be maintained.

In addition, the VDD of the overflow gate OFG21 adjacent to the lower photodiode PD21 of the global shutter shared pixel (100-11, 100-21) is shared with the VDD connected to the drain of the source follower transistor SF22 of the global shutter shared pixel (100-32, 100-42). Therefore, the global shutter shared pixel (100-11, 100-21) and the global shutter shared pixel (100-32, 100-42) can be efficiently arranged, and the characteristics of the photodiode section and the charge storage section can be maintained.

The sensitivity characteristics and saturation charge amount of a solid-state imaging element depend on the area of the photodiode section PD. In addition, the saturation charge amount of a global shutter pixel depends on the area of the charge holding section MEM. Therefore, by efficiently arranging the pixels in an angled arrangement, the areas of the photodiode section PD and the charge holding section MEM can be maintained, and the same characteristics can be maintained as with a normal pixel arrangement.

In addition, by making the layout of each unit pixel and each global shutter shared pixel the same, it is possible to uniformize various characteristics of each pixel, such as the sensitivity, saturation charge, dark noise characteristics, and charge transfer characteristics.

In addition, a drive wiring (row selection signal) SEL1 is connected to the row selection transistors SEL11, SEL12, SEL13, and SEL14, and the drive wiring connected to the row selection transistors SEL11 and SEL13 and the drive wiring connected to the row selection transistors SEL12 and SEL14 are separate wirings. This allows the row selection signal SEL1 to be wired efficiently.

In addition, a drive wiring (row reset signal) RST1 is connected to the reset transistors RST11, RST12, RST13, and SEL14, and the drive wiring connected to the reset transistors RST11 and RST13 and the drive wiring connected to the reset transistors RST12 and RST14 are separate wirings. This allows the row reset signal RST1 to be wired efficiently.

In addition, the drive wiring SEL1 and RST1 are connected to each global shutter shared pixel by two wirings, but the order of arrangement in the column direction is reversed when wiring is provided above the global shutter shared pixel and when wiring is provided below the global shutter shared pixel. This allows the row selection signal SEL1 and row reset signal RST1 to be wired efficiently.

<Summary>
A solid-state imaging device according to a first aspect of the present invention is a solid-state imaging device in which a plurality of 2×2 pixel units each having a global shutter shared pixel arranged adjacent to each other are arranged, and the adjacent 2×2 pixel units are arranged at a period of two pixels in the column direction and at a period of one pixel in the row direction. In each 2×2 pixel unit, a first global shutter shared pixel and a second global shutter shared pixel having the same layout as the first global shutter shared pixel but inverted in the column direction are arranged adjacent to each other with a shift of ½ pixel pitch in the row direction and the column direction, and each of the first global shutter shared pixel and the second global shutter shared pixel is a pair of unit pixels A pair of unit pixels are arranged opposite each other in the column direction and share a floating diffusion section that accumulates charge, a signal charge detection section that generates a pixel signal in accordance with the charge accumulated in the floating diffusion section, and a signal charge reset section that discharges the charge accumulated in the floating diffusion section, and each of the unit pixels includes a photodiode section that photoelectrically converts an optical signal to accumulate charge, a first charge transfer section that transfers the charge accumulated in the photodiode section, a charge holding section that holds the charge transferred by the first charge transfer section, and a second charge transfer section that transfers the charge held in the charge holding section to the floating diffusion section.

The above configuration allows the number of read lines to be reduced, making it possible to achieve a high frame rate.

A solid-state imaging device according to aspect 2 of the present invention is the same as that of aspect 1 above, except that the second charge transfer unit of the upper unit pixel in the first global shutter shared pixel and the second charge transfer unit of the upper unit pixel in the second global shutter shared pixel are driven by a first row readout drive signal, and the second charge transfer unit of the lower unit pixel of the first global shutter shared pixel and the second charge transfer unit of the lower unit pixel of the second global shutter shared pixel are driven by a second row readout drive signal.

The above configuration allows the number of read lines to be reduced, making it possible to achieve a high frame rate.

In the solid-state imaging device according to aspect 3 of the present invention, in the above aspect 1 or 2, the unit pixel further includes a third charge transfer section that discharges a charge that is greater than the saturated charge amount of the photodiode section, and the overflow drain section of the third charge transfer section of the unit pixel in the first global shutter shared pixel and the drain section of the signal charge reset section in the second global shutter shared pixel are formed from the same first semiconductor region.

The above configuration allows the first global shutter shared pixel and the second global shutter shared pixel to be arranged efficiently, making it possible to maintain the characteristics of the photodiode section and the charge storage section.

In the solid-state imaging device according to aspect 4 of the present invention, in the above aspect 1 or 2, the unit pixel further includes a third charge transfer section that discharges a charge that is greater than the saturated charge amount of the photodiode section, and the overflow drain section of the third charge transfer section of the unit pixel in the first global shutter shared pixel and the drain section of the signal charge detection section in the second global shutter shared pixel are formed from the same first semiconductor region.

The above configuration allows the first global shutter shared pixel and the second global shutter shared pixel to be arranged efficiently, making it possible to maintain the characteristics of the photodiode section and the charge storage section.

In the solid-state imaging device according to aspect 5 of the present invention, in any one of aspects 1 to 4 above, the row selection signal connected to the signal charge detection unit in the first global shutter shared pixel and the row selection signal connected to the signal charge detection unit in the second global shutter shared pixel have the same signal waveform and are connected by different wiring.

The above configuration allows for efficient wiring of row selection signals.

In the solid-state imaging device according to aspect 6 of the present invention, in the above-mentioned aspect 5, the row reset signal connected to the signal charge reset unit in the first global shutter shared pixel and the row reset signal connected to the signal charge reset unit in the second global shutter shared pixel have the same signal waveform and are connected by different wiring.

The above configuration allows for efficient wiring of row reset signals.

In the solid-state imaging device according to aspect 7 of the present invention, the wiring arrangement of the row selection signal and row reset signal connected to the first global shutter shared pixel is reversed to the wiring arrangement of the row selection signal and row reset signal connected to the second global shutter shared pixel in the above-mentioned aspect 6.

The above configuration allows efficient wiring of row selection signals and row reset signals.

The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. The technical scope of the present invention also includes embodiments obtained by appropriately combining the technical means disclosed in the different embodiments. Furthermore, new technical features can be formed by combining the technical means disclosed in the respective embodiments.

1 Solid-state imaging device 100, 100-1 to 100-2, 100-11 to 100-44 Unit pixel PD, PD1 to PD2, PD11 to PD44 Photodiode TRX, TRX1 to TRX2, RX11 to TRX44 First charge transfer section TRG, TRG1 to TRG2, TRG11 to TRG44 Second charge transfer section OFG, OFG1 to OFG2, OFG11 to OFG44 Overflow gate section FD Floating diffusion section SF, SF11 to SF24 Source follower transistor SEL, SEL11 to SEL24 Row selection transistor RST, RST11 to RST24 Signal charge reset section VDD Power supply wiring

Claims (6)

A solid-state imaging device in which a plurality of 2×2 pixel units are arranged, each having a global shutter shared pixel arranged adjacent to each other,
The adjacent 2×2 pixel units are arranged in a plurality of units at a period of two pixels in the column direction and at a period of one pixel in the row direction,
In the 2×2 pixel unit, a first global shutter shared pixel and a second global shutter shared pixel having the same layout as the first global shutter shared pixel but inverted in the column direction are adjacently arranged with a shift of ½ pixel pitch in the row and column directions,
each of the first global shutter shared pixel and the second global shutter shared pixel includes a pair of unit pixels arranged opposite to each other in a column direction, and the pair of unit pixels share a floating diffusion section that accumulates electric charges, a signal charge detection section that generates a pixel signal in accordance with the electric charges accumulated in the floating diffusion section, and a signal charge reset section that discharges the electric charges accumulated in the floating diffusion section;
Each of the pair of unit pixels includes a photodiode section that photoelectrically converts an optical signal and accumulates an electric charge, a first charge transfer section that transfers the electric charge accumulated in the photodiode section, a charge holding section that holds the electric charge transferred by the first charge transfer section, and a second charge transfer section that transfers the electric charge held in the charge holding section to the floating diffusion section ,
the second charge transfer unit of an upper unit pixel in the first global shutter shared pixel and the second charge transfer unit of an upper unit pixel in the second global shutter shared pixel are driven by a first row readout drive signal;
a second charge transfer unit of a unit pixel below the first global shutter shared pixel and a second charge transfer unit of a unit pixel below the second global shutter shared pixel, the second charge transfer unit being driven by a second row readout drive signal . the unit pixel further includes a third charge transfer section configured to discharge a charge amount greater than a saturation charge amount of the photodiode section,
2. The solid-state imaging device according to claim 1, wherein an overflow drain portion of the third charge transfer portion of a unit pixel in the first global shutter shared pixel and a drain portion of the signal charge reset portion in the second global shutter shared pixel are formed from the same first semiconductor region. the unit pixel further includes a third charge transfer section configured to discharge a charge amount greater than a saturation charge amount of the photodiode section,
2. The solid-state imaging device according to claim 1, wherein an overflow drain portion of the third charge transfer portion of a unit pixel in the first global shutter shared pixel and a drain portion of the signal charge detection portion in the second global shutter shared pixel are formed from the same first semiconductor region. 4. The solid-state imaging device according to claim 1, wherein a row selection signal connected to the signal charge detection unit in the first global shutter shared pixel and a row selection signal connected to the signal charge detection unit in the second global shutter shared pixel have the same signal waveform and are connected by different wirings. 5. The solid-state imaging device according to claim 4, wherein a row reset signal connected to the signal charge reset unit in the first global shutter shared pixel and a row reset signal connected to the signal charge reset unit in the second global shutter shared pixel have the same signal waveform and are connected by different wiring. 6. The solid-state imaging device according to claim 5, wherein an arrangement of wirings of the row selection signal and the row reset signal connected to the first global shutter shared pixel is reversed to an arrangement of wirings of the row selection signal and the row reset signal connected to the second global shutter shared pixel.

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