JP7545940B2 - Semiconductor heat treatment member and its manufacturing method - Google Patents

Description

The present invention relates to a semiconductor heat treatment component, for example, a semiconductor heat treatment component suitable for use in an RTP apparatus (rapid thermal processing apparatus) and applicable to a ring that holds a semiconductor wafer, and a method for manufacturing the same.

In the semiconductor manufacturing process, an RTP apparatus is used as a technology for heat-treating semiconductor wafers using a heat treatment device. RTP (Rapid Thermal Process) stands for rapid heat treatment, and this RTP apparatus can create ultra-thin silicon oxide films with a thickness of less than 10 nm.

The RTP device is a thermal processing technology that uses lamp heating. The feature of this technology is that it heats the wafer rapidly (to about 1000°C in a few tens of seconds) and individually controls the evenly arranged infrared lamps through feedback from the wafer surface temperature. This makes it possible to control the temperature difference of the wafer surface with high precision.

A typical RTP device uses a tungsten halogen lamp or the like as a light source lamp.
The energy of the light source lamp is directly absorbed by the semiconductor wafer placed and held on the wafer holding ring. Since a clean gas atmosphere such as _N2 gas is required as the environment for processing the semiconductor wafer, the processing chamber body is sealed with a quartz window made of quartz, which is a thermally stable material with good halogen light transmission efficiency. The wafer is placed on the wafer holding ring near the center of the processing chamber where the light irradiation balance is good. In this method using the RTP device, the wafer can be heated without using a heat medium, so the heat capacity that determines the thermal response of the device can be minimized. As a result, instantaneous heating can be realized, so there is little possibility of destroying the structure of the wafer, and it is considered to be particularly effective for wafer annealing.

In this RTP apparatus, the wafer retaining ring on which the wafer is placed is generally made of silicon carbide ceramics. This is because silicon carbide materials have high heat resistance and thermal conductivity, allowing the semiconductor wafer to be heated uniformly and being less susceptible to damage (see Patent Document 1). Also commonly used are those in which a silicon carbide film is applied to the surface of a base material such as carbon by the CVD method (see Patent Document 2).

In particular, in cases where a large amount of heat is applied in a short period of time, such as in an RTP apparatus, attempts are being made to reduce the thickness of the wafer retaining ring in order to minimize the thermal capacity that determines the thermal response of the apparatus.
However, while the thinner the conventional wafer retaining ring, the better its thermal properties. the silicon carbide material from which the wafer retaining ring is made has low toughness, making the ring thinner reduces its mechanical strength, increasing the likelihood of structural and thermal failure.

In particular, to make the thickness in the heat transfer direction 1.2 mm or less, machining using diamond grindstones or loose abrasive grains is necessary, but because fine polishing scratches (tool marks) remain on the processed surface of the wafer retaining ring, the strength is significantly reduced compared to the inherent strength of silicon carbide. In other words, the wafer retaining ring is often damaged by fine polishing scratches on the processed surface.

In addition, the silicon carbide material from which the wafer retaining ring is made is dense, with a purity of 99.5% or more and a theoretical density of 97% or more. Silicon carbide material with low purity and low density has low thermal conductivity, which in turn increases the difference in heat distribution throughout the product in an RTP apparatus, increasing the generated thermal stress and possibly leading to destruction during use.
Furthermore, if the arithmetic mean roughness Ra of the surface of a wafer retaining ring exceeds 1.6 μm and the thickness is 1 mm or less, the wafer retaining ring is highly likely to be damaged due to physical damage such as breakage during handling and transportation, or due to repeated thermal contraction.

In response to these issues, Patent Document 3 discloses a wafer retaining ring whose base material is made of silicon carbide ceramics and whose surface is coated with a silicon oxide film having a thickness of 0.05 μm to 5 μm. The arithmetic mean roughness Ra of this wafer retaining ring is 1.6 μm or less, and it is described as preventing a decrease in mechanical strength due to minute polishing scratches on the processed surface and damage due to thermal stress, making it suitable for use in rapid heat treatment devices such as RTP devices.

JP 2000-315720 A JP 2002-231713 A JP 2004-152900 A

However, in the wafer retaining ring disclosed in Patent Document 3, even if the arithmetic mean roughness Ra is 1.6 μm or less, it is insufficient to control the heat transfer to the semiconductor wafer and form an oxide film with good thickness uniformity on the wafer surface.
As a result of extensive research, the inventors of the present application have discovered that in order to control the heat transfer to the wafer and form a good oxide film on the wafer surface, it is important to control both the arithmetic mean roughness Ra, which is an index in the height direction, and the mean length RSm, which is an index in the planar direction, on the wafer mounting surface.
The present inventors have arrived at the present invention on the premise of controlling both the arithmetic mean roughness Ra, which is an index in the height direction, and the mean length RSm, which is an index in the planar direction.

The present invention was made under the above circumstances, and aims to provide a semiconductor heat treatment component applicable to a ring that holds a semiconductor wafer, which has uniform heat transfer to the semiconductor wafer when an oxide film is formed on the semiconductor wafer by heat treatment, and a method for manufacturing the same, which can reduce the variation in thickness of the oxide film formed on the wafer surface.

The semiconductor heat treatment member of the present invention, which has been made to solve the above problems, is a semiconductor heat treatment member having a substrate made of silicon carbide whose surface is coated with an oxide film and which holds a semiconductor wafer, and is characterized in that the arithmetic mean roughness Ra of the surface of the wafer holding part in contact with the semiconductor wafer is 0.3 μm or less, and the average element length RSm is 40 μm or less.
It is preferable that the difference ΔRa between the maximum and minimum values of the arithmetic mean roughness Ra of the surface of the wafer holder is 0.15 μm or less.
It is also preferable that the thickness of the wafer holder is set to 1 mm or less.
Moreover, it is desirable that the thickness of the oxide film formed on the surface of the wafer holder is 0.3 μm or more and 3 μm or less.

With a semiconductor heat treatment member configured in this manner, the surface in contact with the semiconductor wafer is formed to have an arithmetic mean roughness Ra of 0.3 μm or less and an average length of the roughness elements RSm of 40 μm or less. This makes the heat transfer to the held semiconductor wafer uniform, and when an oxide film is formed on the semiconductor wafer by heat treatment, it is possible to reduce the variation in the thickness of the oxide film formed on the wafer surface.

In addition, the manufacturing method of the present invention, which has been made to solve the above-mentioned problems, is a manufacturing method of the above-mentioned semiconductor heat treatment member, and is characterized in that it comprises the steps of obtaining a ring-shaped silicon carbide substrate, processing the surface of the substrate with a diamond grinding wheel so that the arithmetic mean roughness Ra is 0.3 μm or less and the average element length RSm is 40 μm or less, and heating the substrate in an oxidizing atmosphere to form an oxide film having a thickness of 0.3 μm or more and 3 μm or less on the surface of the substrate.
According to this method, a semiconductor heat treatment member having the above-mentioned characteristics can be obtained.

The present invention provides a semiconductor heat treatment component that can be applied to a ring that holds a semiconductor wafer, and a manufacturing method thereof that can uniformly transfer heat to the semiconductor wafer when an oxide film is formed on the semiconductor wafer by heat treatment, thereby reducing the variation in thickness of the oxide film formed on the wafer surface.

FIG. 1 is a cross-sectional view of a semiconductor heat treatment member according to the present invention. FIG. 2 is a cross-sectional view taken along line AA of FIG. FIG. 3 is a cross-sectional view showing a schematic diagram of an RTP apparatus using the semiconductor heat treatment member shown in FIG.

An embodiment of a semiconductor heat treatment member according to the present invention will be described below with reference to Figures 1 and 2. Figure 1 is a plan view of a ring as a semiconductor heat treatment member according to the present invention, and Figure 2 is a cross-sectional view taken along the line A-A in Figure 1. Note that the figures are schematic or conceptual, and the relationship between the thickness and width of each portion, the size ratio between portions, etc. are not accurately shown.
In addition, in this embodiment, an example will be described in which a ring is used in an RTP apparatus as the semiconductor heat treatment member of the present invention, and which holds a semiconductor wafer in order to perform a process such as forming an oxide film on the surface of the semiconductor wafer.

As shown in FIG. 1, the ring 1 (semiconductor heat treatment member) is composed of a ring-shaped frame 2 and a wafer holder 3 formed below and inside the frame 2 for placing a semiconductor wafer thereon.
The frame 2 and the wafer holder 3 are made of a substrate 4 made of silicon carbide on which an oxide film 5 is formed, and the thickness of the oxide film 5 is about 0.3 μm to 3 μm, preferably 0.8 μm to 1.2 μm. The oxide film 5 is formed so that a compressive stress is applied in the direction of the substrate 4, and the substrate 4 has resistance, and therefore, even if the substrate 4 is formed thin, the ring 1 can be prevented from being damaged by mechanical loads, such as when a wafer is mounted, or loads due to thermal cycles.

If the thickness of the oxide film 5 is thinner than 0.3 μm, the resistance to mechanical loads and loads due to thermal cycles will be low when the substrate 4 is formed thin, and there is a risk of the ring 1 being damaged. On the other hand, if the thickness of the oxide film 5 is thicker than 3 μm, there is a risk of the thermal conductivity of the ring 1 decreasing, and there is a risk of unevenness in the heat treatment results. There is also a risk that the oxide film will peel off and cause wafer contamination by particles.

Furthermore, the thickness t of the wafer holder 3 (the combined thickness of the substrate 4 and the oxide film 5) is set to 1 mm or less, more preferably 0.5 mm or less. By forming the wafer holder 3 thin in this manner, the heat capacity of the substrate 4 is reduced, improving the thermal response. The thickness t is preferably set to 0.20 mm or more to ensure strength.
If the thickness of the wafer holder 3 is more than 1 mm, the heat capacity of the base material 4 increases, undesirably lowering the thermal response.

Furthermore, the inner diameter of the ring-shaped frame portion 2 formed on the ring 1 is not particularly limited as long as it is possible to fit a semiconductor wafer therein, and any size can be used depending on the outer diameter of the semiconductor wafer to be subjected to heat treatment.
Furthermore, it is preferable that the wafer holding portion 3 provided on the lower inner periphery of the frame portion 2 has a surface that is substantially parallel to the upper surface of the semiconductor heat treatment member 1 when a semiconductor wafer 4 is placed on the upper surface of the wafer holding portion 3, so that the entire semiconductor wafer can be uniformly heated and treated during heat treatment using an RTP apparatus or the like.

The inner diameter of the wafer holder 3 is not particularly limited as long as the semiconductor wafer can be placed thereon, but it is preferable that the inner diameter be slightly smaller than the outer diameter of the semiconductor wafer to be placed thereon. This reduces the contact area between the wafer holder 3 and the semiconductor wafer, preventing the heat applied to the semiconductor wafer from diffusing from the wafer holder 3, and reducing unevenness in heat distribution to heat the semiconductor wafer uniformly.

The surface of the wafer holder 3 is formed so that the arithmetic mean roughness Ra, which is an index in the height direction, is 0.3 μm or less, and the mean length RSm of the elements of the roughness curve is 40 μm or less.
If the arithmetic mean roughness Ra is greater than 0.3 μm, a gap will occur between the semiconductor wafer and the surface (mounting surface) of the wafer holder 3, reducing heat transfer, making it difficult to transfer heat uniformly to the semiconductor wafer.
Furthermore, if the average length RSm of the roughness curve elements exceeds 40 μm, the contact area between the semiconductor wafer and the wafer holder 3 becomes small, which is undesirable because there is a risk of deterioration in heat transfer due to thermal conduction.
Incidentally, the average length RSm of the roughness curve element is preferably 15 μm or more in order to prevent the wafer from sticking to the wafer holder 3 during heat treatment.

In addition, it is preferable that the variation in the arithmetic mean roughness Ra of the wafer mounting surface is small, and the difference ΔRa between the maximum and minimum values of Ra is 0.15 μm or less. More preferably, ΔRa is 0.1 μm or less, which shows good heat transfer and allows the production of wafers with better oxide film thickness uniformity in the oxide film formation process on semiconductor wafers. By processing semiconductor wafers using a ring 1 with such a wafer holding portion 3 (wafer mounting surface), it is possible to reduce the variation in oxide film thickness within the wafer surface to 0.10 nm or less.

Next, a method for manufacturing the ring 1 according to the present invention will be described. First, when manufacturing the substrate 4 made of silicon carbide, silicon carbide is formed into a predetermined ring-shaped body, and this body is sintered to obtain the ring-shaped substrate 4 having high thermal conductivity. Alternatively, silicon carbide is grown on the surface of a carbon substrate by a CVD method, and then the carbon substrate is removed to obtain a ring-shaped silicon carbide substrate 4 having high thermal conductivity.

Next, the surface of this ring-shaped substrate 4 is ground, polished, or otherwise processed with a diamond grindstone so that the arithmetic mean roughness Ra is 0.3 μm or less and the mean element length RSm is 40 μm or less. Furthermore, the substrate 4 is oxidized by applying heat at 1000°C to 1300°C in an oxidizing atmosphere to form an oxide film 5 with a thickness of about 0.3 μm to 3 μm, preferably 0.8 μm to 1.2 μm, on the entire surface of the substrate 4, and the ring 1 is obtained.

Figure 3 shows one embodiment of an RTP apparatus equipped with the ring 1 of the present invention. As shown in Figure 3, the RTP apparatus 10 comprises a chamber (reaction tube) 20 equipped with an atmospheric gas inlet 20a and an atmospheric gas outlet 20b, a plurality of lamps 30 spaced apart at the top of the chamber 20, and a substrate support 40 that supports a semiconductor wafer W in a reaction space 25 within the chamber 20. In addition, although not shown, the apparatus is equipped with a rotation means for rotating the semiconductor wafer W around its central axis at a predetermined speed.

The substrate support 40 comprises a ring 1 of the present invention that supports the outer periphery of the semiconductor wafer W, and a stage 40a that supports the ring 1. The chamber 20 is made of, for example, quartz. The lamps 30 are made of, for example, halogen lamps. The stage 40a is made of, for example, quartz. This RTP device can uniformly heat and process the entire semiconductor wafer W with a temperature gradient of 10°C to 300°C/sec for heating or cooling.

The temperature in the reaction space 25 in this RTP device 10 is controlled by measuring the average temperature at multiple points (e.g., nine points) on the substrate surface in the radial direction of the substrate below the ring 1 using multiple radiation thermometers 50 embedded in the stage 40a of the substrate support part 40, and controlling the multiple halogen lamps 30 (individual ON-OFF control of each lamp, control of the emission intensity of the emitted light, etc.) based on the measured temperature.

Next, a method of heat treating a semiconductor wafer W using an RTP apparatus 10 having a ring as a semiconductor heat treatment member according to this embodiment will be described with reference to FIG.
First, the semiconductor wafer W is placed and fixed on the ring 1. The lower surface of the peripheral portion of the semiconductor wafer W comes into contact with the wafer holder 3. This ring 1 is fixed to the upper part of the stage 40a installed in the reaction space 25 under an oxidizing atmosphere so that the upper surface of the semiconductor wafer W is approximately parallel to the upper part of the stage 40a.

Furthermore, a process gas is introduced through the atmospheric gas inlet 20a, and the gas within the reaction space 25 is exhausted through the atmospheric gas outlet 20b, thereby forming a predetermined air flow above the semiconductor wafer W.
Next, the halogen lamps 30 arranged in an even array are individually controlled by feedback from the surface temperature of the semiconductor wafer W to control the surface temperature of the semiconductor wafer W, thereby rapidly heating the semiconductor wafer W (for example, to about 1,000° C. in several tens of seconds) to perform a heat treatment of the semiconductor wafer W. As a result, a desired oxide film is formed on the surface of the semiconductor wafer W.

As described above, according to the ring 1 (semiconductor heat treatment member) of this embodiment, the ring 1 is composed of the frame 2 and the wafer holding part 3, which are formed on the surface of the substrate 4 made of silicon carbide with an oxide film 5. Here, the surface of the wafer holding part 3 is formed to have an arithmetic mean roughness Ra of 0.3 μm or less and an average length RSm of the roughness elements of 40 μm or less. This makes the heat transfer to the semiconductor wafer W held by the wafer holding part 3 uniform, and when an oxide film is formed on the semiconductor wafer W by heat treatment, it is possible to reduce the variation in the thickness of the oxide film formed on the wafer surface.

In the above embodiment, a ring has been used as an example of the semiconductor heat treatment member according to the present invention, but the present invention is not limited to this form and can be widely applied to semiconductor heat treatment members having an oxide film coating on the surface of a silicon carbide base material.

The semiconductor heat treatment member and the manufacturing method thereof according to the present invention will be further described with reference to examples.
[Experiment 1]
In experiment 1, multiple rings with different surface conditions of the wafer holding part (wafer mounting surface) were created (Examples 1 to 5, Comparative Examples 1 to 3), semiconductor wafers held in the rings were heat-treated, and the thickness uniformity of the oxide film formed on the wafer surface was investigated.
In the preparation of the ring, the surface of the substrate was ground with a diamond grindstone so that the arithmetic mean roughness Ra was 0.3 μm or less and the mean element length RSm was 40 μm or less. The substrate was then subjected to an oxidation treatment by applying heat at 1000° C. to 1300° C. in an oxidizing atmosphere to form an oxide film with a thickness of 1.0 μm on the entire surface of the substrate, thereby obtaining a wafer holding ring. The arithmetic mean roughness Ra, the mean element length RSm, and the difference ΔRa between the arithmetic mean roughness Ra of the surface of the wafer holding part at this time were as shown in Table 1.

The surface roughness of the wafer holder (wafer mounting surface) of each ring was changed by changing the grit size of the diamond grindstone. The surface roughness was measured using a non-contact roughness meter. The surface roughness was measured at four points on the surface of the wafer holder at 90 degree intervals, and the average value was taken. The difference ΔRa in the arithmetic mean roughness Ra, which is an index in the height direction, was calculated by subtracting the minimum value Ra from the maximum value Ra of the four points.
The average element length RSm was calculated by measuring four points on the surface of the wafer holder at 90 degree intervals with a non-contact roughness meter and calculating the average value.

The conditions for the heat treatment of the semiconductor wafer were a dry oxidizing atmosphere at 1000° C. to 1150° C. for 60 seconds to 300 seconds.
Table 1 shows the conditions and results of the examples and comparative examples. The evaluations shown in Table 1 are for the uniformity of the thickness of the oxide film formed on the semiconductor wafer, with an in-plane variation of 0.06 nm or less being rated as ⊚, an in-plane variation of more than 0.06 nm and less than 0.08 nm being rated as ◯, and an in-plane variation of more than 0.08 nm and less than 0.10 nm being Δ. Also, an in-plane variation exceeding 0.10 nm was rated as x.

As shown in Table 1, when the arithmetic mean roughness Ra of the wafer holder was 0.3 μm or less and the average length RSm of the roughness elements in the planar direction was 40 μm or less, the in-plane variation of the oxide film formed on the surface of the semiconductor wafer was small and good, being 0.10 nm or less (Examples 1 to 5).
On the other hand, when the arithmetic mean roughness Ra of the wafer holder was greater than 0.3 μm or the mean length RSm of the roughness elements in the surface direction was greater than 40 μm, the in-surface variation of the wafer oxide film became large (Comparative Examples 1 to 3).
Therefore, as a result of this experiment 1, it was confirmed that by setting the arithmetic mean roughness Ra of the wafer holding part to 0.3 μm or less and the average length RSm of the roughness elements in the surface direction to 40 μm or less, the in-plane variation of the oxide film formed on the surface of the semiconductor wafer can be reduced to 0.10 nm or less.

[Experiment 2]
In experiment 2, multiple rings with different oxide film thicknesses formed on the wafer holder (wafer mounting surface) were created (Examples 6 to 11), and the semiconductor wafers held by the rings were heat-treated to examine the thickness uniformity of the oxide film formed on the wafer surface and the generation of particles. The thickness of the oxide film on the ring was adjusted by the heat treatment time in an oxidizing atmosphere. The conditions and evaluation results of experiment 2 are shown in Table 2. Among the evaluations shown in Table 2, the uniformity of the thickness of the oxide film formed on the semiconductor wafer was evaluated as follows: ◎ when the in-plane variation was 0.06 nm or less, ○ when the in-plane variation was more than 0.06 nm and less than 0.08 nm, and △ when the in-plane variation was more than 0.08 nm and less than 0.10 nm.
In addition, when a wafer was loaded on the ring and used repeatedly 100 times, those which showed particle abnormalities 10 or more times were rated as △, and the rest were rated as ◯.

As a result of the above experiment 2, it was confirmed that the thickness of the oxide film formed on the substrate should be approximately 0.3 μm to 3 μm, and preferably 0.8 μm to 1.2 μm.

Reference Signs List 1 Ring 2 Frame 3 Wafer holder 4 Base material 5 Oxide film 10 RTP device W Semiconductor wafer

Claims (5)

A semiconductor heat treatment member having a surface of a substrate made of silicon carbide covered with an oxide film and configured to hold a semiconductor wafer,
A semiconductor heat treatment member, characterized in that the arithmetic mean roughness Ra of the surface of the wafer holder in contact with the semiconductor wafer is 0.3 μm or less, and the mean element length RSm is 40 μm or less. The semiconductor heat treatment member according to claim 1, characterized in that the difference ΔRa between the maximum and minimum values of the arithmetic mean roughness Ra of the surface of the wafer holder is 0.15 μm or less. The semiconductor heat treatment member according to claim 1 or 2, characterized in that the thickness of the wafer holding portion is formed to 1 mm or less. A semiconductor heat treatment member according to any one of claims 1 to 3, characterized in that the thickness of the oxide film formed on the surface of the wafer holder is 0.3 μm or more and 3 μm or less. A method for manufacturing a semiconductor heat treatment member according to any one of claims 1 to 4, comprising the steps of:
Obtaining a ring-shaped silicon carbide substrate;
A step of processing the surface of the substrate with a diamond grindstone so that the arithmetic mean roughness Ra is 0.3 μm or less and the mean length RSm of the elements is 40 μm or less;
and heating the base material in an oxidizing atmosphere to form an oxide film having a thickness of 0.3 μm or more and 3 μm or less on the surface of the base material.

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