JP7547795B2 - Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device - Google Patents

Description

This invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device.

Silicon carbide (SiC) has excellent characteristics such as a higher dielectric breakdown field strength and a higher thermal conductivity than silicon (Si), and is therefore expected to be particularly applicable to power devices. In addition, silicon carbide can form an oxide film (SiO ₂ film) by thermal oxidation, just like silicon. For this reason, in semiconductor devices using silicon carbide (hereinafter referred to as silicon carbide semiconductor devices), development is underway of MOS-type silicon carbide semiconductor devices equipped with a MOS gate (insulated gate made of metal-oxide film-semiconductor) using an oxide film formed by thermal oxidation as a gate insulating film.

15 is a flow chart showing an outline of the formation of a gate insulating film of a conventional silicon carbide semiconductor device. First, an epitaxial film made of silicon carbide is formed on a semiconductor substrate using silicon carbide (hereinafter referred to as a silicon carbide substrate). Next, a high temperature oxide film (High Temperature Oxide: HTO film) is formed on the surface of the epitaxial film by a CVD method or the like (step S31). Next, a gate insulating film made of SiO ₂ is formed by oxynitriding at a high temperature (1300° C.) for 30 minutes (step S32).

As silicon carbide semiconductor devices using such gate insulating films, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) with planar gate and trench gate structures have been commercialized.

A technology is known for forming a silicon carbide semiconductor device with excellent electrical characteristics such as channel mobility by comprising an epitaxial layer formation process for preparing a semiconductor film made of silicon carbide, a gate insulating film formation process for forming an oxide film on the surface of the semiconductor film, a nitrogen annealing process for heat treating the semiconductor film on which the oxide film has been formed in an atmosphere containing nitrogen, and a post-heat treatment process for post-heat treatment in an atmosphere containing an inert gas, the heat treatment temperature in the post-heat treatment process being higher than the heat treatment temperature in the nitrogen annealing process and lower than the melting point of the oxide film (see, for example, Patent Document 1 below).

International Publication No. 2011/111627

In silicon carbide MOSFETs (SiC-MOSFETs), the effect of excess carbon at the interface between the epitaxial film and the gate insulating film is thought to be a factor in reducing the mobility characteristics and reliability of SiC-MOSFETs. In order to reduce this excess carbon, studies are being conducted on the introduction of a nitrogen addition process and an ultra-high temperature oxidation process.

However, even with the conventional nitrogen addition process, the reduction of excess carbon is insufficient, and ultra-high temperature oxidation has the drawback that it is difficult to introduce process equipment suitable for mass production. For this reason, the conventional process was unable to reduce excess carbon, and was unable to adequately prevent a decrease in mobility characteristics and reliability.

The present invention aims to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can reduce excess carbon at the interface between the gate insulating film and the silicon carbide semiconductor in order to solve the problems associated with the conventional technology described above.

In order to solve the above-mentioned problems and achieve the object of the present invention, the method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features. In the step of forming the gate insulating film on a semiconductor layer made of silicon carbide in the method for manufacturing a silicon carbide semiconductor device having a gate insulating film, a first step is performed in which a deposited oxide film is formed on a front surface of the semiconductor layer made of silicon carbide. Next, a second step is performed in which an interface between the semiconductor layer and the deposited oxide film is oxidized and nitrided using a gas containing nitrogen. Next, a third step is performed in which a first oxygen anneal is performed on the interface at a temperature of 300° C. to 650° C. Next, a fourth step is performed in which an inert gas anneal is performed on the interface at a temperature of 900° C. to 1400° C. Next, a fifth step is performed in which a second oxygen anneal is performed on the interface at a temperature of 500° C. to 750° C.

The method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the second to fifth steps are repeated multiple times.

The method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the third to fifth steps are repeated multiple times.

The method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that in the second step, the interface is oxidized and nitrided using nitric oxide or nitrous oxide.

The method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that in the fourth step, the inert gas annealing is performed using nitrogen gas or argon gas.

In order to solve the above problems and achieve the object of the present invention, the silicon carbide semiconductor device according to the present invention has the following features. In a silicon carbide semiconductor device having a gate insulating film on a semiconductor layer made of silicon carbide, the amount of excess carbon present at the interface between the semiconductor layer and the gate insulating film, as evaluated by electron energy loss spectroscopy (EELS), is 0.05 or less in terms of area intensity ratio to silicon carbide, and the CN peak of the gate insulating film, as evaluated by X-ray photoelectron spectroscopy, is 0.09 or less in terms of area intensity ratio to N1s.

According to the above-mentioned invention, after forming the HTO film (deposited oxide film), the interface oxidation is allowed to proceed slightly, and the excess carbon (CC bonds, CO bonds) and CN bonds generated are decomposed and removed by the first oxygen annealing, the remaining CO bonds are desorbed by high-temperature inert gas annealing, and the defects inside the gate insulating film generated by the high-temperature inert gas annealing are terminated by the second oxygen annealing. This makes it possible to reduce the excess carbon (CC bonds, CO bonds) and CN bonds remaining in the gate insulating film. This makes it possible to prevent the mobility characteristics and reliability of the silicon carbide semiconductor device from deteriorating.

The silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention have the effect of reducing excess carbon at the interface between the gate insulating film and the silicon carbide semiconductor.

1 is a cross-sectional view showing a structure of a lateral MOSFET of a silicon carbide semiconductor device according to an embodiment; 1 is a cross-sectional view showing a structure of a vertical MOSFET of a silicon carbide semiconductor device according to an embodiment. FIG. 2 is a loss energy intensity distribution diagram showing a loss energy intensity distribution measured by electron energy loss spectroscopy (EELS) and a component spectrum separated from the loss energy intensity distribution. FIG. 2 is an explanatory diagram illustrating a schematic diagram of measurement points of EELS. FIG. 4B is a loss energy intensity distribution diagram showing the loss energy intensity distribution at each measurement point in FIG. 4A and the component spectrum of excess carbon separated from the loss energy intensity distribution. FIG. 4C is a characteristic diagram showing the area intensity distribution of the component spectrum of excess carbon at each measurement point in FIG. 4B. 1 is a graph showing the N1s spectrum of a sample by photoelectron spectroscopy. 1 is a first flowchart illustrating an overview of formation of a gate insulating film of a silicon carbide semiconductor device according to an embodiment. 1A to 1C are cross-sectional views showing a state during the manufacture of a gate insulating film of a silicon carbide semiconductor device according to an embodiment (part 1). 11A to 11C are cross-sectional views showing a state during the manufacture of a gate insulating film of a silicon carbide semiconductor device according to an embodiment (part 2). 11A to 11C are cross-sectional views showing a state during the manufacture of a gate insulating film of a silicon carbide semiconductor device according to an embodiment (part 3). 4 is a cross-sectional view showing a gate insulating film of the silicon carbide semiconductor device according to the embodiment in the course of manufacturing the same (part 4). FIG. 5 is a cross-sectional view showing a gate insulating film in the process of being manufactured in the silicon carbide semiconductor device according to the embodiment; FIG. 4 is an example of a temperature profile for forming a gate insulating film of a silicon carbide semiconductor device according to an embodiment. 11 is a second flowchart illustrating an overview of formation of a gate insulating film of a silicon carbide semiconductor device according to an embodiment. 1 is a table showing the field effect mobility, the amount of excess carbon, and the CN peak in Examples and Comparative Examples. 1 is a flowchart outlining the formation of a gate insulating film of a conventional silicon carbide semiconductor device.

The preferred embodiments of the silicon carbide semiconductor device and the method of manufacturing the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the attached drawings. In this specification and the attached drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p respectively mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with n or p. Note that in the following description of the embodiment and the attached drawings, the same reference numerals are used for similar configurations, and duplicated explanations are omitted. In addition, in this specification, in the notation of Miller indices, "-" means a bar attached to the index immediately following it, and adding "-" before an index represents a negative index. In addition, the description of "same" or "equivalent" should include up to 5% in consideration of manufacturing variations.

(Embodiment)
The structure of a silicon carbide (SiC) semiconductor device according to the embodiment will be described by taking as examples a planar gate type lateral MOSFET 50 and a vertical MOSFET 70. Fig. 1 is a cross-sectional view showing the structure of a lateral MOSFET of a silicon carbide semiconductor device according to the embodiment.

As shown in FIG. 1 , in the silicon carbide semiconductor device according to the embodiment, a p ^- type base layer 6 is deposited on a first main surface (front surface), for example a (0001) surface (Si surface), of an n + -type silicon carbide substrate 1 .

The n ⁺ type silicon carbide substrate 1 is a silicon carbide single crystal substrate. The p type base layer 6 is a silicon carbide layer formed by epitaxially growing silicon carbide on the n ⁺ type silicon carbide substrate 1. Hereinafter, the n ⁺ type silicon carbide substrate 1 and the p type base layer 6 are collectively referred to as a silicon carbide semiconductor base (a semiconductor substrate made of silicon carbide).

An n ⁺ type source region 7 and an n ⁺ type drain region 19 are selectively provided on the first main surface side of the silicon carbide semiconductor substrate inside the p type base layer 6. The n ⁺ type source region 7 and the n ⁺ type drain region 19 are provided at a distance from each other. A gate insulating film 9 is provided on the upper surface of the p type base layer 6 sandwiched between the n ⁺ type source region 7 and the n ⁺ type drain region 19, and a gate electrode 10 is provided on the gate insulating film 9. A source electrode 12 is provided on the n ⁺ type source region 7, and a drain electrode 13 is provided on the n ⁺ type drain region 19 so as to be in ohmic contact with each other. An interlayer insulating film, a field insulating film, and the like are omitted from the illustration. An insulated gate structure is formed by the gate insulating film 9 and the p type base layer 6 in contact with the gate insulating film 9.

1 is an example, and the p-type base layer 6 may be a well region or the like embedded in the upper part of the n ⁺ -type silicon carbide substrate 1, or the p-type semiconductor substrate itself may be the p-type base layer 6. Furthermore, in the structure of FIG. 1 , a structure in which a low impurity concentration n-type drift region is sandwiched between the p-type base layer 6 and the n ⁺ -type drain region 19 may be used.

Figure 2 is a cross-sectional view showing the structure of a trench-type vertical MOSFET, which is a silicon carbide semiconductor device according to an embodiment. One unit cell (a constituent unit of an element) of the MOSFET is shown in Figure 2, and other unit cells adjacent to the unit cell are not shown. Also, in Figure 2, only the active region is shown, and the edge termination region surrounding the active region is not shown.

The active region is a region through which current flows when the silicon carbide semiconductor device is in the on state. The edge termination region is a region between the active region and the side of the silicon carbide substrate (semiconductor substrate made of silicon carbide: semiconductor chip), and is a region that maintains a breakdown voltage by relaxing the electric field on the front surface of the substrate (front surface of the silicon carbide substrate) side of the drift region. In the edge termination region, for example, a guard ring or a p-type region that constitutes a junction termination extension (JTE) structure, a field plate, a resurf, or other breakdown-resistant structure is arranged. The breakdown voltage is the maximum voltage (withstand voltage) at which the semiconductor device does not malfunction or break down.

As shown in FIG. 2 , in the silicon carbide semiconductor device according to the embodiment, an n ⁻ type silicon carbide epitaxial layer 2 is deposited on a first main surface (front surface), for example a (0001) surface (Si surface), of an n ⁺ type silicon carbide substrate 1.

The n ⁺ type silicon carbide substrate 1 is a silicon carbide single crystal substrate. The n ^- type silicon carbide epitaxial layer 2 has a lower impurity concentration than the n ⁺ type silicon carbide substrate 1, and is, for example, a low-concentration n-type drift layer. An n-type high-concentration region 5 may be provided on the surface of the n ^- type silicon carbide epitaxial layer 2 opposite to the n ⁺ type silicon carbide substrate 1 side. The n-type high-concentration region 5 is a high-concentration n-type drift layer having an impurity concentration lower than the n ⁺ type silicon carbide substrate 1 and higher than the n ^- type silicon carbide epitaxial layer 2.

A p ^- type base layer 6 is provided on the surface of n ^-type silicon carbide epitaxial layer 2 opposite to n + type silicon carbide substrate 1. Hereinafter, n ⁺ type silicon carbide substrate 1, n -type silicon carbide epitaxial layer 2, n ^- type high concentration region 5, and p-type base layer 6 will be collectively referred to as silicon carbide semiconductor base (semiconductor substrate made of silicon carbide) 18.

A drain electrode serving as a back surface electrode 13 is provided on a second main surface (back surface, i.e., the back surface of the silicon carbide semiconductor base 18) of the n ⁺ type silicon carbide substrate 1. A drain electrode pad (not shown) is provided on the surface of the back surface electrode 13.

A trench structure is formed on the first main surface side (p-type base layer 6 side) of the silicon carbide semiconductor substrate 18. Specifically, the trench 16 penetrates the p-type base layer 6 from the surface of the opposite side (first main surface side of the silicon carbide semiconductor substrate 18) of the p-type base layer 6 relative to the n ⁺ -type silicon carbide substrate 1 side to reach the n-type high concentration region 5 (n ^- -type silicon carbide epitaxial layer 2 when the n-type high concentration region 5 is not provided, hereinafter simply referred to as (2)). A gate insulating film 9 is formed on the bottom and side walls of the trench 16 along the inner wall of the trench 16, and a gate electrode 10 is formed inside the gate insulating film 9 in the trench 16. The gate electrode 10 is insulated from the n-type high concentration region 5 (2) and the p-type base layer 6 by the gate insulating film 9. A part of the gate electrode 10 may protrude from the upper side of the trench 16 (the side where the source electrode 12 described later is provided) to the source electrode 12 side. In addition, the surface on which the channel is formed is preferably an m-plane. For example, when a trench structure is formed, the sidewall of the trench 16 is preferably an m-plane.

A first p ⁺ type base region 3 is provided between the trenches 16 in the surface layer on the opposite side (the first main surface side of the silicon carbide semiconductor base 18) of the n-type high concentration region 5 (2) with respect to the n ^{+ type silicon carbide substrate 1 side. A second p + type base region 4 that contacts the bottom of the trench 16 is provided in the n-type high concentration region 5 (2). The second p + type base} region 4 is provided at a position facing the bottom of the trench 16 in the depth direction (the direction from the source electrode 12 to the back electrode). The width of the second p ⁺ type base region 4 is the same as or wider than the width of the trench 16. The bottom of the trench 16 may reach the second p ⁺ type base region 4, or may be located in the n-type high concentration region 5 (2) sandwiched between the p-type base layer 6 and the second p ⁺ type base region 4.

Furthermore, an n ⁺ type region 17 having a peak impurity concentration higher than that of n type high concentration region 5(2) is provided in n ⁻ type silicon carbide epitaxial layer 2 at a position deeper than first p ⁺ type base region 3 between trenches 16. Note that the deeper position refers to a position closer to drain electrode 13 than first p ⁺ type base region 3.

Within p-type base layer 6, n ⁺ -type source region 7 is selectively provided on the first main surface side of silicon carbide semiconductor substrate 18. Also, p ⁺ -type contact region 8 may be selectively provided. Also, n ⁺ -type source region 7 and p ⁺ -type contact region 8 are in contact with each other.

The interlayer insulating film 11 is provided on the entire surface of the first main surface side of the silicon carbide semiconductor substrate 18 so as to cover the gate electrode 10 embedded in the trench 16. The source electrode 12 contacts the n ⁺ type source region 7 and the p type base layer 6 through a contact hole opened in the interlayer insulating film 11. When the p ⁺ type contact region 8 is provided, the source electrode 12 contacts the n ⁺ type source region 7 and the p ⁺ type contact region 8. The source electrode 12 is electrically insulated from the gate electrode 10 by the interlayer insulating film 11. A source electrode pad (not shown) is provided on the source electrode 12. A barrier metal 14 for preventing diffusion of metal atoms from the source electrode 12 to the gate electrode 10 side may be provided between the source electrode 12 and the interlayer insulating film 11.

Although details will be described later, the gate insulating film 9 of the embodiment is formed by performing a first low-temperature oxygen anneal, an inert gas anneal, and a second low-temperature oxygen anneal on the oxynitride film. Therefore, the amount of excess carbon present at the interface between the p-type base layer 6 and the gate insulating film 9 and at the interface between the n ⁺ -type source region 7 and the gate insulating film 9 evaluated by electron energy loss spectroscopy is 0.05 or less in terms of area intensity ratio to silicon carbide. Hereinafter, the p-type base layer 6 and the n ⁺ -type source region 7 are referred to as the silicon carbide layer 22 (see FIG. 4A and FIG. 7 to FIG. 11). In addition, the CN peak of the gate insulating film 9 evaluated by X-ray photoelectron spectroscopy (XPS) is 0.09 or less in terms of area intensity ratio to N1s.

Here, electron energy loss spectroscopy (EELS) is a method for measuring the energy lost by electrons as they pass through atoms through the material. From the distribution of energy loss intensity measured by EELS, it is possible to obtain component spectra separated for each element and for each bond between atoms (single bond or double bond).

First, a method for calculating the area intensity ratio of excess carbon to silicon carbide at the interface between the silicon carbide layer 22 and the gate insulating film 9 (hereinafter referred to as the SiO ₂ /SiC interface 44) will be described. FIG. 3 is a loss energy intensity distribution diagram showing a loss energy intensity distribution measured by EELS and a component spectrum separated from the loss energy intensity distribution. The horizontal axis of FIG. 3 is the electron loss energy (eV), and the vertical axis is the intensity (arbitrary unit (au)) representing the number of electrons obtained for each loss energy (similarly in FIG. 4B ). As shown in FIG. 3 , the loss energy intensity distribution 30 measured by EELS is a silicon carbide component spectrum 32, an excess carbon component spectrum 33, and a component spectrum (not shown) of a carbon atom having a σ bond in an sp ³ hybrid orbital, an sp ² hybrid orbital, or an sp hybrid orbital. Although not shown, the component spectrum of a carbon atom having a σ bond in an sp ³ hybrid orbital, sp ² hybrid orbital, or sp hybrid orbital appears in a range exceeding the maximum intensity of the loss energy of silicon carbide.

From the loss energy intensity distribution 31 after fitting processing of the loss energy intensity distribution 30 near the SiO ₂ /SiC interface 44, the component spectra 32, 33 of silicon carbide and excess carbon are obtained. To calculate the areal intensity ratio of excess carbon to silicon carbide at the SiO ₂ /SiC interface 44, the loss energy intensity distribution 30 is obtained by EELS at multiple measurement points as described above. Then, each component spectrum 33 of excess carbon is separated from the loss energy intensity distribution 30 by EELS at the multiple measurement points, and the separated component spectrum 33 of excess carbon is integrated. In this way, the areal intensity of each component spectrum 33 of excess carbon is calculated.

Specifically, a method for calculating the area intensity of each component spectrum 33 of excess carbon will be described with reference to FIGS. 4A to 4C. FIG. 4A is an explanatory diagram showing a schematic diagram of measurement points of EELS. FIG. 4A shows a state in which the test piece 40 is viewed from the main surface (a surface perpendicular to the SiO ₂ /SiC interface 44) of the test piece 40. FIG. 4B is a loss energy intensity distribution diagram showing the loss energy intensity distribution at each measurement point of FIG. 4A and the component spectrum of excess carbon separated from the loss energy intensity distribution. FIG. 4C is a characteristic diagram showing the area intensity distribution of the component spectrum of excess carbon at each measurement point of FIG. 4B. The horizontal axis of FIG. 4C is the depth from the SiO ₂ /SiC interface 44 to the silicon carbide substrate 1 side (SiC side) and the gate insulating film 9 side (SiO ₂ side), and the vertical axis is the area intensity (arbitrary unit (a.u.)) of the component spectrum of excess carbon.

First, as shown in FIG. 4A, a thin plate-like test piece 40 having a thickness of, for example, about 40 nm is prepared by cutting the n ⁺ type silicon carbide substrate 1 so that the surface perpendicular to the SiO ₂ /SiC interface 44 becomes the main surface in a portion including the n ⁺ type silicon carbide substrate 1 and the gate insulating film 9. The test piece 40 is irradiated with an electron beam in a transmission electron microscope at predetermined measurement points 41-1 to 41-9 from a direction perpendicular to the main surface of the test piece 40, and the energy lost due to the interaction between the electrons and the atoms in the test piece 40 is measured. As a result, the loss energy intensity distribution 30 (see FIG. 3) is obtained at each of the measurement points 41-1 to 41-9 of the test piece 40. At this time, it is preferable to set the measurement points 41-1 to 41-9 to points that do not include damage caused during the preparation of the test piece 40. The number of measurement points of the test piece 40 can be variously changed depending on the conditions of the test piece 40.

The measurement points 41-1 to 41-9 of the test piece 40 are set on a straight line 40a that is parallel to the main surface of the test piece 40 and intersects with the SiO ₂ /SiC interface 44. In FIG. 4A, the measurement points of the test piece 40 are sequentially labeled with reference numerals 41-1 to 41-9 from the deepest measurement point inside the n ⁺ type silicon carbide substrate 1 to the deepest measurement point inside the gate insulating film 9. The straight line 40a on which the measurement points 41-1 to 41-9 of the test piece 40 are set may be at an angle of 90 degrees with respect to the SiO ₂ /SiC interface 44, but preferably has a predetermined inclination angle θ other than 90 degrees. This is because, when the measurement points 41-1 to 41-9 are set on a straight line perpendicular to the SiO ₂ /SiC interface 44, there is a risk of carbon contamination due to EELS measurements at other measurement points.

The inclination angle θ of the straight line 40a on which the measurement points 41-1 to 41-9 of the test piece 40 are set with respect to the SiO ₂ /SiC interface 44 can be changed in various ways, and may be, for example, about 30 degrees. The spot diameter (diameter) r of the electron beam irradiated to each of the measurement points 41-1 to 41-9 of the test piece 40 and the interval w between the adjacent measurement points 41-1 to 41-9 can be changed in various ways, and may be, for example, about 0.2 nm and about 0.4 nm, respectively. However, it is preferable to make the spot diameter r smaller than the measurement interval w, since the measurement points do not overlap. The symbol D1 is the distance on the straight line 40a between the most distant measurement points 41-1 and 41-9 along each of the measurement points 41-1 to 41-9 (hereinafter referred to as the first analysis distance). The symbol D2 is the distance between the most distant measurement points 41-1 and 41-9 in a direction perpendicular to the SiO ₂ /SiC interface 44 (hereinafter referred to as the second analysis distance).

Figure 4B shows the loss energy intensity distribution 30 measured at measurement points 41-1 to 41-9 of these test pieces 40 and the component spectrum 33 of excess carbon separated from the loss energy intensity distribution 30.

4B, the maximum intensity of the loss energy intensity distribution 30 (similarly for the loss energy intensity distribution 31 after fitting) near the SiO ₂ /SiC interface 44 acquired at each of the measurement points 41-1 to 41-9 is maximum at the measurement point 41-1, which is deeper inside the silicon carbide layer 22 than the SiO ₂ /SiC interface 44, and is minimum at the measurement point 41-9, which is deeper inside the gate insulating film 9 than the SiO ₂ /SiC interface 44. The suffixes 1 to 9 of the loss energy intensity distribution 30 and component spectrum 33 in FIG. 4B correspond to the loss energy intensity distribution 30 and component spectrum 33 in FIG. 2 detected at the measurement points 41-1 to 41-9 in FIG. 4A, respectively.

The reason why the loss energy intensity distribution 30 near the _SiO2 /SiC interface 44 is maximum at the measurement point 41-1 is because silicon carbide is being measured, while the reason why the loss energy intensity distribution 31 near the _SiO2 /SiC interface 44 is minimum at the measurement point 41-9 is because the gate insulating film 9 is being measured.

As shown in Fig. 4C, the area intensity of the excess carbon component spectrum 33-1 to 33-9 is highest at the measurement point 41-5 on the SiO ₂ /SiC interface 44 of the test piece 40 in the illustrated example, and is distributed in a mountain shape that decreases as the distance from the SiO ₂ /SiC interface 44 increases. In Fig. 4C, the plots at the measurement points 41-1 to 41-9 of the test piece 40 are indicated by reference numerals 42-1 to 42-9, respectively. At the measurement points 41-1 and 41-9 of the test piece 40 that are the farthest from the SiO ₂ /SiC interface 44, the area intensity of the excess carbon component spectrum is zero. The area intensities 42-1 to 42-9 (Fig. 4C) of the excess carbon component spectrum at the measurement points 41-1 to 41-9 of the test piece 40 are integrated to calculate the integrated intensity of the excess carbon component spectrum 33 (hatched portion in Fig. 4C). The integrated intensity of this excess carbon component spectrum 33 is the amount of excess carbon at the SiO ₂ /SiC interface 44 .

Measurement point 41-1, which is the farthest from SiO ₂ /SiC interface 44, can be regarded as the loss energy intensity distribution of silicon carbide. Therefore, component spectrum 32 caused by carbon in silicon carbide was separated from the loss energy intensity distribution of measurement point 41-1, and its area intensity was taken as the amount of carbon in silicon carbide. The ratio of the integrated intensity (the sum of 42-1 to 42-9) of component spectrum 33 of excess carbon to the area intensity of component spectrum 32 caused by carbon in silicon carbide is the area intensity ratio of excess carbon at SiO ₂ /SiC interface 44 to silicon carbide.

Next, the N1s area intensity ratio of the CN peak evaluated by X-ray photoelectron spectroscopy will be described. XPS is a method for analyzing the constituent elements and their electronic states of a material to be measured by irradiating the surface of the material to be measured with X-rays and measuring the energy of the photoelectrons generated. In this embodiment, the proportion of nitrogen bonded to carbon (CN) among the chemical states of nitrogen is measured by photoelectron spectroscopy.

First, as a pretreatment, the oxide film on the sample was removed with hydrofluoric acid (HF). For XPS, AlKα radiation (1486.6 eV) was used as the light source, and the sample size was approximately 10 mm x 10 mm. From the viewpoint of ease of handling, the sample size is preferably 5 mm x 5 mm or more, but due to the size of the sample holder, it needs to be 100 mm x 100 mm or less.

The sample was also placed at a 45 degree angle to the detector (the standard position for a typical photoelectron spectrometer) for measurement. Based on the type of radiation source and the angle of the detector, the analysis depth of the SiC was 4-5 nm from the surface. The energy range (horizontal axis) for measurement was 396-402 eV, where the N1s peak is detected.

Figure 5 is a graph showing the N1s spectrum of a sample by photoelectron spectroscopy. In Figure 5, the vertical axis shows the intensity of the spectrum in units of photoelectrons per second. The horizontal axis shows the binding energy in units of eV.

The graph shown as N1s in FIG. 5 is the N1s spectrum. The N1s spectrum is fitted with two peaks, and the peak on the high energy side is assigned to CN (a mixture of C≡N, C═N, and C—N), and the peak on the low energy side is assigned to Si ₃ N. Specifically, since the CN spectrum exists only on the high energy side of the peak of the N1s spectrum, a graph of the CN spectrum and the Si ₃ N spectrum can be obtained by fitting a peak near the peak of the N1s spectrum and on the high energy side. This CN spectrum is a mixed spectrum of C≡N, C═N, and C—N.

Next, after removing the background components, the areas of the CN spectrum and N1s spectrum are found, and the ratio of the area of the CN spectrum to the area of the N1s spectrum (area of the CN spectrum/area of the N1s spectrum) is calculated to obtain the area intensity ratio of the CN peak to the N1s area. The area of the N1s spectrum is the area enclosed by the N1s spectrum and the straight line l of C/S = 0. The same applies to the area of the CN spectrum.

(Method of Manufacturing Silicon Carbide Semiconductor Device)
Next, a method for manufacturing a silicon carbide semiconductor device will be described. In the manufacturing method, a method for manufacturing a planar-gate lateral MOSFET 50 will be described. First, an n ⁺ type silicon carbide substrate 1, for example, n-type 4H SiC single crystal (4H-SiC), is prepared. Then, for example, a SiC semiconductor layer is laminated by epitaxial growth or the like on the (0001) surface of the n ⁺ type silicon carbide substrate 1 so as to form the p-type base layer 6 shown in FIG. 1 .

Next, a mask insulating film of, for example, SiO ₂ is deposited on the upper part of the p-type base layer 6 by CVD or the like. Then, a photoresist film is applied on the mask insulating film, and a pattern that serves as an etching mask for the photoresist film is formed using photolithography technology. Then, the mask insulating film is selectively etched using the etching mask to perform patterning. Then, ions of n-type impurities such as nitrogen (N) are implanted using the two-layer structure of the photoresist film and the patterned mask insulating film as an ion implantation mask. By this ion implantation, an n-type ion implantation layer that serves as a source region and an n-type ion implantation layer that serves as a drain region are formed on the upper part of the p-type base layer 6. Next, the two-layer ion implantation mask of the photoresist film and the mask insulating film is removed, and then the n-type ion implantation layer is activated by high-temperature activation annealing at about 1600° C., and the n ⁺ source region 7 and the n ⁺ drain region 19 shown in FIG. 1 are formed.

Next, the p-type base layer 6 having the n ⁺ type source region 7 and the n ⁺ type drain region 19 buried therein is etched or annealed to improve the upper surface of the p-type base layer 6 in which a channel is formed so as to suppress variations in charge distribution.

Here, the excess carbon at the interface between the gate insulating film 9 and the silicon carbide semiconductor is decomposed by oxygen or oxynitride gas, but if the decomposition product, carbon-oxygen bonds (CO bonds), remain in the oxide film or on the SiC surface (oxide film interface), they become the source of interface states and fixed charges, causing mobility and threshold fluctuations. Considering the stability of carbon monoxide (CO) generated by the decomposition of excess carbon, it is thought that this CO bond will be desorbed over time and pass through the oxide film and exit. For this reason, if the decomposition of excess carbon and the desorption of the CO bonds formed by it can be promoted during SiC oxidation in oxygen or oxynitride gas, the excess carbon and CO bonds remaining in the oxide film or on the SiC surface (oxide film interface) can be reduced. Similarly, for CN bonds generated by oxynitride, it is possible to reduce the CN bonds by generating CO and NO from the CN bonds by low-temperature oxygen annealing and desorbing the CO and NO as gases by inert gas annealing.

In the embodiment, in order to promote decomposition and detachment of CC bonds, CO bonds, and CN bonds, the gate insulating film 9 is formed as follows. FIG. 6 is a first flowchart showing an overview of the formation of the gate insulating film of the silicon carbide semiconductor device according to the embodiment. FIGS. 7 to 11 are cross-sectional views showing the state during the manufacturing of the gate insulating film of the silicon carbide semiconductor device according to the embodiment. FIG. 12 is an example of a temperature profile for forming the gate insulating film of the silicon carbide semiconductor device according to the embodiment.

First, a deposited oxide film (HTO film) 20 with a thickness of about 50 nm is formed on the surface of the silicon carbide layer 22 by a CVD method or the like (step S11: first process). The silicon carbide layer 22 is a semiconductor layer that is in contact with the gate insulating film 9, and corresponds to the p-type base layer 6 in FIG. 1 and the p-type base layer 6 and n-type high concentration region 5 in contact with the side wall of the trench 16 in FIG. 2. The state up to this point is shown in FIG. 7. In this state, there are many dangling bonds in Si and C on the top surface of the silicon carbide layer 22 that forms the interface with the deposited oxide film 20.

Next, the silicon carbide layer 22 on which the deposited oxide film 20 is formed is heat-treated in a gas atmosphere containing nitrogen, thereby oxynitriding the interface between the deposited oxide film 20 and the silicon carbide layer 22 (step S12: second process). As a result, a SiO ₂ /SiC interface 21 is formed at the interface between the deposited oxide film 20 and the silicon carbide layer 22. The oxynitridation is performed, for example, using nitric oxide (NO) at a high temperature of 1200° C. or more and 1400° C. or less for 10 minutes (FIG. 12 (1)), to slightly advance oxynitridation at the interface (the surface where the silicon carbide layer 22 and the deposited oxide film 20 contact each other). For example, the interface oxynitridation is advanced to about L=1 nm. Nitrous oxide (N ₂ O) may be used for the oxynitridation. By this process, the dangling bonds present on the outermost surface of the silicon carbide layer 22 are terminated with nitrogen, but at the same time, excess carbon (CC bond, CO bond) is generated. However, since the oxynitriding time is short, the amount of excess carbon is smaller than in the conventional method. The state up to this point is shown in FIG.

Next, a first low-temperature oxygen anneal is performed on the SiO ₂ /SiC interface 21 (step S13: third process). The first low-temperature oxygen anneal is performed, for example, by introducing oxygen (O ₂ ) gas and performing it at a temperature of 300° C. or more and 650° C. or less for 30 minutes ((2) in FIG. 12). As a result, oxygen reaches the SiO ₂ /SiC interface region 21 in FIG. 9, and the excess carbon (CC bond, CO bond) and CN bond generated in the SiO ₂ /SiC interface region 21 are decomposed and removed. A low temperature is preferable for the first low-temperature oxygen anneal in order not to promote oxidation, but a temperature of 300° C. or more is required because the excess carbon decomposition effect is lost if the temperature is less than 300° C. The state up to this point is shown in FIG. 9.

Next, inert gas annealing is performed on the SiO ₂ /SiC interface 21 (step S14: fourth step). The inert gas annealing is performed for 20 minutes at a temperature of 900° C. or higher and 1400° C. or lower using, for example, nitrogen (N ₂ ) gas or argon (Ar) gas (FIG. 12 (3)). The annealing is performed with inert gas so that the interface oxidation does not progress. As a result, the CO bonds remaining in the first low-temperature oxygen annealing are desorbed by the high-temperature inert gas annealing. However, this inert gas annealing causes oxygen vacancies (V _o ) in the deposited oxide film 20, which become defects that deteriorate the MOSFET characteristics. The state up to this point is shown in FIG. 10.

Next, a second low-temperature oxygen anneal is performed on the SiO ₂ /SiC interface 21 (step S15: fifth step). The second low-temperature oxygen anneal is performed, for example, for 15 minutes at a temperature of 500° C. to 750° C. by introducing oxygen gas diluted with an inert gas and having a concentration of 10% ((4) in FIG. 12). As a result, the oxygen vacancies (V _o ) in the deposited oxide film 20 generated by the high-temperature inert gas anneal are terminated by the second low-temperature oxygen anneal. The state up to this point is shown in FIG. 11. The second low-temperature oxygen anneal is preferably performed at a higher temperature than the first low-temperature oxygen anneal in order to terminate the oxygen vacancies. The first and second low-temperature oxygen anneals are performed under conditions that do not advance the oxidation of the interface and suppress the generation of new excess carbon.

Next, it is confirmed whether steps S12 to S15 have been repeated a predetermined number of times (step S16). The predetermined number of times may be once, but is preferably a plurality of times, for example, about three times. If the predetermined number of times has not been repeated (step S16: No), steps S12 to S15 are performed again to thicken the deposited oxide film 20, and the oxidation of the CC bonds, the desorption of the CO generated thereby, and the repair of the oxygen vacancies are repeated, thereby completing the oxynitridation process of the SiO ₂ /SiC interface 21. If the predetermined number of times has been repeated (step S16: Yes), the deposited oxide film 20 becomes the gate insulating film 9, and the formation of the gate insulating film 9 is completed.

Next, a polycrystalline silicon film (doped polysilicon film) with impurities added thereto is deposited by CVD or the like on the upper surface of the p-type base layer 6 on which the gate insulating film 9 is provided. The doped polysilicon film is then patterned into a predetermined shape using photolithography and etching techniques to form the gate electrode 10 as shown in FIG. 1.

Next, an interlayer insulating film (not shown) such as a SiO ₂ film is deposited on the entire surface by CVD or the like so as to cover the gate electrode 10. Then, the interlayer insulating film is patterned using photolithography and etching techniques to open contact holes so that parts of the upper surfaces of the n ⁺ source region 7 and the n ⁺ drain region 19 are exposed. Then, an ohmic contact is formed by a NiSi film at the opening of the contact hole. After that, a metal film containing titanium (Ti), aluminum (Al), or the like is deposited on the entire surface by sputtering or the like so as to cover the contact hole. The deposited metal film is patterned into a desired shape using photolithography and etching techniques, and the source electrode 12 and drain electrode 13 shown in FIG. 1 are formed, respectively, to complete the insulated gate semiconductor device according to the embodiment. Furthermore, although not shown, a passivation film is deposited on the entire surface so as to cover the source electrode 12 and drain electrode 13, and a part of the passivation film is opened, and an electrode pad may be patterned in this opening.

The vertical MOSFET 70 shown in FIG. 2 can be manufactured by forming the gate insulating film 9 as described above and forming other structures by general methods. For this reason, a detailed description of the manufacturing method will be omitted.

Figure 13 is a second flowchart showing an overview of the formation of a gate insulating film of a silicon carbide semiconductor device according to an embodiment. The second flowchart differs from the first flowchart in that the oxynitriding process is performed in one go. That is, in the first flowchart, the oxynitriding process in step S12 is performed multiple times, and excess carbon is removed each time, whereas in the second flowchart, the oxynitriding process is completed all at once, and the decomposition and removal of excess carbon (CC bonds, etc.) is performed in multiple steps.

First, as in the first flowchart, an HTO film (deposited oxide film) 20 with a thickness of about 50 nm is formed on the surface of the silicon carbide layer 22 by a CVD method or the like (step S21: first process).

Next, the silicon carbide layer 22 on which the deposited oxide film 20 is formed is heat-treated in a nitrogen-containing gas atmosphere to oxynitride the _SiO2 /SiC interface 21 (step S22: second process). The oxynitridation is performed for 30 minutes at a high temperature of 1200°C to 1400°C using, for example, nitric oxide (NO), and the interface oxidation proceeds by about 3 nm. Through this process, dangling bonds present on the outermost surface of the silicon carbide layer 22 are terminated with nitrogen, and at the same time, excess carbon (CC bonds, etc.) is generated.

Next, similarly to the first flow chart, a first low-temperature oxygen anneal is performed on the _SiO2 /SiC interface 21 (step S23: third process). The first low-temperature oxygen anneal is performed, for example, by introducing oxygen gas and performing it for 30 minutes at a temperature of 300°C to 650°C. As a result, oxygen reaches the C-C bonds and the like, thereby decomposing and removing the excess carbon (C-C bonds, C-O bonds) and C-N bonds generated at the _SiO2 /SiC interface 21.

Next, in the same manner as in the first flow chart, inert gas annealing is performed on the _SiO2 /SiC interface 21 (step S24: fourth process). The inert gas annealing is performed for 20 minutes at a temperature of 900°C to 1400°C using, for example, nitrogen gas or argon gas. The annealing is performed with the inert gas so that the oxidation of the interface does not progress. As a result, the CO bonds remaining in the first low-temperature oxygen annealing are desorbed by the high-temperature inert gas annealing. At the same time, oxygen deficiency (Vo) occurs in the deposited oxide film 20 near the _SiO2 /SiC interface 21.

Next, similarly to the first flow chart, a second low-temperature oxygen anneal is performed on the _SiO2 /SiC interface 21 (step S25: fifth process). The second low-temperature oxygen anneal is performed, for example, by introducing oxygen gas and at a temperature of 500°C to 750°C for, for example, 15 minutes. As a result, the oxygen vacancies (Vo) in the deposited oxide film 20 generated by the high-temperature inert gas anneal are terminated by the second low-temperature oxygen anneal. The first and second low-temperature oxygen anneals are performed under conditions that do not advance oxidation of the interface and suppress the generation of new excess carbon.

Next, it is confirmed whether steps S23 to S25 have been repeated a predetermined number of times (step S26). The predetermined number of times may be once, but is preferably multiple times, for example, about three times. If the predetermined number of times has not been repeated (step S26: No), steps S23 to S25 are performed again to repeat the oxidation of the CC bonds, the desorption of the CO generated thereby, and the repair of the oxygen vacancies. If the predetermined number of times has been repeated (step S26: Yes), the deposited oxide film 20 becomes the gate insulating film 9, and the formation of the gate insulating film 9 is completed.

The following shows the results of measuring the mobility of MOSFETs formed using the manufacturing method of the embodiment under various conditions. Also shown are the results of measuring the mobility of MOSFETs formed using a conventional manufacturing method. Here, Examples 1-1 to 1-4 and Comparative Examples 1-1 to 1-4 were performed to confirm the temperature dependency of low-temperature oxygen annealing, and Examples 1-5 to 1-6 and Comparative Examples 1-5 to 1-6 were performed to confirm the temperature dependency of inert gas annealing. Example 2 and Comparative Example 2 show the results of measuring the mobility of a vertical MOSFET 70.

(Example 1-1)
First, a planar gate lateral MOSFET 50 was fabricated using a 4H—SiC substrate having a surface inclined by 4 degrees from the (0001) plane as the main surface of the substrate as the n ⁺ -type silicon carbide substrate 1. In the process of forming the gate insulating film 9, the following process was carried out after forming a high-temperature deposition film (HTO film).
(1) After treatment in a nitric oxide (NO) gas atmosphere (10%) at 1300°C for 10 minutes, the introduction of NO gas is stopped and the temperature is lowered to 600°C.
(2) Oxygen gas is introduced, and a first low-temperature oxygen anneal is carried out for 30 minutes in an atmosphere of 600° C. and 1 atm. After the treatment, the introduction of oxygen is stopped, and the temperature is increased to 1300° C.
(3) Argon gas is introduced and argon annealing is performed for 20 minutes in an atmosphere of 1300° C. and 1 atm. After the treatment, the introduction of argon gas is stopped and the temperature is reduced to 700° C.
(4) 10% oxygen gas is introduced, and a second low-temperature oxygen anneal is carried out at 700° C. and 1 atm for 15 minutes.
The above steps (1) to (4) were repeated three times to form the gate insulating film 9. The thickness of the formed gate insulating film 9 was 60 nm. The mobility of the lateral MOSFET 50 of Example 1 was about 80 cm ² /Vs.

(Example 1-2)
First, a planar gate lateral MOSFET 50 was fabricated using a 4H—SiC substrate having a surface inclined by 4 degrees from the (0001) plane as the main surface of the substrate as the n ⁺ -type silicon carbide substrate 1. In the process of forming the gate insulating film 9, the following process was carried out after forming a high-temperature deposition film (HTO film).
(1) After treatment in a nitric oxide (NO) gas atmosphere (10%) at 1300°C for 10 minutes, the introduction of NO gas is stopped and the temperature is reduced to 650°C.
(2) Oxygen gas is introduced, and a first low-temperature oxygen anneal is carried out for 30 minutes in an atmosphere of 650° C. and 1 atm. After the treatment, the introduction of oxygen is stopped, and the temperature is increased to 1300° C.
(3) Argon gas is introduced, and argon annealing is performed for 20 minutes in an atmosphere of 1300° C. and 1 atm. After the treatment, the introduction of argon gas is stopped, and the temperature is reduced to 750° C.
(4) 10% oxygen gas is introduced, and a second low-temperature oxygen anneal is carried out at 750° C. and 1 atm for 10 minutes.
The above steps (1) to (4) were repeated three times to form the gate insulating film 9. The thickness of the formed gate insulating film 9 was 60 nm. The mobility of the lateral MOSFET 50 of Example 1-2 was about 75 cm ² /Vs.

(Examples 1 to 3)
First, a planar gate lateral MOSFET 50 was fabricated using a 4H—SiC substrate having a surface inclined by 4 degrees from the (0001) plane as the main surface of the substrate as the n ⁺ -type silicon carbide substrate 1. In the process of forming the gate insulating film 9, the following process was carried out after forming a high-temperature deposition film (HTO film).
(1) After treatment in a nitric oxide (NO) gas atmosphere (10%) at 1300°C for 10 minutes, the introduction of NO gas is stopped and the temperature is lowered to 300°C.
(2) Oxygen gas is introduced, and a first low-temperature oxygen anneal is carried out for 120 minutes in an atmosphere of 300° C. and 1 atm. After the treatment, the introduction of oxygen is stopped, and the temperature is increased to 1300° C.
(3) Argon gas is introduced, and argon annealing is performed for 20 minutes in an atmosphere of 1300° C. and 1 atm. After the treatment, the introduction of argon gas is stopped, and the temperature is reduced to 500° C.
(4) 10% oxygen gas is introduced, and a second low-temperature oxygen anneal is carried out at 500° C. and 1 atm for 30 minutes.
The above steps (1) to (4) were repeated three times to form the gate insulating film 9. The thickness of the formed gate insulating film 9 was 60 nm. The mobility of the lateral MOSFET 50 of Example 1-3 was about 75 cm ² /Vs.

(Examples 1 to 4)
First, a planar gate lateral MOSFET 50 was fabricated using a 4H—SiC substrate having a surface inclined by 4 degrees from the (0001) plane as the main surface of the substrate as the n ⁺ -type silicon carbide substrate 1. In the process of forming the gate insulating film 9, the following process was carried out after forming a high-temperature deposition film (HTO film).
(1) After treatment in a nitric oxide (NO) gas atmosphere (10%) at 1300°C for 30 minutes, the introduction of NO gas is stopped and the temperature is reduced to 650°C.
(2) Oxygen gas is introduced, and a first low-temperature oxygen anneal is carried out for 30 minutes in an atmosphere of 650° C. and 1 atm. After the treatment, the introduction of oxygen is stopped, and the temperature is increased to 1300° C.
(3) Argon gas is introduced, and argon annealing is performed for 20 minutes in an atmosphere of 1300° C. and 1 atm. After the treatment, the introduction of argon gas is stopped, and the temperature is reduced to 750° C.
(4) 10% oxygen gas is introduced, and a second low-temperature oxygen anneal is carried out at 750° C. and 1 atm for 10 minutes.
The above steps (2) to (4) were repeated three times to form the gate insulating film 9. The thickness of the formed gate insulating film 9 was 60 nm. The mobility of the lateral MOSFET 50 of Example 1-4 was about 77 cm ² /Vs.

(Examples 1 to 5)
First, a planar gate lateral MOSFET 50 was fabricated using a 4H—SiC substrate having a surface inclined by 4 degrees from the (0001) plane as the main surface of the substrate as the n ⁺ -type silicon carbide substrate 1. In the process of forming the gate insulating film 9, the following process was carried out after forming a high-temperature deposition film (HTO film).
(1) After treatment in a nitric oxide (NO) gas atmosphere (10%) at 1300°C for 10 minutes, the introduction of NO gas is stopped and the temperature is lowered to 600°C.
(2) Oxygen gas is introduced, and a first low-temperature oxygen anneal is carried out for 30 minutes in an atmosphere of 600° C. and 1 atm. After the treatment, the introduction of oxygen is stopped, and the temperature is increased to 900° C.
(3) Argon gas is introduced, and argon annealing is performed for 90 minutes in an atmosphere of 900° C. and 1 atm. After the treatment, the introduction of argon gas is stopped, and the temperature is reduced to 700° C.
(4) 10% oxygen gas is introduced, and a second low-temperature oxygen anneal is carried out at 700° C. and 1 atm for 15 minutes.
The above steps (1) to (4) were repeated three times to form the gate insulating film 9. The thickness of the formed gate insulating film 9 was 60 nm. The mobility of the lateral MOSFET 50 of Example 1-5 was about 80 cm ² /Vs.

(Examples 1 to 6)
First, a planar gate lateral MOSFET 50 was fabricated using a 4H—SiC substrate having a surface inclined by 4 degrees from the (0001) plane as the main surface of the substrate as the n ⁺ -type silicon carbide substrate 1. In the process of forming the gate insulating film 9, the following process was carried out after forming a high-temperature deposition film (HTO film).
(1) After treatment in a nitric oxide (NO) gas atmosphere (10%) at 1300°C for 10 minutes, the introduction of NO gas is stopped and the temperature is lowered to 600°C.
(2) Oxygen gas is introduced, and a first low-temperature oxygen anneal is carried out for 30 minutes in an atmosphere of 600° C. and 1 atm. After the treatment, the introduction of oxygen is stopped, and the temperature is increased to 1400° C.
(3) Argon gas is introduced, and argon annealing is performed for 15 minutes in an atmosphere of 1400° C. and 1 atm. After the treatment, the introduction of argon gas is stopped, and the temperature is reduced to 700° C.
(4) 10% oxygen gas is introduced, and a second low-temperature oxygen anneal is carried out at 700° C. and 1 atm for 15 minutes.
The above steps (1) to (4) were repeated three times to form the gate insulating film 9. The thickness of the formed gate insulating film 9 was 60 nm. The mobility of the lateral MOSFET 50 of Example 1-6 was about 80 cm ² /Vs.

(Comparative Example 1-1)
First, a planar gate lateral MOSFET 50 was fabricated using a 4H—SiC substrate having a surface inclined by 4 degrees from the (0001) plane as the main surface of the substrate as the n ⁺ -type silicon carbide substrate 1. In the process of forming the gate insulating film 9, the following process was carried out after forming a high-temperature deposition film (HTO film).
(1) Treatment was carried out in a nitric oxide (NO) gas atmosphere (10%) at 1300° C. for 30 minutes.
The thickness of the formed gate insulating film 9 was 60 nm. The mobility of the lateral MOSFET 50 of Comparative Example 1-1 was about 20 cm ² /Vs.

(Comparative Example 1-2)
First, a planar gate lateral MOSFET 50 was fabricated using a 4H—SiC substrate having a surface inclined by 4 degrees from the (0001) plane as the main surface of the substrate as the n ⁺ -type silicon carbide substrate 1. In the process of forming the gate insulating film 9, the following process was carried out after forming a high-temperature deposition film (HTO film).
(1) After treatment in a nitric oxide (NO) gas atmosphere (10%) at 1300°C for 10 minutes, the introduction of NO gas is stopped and the temperature is lowered to 250°C.
(2) Oxygen gas is introduced, and a first low-temperature oxygen anneal is carried out for 180 minutes in an atmosphere of 250° C. and 1 atm. After the treatment, the introduction of oxygen is stopped, and the temperature is increased to 1300° C.
(3) Argon gas is introduced, and argon annealing is performed for 20 minutes in an atmosphere of 1300° C. and 1 atm. After the treatment, the introduction of argon gas is stopped, and the temperature is reduced to 450° C.
(4) 10% oxygen gas is introduced, and a second low-temperature oxygen anneal is carried out at 450° C. and 1 atm for 60 minutes.
The above steps (1) to (4) were repeated three times to form the gate insulating film 9. The thickness of the formed gate insulating film 9 was 60 nm. The mobility of the lateral MOSFET 50 of Comparative Example 1-2 was about 25 cm ² /Vs.

(Comparative Example 1-3)
First, a planar gate lateral MOSFET 50 was fabricated using a 4H—SiC substrate having a surface inclined by 4 degrees from the (0001) plane as the main surface of the substrate as the n ⁺ -type silicon carbide substrate 1. In the process of forming the gate insulating film 9, the following process was carried out after forming a high-temperature deposition film (HTO film).
(1) After treatment in a nitric oxide (NO) gas atmosphere (10%) at 1300°C for 10 minutes, the introduction of NO gas is stopped and the temperature is lowered to 700°C.
(2) Oxygen gas is introduced, and a first low-temperature oxygen anneal is carried out for 20 minutes in an atmosphere of 700° C. and 1 atm. After the treatment, the introduction of oxygen is stopped, and the temperature is increased to 1300° C.
(3) Argon gas is introduced, and argon annealing is performed for 20 minutes in an atmosphere of 1300° C. and 1 atm. After the treatment, the introduction of argon gas is stopped, and the temperature is reduced to 750° C.
(4) 10% oxygen gas is introduced, and a second low-temperature oxygen anneal is carried out at 750° C. and 1 atm for 10 minutes.
The above steps (1) to (4) were repeated three times to form the gate insulating film 9. The thickness of the formed gate insulating film 9 was 60 nm. The mobility of the lateral MOSFET 50 of Comparative Example 1-3 was about 25 cm ² /Vs.

(Comparative Examples 1 to 4)
First, a planar gate lateral MOSFET 50 was fabricated using a 4H—SiC substrate having a surface tilted 4 degrees from the (0001) plane as the main surface of the substrate as the n ⁺ -type silicon carbide substrate 1. In the process of forming the gate insulating film 9, the following process was carried out after forming a high-temperature deposition film (HTO film).
(1) After treatment in a nitric oxide (NO) gas atmosphere (10%) at 1300°C for 10 minutes, the introduction of NO gas is stopped and the temperature is lowered to 800°C.
(2) Oxygen gas is introduced, and a first low-temperature oxygen anneal is carried out for 10 minutes in an atmosphere of 800° C. and 1 atm. After the treatment, the introduction of oxygen is stopped, and the temperature is increased to 1300° C.
(3) Argon gas is introduced, and argon annealing is performed for 20 minutes in an atmosphere of 1300° C. and 1 atm. After the treatment, the introduction of argon gas is stopped, and the temperature is reduced to 800° C.
(4) 10% oxygen gas is introduced, and a second low-temperature oxygen anneal is carried out at 800° C. and 1 atm for 5 minutes.
The above steps (1) to (4) were repeated three times to form the gate insulating film 9. The thickness of the formed gate insulating film 9 was 60 nm. The mobility of the lateral MOSFET 50 of Comparative Example 1-4 was about 15 cm ² /Vs.

(Comparative Example 1-5)
First, a planar gate lateral MOSFET was fabricated using a 4H-SiC substrate having a surface tilted 4 degrees from the (0001) plane as the main surface of the n ⁺ -type silicon carbide substrate 1. In the process of forming the gate insulating film 9, the following process was carried out after forming a high-temperature deposition film (HTO film).
(1) After treatment in a nitric oxide (NO) gas atmosphere (10%) at 1300°C for 10 minutes, the introduction of NO gas is stopped and the temperature is lowered to 600°C.
(2) Oxygen gas is introduced, and a first low-temperature oxygen anneal is carried out for 30 minutes in an atmosphere of 600° C. and 1 atm. After the treatment, the introduction of oxygen is stopped, and the temperature is increased to 800° C.
(3) Argon gas is introduced, and argon annealing is performed for 120 minutes in an atmosphere of 800° C. and 1 atm. After the treatment, the introduction of argon gas is stopped, and the temperature is reduced to 700° C.
(4) 10% oxygen gas is introduced, and a second low-temperature oxygen anneal is carried out at 700° C. and 1 atm for 15 minutes.
The above steps (1) to (4) were repeated three times to form the gate insulating film 9. The thickness of the formed gate insulating film 9 was 60 nm. The mobility of the lateral MOSFET 50 of Comparative Example 1-5 was about 40 cm ² /Vs.

(Comparative Example 1-6)
First, a planar gate lateral MOSFET 50 was fabricated using a 4H—SiC substrate having a surface inclined by 4 degrees from the (0001) plane as the main surface of the substrate as the n ⁺ -type silicon carbide substrate 1. In the process of forming the gate insulating film 9, the following process was carried out after forming a high-temperature deposition film (HTO film).
(1) After treatment in a nitric oxide (NO) gas atmosphere (10%) at 1300°C for 10 minutes, the introduction of NO gas is stopped and the temperature is lowered to 600°C.
(2) Oxygen gas is introduced, and a first low-temperature oxygen anneal is carried out for 30 minutes in an atmosphere of 600° C. and 1 atm. After the treatment, the introduction of oxygen is stopped, and the temperature is increased to 1500° C.
(3) Argon gas is introduced, and argon annealing is performed for 10 minutes in an atmosphere of 1500° C. and 1 atm. After the treatment, the introduction of argon gas is stopped, and the temperature is reduced to 700° C.
(4) 10% oxygen gas is introduced, and a second low-temperature oxygen anneal is carried out at 700° C. and 1 atm for 15 minutes.
The above steps (1) to (4) were repeated three times to form the gate insulating film 9. The thickness of the formed gate insulating film 9 was 60 nm. The mobility of the lateral MOSFET 50 of Comparative Example 1-6 was about 30 cm ² /Vs.

Example 2
First, a trench-type vertical MOSFET 70 was fabricated using a 4H-SiC substrate having a surface tilted by 4 degrees from the (0001) plane as the main surface of the substrate as the n ⁺ -type silicon carbide substrate 1. The gate insulating film 9 was formed in the same manner as in Example 1-1. The thickness of the formed gate insulating film 9 was 60 nm. The mobility of the vertical MOSFET 70 of Example 2 was approximately 120 cm ² /Vs.

(Comparative Example 2)
First, a trench-type vertical MOSFET 70 was fabricated using a 4H-SiC substrate having a surface tilted 4 degrees from the (0001) plane as the main surface of the substrate as the n ⁺ -type silicon carbide substrate 1. The gate insulating film 9 was formed in the same manner as in Comparative Example 1-1. The thickness of the formed gate insulating film 9 was 60 nm. The mobility of the vertical MOSFET 70 of Example 2 was approximately 60 cm ² /Vs.

Figure 14 is a table showing the field effect mobility, excess carbon amount, and CN peak in the examples and comparative examples. Here, the excess carbon amount and CN peak in Figure 14 were measured by the EELS and XPS described above, respectively.

As shown in Figure 14, the amount of excess carbon (CC bonds, CO bonds) and the CN peak are both lower in the examples than in the comparative examples, and it can be seen that components that can become defects are reduced. When the amount of excess carbon is 0.05 or less in terms of the area intensity ratio to SiC and the CN peak is 0.09 or less in terms of the area intensity ratio to N1s, a significant improvement in mobility is observed. Therefore, it is believed that the improvement in mobility is due to the reduction in these components.

In addition, from Comparative Examples 1-2 to 1-4, when the first low-temperature oxygen annealing temperature is less than 300°C and the second low-temperature oxygen annealing temperature is less than 500°C, the low thermal energy causes no excess carbon decomposition effect or no oxygen vacancy termination effect in the oxide film. When the first low-temperature oxygen annealing temperature is 700°C or higher, the oxygen adsorption effect on excess carbon decomposition disappears, and when the second low-temperature oxygen annealing temperature is 800°C or higher, oxidation of SiC begins to occur, causing an increase in the amount of excess carbon.

In addition, Comparative Example 1-5 shows that when the inert gas annealing temperature using argon is less than 900°C, the CO desorption effect is lost due to the low thermal energy, and Comparative Example 1-6 shows that when the temperature is 1500°C or higher, the amount of excess carbon increases due to the influence of oxygen remaining in the atmosphere. Although not shown in the examples, the same effect was obtained when nitrogen gas was used instead of argon in the inert gas annealing.

From the above results, the temperature range of the first low-temperature oxygen anneal is preferably 300°C or higher and 650°C or lower, the temperature range of the second low-temperature oxygen anneal is preferably 500°C or higher and 750°C or lower, and the temperature range of the inert gas anneal is preferably 900°C or higher and 1400°C or lower.

The processing times for the first and second low-temperature oxygen anneals and inert gas anneals may be longer than those shown in the examples when performed at the relevant processing temperatures (because these are low-temperature processes and the reaction and desorption rates are slow), but considering the efficiency of the process, it is preferable to keep the processing times within two hours.

Although not shown in Figure 14, in Examples 1-1 to 1-6 and 2, even if steps (1) to (4) above are performed once, the same effects as in the examples are obtained with respect to the field effect mobility, the amount of excess carbon, and the CN peak.

As described above, according to the embodiment, after forming the HTO film, the interface oxidation is slightly advanced, and the excess carbon (CC bonds, CO bonds) and CN bonds generated are decomposed and removed by the first low-temperature oxygen anneal, the remaining CO bonds are desorbed by the high-temperature inert gas anneal, and the internal defects generated by the high-temperature inert gas anneal are terminated by the second low-temperature oxygen anneal. This makes it possible to reduce the excess carbon (CC bonds, CO bonds) and CN bonds remaining in the gate insulating film. This makes it possible to prevent the mobility characteristics and reliability of the silicon carbide semiconductor device from deteriorating.

The present invention can be modified in various ways without departing from the spirit of the invention, and in each of the above-mentioned embodiments, for example, the dimensions of each part and the impurity concentration are set in various ways according to the required specifications. The present invention can also be applied to silicon carbide semiconductor devices of various structures that have a MOS gate with a thermal oxide film provided on the main surface of a silicon carbide substrate as the gate insulating film. For example, the present invention can be applied to MOS-type silicon carbide semiconductor devices such as MOSFETs and IGBTs (Insulated Gate Bipolar Transistors), and the structure may be any of vertical, horizontal, planar gate, and trench gate structures.

As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention are useful for MOS-type silicon carbide semiconductor devices.

DESCRIPTION OF SYMBOLS 1 n ⁺ type silicon carbide substrate 2 ^n- type silicon carbide epitaxial layer 3 First p ⁺ type base region 4 Second p ⁺ type base region 5 N type high concentration region 6 p type base layer 7 n ⁺ type source region 8 p ⁺ type contact region 9 Gate insulating film 10 Gate electrode 11 Interlayer insulating film 12 Source electrode 13 Drain electrode 14 Barrier metal 16 Trench 17 n ⁺ type region 18 Silicon carbide semiconductor substrate 19 n ⁺ type drain region 20 Deposited oxide film 21 _SiO2 /SiC interface 22 Silicon carbide layer 50 Lateral MOSFET
70 Vertical MOSFET

Claims (6)

1. A method for manufacturing a silicon carbide semiconductor device having a gate insulating film, comprising:
The step of forming the gate insulating film on the semiconductor layer made of silicon carbide includes:
A first step of forming a deposited oxide film on a front surface of the semiconductor layer made of silicon carbide;
a second step of oxynitriding the interface between the semiconductor layer and the deposited oxide film using a nitrogen-containing gas;
a third step of performing a first oxygen anneal on the interface at a temperature of 300° C. or more and 650° C. or less ;
A fourth step of performing inert gas annealing on the interface at a temperature of 900° C. or more and 1400° C. or less ;
A fifth step of performing a second oxygen anneal on the interface at a temperature of 500° C. to 750° C.;
A method for manufacturing a silicon carbide semiconductor device comprising the steps of: The method for manufacturing a silicon carbide semiconductor device according to claim 1, characterized in that the second to fifth steps are repeated multiple times. The method for manufacturing a silicon carbide semiconductor device according to claim 1, characterized in that the third to fifth steps are repeated multiple times. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 3, characterized in that in the second step, the interface is oxidized and nitrided using nitric oxide or nitrous oxide. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 4, characterized in that in the fourth step, the inert gas annealing is performed using nitrogen gas or argon gas. A silicon carbide semiconductor device having a gate insulating film on a semiconductor layer made of silicon carbide,
The amount of excess carbon present at the interface between the semiconductor layer and the gate insulating film, as evaluated by electron energy loss spectroscopy, is 0.05 or less in terms of an area intensity ratio to silicon carbide, and
a CN peak of the gate insulating film evaluated by X-ray photoelectron spectroscopy to have an area intensity ratio to N1s of 0.09 or less;

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