JP7548232B2 - METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND SILICON CARBIDE SEMICONDUCTOR DEVICE - Google Patents

Description

The present disclosure relates to a method for manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device.

This application claims priority to Japanese Application No. 2019-131803, filed on July 17, 2019, and incorporates by reference all of the contents of said Japanese application.

In the manufacturing process of silicon carbide semiconductor devices, when forming a drain electrode, etc., there is a process in which a Ni (nickel) film is formed on the surface of the silicon carbide substrate and then heat-treated to alloy the Si (silicon) contained in the silicon carbide substrate with the Ni to form an ohmic electrode.

Japanese Patent Application Publication No. 2005-276978 Japanese Patent Application Publication No. 2017-175115 Japanese Patent Application Publication No. 2012-99598

The method for manufacturing a silicon carbide semiconductor device disclosed herein includes the steps of preparing a silicon carbide substrate, forming an insulating film on one main surface of the silicon carbide substrate, forming a contact hole in the insulating film and exposing one main surface of the silicon carbide substrate at the bottom of the contact hole, and forming a Si film on the bottom of the contact hole. The method further includes the steps of forming a Ni film on the Si film, performing a first heat treatment at a first temperature at which Ni and Si react after the Ni film forming step, removing an unreacted portion of the Ni film that has not reacted with the Si film by wet etching after the first heat treatment, and performing a second heat treatment at a second temperature higher than the first temperature after the unreacted portion removing step.

FIG. 1 is an explanatory diagram (1) of a method for manufacturing a semiconductor device. FIG. 2 is an explanatory diagram (2) of the method for manufacturing a semiconductor device. FIG. 3 is an explanatory diagram (3) of the method for manufacturing a semiconductor device. FIG. 4 is an explanatory diagram (4) of the method for manufacturing a semiconductor device. FIG. 5 is an explanatory diagram (5) of the method for manufacturing a semiconductor device. FIG. 6 is a flowchart of the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. FIG. 7 is an explanatory diagram (1) of the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. FIG. 8 is an explanatory diagram (2) of the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. FIG. 9 is an explanatory diagram (3) of the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. FIG. 10 is an explanatory diagram (4) of the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. FIG. 11 is an explanatory diagram (5) of the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. FIG. 12 is an explanatory diagram (6) of the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. FIG. 13 is an explanatory diagram (7) of the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. FIG. 14 is an explanatory diagram (8) of the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. FIG. 15 is an explanatory diagram (1) of the manufacturing method of the modified example 1 of the semiconductor device according to the first embodiment of the present disclosure. FIG. 16 is an explanatory diagram (2) of the manufacturing method of the modified example 1 of the semiconductor device according to the first embodiment of the present disclosure. FIG. 17 is an explanatory diagram (1) of the manufacturing method of the modified example 2 of the semiconductor device according to the first embodiment of the present disclosure. FIG. 18 is an explanatory diagram (2) of the manufacturing method of the modified example 2 of the semiconductor device according to the first embodiment of the present disclosure. FIG. 19 is an explanatory diagram of a manufacturing method of the semiconductor device according to the third modification of the first embodiment of the present disclosure. FIG. 20 is an explanatory diagram of the semiconductor device according to the first embodiment of the present disclosure. FIG. 21 is an explanatory diagram (1) of the manufacturing method of the semiconductor device according to the second embodiment of the present disclosure. FIG. 22 is an explanatory diagram (2) of the manufacturing method of the semiconductor device according to the second embodiment of the present disclosure. FIG. 23 is an explanatory diagram (3) of the method for manufacturing a semiconductor device according to the second embodiment of the present disclosure. FIG. 24 is an explanatory diagram (4) of the method for manufacturing a semiconductor device according to the second embodiment of the present disclosure. FIG. 25 is an explanatory diagram (5) of the method for manufacturing a semiconductor device according to the second embodiment of the present disclosure. FIG. 26 is an explanatory diagram (6) of the method for manufacturing a semiconductor device according to the second embodiment of the present disclosure. FIG. 27 is an explanatory diagram (7) of the method for manufacturing a semiconductor device according to the second embodiment of the present disclosure. FIG. 28 is an explanatory diagram (1) of a manufacturing method of a modified example of the semiconductor device according to the second embodiment of the present disclosure. FIG. 29 is an explanatory diagram (2) of a manufacturing method of a modified example of the semiconductor device according to the second embodiment of the present disclosure. FIG. 30 is an explanatory diagram (3) of a manufacturing method of a modified example of the semiconductor device according to the second embodiment of the present disclosure. FIG. 31 is an explanatory diagram (4) of a manufacturing method of a modified example of the semiconductor device according to the second embodiment of the present disclosure.

[Problem to be solved by this disclosure]
Since silicon carbide substrates contain C (carbon) in addition to Si, when the Si contained in silicon carbide is used for alloying with Ni, unreacted C is generated, and this unreacted C may precipitate on the surface of the alloyed ohmic electrode, etc. If C precipitates on the surface of the ohmic electrode in this way, there is a risk of causing a decrease in reliability, etc., when a metal wiring layer is formed on the ohmic electrode.

For this reason, there is a demand for a method for manufacturing a silicon carbide semiconductor device that can form an ohmic electrode without carbon being deposited on the surface of the ohmic electrode.

[Effects of the present disclosure]
According to the present disclosure, when an ohmic electrode is formed on a surface of a silicon carbide substrate, precipitation of carbon on the surface of the ohmic electrode can be suppressed.

The form of implementation is described below.

[Description of the embodiments of the present disclosure]
First, the embodiments of the present disclosure will be described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description thereof will not be repeated.

[1] A method for manufacturing a semiconductor device according to one embodiment of the present disclosure includes the steps of preparing a silicon carbide substrate, forming an insulating film on one main surface of the silicon carbide substrate, forming a contact hole in the insulating film and exposing one main surface of the silicon carbide substrate at a bottom surface of the contact hole, forming a Si film on the bottom surface of the contact hole, forming a Ni film on the Si film, performing a first heat treatment at a first temperature at which Ni and Si react after the Ni film forming step, removing an unreacted portion of the Ni film that has not reacted with the Si film by wet etching after the first heat treatment, and performing a second heat treatment at a second temperature higher than the first temperature after the unreacted portion removing step.

This allows an ohmic electrode to be formed on the surface of the silicon carbide substrate without precipitating carbon on the surface of the ohmic electrode.

[2] The process of forming a Si film on the bottom surface of the contact hole includes a process of forming a first Si film on the bottom and side surfaces of the contact hole and on the upper surface of the insulating film, and after the process of forming the first Si film, a process of removing at least the first Si film on the upper surface of the insulating film by dry etching.

This determines the area where the nickel silicide reaction precursor is formed. Ni is generally difficult to dry etch, so microfabrication by dry etching is not possible, but by dry etching the first Si film, the nickel silicide reaction precursor can be formed with the same microfabrication precision as dry etching.

[3] The first temperature is greater than or equal to 200°C and less than or equal to 400°C.

This allows a reactive precursor layer of nickel silicide to be formed.

[4] The second temperature is greater than or equal to 800°C and less than or equal to 1100°C.

This allows the reactive precursor layer to form an ohmic electrode in the portion that is in contact with the main surface of the silicon carbide substrate.

[5] The thickness of the Si film at the bottom of the contact hole is 5 nm or more and 100 nm or less.

If the Si film is thinner than 5 nm, the effect of local variations within the surface, even variations of a few nm, cannot be ignored, making it difficult to control the process. Also, if the film thickness is thicker than 100 nm, the amount becomes too large to react with the Ni film, resulting in non-uniform reaction precursors.

[6] The thickness of the Ni film at the bottom of the contact hole is 5 nm or more and 100 nm or less.

If the Ni film is thinner than 5 nm, the effect of local variations within the surface, even variations of a few nm, cannot be ignored, making it difficult to control the process. Also, if the film thickness is thicker than 100 nm, the amount becomes too large to react with the Si film, resulting in non-uniform reaction precursors.

[7] The Si film is also formed on the side of the contact hole.

Generally, dry etching has a fast etching rate in the vertical direction and a slow etching rate in the horizontal direction, so even if you try to leave only the bottom of the contact hole, some of it may remain on the sides as well. Of course, it is possible to remove it by innovating the process.

[8] At the bottom of the contact hole with the Ni film formed on the Si film, when the number of Si atoms contained in the Si film per unit area accumulated in the thickness direction is N _Si and the number of Ni atoms contained in the Ni film per unit area accumulated in the thickness direction _{is N Ni ≧} N _Si /2 holds.

When silicon carbide and nickel alone are reacted to create an ohmic electrode, Ni ₂ Si is formed as the main component. In this embodiment, in order to match the reaction precursor to this composition, it is necessary to adjust the atomic number to Ni:Si=2:1. In addition, by increasing the amount of Ni from this composition, the reactivity with silicon carbide is improved. Conversely, if the amount of Ni is reduced from this composition, Ni becomes insufficient and it becomes difficult to react with silicon carbide.

[9] A semiconductor device comprising: a silicon carbide substrate having a main surface; an insulating film provided on the main surface of the silicon carbide substrate; a contact hole provided in the insulating film; a first electrode provided on a portion of a bottom surface of the contact hole and in contact with the silicon carbide substrate; and a second electrode provided on a side surface of the contact hole, spaced apart from the first electrode, wherein the first electrode contains Si and Ni and is in ohmic contact with the silicon carbide substrate.

An ohmic electrode can be formed on the bottom of the contact hole to the minimum extent necessary, and not formed in unnecessary areas. Since the sides of the contact hole are particularly susceptible to etching damage, the second electrode can be used as a barrier film. In addition, by separating the electrodes on the bottom and sides of the contact hole, the stress on the substrate and insulating film can be alleviated.

[10] At the bottom of the contact hole, the distance between the first electrode and the second electrode is 0.1 μm or more and 1 μm or less.

If it is shorter than 0.1 μm, problems with processing accuracy will occur and some areas will become unable to be separated locally. Also, if it is 1 μm or less, there is a margin for variation in general processing accuracy, but if it exceeds 1 μm, the resistance of the device will increase.

[Details of the embodiment of the present disclosure]
Hereinafter, an embodiment of the present disclosure will be described in detail, but the present embodiment is not limited thereto.

First Embodiment
First, a process of forming an ohmic electrode on the surface of a silicon carbide substrate in a method for manufacturing a silicon carbide semiconductor device will be described. When forming an ohmic electrode on the surface of a silicon carbide substrate, a Ni film is formed on the surface of the silicon carbide substrate by sputtering, and then unnecessary Ni film is removed by wet etching or the like. Then, Si and Ni contained in the silicon carbide substrate are alloyed by heating to form a nickel silicide film that becomes an ohmic electrode. At this time, Si on the surface of the silicon carbide substrate is taken away due to alloying with Ni, and unreacted C precipitates on the surface of the nickel silicide film. Then, when an Al film is formed by sputtering to form a wiring layer, if C precipitates on the surface of the nickel silicide film that becomes an ohmic electrode, the Al film is easily peeled off, resulting in a decrease in reliability.

Various methods are being considered to address this issue.

For example, a method is considered in which a film containing Ni and Si is formed on the surface of a silicon carbide substrate, and then the film containing Ni and Si is removed from areas other than the desired area, followed by heat treatment. In this method, the Ni and Si in the film containing Ni and Si are alloyed to form an ohmic electrode. Therefore, when forming the ohmic electrode, almost no Si contained in the silicon carbide substrate is lost, and precipitation of C can be prevented as much as possible.

However, because Ni is difficult to remove by dry etching and Si is difficult to remove by wet etching, a film containing Ni and Si is difficult to remove by either dry etching or wet etching. In addition, a method for forming a film containing Ni and Si in a desired region can be achieved by lift-off, but lift-off is not preferred because the peeled film may reattach, resulting in reduced reliability.

Therefore, in a method of forming a film containing Ni and Si on the surface of a silicon carbide substrate and then performing a heat treatment, it is difficult to remove the film containing Ni and Si from areas other than the desired area, and therefore it is not easy to leave the film containing Ni and Si in the desired area.

Another method that can be considered besides the above is to form an ohmic electrode without using a resist, etc.

Specifically, first, as shown in Figure 1, an insulating film 20 serving as an interlayer insulating film having a contact hole 21 is formed on the main surface 10a, which is the surface of the silicon carbide substrate 10, and a TiN film 30 is formed to cover the contact hole 21 and the insulating film 20. Thereafter, the TiN film 30 on the bottom surface 21a of the contact hole 21 is removed to form an opening 30a, exposing the main surface 10a of the silicon carbide substrate 10. As a result, the insulating film 20 on the side surface 21b of the contact hole 21 and the upper surface 20a of the insulating film 20 are covered with the TiN film 30.

Next, as shown in Fig. 2, a Ni film 40 is formed by sputtering. As a result, the Ni film 40 is formed on the main surface 10a of the silicon carbide substrate 10 exposed at the bottom surface 21a of the contact hole 21 and on the TiN film 30.

3, a heat treatment is performed at a temperature of 500°C to 700°C to form a reaction precursor layer 41 of nickel silicide in which Ni and Si are alloyed at the interface between the silicon carbide substrate 10 and the Ni film 40. The TiN film 30 is provided to prevent Ni from penetrating into the insulating film 20 during this heat treatment.

Next, as shown in FIG. 4, the Ni film 40 is removed by wet etching using dilute hydrochloric acid or dilute nitric acid. As a result, a reaction precursor layer 41 remains on the main surface 10a of the silicon carbide substrate 10 in the opening 30a of the TiN film 30.

Next, as shown in FIG. 5, the reaction precursor layer 41 is heat-treated at a temperature of approximately 1000°C to form an ohmic electrode 41a.

The ohmic electrode 41a thus formed is extremely thin, with a thickness of only a few nm, so that in the subsequent process, the ohmic electrode 41a may be removed by reverse sputtering when forming the wiring layer. In addition, with this method, unreacted C precipitates on the surface of the ohmic electrode 41a.

(Method of manufacturing a semiconductor device)
Next, a method for manufacturing a semiconductor device according to the first embodiment will be described with reference to Fig. 6 to Fig. 14. Fig. 6 is a flowchart of the method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. Figs. 7 to 14 are process diagrams of the method for manufacturing a semiconductor device according to the first embodiment of the present disclosure.

First, as shown in Fig. 7, a silicon carbide substrate 10 having one main surface 10a and the other main surface 10b is prepared (step S1), and an insulating film 20 having a thickness of 0.8 μm, which will be an interlayer insulating film, is formed on one main surface 10a of the silicon carbide substrate 10 by a chemical vapor deposition (CVD) method (step S2). The insulating film 20 is made of silicon oxide.

8, contact holes 21 are formed in the insulating film 20 (step S3). Specifically, a photoresist is applied to the upper surface 20a of the insulating film 20, and exposure and development are performed using an exposure device to form a resist pattern (not shown) having an opening in the area where the contact hole 21 is to be formed. After that, the insulating film 20 in the area where the resist pattern is not formed is removed by dry etching such as RIE (Reactive Ion Etching), and the main surface 10a of the silicon carbide substrate 10 is exposed to form the contact hole 21. After that, the resist pattern (not shown) is removed by an organic solvent or the like. As a result, the contact hole 21 is formed such that the bottom surface 21a becomes the main surface 10a of the silicon carbide substrate 10 and the side surface 21b becomes the insulating film 20.

9, a Si film 130 is formed by sputtering to cover the bottom surface 21a and side surface 21b of the contact hole 21 and the top surface 20a of the insulating film 20 (step S4). The thickness t1 of the Si film 130 is 5 nm or more and 100 nm or less. The thickness t1 of the Si film 130 is the thickness of the Si film 130 at the bottom surface 21a of the contact hole 21.

10, the Si film 130 on the upper surface 20a of the insulating film 20 is removed (step S5). Specifically, a resist pattern (not shown) is formed to cover the bottom surface 21a of the contact hole 21, and the Si film 130 in the area where the resist pattern is not formed is removed by dry etching such as RIE. A fluorine-based or chlorine-based etching gas is used as the etching gas. After that, the resist pattern is removed by an organic solvent or the like. As a result, the Si film 130 covering the bottom surface 21a and the side surface 21b of the contact hole 21 remains. Dry etching such as RIE is anisotropic etching. Therefore, even if the Si film 130 on the upper surface 20a of the insulating film 20 in the area where the resist pattern is not formed is completely removed, the Si film 130 covering the side surface 21b of the contact hole 21 cannot be completely removed and remains thin.

11, a Ni film 140 is formed by sputtering on the Si film 130 on the bottom surface 21a and side surface 21b of the contact hole 21 and on the upper surface 20a of the insulating film 20 (step S6). The thickness t2 of the Ni film 140 is 5 nm or more and 100 nm or less. The thickness t2 of the Ni film 140 is the thickness of the Ni film 140 on the bottom surface 21a of the contact hole 21. The Si film 130 and the Ni film 140 are formed to a thickness such that the relationship N Ni ≧N Si /2 is satisfied, where N _Si is the number of Si atoms per unit area included in the Si film 130 integrated in the thickness direction, and N _Ni is the number of Ni atoms per unit area included in the Ni film 140 integrated in the thickness direction, on the bottom surface _21a of the contact _hole 21. The thickness direction refers to the film thickness direction of the Si film 130 and the Ni film 140 , and is a direction perpendicular to the film surfaces of the Si film 130 and the Ni film 140 .

12, a first heat treatment is performed at a temperature of 200°C or more and 400°C or less, for example, about 350°C (step S7). As a result, the Si of the Si film 130 on the bottom surface 21a and side surface 21b of the contact hole 21 reacts with the Ni of the Ni film 140 to form a reaction precursor layer 141 of nickel silicide. The temperature in the first heat treatment is a temperature at which Si reacts with Ni but Si and Ni contained in SiC do not react with each other. In the present application, this temperature may be referred to as the first temperature. The Ni film 140 is also formed on the upper surface 20a of the insulating film 20, but at the heat treatment temperature of this step, about 350°C, the Ni contained in the Ni film 140 does not penetrate into the insulating film 20. The first temperature is the temperature of the silicon carbide substrate 10. For example, the first heat treatment is performed using a furnace, and the temperature of the silicon carbide substrate 10 is substantially equal to the temperature in the furnace.

13, the unreacted Ni film 140 on the upper surface 20a of the insulating film 20, i.e., the portion of the Ni film 140 that has not reacted with the Si film 130, is removed by wet etching (step S8). As a result, a reaction precursor layer 141 remains on the bottom surface 21a and side surface 21b of the contact hole 21.

14, the electrode layer 142 is formed from the reaction precursor layer 141 by performing a second heat treatment at a temperature of 800°C or more and 1100°C or less, for example, about 1000°C (step S9). The electrode layer 142 includes an ohmic region 142a that is in ohmic contact with the main surface 10a of the silicon carbide substrate 10. The ohmic region 142a can function as an ohmic electrode. The temperature in this step is higher than the first temperature and is a temperature at which Si and Ni contained in SiC react. In the present application, the temperature of this heat treatment step may be described as the second temperature. The second temperature is the temperature of the silicon carbide substrate 10. For example, the second heat treatment is performed using a furnace, and the temperature of the silicon carbide substrate 10 is substantially equal to the temperature in the furnace.

In the electrode layer 142, Si contained in the silicon carbide substrate 10 penetrates into the ohmic region 142a.

In this embodiment, the nickel silicide forming the ohmic region 142a of the electrode layer 142 is mostly formed of Si contained in the Si film 130 and Ni contained in the Ni film 140. Therefore, when forming the ohmic region 142a in the second heat treatment, a small amount of unreacted Ni contained in the reaction precursor layer 141 reacts with Si supplied from the silicon carbide substrate 10. Therefore, the amount of Si supplied from the silicon carbide substrate 10 is small. Therefore, since the amount of unreacted C generated is also small, C is hardly precipitated on the surface of the electrode layer 142. Therefore, even if a wiring layer such as Al is formed on the electrode layer 142, it will not peel off from the surface of the electrode layer 142. The wiring layer may be a film in which TiN and Al are stacked in order.

In addition, in this embodiment, since there is no need to form a TiN film as shown in Figure 1, the number of manufacturing steps when manufacturing a silicon carbide semiconductor device can be reduced, thereby reducing costs.

11, the side surface 21b of the contact hole 21 is covered with the Si film 130, and therefore the silicon oxide forming the side surface 21b of the contact hole 21 is not in direct contact with the Ni film 140. Therefore, even if the second heat treatment is performed at a temperature of about 1000°C, Ni does not penetrate into the insulating film 20, and the insulating film 20 does not deteriorate. Note that if the Ni film is in direct contact with the insulating film formed of silicon oxide, Ni penetrates into the insulating film at a heating temperature of about 500°C, and the insulating film deteriorates.

(Modification)
Next, a modification of this embodiment will be described.

In this modified example, after the process shown in FIG. 9, the size of the remaining Si film 130 is changed by changing the size of the resist pattern (not shown) formed on the Si film 130.

For example, after the process shown in FIG. 9 (step S4), as shown in FIG. 15, a resist pattern 151 is formed on the Si film 130 in an area narrower than the bottom surface 21a of the contact hole 21, and the Si film 130 in the area where the resist pattern 151 is not formed is removed. After that, by performing the same process (steps S5 to S9) as above, as shown in FIG. 16, the first electrode 142b in contact with the bottom surface 21a of the contact hole 21 and the second electrode 142c in contact with the side surface 21b of the contact hole 21 are formed apart from each other. That is, the first electrode 142b and the second electrode 142c are formed apart from each other on the bottom surface 21a of the contact hole 21. The distance L between the first electrode 142b and the second electrode 142c is preferably 0.1 μm or more and 1 μm or less. As shown in FIG. 16, the Ni film does not exist on the upper surface 20 a of the insulating film 20 in contact with the insulating film 20 .

The first electrode 142b is permeated with Si contained in the silicon carbide substrate 10, and the first electrode 142b can function as an ohmic electrode. The second electrode 142c includes an ohmic region 142d, into which Si contained in the silicon carbide substrate 10 has permeated, in the vicinity of the main surface 10a of the silicon carbide substrate 10, and the ohmic region 142d can function as an ohmic electrode. In the second electrode 142c, there is no permeation of Si in a portion farther from the main surface 10a of the silicon carbide substrate 10 than the ohmic region 142d. Therefore, the second electrode 142c has a portion containing less Si than the first electrode 142b, and therefore, the second electrode 142c has a portion with a lower concentration of Si than the first electrode 142b.

When the first electrode 142b is formed, a small amount of Si penetrates from the silicon carbide substrate 10, and as a result, unreacted C contained in the silicon carbide substrate 10 also penetrates into the first electrode 142b. In contrast, in the second electrode 142c, unreacted C may penetrate near the main surface 10a of the silicon carbide substrate 10, but unreacted C does not penetrate into the portion of the second electrode 142c away from the main surface 10a of the silicon carbide substrate 10. Therefore, there is a region in the second electrode 142c that does not contain C, and therefore there is a region with a lower concentration of C than the first electrode 142b.

9 (step S4), a resist pattern 152 is formed on the Si film 130 in an area wider than the bottom surface 21a of the contact hole 21, as shown in Fig. 17, and the Si film 130 in the area where the resist pattern 152 is not formed is removed. After that, by performing the same processes (steps S5 to S9) as described above, the electrode layer 142 is formed on the bottom surface 21a and side surface 21b of the contact hole 21 and the upper surface 20a of the insulating film 20 near the contact hole 21, as shown in Fig. 18.

15, a resist pattern 151 may be formed on the Si film 130 in an area narrower than the bottom surface 21a of the contact hole 21, and the Si film 130 in the area where the resist pattern 151 is not formed may be removed by isotropic dry etching. In this case, the Si film 130 is not formed on the side surface 21b, but is formed on the bottom surface 21a of the contact hole 21, so that an electrode layer 142 serving as an ohmic electrode is formed only on the bottom surface 21a of the contact hole 21, as shown in FIG.

(Semiconductor device)
Next, an example of the semiconductor device in the first embodiment will be described. As shown in FIG. 20, the semiconductor device in this embodiment is, for example, a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Specifically, the semiconductor device in this embodiment has a silicon carbide substrate 10, an electrode layer 142, a wiring layer 70, a gate insulating film 25, and a gate electrode 71, and the gate electrode 71 is covered with an insulating film 20 that serves as an interlayer insulating film. The silicon carbide substrate 10 has a first n-layer 11, a second n-layer 12, a p-body layer 13, an n-source region 14, and a p-region 18. The first n-layer 11 and the n-source region 14 are doped with more impurity elements than the second n-layer 12. The p-region 18 is doped with more impurity elements than the p-body layer 13.

The electrode layer 142 is manufactured by the manufacturing method of this embodiment, and is in ohmic contact with the n-source region 14 on one main surface 10a (the upper surface in the figure) of the silicon carbide substrate 10. The thickness of the electrode layer 142 is, for example, about 100 to 200 nm. A wiring layer 70 is formed on the electrode layer 142 and on the upper surface 20a of the insulating film 20.

The gate electrode 71 is provided on one main surface 10a (upper surface in the figure) of the silicon carbide substrate 10 via a gate insulating film 25, and faces the channel region 13a, which is the surface side of the p-body layer 13. A drain electrode 72 is provided on the other main surface 10b (lower surface in the figure) of the silicon carbide substrate 10.

According to this embodiment, a vertical MOSFET can be obtained in which the wiring layer 70 is less likely to peel off from the electrode layer 142.

In addition, a vertical IGBT (Insulated Gate Bipolar Transistor) may be formed instead of a vertical MOSFET by forming a p-collector layer on the side of the silicon carbide substrate 10 facing the drain electrode 72. Also, a structure (trench gate structure) in which a gate electrode is embedded in a trench formed in the silicon carbide substrate via a gate insulating film may be used.

Second Embodiment
Next, a method for manufacturing the semiconductor device according to the second embodiment will be described with reference to FIGS.

First, as shown in FIG. 21, an insulating film 20 having a contact hole 21 is formed on the main surface 10a of a silicon carbide substrate 10, and a TiN film 120 covering the contact hole 21 and the insulating film 20 is formed by sputtering. After that, a part of the TiN film 120 formed on the bottom surface 21a of the contact hole 21 is removed to expose the main surface 10a of the silicon carbide substrate 10. The thickness of the formed TiN film 120 is 10 nm or more and 200 nm or less.

Next, as shown in FIG. 22, a Si film 130 is formed by sputtering on the exposed main surface 10a of the silicon carbide substrate 10 and the TiN film 120.

23, the Si film 130 formed on the upper surface 20a of the insulating film 20 via the TiN film 120 is removed. At this time, in the vicinity of the contact hole 21, a part of the Si film 130 may remain on the upper surface 20a of the insulating film 20 via the TiN film 120. As a result, the Si film 130 covering the bottom surface 21a and side surface 21b of the contact hole 21 remains.

Next, as shown in FIG. 24, a Ni film 140 is formed on the TiN film 120 and the Si film 130 by sputtering.

25, a first heat treatment is performed at a temperature of 300°C to 400°C, for example, about 350°C. As a result, a nickel silicide reaction precursor layer 141 is formed by the Si of the Si film 130 and the Ni of the Ni film 140 on the Si film 130. Note that the Ni film 140 on the TiN film 120 is not silicided.

26, the unreacted Ni film 140 is removed by wet etching. This leaves a reaction precursor layer 141 on the bottom surface 21a and side surface 21b of the contact hole 21.

27, a second heat treatment is performed at a temperature of about 1000°C to form an electrode layer 142 from the reaction precursor layer 141. The electrode layer 142 includes an ohmic region 142a that is in ohmic contact with the main surface 10a of the silicon carbide substrate 10. When forming the ohmic region 142a, only a small amount of Si is supplied from the silicon carbide substrate 10, so there is almost no precipitation of C on the surface of the electrode layer 142. Therefore, even if a wiring layer such as Al is formed on the electrode layer 142, the wiring layer will not peel off from the surface of the electrode layer 142. The wiring layer may be a film in which TiN and Al are laminated in order.

(Modification)
In this modification, in the step shown in FIG. 21, the TiN film 120 may be formed only on the side surface 21b of the contact hole 21 as shown in FIG. 28. Thereafter, as shown in FIG. 29, a Si film 130 covering the TiN film 120, the bottom surface 21a of the contact hole 21, and the insulating film 20 is formed by sputtering. Thereafter, as shown in FIG. 30, a resist pattern 153 is formed on the Si film 130 in an area narrower than the bottom surface 21a of the contact hole 21, and the Si film 130 in an area where the resist pattern 153 is not formed is removed. Thereafter, by performing the same steps as above (steps S5 to S9), the first electrode 142b and the second electrode 142c are formed apart from each other on the bottom surface 21a of the contact hole 21 as shown in FIG.

All other contents are the same as those of the first embodiment.

Although the embodiments have been described in detail above, the invention is not limited to the specific embodiments, and various modifications and variations are possible within the scope of the claims.

10 Silicon carbide substrate 10a One main surface 10b Other main surface 11 First n layer 12 Second n layer 13 P body layer 14 N source region 18 P region 20 Insulating film 20a Top surface 21 Contact hole 21a Bottom surface 21b Side surface 25 Gate insulating film 30 TiN film 30a Opening 40 Ni film 41 Reaction precursor layer 41a Ohmic electrode 70 Wiring layer 71 Gate electrode 72 Drain electrode 120 TiN film 130 Si film 140 Ni film 141 Reaction precursor layer 142 Electrode layer 142a Ohmic region 142b First electrode 142c Second electrode 142d Ohmic regions 151, 152, 153 Resist pattern

Claims (10)

providing a silicon carbide substrate;
forming an insulating film on one main surface of the silicon carbide substrate;
forming a contact hole in the insulating film and exposing one main surface of the silicon carbide substrate at a bottom surface of the contact hole;
forming a Si film on a bottom surface of the contact hole;
forming a Ni film on the Si film;
After the step of forming the Ni film, a step of performing a first heat treatment at a first temperature at which Ni and Si react with each other;
removing an unreacted portion of the Ni film that has not reacted with the Si film by wet etching after the first heat treatment;
performing a second heat treatment at a second temperature higher than the first temperature after the step of removing the unreacted portion;
The present invention relates to a method for manufacturing a silicon carbide semiconductor device having the above structure. The step of forming a Si film on a bottom surface of the contact hole includes:
forming a first Si film on a bottom surface and a side surface of the contact hole and on an upper surface of the insulating film;
removing the first Si film at least on the upper surface of the insulating film by dry etching after the step of forming the first Si film;
The method for manufacturing a silicon carbide semiconductor device according to claim 1 , comprising the steps of: The method for manufacturing a silicon carbide semiconductor device according to claim 1 or 2, wherein the first temperature is 200°C or higher and 400°C or lower. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 3, wherein the second temperature is 800°C or higher and 1100°C or lower. A method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 4, wherein the thickness of the Si film at the bottom of the contact hole is 5 nm or more and 100 nm or less. A method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 5, wherein the thickness of the Ni film at the bottom surface of the contact hole is 5 nm or more and 100 nm or less. A method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 6, wherein the Si film is also formed on the side surface of the contact hole. 8. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein, at a bottom surface of the contact hole with the Ni film formed on the Si film, when the number of Si atoms per unit area contained in the Si film accumulated in the thickness direction is _{N Si and} the number of Ni atoms contained in the Ni film accumulated in the thickness direction is N _Ni ≧ N _Si /2 holds. a silicon carbide substrate having a main surface;
an insulating film provided on a main surface of the silicon carbide substrate;
a contact hole provided in the insulating film;
a first electrode provided on a part of a bottom surface of the contact hole and in contact with the silicon carbide substrate;
a second electrode provided on a side surface of the contact hole and spaced apart from the first electrode;
having
The first electrode contains Si and Ni and is in ohmic contact with the silicon carbide substrate. The silicon carbide semiconductor device according to claim 9, wherein the distance between the first electrode and the second electrode at the bottom surface of the contact hole is 0.1 μm or more and 1 μm or less.

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