JP7549748B2 - Gate driver for power semiconductor device and power conversion device - Google Patents

Description

The present invention relates to a gate drive device for a power semiconductor element and a power conversion device.

Various gate drive devices have been proposed that turn on and off each of the semiconductor switching elements, which are power semiconductor elements connected in series.

For example, in a semiconductor switch circuit comprising a plurality of voltage-driven semiconductor elements connected in series to form arms, and a gate drive circuit that supplies gate signals to the gate terminals of each of the plurality of voltage-driven semiconductor elements in each arm, a control device for series-connected voltage-driven semiconductor elements is known, characterized in that gate lines connecting the gate drive circuit to the gate terminals of each of the voltage-driven semiconductor elements in each arm are magnetically coupled to each other (see, for example, Patent Document 1).

For example, in a drive circuit that turns on and off multiple voltage-driven semiconductor elements connected in series to each arm of a power converter, a voltage variation suppression method for voltage-driven semiconductor elements is known in which an equivalent circuit consisting of a series circuit of a capacitor and a winding is connected between the collector and gate of each voltage-driven semiconductor element, and a balance circuit in which the windings are magnetically coupled between adjacent drive circuits is connected to suppress variation in element voltage (see, for example, Patent Document 2).

Patent No. 4396036 Patent No. 4639687

In the invention described in Patent Document 1 (JP Patent No. 4396036), the gate lines of the voltage-driven semiconductor element are magnetically coupled, and if the current values flowing through the gate lines differ when the voltage-driven semiconductor element is turned on or off, the impedance of the gate lines is instantly changed according to the difference, thereby matching the gate currents and suppressing the variation in switching timing. However, the invention described in Patent Document 1 (JP Patent No. 4396036) has the effect of correcting the time difference in gate voltage due to the delay of the gate voltage signal and matching the switching timing of the on operation or off operation when the gate threshold voltages (the gate voltages at which the voltage-driven semiconductor element starts to turn on) of the voltage-driven semiconductor elements are the same, but the effect is small when the gate threshold voltages are different. In many cases, the gate threshold voltage varies depending on the voltage-driven semiconductor element, so the effect of matching the switching timing of the on operation and the off operation is poor, and the imbalance of the applied voltage during the on operation and the off operation becomes large.

In addition, the invention described in Patent Document 2 (Patent Publication No. 4639687) is effective in aligning the switching timing of on or off operations when there is variation in the characteristics of the power semiconductor elements, but is not very effective in aligning the switching timing of on and off operations when there is variation in the transmission time of the gate signal, and the imbalance in the applied voltage during on and off operations becomes greater.

Therefore, in a gate drive device for multiple power semiconductor elements connected in series and a power conversion device equipped with the same, there is a need for technology that can align the switching timing for the on and off operations of each power semiconductor element, even if there is variation in the transmission time of the gate signal or the characteristics of the power semiconductor elements, and suppress imbalances in the voltages applied to the power semiconductor elements.

According to one aspect of the present disclosure, a gate drive device for a plurality of power semiconductor elements connected in series includes a gate drive voltage output unit provided corresponding to each of the power semiconductor elements and outputting a gate drive voltage, a gate line that supplies the gate drive voltage output from the gate drive voltage output unit to the gate terminal of each of the corresponding power semiconductor elements, a magnetic coupling unit that magnetically couples each of the gate lines to each other, and a capacitor provided corresponding to each of the power semiconductor elements and connected between the current inflow terminal and the gate terminal of the power semiconductor element.

Here, in the above-mentioned gate drive device, when the value of the parasitic capacitance between the current outflow terminal and the gate terminal of the power semiconductor element is _C1 , and the value of the parasitic capacitance between the current inflow terminal and the gate terminal is _C2 , the capacitor may have a capacitance value _Cx that satisfies _Cx /( _C1 + _C2 )≧5× ^10-5 .

Furthermore, in the above-mentioned gate drive device, when the value of the parasitic capacitance between the current outflow terminal and the gate terminal of the power semiconductor element is _C1 , the voltage applied between the current inflow terminal and the current outflow terminal is _V1 , and the maximum allowable applied voltage between the gate terminal and the current outflow terminal is _Vmax , the capacitor may have a capacitance _Cx that satisfies _Vmax /( _V1 - _Vmax ) × _C1 ≧ _Cx .

In addition, in the above gate drive device, each of the capacitors may be arranged in close proximity to a corresponding power semiconductor element.

In addition, in the above gate drive device, each of the power semiconductor elements may be cooled by the same cooler.

In addition, in the above gate drive device, the current input terminal of the power semiconductor element may be a drain terminal, a collector terminal, or an anode terminal.

In addition, in the above gate drive device, the current output terminal of the power semiconductor element may be a source terminal, an emitter terminal, or a cathode terminal.

According to one aspect of the present disclosure, the power conversion device includes the gate drive device, a power conversion circuit unit having two arms each having a plurality of power semiconductor elements connected in series and capacitors corresponding to the power semiconductor elements, and performing power conversion operation in response to the on/off operation of the power semiconductor elements, and a power conversion control unit that controls the power conversion operation of the power conversion circuit unit.

Here, the power conversion device may further include a switch provided corresponding to each of the power semiconductor elements and connected between the current output terminal and the gate terminal of the power semiconductor element.

Here, the above power conversion device may further include a switch control unit that controls the on/off operation of the switch so that, during an off period of the power semiconductor element in one cycle related to the on/off operation of the power semiconductor element, there is at least an on period of the switch provided in the arm to which the power semiconductor element belongs that is in the off period.

Here, in the above power conversion device, the on-period of the switch may be longer than the on-period of a power semiconductor element provided in an arm other than the arm to which the switch belongs, and shorter than the off-period of a power semiconductor element provided in the arm to which the switch belongs.

According to one aspect of the present disclosure, in a gate drive device for multiple power semiconductor elements connected in series and a power conversion device including the same, even if there is variation in the transmission time of the gate signal or the characteristics of the power semiconductor elements, the switching timing for the on and off operations of each of the power semiconductor elements can be aligned, thereby suppressing imbalances in the voltages applied to the power semiconductor elements.

FIG. 2 is a circuit diagram illustrating a gate driver according to one embodiment of the present disclosure. FIG. 2 illustrates a magnetic coupling portion in a gate drive device according to an embodiment of the present disclosure. 10 is a diagram illustrating a state in which a gate current starts to flow in a gate driver according to an embodiment of the present disclosure. FIG. 4 is a diagram illustrating a flow of a gate current when the power semiconductor element _QA is turned on before the power semiconductor element _QB after the state of FIG. 3 in the gate driver according to the embodiment of the present disclosure. FIG. 5 is a diagram illustrating a flow of a gate current when the power semiconductor element _QA is turned off before the power semiconductor element _QB after the state of FIG. 4 in the gate driver according to the embodiment of the present disclosure. FIG. FIG. 1 illustrates a power converter including a gate drive according to one embodiment of the present disclosure. 7 is a circuit diagram showing an arm provided in the power conversion device shown in FIG. 6. 10 is a diagram for explaining the definition of the imbalance degree of applied voltage during off operation when there is variation in the transmission time of a gate signal to two power semiconductor elements or in the characteristics of the two power semiconductor elements; 10 is a diagram for explaining the definition of the imbalance of applied voltages during an ON operation when there is variation in the transmission time of a gate signal to two power semiconductor elements or in the characteristics of the two power semiconductor elements; FIG. 11 is a comparative example of simulation results regarding the degree of imbalance for a configuration in which there is no magnetic coupling of the gate lines, a configuration according to Patent Document 1 (Japanese Patent No. 4,396,036) in which there is magnetic coupling of the gate lines, a configuration according to Patent Document 2 (Japanese Patent No. 4,639,687) in which there is magnetic coupling of the gate lines and a capacitor, and an embodiment of the present disclosure, when there is variation in the transmission time of the gate signal to the power semiconductor element. FIG. 11 is a comparative example of simulation results regarding the degree of imbalance for a configuration in which there is no magnetic coupling of the gate lines, a configuration according to Patent Document 1 (Japanese Patent No. 4,396,036) in which there is magnetic coupling of the gate lines, a configuration according to Patent Document 2 (Japanese Patent No. 4,639,687) in which there is magnetic coupling of the gate lines and a capacitor, and an embodiment of the present disclosure, when there is variation in the characteristics of the power semiconductor elements. FIG. 11 is a comparative example showing simulation results of the degree of imbalance for a configuration without magnetic coupling of gate lines, a configuration according to Patent Document 1 (Japanese Patent No. 4,396,036) in which there is magnetic coupling of gate lines, a configuration according to Patent Document 2 (Japanese Patent No. 4,639,687) in which there is magnetic coupling of gate lines and a capacitor, and an embodiment of the present disclosure, in cases where there is variation in the transmission time of gate signals to power semiconductor elements and there is variation in the characteristics of the power semiconductor elements. FIG. 2 is a circuit diagram illustrating the parasitic capacitance of a MOSFET. 1 is a diagram illustrating the relationship between the current capacity of a power semiconductor element and the parasitic capacitance of the power semiconductor element. 1 is a diagram illustrating an example of the relationship between the current capacity and the input capacitance Ciss of power semiconductor elements having different specifications. FIG. 11 is a diagram showing the relationship between the capacitance ratio C _x ^* of capacitors provided corresponding to power semiconductor elements and the degree of imbalance in applied voltages when two power semiconductor elements having different gate threshold voltages are driven by a gate driving device according to an embodiment of the present disclosure. 1 is a circuit diagram showing a gate driver for turning on and off three power semiconductor devices connected in series according to an embodiment of the present disclosure; FIG. 2 is a circuit diagram showing a leg formed by an arm having two power semiconductor elements connected in series in an embodiment of the present disclosure. 18 is a diagram illustrating an example of voltages applied to power semiconductor elements in each arm in the leg shown in FIG. 17 . 18 is a diagram illustrating an example of the gate-source voltage of each power semiconductor element in the leg shown in FIG. 17. FIG. 11 is a circuit diagram showing a gate driver according to a modified example of an embodiment of the present disclosure. FIG. 11 is a circuit diagram showing a case where a switch provided in a gate driver according to a modified example of an embodiment of the present disclosure is configured with a MOSFET. FIG. 11 is a circuit diagram showing a power conversion device including a leg configured by an arm having two power semiconductor elements connected in series in a modified example of an embodiment of the present disclosure. 21 is a diagram for explaining the operation of a switch control section when a power semiconductor element in an upper arm is turned on and a power semiconductor element in a lower arm is turned off in the power converter shown in FIG. 20. 21 is a diagram for explaining the operation of the switch control section when the power semiconductor element in the upper arm in the power converter shown in FIG. 20 is turned off and the power semiconductor element in the lower arm is turned on. FIG. 2 is a see-through perspective view showing an example of an arrangement of capacitors in a gate driver according to an embodiment of the present disclosure. 1 is a perspective view illustrating a power module having an IGBT as a power semiconductor element. FIG. 2 is a perspective view illustrating a cooler provided in a gate drive device according to an embodiment of the present disclosure.

The gate drive device and power conversion device for power semiconductor elements will be described below with reference to the drawings. In each drawing, similar components are given similar reference symbols. In addition, the scale of these drawings has been appropriately changed to facilitate understanding. The illustrated forms are one example for carrying out the invention, and the invention is not limited to these forms.

The gate drive device according to each embodiment of the present disclosure drives a plurality of power semiconductor elements connected in series to turn on and off. Examples of power semiconductor elements include MOSFETs, IGBTs, thyristors, GTOs, and transistors. MOSFETs have gate, drain, and source terminals as their terminals. IGBTs have gate, collector, and emitter terminals as their terminals. Transistors have base, collector, and emitter terminals as their terminals. Thyristors and GTOs have gate, anode, and cathode terminals as their terminals. The "current inflow terminals" of power semiconductor elements correspond to the "drain terminals" of MOSFETs, the "collector terminals" of IGBTs and transistors, and the "anode terminals" of thyristors and GTOs, respectively. The "current outflow terminals" of power semiconductor elements correspond to the "source terminals" of MOSFETs, the "emitter terminals" of IGBTs and transistors, and the "cathode terminals" of thyristors and GTOs, respectively. The "control terminal" of a power semiconductor element corresponds to the "gate terminal" of a MOSFET, an IGBT, a thyristor, and a GTO, and the "base terminal" of a transistor.

As an example, the power semiconductor element is described below as being composed of a MOSFET, but the embodiments of the present disclosure are applicable to IGBTs, thyristors, GTOs, or transistors. When the power semiconductor element is composed of an IGBT, the "drain" which is the current inflow terminal is replaced with the "collector" and the "source" which is the current outflow terminal is replaced with the "emitter", and the embodiments of the present disclosure are applied. When the power semiconductor element is composed of a transistor, the "gate" which is the control terminal is replaced with the "base", the "drain" which is the current inflow terminal is replaced with the "collector", and the "source" which is the current outflow terminal is replaced with the "emitter", and the embodiments of the present disclosure are applied. When the power semiconductor element is composed of a thyristor or GTO, the "drain" which is the current inflow terminal is replaced with the "anode" and the "source" which is the current outflow terminal is replaced with the "cathode", and the embodiments of the present disclosure are applied.

Figure 1 is a circuit diagram showing a gate driver according to one embodiment of the present disclosure. Hereinafter, components with the same reference symbols in different drawings have the same functions.

A gate driver 1 according to an embodiment of the present disclosure drives a plurality of power semiconductor elements connected in series to turn on and off. Here, as an example, a description will be given of an example in which two power semiconductor elements _QA and _QB connected in series are driven on and off.

A diode D _A is connected in anti-parallel to the power semiconductor element Q _A. Similarly, a diode D _B is connected in anti-parallel to the power semiconductor element Q _B.

The gate drive device 1 comprises gate drive voltage output units 11-A and 11-B, gate lines 12-A and 12-B, a magnetic coupling unit 13, and capacitors 14-A and 14-B.

The gate drive voltage output section 11-A is provided corresponding to the power semiconductor element _QA , and outputs a positive gate drive voltage (for example, 10V) corresponding to the on signal of the gate signal, and a 0V or negative gate drive voltage corresponding to the off signal of the gate signal. The gate drive voltage output section 11-B is provided corresponding to the power semiconductor element _QB , and outputs a positive gate drive voltage (for example, 10V) corresponding to the on signal of the gate signal, and a 0V or negative gate drive voltage corresponding to the off signal of the gate signal. The gate drive voltage output sections 11-A and 11-B insulate or convert the voltage level of the input on or off signal, and output gate drive voltages corresponding to the power semiconductor elements _QA and _QB . For the sake of simplicity, hereinafter, the off signal of the gate signal will be described as corresponding to a gate drive voltage of 0V, but the off signal of the gate signal may be a negative gate drive voltage.

The gate line 12-A supplies the gate drive voltage output from the gate drive voltage output unit 11-A to a gate terminal 21-A which is the control terminal of the corresponding power semiconductor element Q _A. When a positive gate drive voltage is applied to the gate terminal of the power semiconductor element Q _A , the power semiconductor element Q _A turns on, and when a gate drive voltage of 0 V is applied to the gate terminal of the power semiconductor element Q _A , the power semiconductor element Q _A turns off.

The gate line 12-B supplies the gate drive voltage output from the gate drive voltage output unit 11-B to a gate terminal 21-B which is the control terminal of the corresponding power semiconductor element Q _B. When a positive gate drive voltage is applied to the gate terminal of the power semiconductor element Q _B , the power semiconductor element Q _B is turned on, and when a gate drive voltage of 0 V is applied to the gate terminal of the power semiconductor element Q _B , the power semiconductor element Q _B is turned off.

The magnetic coupling unit 13 magnetically couples the gate line 12-A and the gate line 12-B. FIG. 2 is a diagram illustrating a magnetic coupling unit in a gate driver according to an embodiment of the present disclosure. The magnetic coupling unit 13 has a magnetic body 30. The gate lines 12-A and 12-B are wound around the magnetic body 30. For example, as shown in FIG. 2, when a gate current Ig ₁ flows, a magnetic flux Φ1 is generated in the magnetic body 30 and crosses the gate line 12-B. Similarly, when a gate current Ig ₂ flows, a magnetic flux Φ2 is generated in the magnetic body 30 and crosses the gate line 12-A. This magnetically couples the gate lines 12-A and 12-B. The number of turns _N1 of the gate line 12-A to the magnetic body 30 is set to be the same as the number of turns _N2 of the gate line 12-B to the magnetic body 30, and when the gate currents _Ig1 and _Ig2 are equal, |Φ1|=|Φ2| holds, and when the gate currents _Ig1 and _Ig2 have opposite polarities, Φ1 and Φ2 have opposite polarities.

For example, if the timing of the power semiconductor element _QA and the power semiconductor element _QB to turn off is not synchronized, and the power semiconductor element _QA turns off before the power semiconductor element _QB , when the gate current _Ig1 flows out before the gate current _Ig2 , the magnetic flux Φ1 and the magnetic flux Φ2 are not equal, so that a magnetic flux of |Φ1-Φ2| is generated in the magnetic body 30, and they are magnetically coupled. At this time, an inductance _L1 is generated in the gate line 12-A, and an inductance _L2 is generated in the gate line 12-B, and these inductances _L1 and _L2 are proportional to |Φ1-Φ2|. The greater the imbalance between the gate current _Ig1 and the gate current _Ig2 , the larger the inductances _L1 and _L2 become. Also, as the inductances _L1 and _L2 increase, the impedance of the gate lines 12-A and 12-B increases, making it difficult for the gate currents _Ig1 and _Ig2 to flow. As a result, the impedance of the gate lines 12-A and 12-B changes according to the imbalance between the gate currents Ig ₁ and Ig ₂ , so that the gate currents Ig ₁ and Ig ₂ can be operated to match each other.

In this way, the magnetic coupling portion 13 has a function of operating so that the gate currents _Ig1 and _Ig2 coincide with each other even if the timing of the OFF operation of the power semiconductor element _QA and the power semiconductor element _QB is _not aligned, but in the embodiment of the present disclosure, by providing the capacitors 14-A and 14-B corresponding to the power semiconductor elements _QA and _QB , the timing difference of the ON/OFF operation of the power semiconductor element _QA and the power semiconductor element QB is more reliably corrected even if there is _variation in the transmission time of the gate signal to the power semiconductor elements _QA and _QB or in the characteristics of the two power semiconductor elements QA and _QB .

The capacitor 14-A is provided corresponding to the power semiconductor element Q _A , and is connected between the drain terminal 22- _A which is the current input terminal and the gate terminal 21-A which is the control terminal for the power semiconductor element Q A. The capacitor 14-B is provided corresponding to the power semiconductor element Q _B , and is connected between the drain terminal 22-B which is the current input terminal and the gate terminal 21-B which is the control terminal for the power semiconductor element Q _B.

Here, as an example, a current flow through the magnetic coupling portion 13 and the capacitors 14-A and 14-B when the power semiconductor element _QA turns on and off earlier than the power semiconductor element _QB will be described with reference to FIGS. 3 to 5.

3 is a diagram illustrating a state where a gate current starts to flow in a gate drive device according to an embodiment of the present disclosure, FIG. 4 is a diagram illustrating a gate current flow in a gate drive device according to an embodiment of the present disclosure when the power semiconductor element _QA is turned on before the power semiconductor element _QB after the state of FIG. 3, and FIG. 5 is a diagram illustrating a gate current flow in a gate drive device according to an embodiment of the present disclosure when the power semiconductor element _QA is turned off before the power semiconductor element _QB after the state of FIG. 4.

3, for example, when the gate drive voltage output unit 11-A outputs a positive gate drive voltage that is an ON gate signal before the gate drive voltage output unit 11-B, the current I _A1 output from the gate drive voltage output unit 11-A flows to the magnetic coupling unit 13, inducing a current I _B1 . A positive gate drive voltage is applied to the gate terminal 21-A of the power semiconductor element Q _A by the current I _A1 , turning on the power semiconductor element Q _A , and as shown in FIG. 4, a current I _A2 flows through the capacitor 14-A, and a current I _B2 is further induced by the magnetic coupling unit 13, and a positive gate drive voltage is applied to the gate terminal 21-B of the power semiconductor element Q _B by this current I _B2 , assisting the ON operation of the power semiconductor element Q _B to coincide with the operation of the power semiconductor element Q _A. Thereafter, when the gate drive voltage output unit 11-A outputs a gate drive voltage of 0V, which is an OFF gate signal, before the gate drive voltage output unit 11-B, a current is induced by the current flowing from the gate terminal 21-A toward the gate drive voltage output unit 11-A flowing to the magnetic coupling unit 13. The voltage of the gate terminal 21-A of the power semiconductor element _QA becomes 0V, turning the power semiconductor element _QA OFF, and as shown in Fig. 5, a current I _A3 flows from the drain terminal of the power semiconductor element _QA via the capacitor 14-A to the magnetic coupling unit 13, and a current I _B3 is further induced by this current I _A , and the voltage of the gate terminal 21-B of the power semiconductor element _QB becomes 0V, assisting the OFF operation of the power semiconductor element _QB to coincide with the operation of the power semiconductor element _QA .

The above-mentioned gate drive device 1 can also drive the power semiconductor elements on and off in a power conversion device configured with multiple arms connected in series, each arm having multiple power semiconductor elements connected in series.

Fig. 6 is a diagram showing a power conversion device including a gate driver according to an embodiment of the present disclosure. Fig. 7 is a circuit diagram showing an arm provided in the power conversion device shown in Fig. 6. Here, as an example, an example in which the arm 50 is formed by two power semiconductor elements _QA and _QB connected in series will be described.

The power conversion device 100 according to one embodiment of the present disclosure comprises the above-mentioned gate drive device 1, a power conversion circuit unit 2 having four arms 50 each having a plurality of power semiconductor elements connected in series and capacitors corresponding to the power semiconductor elements, and performing power conversion operation in response to the on/off operation of the power semiconductor elements, and a power conversion control unit 3 that controls the power conversion operation of the power conversion circuit unit 2.

As shown in FIG. 7, the arm 50 is composed of, for example, two power semiconductor elements _QA and _QB connected in series, and capacitors 14-A and 14-B corresponding to the power semiconductor elements _QA and _QB , respectively. The capacitor 14-A is connected between the drain terminal 22- _A and the gate terminal 21-A of the power semiconductor element QA. The capacitor 14- _B is connected between the drain terminal 22-B and the gate terminal 21-B of the power semiconductor element QB. A terminal _P1 is drawn from the drain terminal of the power semiconductor element _QA , and a terminal _P2 is drawn from the source terminal of the power semiconductor element _QB . In the power conversion circuit unit 2, a terminal _P2 of a certain arm 50 is connected to a terminal _P1 of another arm 50, and the connection point is connected to one terminal of the load 300. In the example shown in FIG. 6, two arms 50 are connected in series to form one leg 60, and the power conversion circuit unit 2 is composed of the two legs 60.

A DC power supply 200 is connected to a leg 60 composed of the arms 50 connected in series. A load 300 is connected between a terminal _T1 between the arms 50 connected in series in one leg 60 and a terminal _T2 between the arms 50 connected in series in the other leg 60.

A gate driver 1 is provided corresponding to each arm 50. The power semiconductor element _QA and the power semiconductor element _QB in each arm 50 are turned on and off by the corresponding gate driver 1. That is, the gate driver voltage output unit 11-A and the gate driver voltage output unit 11-B generate gate driver voltages and control the voltages applied to the gate terminals of the power semiconductor elements _QA and _QB , respectively.

The power conversion control unit 3 controls the magnitude of the gate drive voltage output from the gate drive voltage output units 11-A and 11-B in each gate drive device 1. That is, the power conversion control unit 3 generates a gate command signal for controlling the gate drive voltage output units 11-A and 11-B in each gate drive device 1 to output a positive gate drive voltage (for example, _10V ) or a gate drive voltage of ^0V so that there is no deviation between the detection value i of the current flowing from the positive terminal T1 to the load 300 and the current command i*, which is the control target value. The generated gate command signal is transmitted to the gate drive voltage output units 11-A and 11-B. In response to this, the gate drive voltage output units 11- _A and 11-B output a positive gate drive voltage (for example, 10V) corresponding to the ON signal of the gate signal and a gate drive voltage of 0V corresponding to the OFF signal of the gate signal to the gate terminals of the power semiconductor elements QA and _QB . The power semiconductor elements _QA and _QB perform ON and OFF operations depending on the magnitude of the gate drive voltage applied to the gate terminals. As a result, the power conversion circuit unit 2 performs a power conversion operation of converting the DC power supplied from the DC power supply 200 into a desired power and supplying it to the load 300 .

An arithmetic processing device (processor) is provided within the power conversion device 100. This arithmetic processing device has a power conversion control unit 3 and a switch control unit 4 described later. The power conversion control unit 3 and the switch control unit 4 of the arithmetic processing device are functional modules realized, for example, by a computer program executed on the processor. For example, when the power conversion control unit 3 is constructed in the form of a computer program, the arithmetic processing device can be operated according to the computer program to realize the function. The computer program for executing the processing of the power conversion control unit 3 and the switch control unit 4 may be provided in a form recorded on a computer-readable recording medium such as a semiconductor memory, a magnetic recording medium, or an optical recording medium. Alternatively, the power conversion control unit 3 and the switch control unit 4 may be realized as a semiconductor integrated circuit in which a computer program that realizes the function is written.

Next, we will explain the degree of imbalance in the applied voltage during on and off operation when there is variation in the transmission time of the gate signal to each power semiconductor element and in the characteristics of each power semiconductor element.

Figure 8A is a diagram explaining the definition of the imbalance in applied voltage during off operation when there is variation in the transmission time of a gate signal to two power semiconductor elements or in the characteristics of the two power semiconductor elements, and Figure 8B is a diagram explaining the definition of the imbalance in applied voltage during on operation when there is variation in the transmission time of a gate signal to two power semiconductor elements or in the characteristics of the two power semiconductor elements.

8A, as a phenomenon occurring when power semiconductor elements _QA and _QB are off, when the gate potential of power semiconductor element QA is changed from a certain positive potential to a certain negative potential, the drain-source voltage of power semiconductor element _QA changes from 0 [V] to Vds _A [V], and when the gate potential of power semiconductor element _QB is changed from a certain positive potential to a certain negative potential, the drain-source voltage of power _{semiconductor} element _QB changes from 0 [V] to Vds _B [V]. At this time, the imbalance of applied voltages during off operation is defined as ΔVds _off [%] as shown in Equation 1.

Furthermore, as shown in FIG. 8B , when the average value of the drain-source voltages of the power semiconductor elements _QA and _QB in the off state when the gate potentials of the power semiconductor elements _QA and _QB are at a certain negative potential is defined as Vds _ave [V], and when the gate potentials of the power semiconductor elements _QA and _QB are changed from a certain negative potential to a certain positive potential to turn on the power semiconductor elements _QA and _QB , the difference between Vds _ave [V] and a maximum rise voltage which is a jump in the drain-source voltage of either one of the power semiconductor elements that occurs and Vp [V] is defined as Vp [V], the imbalance of the applied voltages during the on operation is defined as ΔVds _on [%] as shown in Equation 2.

Here, the imbalance degree for each of the cases where there is no magnetic coupling of the gate lines, the case where there is magnetic coupling of the gate lines in Patent Document 1 (JP Patent No. 4396036), the case where there is magnetic coupling of the gate lines and a capacitor in Patent Document 2 (JP Patent No. 4639687), and one embodiment of the present disclosure will be compared and examined in the simulations shown in Figures 9 to 11. A simulation was performed assuming that a current of 750 A flows when a voltage of 3.6 kV is applied when SiC-MOSFET power semiconductor elements Q _A and Q _B with a breakdown voltage of 3.3 kV are connected in series. In addition, in the simulation, each value of the primary inductance and secondary inductance of the transformer constituting the magnetic coupling part is set to 70 μH, the coupling coefficient k of the transformer is set to 0.97, and the capacitance value C _x of the capacitor provided in Patent Document 2 (JP Patent No. 4639687) and one embodiment of the present disclosure is set to 220 pF.

Figure 9 is a comparative example of simulation results regarding the degree of imbalance for a configuration in which there is no magnetic coupling of the gate lines, a configuration according to Patent Document 1 (Patent Publication No. 4,396,036) in which there is magnetic coupling of the gate lines, a configuration according to Patent Document 2 (Patent Publication No. 4,639,687) in which there is magnetic coupling of the gate lines and a capacitor, and one embodiment of the present disclosure, when there is variation in the transmission time of the gate signal to the power semiconductor element.

In Fig. 9, a simulation was performed assuming that the gate signal ON signal for the power semiconductor element _QA is output 250 ns earlier than the gate signal ON signal for the power semiconductor element _QB , and the gate signal OFF signal for the power _{semiconductor} element QA is output 250 ns earlier than the gate signal OFF signal for the power semiconductor element _QB . As shown in Fig. 9, when there is variation in the transmission time of the gate signals to the power semiconductor elements, it can be seen that one embodiment of the present disclosure is most effective in aligning the timing of the ON operation and the timing of the OFF operation between the power semiconductor element _QA and the power semiconductor element _QB .

Figure 10 is a comparative example of simulation results regarding the degree of imbalance for a configuration in which there is no magnetic coupling of the gate lines, a configuration according to Patent Document 1 (Patent Publication No. 4,396,036) in which there is magnetic coupling of the gate lines, a configuration according to Patent Document 2 (Patent Publication No. 4,639,687) in which there is magnetic coupling of the gate lines and a capacitor, and one embodiment of the present disclosure, when there is variation in the characteristics of the power semiconductor elements.

10, a simulation was performed for a case where the power semiconductor element _QA has a first gate threshold voltage _VthA , and the power semiconductor element _QB has a second gate threshold voltage _VthB higher than the first gate threshold voltage (i.e., _VthA < _VthB ). As shown in FIG. 10, when there is variation in the characteristics of the power semiconductor elements, it can be seen that the embodiment of the present disclosure is most effective in aligning the timing of the ON operation and the timing of the OFF operation of the power semiconductor element _QA and the power semiconductor element _QB .

Figure 11 is a comparative example showing simulation results of the degree of imbalance for a configuration in which there is no magnetic coupling of the gate lines, a configuration according to Patent Document 1 (Patent Publication No. 4,396,036) in which there is magnetic coupling of the gate lines, a configuration according to Patent Document 2 (Patent Publication No. 4,639,687) in which there is magnetic coupling of the gate lines and a capacitor, and one embodiment of the present disclosure, when there is variation in the transmission time of the gate signal to the power semiconductor element and variation in the characteristics of the power semiconductor element.

11, in the case where the power semiconductor element _QA has a first gate threshold voltage _VthA and the power semiconductor element _QB has a second gate threshold voltage _VthB higher than the first gate threshold voltage (i.e., _VthA < _VthB ), a simulation was performed assuming that the ON signal of the gate signal for the power semiconductor element _QB is output 250 ns earlier than the ON signal of the gate signal for the power semiconductor element _QA , and the OFF signal of the gate signal for the power semiconductor element _QB is output 250 ns earlier than the OFF signal of the gate signal for the power semiconductor element _QA . As shown in FIG. 11, when there is variation in the transmission time of the gate signal to the power semiconductor elements and there is variation in the characteristics of the power semiconductor elements, it can be seen that one embodiment of the present disclosure is most effective in aligning the timing of the ON operation and the timing of the OFF operation between the power semiconductor element _QA and the power semiconductor element _QB .

Thus, according to one embodiment of the present disclosure, in a gate drive device for multiple power semiconductor elements connected in series and a power conversion device including the same, even if there is variation in the transmission time of the gate signal or the characteristics of the power semiconductor elements, the switching timing for the on and off operations of each of the power semiconductor elements can be aligned, thereby suppressing imbalances in the voltages applied to the power semiconductor elements.

Next, we will provide a more detailed description of the capacitor that is provided in correspondence with the power semiconductor element in one embodiment of the present disclosure.

Fig. 12 is a circuit diagram for explaining the parasitic capacitance of a MOSFET. In general, parasitic capacitance exists between each terminal of a power semiconductor element. As shown in Fig. 12, for example, in a MOSFET, a parasitic capacitance _Cgs exists between the source terminal and the gate terminal, a parasitic capacitance _Cdg exists between the drain terminal and the gate terminal, and a parasitic capacitance _Cds exists between the drain terminal and the source terminal.

Figure 13 is a diagram explaining the relationship between the current capacity of a power semiconductor element and the parasitic capacitance of the power semiconductor element. In general, the parasitic capacitance of a power semiconductor element changes depending on the current capacity and withstand voltage. In other words, when the current capacity of a power semiconductor element increases, the semiconductor chip area of the power semiconductor element increases, and the value of the parasitic capacitance becomes larger. For example, if the parasitic capacitance value is "1" when the current capacity of a power semiconductor element is "1", if the current capacity of the power semiconductor element becomes four times that, the semiconductor chip area will become four times larger, and the parasitic capacitance value will also become four times larger.

The capacitance of a capacitor provided between the drain terminal and gate terminal of a MOSFET, which is a power semiconductor element, is assumed to be C _x [F]. The drain-source voltage V _ds [V] applied between the drain terminal and source terminal of the MOSFET is divided, and a gate-source voltage V _gs1 [V] appears between the gate terminal and the source terminal as shown in Equation 3.

When the drain-source voltage V _ds [V] of the MOSFET is large (for example, 1800 V), the parasitic capacitance value C _dg [F] between the drain terminal and the gate terminal is small compared to C _x [F], and the capacitance value C _x [F] of the capacitor provided between the drain terminal and the gate terminal needs to be large enough to affect the gate-source voltage V _gs1 [V], so the value C _dg [F] in the numerator of Equation 3 is ignored. The parasitic capacitance value C _gs [F] between the gate terminal and the source terminal is large compared to the parasitic capacitance value C _dg [F] between the drain terminal and the gate terminal and the capacitance value C _x [F] of the capacitor provided between the drain terminal and the gate terminal, so the values C _dg [F] and C _x [F] in the denominator of Equation 3 can be ignored. On the other hand, since the sum of the parasitic capacitance value C _gs [F] between the gate terminal and the source terminal and the parasitic capacitance value C _dg [F] between the drain terminal and the gate terminal corresponds to the input capacitance C _iss [F] generally specified in the data sheet of a MOSFET, the denominator of Equation 3 is the sum of the parasitic capacitance value C _dg [F] between the drain terminal and the gate terminal and the parasitic capacitance value C _gs [F] between the gate terminal and the source terminal. The gate-source voltage V _gs [V] is affected according to the change in the drain-source voltage V _ds [V]. The degree of the influence is determined by the ratio of the parasitic capacitance value of the MOSFET shown in Equation 3 to the capacitance value C _x [V] of the capacitor provided between the drain terminal and the gate terminal. Therefore, in accordance with Equation 3, in the embodiment of the present disclosure, the capacitance value C _x [F] of the capacitor provided between the drain terminal and the gate terminal of the MOSFET is generalized to the value C _x ^* (hereinafter referred to as the "capacitance ratio C _x ^* ") expressed in Equation 4.

By expressing the capacitance value C _x [F] of the capacitor provided between the drain terminal and gate terminal of a MOSFET as a generalized capacitance ratio C _x ^* as shown in Equation 4, the relationship between the imbalance degree ΔVds _off or ΔVds _on of the applied voltage and the capacitance value C _x [F] of the capacitor provided between the drain terminal and gate terminal can be uniquely shown in the on/off operation of series-connected MOSFETs, even if the MOSFET specifications vary.

FIG. 14 is a diagram illustrating the relationship between the current capacity and the input capacitance Ciss of power semiconductor elements of different specifications. In FIG. 14, for reference, the relationship between the current capacity and _Ciss (input capacitance _Cies in the case of IGBT) of each of the 1.2 kV-SiC diode/SiC-MOSFET and 1.2 kV-SiC diode/Si-IGBT power modules is shown. It can be seen that the value of _Ciss changes in proportion to the current capacity of the MOSFET. Since the value of _Ciss differs depending on the current capacity specification, MOSFETs with different current capacity specifications have different capacitance values _Cx [F] of the capacitor provided between the suitable drain terminal and gate terminal. However, by expressing it as a generalized capacitance ratio _Cx ^* , the relationship between the imbalance degree ΔVds _off or ΔVds _on of the applied voltage of MOSFETs with different current capacity values and the capacitance value _Cx [F] of the capacitor provided between the drain terminal and the gate terminal can be unified.

Here, we explain the preferred range of capacitance values of the capacitors provided corresponding to the power semiconductor elements in one embodiment of the present disclosure.

First, we will explain the lower limit of the capacitance value of a capacitor that is provided corresponding to a power semiconductor element, using a MOSFET as an example.

15 is a diagram showing the relationship between the capacitance ratio C _x ^* of the capacitors provided corresponding to the power semiconductor elements and the imbalance degree of the applied voltage when two power semiconductor elements having different gate threshold voltages are driven by a gate driver according to an embodiment of the present disclosure. In FIG. 15, the capacitance value C _x [pF] of the capacitor is also shown in addition to the capacitance ratio C _x ^* of the capacitor provided corresponding to a 3.3 kV SiC MOSFET power module.

15, it can be seen that the larger the capacitance ratio C _x ^* of the capacitors is, the more the applied voltage imbalance ΔVds _off during off operation can be suppressed, and the effect becomes significant when the capacitance ratio C _x ^* of the capacitors is 5×10 ^-5 or more. Therefore, in an embodiment of the present disclosure, as represented by, for example, formula 5, the lower limit of the capacitance ratio C _x ^* of the capacitors that exhibits a significant effect of suppressing the applied voltage imbalance (e.g., an improvement of 10% or more) may be set to 5×10 ^-5 .

Converting this to a capacitor capacitance value _Cx [pF], for example, by setting the capacitor capacitance value _Cx to 10 pF or more in the case of a 3.3 kV SiC MOSFET power module, and Cx to 1.7 pF or more in the case of a 1.2 kV SiC MOSFET power module (input capacitance _{Ciss is} 34 nF), it is possible to improve the imbalance of applied voltages by 10% or more compared to a conventional configuration in which there is no magnetic coupling of the gate lines.

Next, we will explain the upper limit of the capacitance value of a capacitor that is provided corresponding to a power semiconductor element, using a MOSFET as an example.

When a drain-source voltage V _ds [V] is applied to a MOSFET and the gate terminal becomes unstable (open state), a voltage V _gs2 [V] as shown in Equation 6 is applied to the gate terminal.

Generally, in a data sheet for a MOSFET, an upper limit V _gsmax is defined to prevent breakdown due to the gate-source voltage V _gs [V] becoming an overvoltage. If this upper limit V _gsmax is set to V _gs2 in Equation 6, Equation 7 can be derived.

In a region where the drain-source voltage V _ds [V] is high, C _dg [F] is small and can be ignored, and equation 7 is solved for the capacitance value C _x [F] of the capacitor to obtain equation 8.

In this way, there is an upper limit to the capacitance value C _x [F] of the capacitor as shown in Equation 8.

For example, if the power semiconductor element driven by the gate driver 1 is configured as a 3.3 kV/750 A-All SiC MOSFET power module, then if V _gsmax = 20 V, V _ds = 1650 V (= 3.3 kV/2), and C _gs = 200 nF (1.65 kV), then the upper limit value of the capacitor provided corresponding to the MOSFET will be 2.45 nF.

For example, if the power semiconductor element driven by the gate driver 1 is configured as a 1.2 kV/400 A-All SiC MOSFET power module, then if V _gsmax = 20 V, V _ds = 600 V (= 1.2 kV/2), and C _gs = 32 nF (600 V), the upper limit value of the capacitor provided corresponding to the MOSFET will be 1.10 nF.

Thus, in one embodiment of the present disclosure, the capacitance value C _x [F] of the capacitor provided corresponding to the MOSFET has a lower limit that satisfies Expression 5, and an upper limit that satisfies Expression 8. As with MOSFETs, IGBTs, thyristors, GTOs, and transistors also have parasitic capacitance between their terminals. Therefore, even if a power semiconductor element is composed of an IGBT, a thyristor, a GTO, or a transistor, the capacitance value of the capacitor provided corresponding to the power semiconductor element has lower and upper limits, just like a MOSFET.

Equation 5 defined for MOSFETs is generalized to equation 9, and equation 8 defined for MOSFETs is generalized to equation 10. In equations 9 and 10, the value of the parasitic capacitance between the current outflow terminal and gate terminal of the power semiconductor element is C ₁ [F] (corresponding to C _gs [F] of MOSFET), the value of the parasitic capacitance between the current inflow terminal and gate terminal is C ₂ [F] (corresponding to C _dg [F] of MOSFET), the voltage applied between the current inflow terminal and current outflow terminal is V ₁ [V] (corresponding to V _ds [V] of MOSFET), and the maximum allowable applied voltage between the gate terminal and current outflow terminal is V _max [V] (corresponding to V _gsmax [V] of MOSFET).

In this way, for the capacitance value C _x [F] of the capacitor provided corresponding to the power semiconductor element in one embodiment of the present disclosure, there exists a lower limit value that satisfies Expression 9, and there exists an upper limit value that satisfies Expression 10.

As described above, an example of turning on and off two power semiconductor elements connected in series has been described, but the gate drive device 1 according to one embodiment of the present disclosure can also turn on and off three or more power semiconductor elements connected in series.

16 is a circuit diagram showing a gate driver for turning on and off three power semiconductor elements connected in series according to an embodiment of the present disclosure. As an example, an example of turning on and off three power semiconductor elements _QA , _QB , and _QC connected in series will be described.

A diode D _A is connected in anti-parallel to the power semiconductor element Q _A. Similarly, a diode D _B is connected in anti-parallel to the power semiconductor element Q _B , and a diode D _C is connected in anti-parallel to the power semiconductor element Q _C.

The gate drive device 1 comprises gate drive voltage output units 11-A, 11-B and 11-C, gate lines 12-A, 12-B and 12-C, a magnetic coupling unit 13, and capacitors 14-A, 14-B and 14-C.

The gate drive voltage output section 11-A is provided corresponding to the power semiconductor element _QA , and outputs a positive gate drive voltage (e.g., 10V) corresponding to an on-signal of a gate signal, and a gate drive voltage of 0V corresponding to an off-signal of a gate signal. The gate drive voltage output section 11-B is provided corresponding to the power semiconductor element _QB , and outputs a positive gate drive voltage (e.g., 10V) corresponding to an on-signal of a gate signal, and a gate drive voltage of 0V corresponding to an off-signal of a gate signal. The gate drive voltage output section 11-C is provided corresponding to the power semiconductor element _QC , and outputs a positive gate drive voltage (e.g., 10V) corresponding to an on-signal of a gate signal, and a gate drive voltage of 0V corresponding to an off-signal of a gate signal.

The gate line 12-A supplies the gate drive voltage output from the gate drive voltage output unit 11-A to a gate terminal 21-A which is the control terminal of the corresponding power semiconductor element Q _A. When a positive gate drive voltage is applied to the gate terminal of the power semiconductor element Q _A , the power semiconductor element Q _A turns on, and when a gate drive voltage of 0 V is applied to the gate terminal of the power semiconductor element Q _A, the power semiconductor element Q _A turns off.

The gate line 12-B supplies the gate drive voltage output from the gate drive voltage output unit 11-B to a gate terminal 21-B which is the control terminal of the corresponding power semiconductor element Q _B. When a positive gate drive voltage is applied to the gate terminal of the power semiconductor element Q _B , the power semiconductor element Q _B is turned on, and when a gate drive voltage of 0 V is applied to the gate terminal of the power semiconductor element Q _B , the power semiconductor element Q _B is turned off.

The gate line 12-C supplies the gate drive voltage output from the gate drive voltage output unit 11-C to a gate terminal 21-C which is the control terminal of the corresponding power semiconductor element Q _C. When a positive gate drive voltage is applied to the gate terminal of the power semiconductor element Q _C , the power semiconductor element Q _C turns on, and when a gate drive voltage of 0 V is applied to the gate terminal of the power semiconductor element Q _C , the power semiconductor element Q _C turns off.

The magnetic coupling portion 13 magnetically couples the gate lines 12-A and 12-B, and magnetically couples the gate lines 12-B and 12-C.

The capacitor 14-A is provided corresponding to the power semiconductor element _QA , and is connected between the drain terminal 22-A which is the current inflow terminal for the power semiconductor element _QA , and the gate terminal 21-A which is the control terminal. The capacitor 14-B is provided corresponding to the power semiconductor element _QB , and is connected between the drain terminal 22-B which is the current inflow terminal for the power semiconductor element _QB, and the gate terminal 21-B which is the control terminal. The capacitor 14-C is provided corresponding to the power semiconductor element _QC , and is connected between the drain terminal 22-C which is the current inflow terminal for the power semiconductor element _QC , and the gate terminal 21-C which is the control terminal.

Thus, the gate drive device 1 according to an embodiment of the present disclosure has a configuration in which the same number of gate drive voltage output units, gate lines, and capacitors as the number of power semiconductor elements connected in series are provided, and the gate lines are magnetically coupled to each other at the magnetic coupling unit. According to an embodiment of the present disclosure, even if there is variation in the transmission time of the gate signal for the power semiconductor elements or the characteristics of the power semiconductor elements, it is possible to align the switching timing for the on and off operations of each of the power semiconductor elements, thereby suppressing imbalances in the voltages applied to the power semiconductor elements.

Next, a modified example of an embodiment of the present disclosure will be described. As an example, an example in which two power semiconductor elements _QA and _QB connected in series are turned on and off will be described, but this modified example can also be applied to a case in which three or more power semiconductor elements connected in series are turned on and off.

Before explaining this modified example, we will explain the possibility of a power supply short circuit occurring when a capacitor is provided in correspondence with a power semiconductor element as in the embodiment of the present disclosure.

Figure 17 is a circuit diagram showing a leg formed by an arm having two power semiconductor elements connected in series in one embodiment of the present disclosure. Also, Figure 18A is a diagram illustrating the voltages applied to the power semiconductor elements in each arm in the leg shown in Figure 17, and Figure 18B is a diagram illustrating the gate-source voltages of each power semiconductor element in the leg shown in Figure 17.

As shown in Fig. 17, for example, in a leg 60 formed by connecting two arms in series, each arm being formed of two power semiconductor elements _QA and _QB connected in series and capacitors 14-A and 14-B corresponding to the power semiconductor elements _QA and _QB , respectively, it is assumed that a load current _ILOAD flows from the terminal _T1 toward the load 300. As shown in Figs. 18A and 18B, in a state in which the gate-source voltage Vgs _-bt1 of the power semiconductor element _QC and the gate-source voltage _Vgs-bt2 of the power semiconductor element _QD are fixed to a negative voltage V(-), for example, and a current flows through the diodes _Dc and _Dd , when the power semiconductor elements _QA and _QB are turned on, the current flowing through the diodes _Dc and _Dd decreases and the current flowing through the power semiconductor elements _QA and _QB increases. When the current flowing through the diodes _Dc and _Dd becomes zero, the applied voltage _Vbt of the lower arm 50-2 rises and the applied voltage _Vup of the upper arm 50-1 drops. When current flows in through the capacitors 14-C and 14-D due to this change in applied voltage, an electromotive force is generated in the parasitic inductance _Lr and gate resistance _Rg of the magnetic coupling portion 13, and the gate-source voltage V _gs-bt1 of the power semiconductor element _QC and the gate-source voltage V _gs-bt2 of the power semiconductor element _QD rise. If this voltage rise is large, the gate-source voltage V _gs-bt1 of the power semiconductor element _QC and the gate-source voltage V _gs-bt2 of the power semiconductor element _QD may exceed the gate threshold voltages of the power semiconductor elements _QC and _QD , resulting in erroneous ON operation. If all of the power semiconductor elements Q _A , Q _B , Q _C , and Q _D are turned ON due to this malfunction, the upper side potential Vp and the lower side potential 0V of the leg 60 are short-circuited.

Therefore, in this modified example, a switch is provided between the gate terminal and source terminal of the power semiconductor element, and the switch is turned on during the period when a power semiconductor element provided in an arm other than the arm to which the switch belongs is on, thereby preventing a rise in the gate-source voltage due to changes in the applied voltage and avoiding a short circuit between the upper potential Vp of leg 60 and the lower potential 0V.

FIG. 19A is a circuit diagram showing a gate driver according to a modified example of an embodiment of the present disclosure. FIG. 19B is a circuit diagram showing a case where a switch provided in a gate driver according to a modified example of an embodiment of the present disclosure is configured with a MOSFET. According to this modified example, the gate driver 1 further includes a switch SW _A connected between a source terminal 23-A, which is a current outflow terminal of the power semiconductor element Q _A , and a gate terminal 21-A, which is a control terminal, and a switch control unit 4 that controls the on/off of the switch SW _A. In the example shown in FIG. 19B, the switch SW _A is configured with an n-channel MOSFET, but may be configured with another semiconductor switching element. In the examples shown in FIGS. 19A and 19B, the switch control unit 4 is provided in the gate drive voltage output unit 11-A, but the switch control unit 4 may be provided outside the gate drive voltage output unit 11-A.

19A and 19B, only a switch SW _A corresponding to the power semiconductor element Q _A is shown, but a switch is provided corresponding to each of a plurality of power semiconductor elements. Fig. 20 is a circuit diagram showing a power conversion device including a leg constituted by an arm having two power semiconductor elements connected in series in a modified example of an embodiment of the present disclosure.

As shown in Fig. 20, for example, an upper arm 50-1 having two serially connected power semiconductor elements _QA and _QB and capacitors 14-A and 14-B corresponding to the power semiconductor elements _QA and _QB , respectively, and a lower arm 50-2 having two serially connected power semiconductor elements _QC and QD and capacitors 14-C and 14- _D corresponding to the power semiconductor elements _QC and _QD , respectively, are connected in series to form a leg 60. A switch SW _A is connected between the source terminal 23-A and the gate terminal 21-A of the power semiconductor element QA. A switch SW _B is connected between the source terminal 23-B and the gate terminal 21-B of the power semiconductor element _QB . A switch SW _C is connected between the source terminal 23-C and the gate terminal 21-C of the power semiconductor element _QC . A switch _{SW D is} connected between the source terminal 23-D and the gate terminal 21-D of the power semiconductor element _QD . 20, the switches SW _A , SW _B , SW _C , and SW _D are configured by n-channel MOSFETs, for example. An n-channel MOSFET turns on when a positive voltage (on signal) is applied to the gate terminal.

In the example shown in Fig. 20, a switch control unit 4 that controls the on/off of switches SW _A , SW _B , SW _c and SW _D is provided in the power conversion control unit 3. The switch control unit 4 controls to turn on the switch provided in the arm to which the power semiconductor element belongs during the off period of the power semiconductor element in one cycle related to the on/off operation of the power semiconductor element. A specific example will be described with reference to Figs. 21A and 21B.

Figure 21A is a diagram explaining the operation of the switch control unit when the power semiconductor element in the upper arm in the power converter shown in Figure 20 is turned on and the power semiconductor element in the lower arm is turned off. Also, Figure 21B is a diagram explaining the operation of the switch control unit when the power semiconductor element in the upper arm in the power converter shown in Figure 20 is turned off and the power semiconductor element in the lower arm is turned on. Note that a dead time is provided for each gate signal to avoid a short circuit when switching the power semiconductor elements on and off.

The switch control unit 4 controls the on/off operation of the switch so that during an off period of a power semiconductor element in one cycle related to the on/off operation of the power semiconductor element, at least an on period of the switch provided in the arm to which the power semiconductor element belongs that is in the off period is provided. The on period of the switch is controlled to be longer than the on period of the power semiconductor element provided in an arm different from the arm to which the switch belongs and shorter than the off period of the power semiconductor element provided in the arm to which the switch belongs.

For example, as shown in Fig. 21A, it is assumed that while a gate signal Gate_1 for power semiconductor elements _QA and _QB in the upper arm 50-1 is in an on period, a gate signal Gate_2 for power semiconductor elements _QC and _QD in the lower arm 50-2 is in an off period. In the example shown in Fig. 21A, the switch control unit 4 controls the on/off operation of the switches _SWC and SWD so that during the off period of the power semiconductor elements _QC and _QD in one cycle of the gate signal _{Gate_2} related to the on/off operation of the power semiconductor elements _QC and _QD , there is at least an on period of the switches _SWC and _SWD provided in the lower arm 50-2 to which the power semiconductor elements _QC and _QD belong that are in the off period. The on-periods of the switches SW _C and SW _D are controlled to _{be longer than the on-periods of the power semiconductor elements Q A and} Q _B provided in the upper arm 50-1 different from the lower arm 50-2 to which the switches SW C and SW _D belong, and shorter than the off-periods of the power semiconductor elements Q _C and Q _D provided in the lower arm 50-2 to which the switches SW _C and SW _D belong.

21B, for example, while a gate signal Gate_2 for power semiconductor elements _QC and _QD in the lower arm 50-2 is in an on period, a gate signal Gate_1 for power semiconductor elements _QA and _QB in the upper arm 50-1 is in an off period. In the example shown in Fig. 21B, the switch control unit 4 controls the on/off operation of the switches SW _A and SW _B so that, during the off period of the power semiconductor elements _QA and _QB in one period of the gate signal Gate_1 related to the on/off operation of the power semiconductor elements _QA and QB, at least an on period of the switches SW _A and SW _B provided in the upper arm 50-1 to which the power semiconductor elements QA and _QB belong _that are _in the off period is provided. The on-periods of the switches SW _A and SW _B are controlled to _be longer than the on-periods of the power semiconductor elements Q _C and Q _D provided in the lower arm 50-2 different from the upper arm 50-1 to which the switches SW A and SW _B belong, and shorter than the off-periods of the power semiconductor elements Q _A and Q _B provided in the upper arm 50-1 to which the switches SW _A and SW _B belong.

In this manner, in this modified example, a switch is provided between the gate and source terminals of a power semiconductor element, and the switch is turned on during the period when a power semiconductor element provided in an arm other than the arm to which the switch belongs is on, thereby preventing a rise in the gate-source voltage due to changes in the applied voltage and avoiding a short circuit between the upper potential Vp of leg 60 and the lower potential 0V.

Next, we will explain examples of the placement of a capacitor between the drain terminal and gate terminal of a MOSFET in one embodiment and a modified example of the present disclosure.

Each of the capacitors is provided corresponding to each of the power semiconductor elements, but if the connection wiring between one terminal of the capacitor and the gate terminal of the power semiconductor element, or the connection wiring between the other terminal of the capacitor and the drain terminal of the power semiconductor element, is long, a large parasitic impedance will be generated. As described with reference to Figures 3 to 5, the timing of the on/off operation of the power semiconductor element is corrected by the current flowing into the capacitor, so if the parasitic impedance is large, the effect of the timing correction will be reduced. Therefore, each of the capacitors is arranged close to the corresponding power semiconductor element. Figure 22A is a transparent perspective view showing an example of the arrangement of capacitors in a gate drive device according to an embodiment of the present disclosure. Figure 22A shows a power module 42 having one power semiconductor element as an example. For example, as shown in Figure 22A, a printed circuit board 41 on which a capacitor 14 is mounted is arranged adjacent to a power module 42 having a power semiconductor element. At this time, the capacitor 14 is arranged close to the power semiconductor element in the corresponding power module 42 (for example, arranged directly above, directly below, or directly beside), so that the connection wiring between one terminal of the capacitor 14 and the gate terminal of the power semiconductor element and the connection wiring between the other terminal of the capacitor 14 and the source terminal of the power semiconductor element are as short as possible. This makes it possible to reduce parasitic impedance. FIG. 22A shows a case where the power semiconductor element is a MOSFET, but FIG. 22B is a perspective view illustrating a power module having an IGBT as the power semiconductor element. For example, when the power semiconductor element is an IGBT, the power module 42 is provided with a gate terminal 21, a collector terminal 22, and an emitter terminal 23 of the IGBT. The capacitor 14 is arranged close to the IGBT of the corresponding power module 42 so that the connection wiring between one terminal of the capacitor 14 and the gate terminal 21 of the IGBT and the connection wiring between the other terminal of the capacitor 14 and the collector terminal 22 of the IGBT are as short as possible.

Next, we will explain the installation of a cooler that can further enhance the effect of suppressing the voltage applied to the power semiconductor element in one embodiment and variant of the present disclosure.

Figure 23 is an oblique view illustrating a cooler provided in a gate drive device according to one embodiment of the present disclosure.

The temperature of the power semiconductor elements rises due to self-heating during on/off operation. Therefore, for example, due to design constraints or the placement position of the power semiconductor elements, temperature differences may occur between the power semiconductor elements in the power conversion device. When the temperature of the power semiconductor elements rises, the gate threshold voltage decreases. If there is a temperature difference between the power semiconductor elements, the gate threshold voltage will vary, and the imbalance of the applied voltage during on operation and off operation will increase. Therefore, by cooling each of the power semiconductor elements by the same cooler 5, the temperature difference between the power semiconductor elements is suppressed to prevent the variation of the gate threshold voltage, the switching timing for the on operation and off operation of each of the power semiconductor elements is aligned, and the imbalance of the voltage applied to the power semiconductor elements is more reliably suppressed.

In the example shown in Figure 23, a printed circuit board 41-A on which a capacitor 14-A is mounted is disposed adjacent to a power module 42-A having a power semiconductor element, and a printed circuit board 41-B on which a capacitor 14-B is mounted is disposed adjacent to a power module 42-B having a power semiconductor element. The power modules 42-A and 42-B are disposed on the same cooler 5 so that the cooler 5 provides the same cooling effect to the power modules 42-A and 42-B. Examples of the cooler 5 include a heat sink, a heat pipe, an air-cooled heat exchanger, and a water-cooled heat exchanger.

As described above, according to one embodiment and variant of the present disclosure, even if there is variation in the transmission time of the gate signal on the gate line or in the characteristics of the power semiconductor elements, the switching timing for the on and off operations of each of the power semiconductor elements can be aligned, and imbalances in the voltages applied to the power semiconductor elements can be suppressed.

REFERENCE SIGNS LIST 1 Gate drive device 2 Power conversion circuit section 3 Power conversion control section 4 Switch control section 5 Cooler 11-A, 11-B, 11-C, 11-D Gate drive voltage output section 12-A, 12-B. 12-C Gate line 13 Magnetic coupling portion 14, 14-A, 14-B, 14-C, 14-D Capacitor 21, 21-A, 21-B, 21-C, 21-D Gate terminal 22 Collector terminal 22-A, 22-B, 22-C, 22-D Drain terminal 23 Emitter terminal 23-A, 23-B, 23-C, 23-D Source terminal 30 Magnetic body 41, 41-A, 41-B Printed circuit board 42 Power module 50 Arm 50-1 Upper arm 50-2 Lower arm 60 Leg 100 Power conversion device 200 DC power supply 300 Load D _A , D _B , D _C , D _D Diode L _r Parasitic inductance P ₁ , P ₂ Terminal Q _A , Q _B , Q _C , _QD Power semiconductor element _Rg Gate resistors SW _A , SW _B , SW _C , SW _D Switches T ₁ , T ₂ Terminals

Claims (11)

A gate driver for a plurality of power semiconductor devices connected in series, comprising:
a gate drive voltage output section provided corresponding to each of the power semiconductor devices and configured to output a gate drive voltage;
a gate line for supplying the gate driving voltage output from the gate driving voltage output unit to a gate terminal of each of the corresponding power semiconductor devices;
a magnetic coupling portion that magnetically couples the gate lines to each other;
a capacitor provided in correspondence with each of the power semiconductor elements and connected between a current input terminal and the gate terminal of the power semiconductor element;
A gate drive device comprising: When the value of the parasitic capacitance between the current outflow terminal and the gate terminal of the power semiconductor element is _C1 , and the value of the parasitic capacitance between the current inflow terminal and the gate terminal is _C2 ,
The capacitor is

2. The gate driver of claim 1, having a capacitance C _x that satisfies: When the value of the parasitic capacitance between the current outflow terminal and the gate terminal of the power semiconductor element is _C1 , the voltage applied between the current inflow terminal and the current outflow terminal is _V1 , and the maximum allowable applied voltage between the gate terminal and the current outflow terminal is _Vmax ,
The capacitor is

3. The gate driver according to claim 1, having a capacitance C _x that satisfies: A gate drive device as described in any one of claims 1 to 3, wherein each of the capacitors is arranged in close proximity to a corresponding one of the power semiconductor elements. A gate drive device as described in any one of claims 1 to 4, wherein each of the power semiconductor elements is cooled by the same cooler. A gate driving device as described in any one of claims 1 to 5, wherein the current input terminal of the power semiconductor element is a drain terminal, a collector terminal, or an anode terminal. A gate drive device as described in any one of claims 1 to 6, wherein the current output terminal of the power semiconductor element is a source terminal, an emitter terminal, or a cathode terminal. A gate driver according to any one of claims 1 to 7;
a power conversion circuit section including two arms each including a plurality of power semiconductor elements connected in series and a capacitor corresponding to the power semiconductor elements, the power conversion circuit section performing a power conversion operation in response to an on/off operation of the power semiconductor elements;
a power conversion control unit that controls a power conversion operation of the power conversion circuit unit;
A power conversion device comprising: The power conversion device according to claim 8, further comprising a switch provided for each of the power semiconductor elements and connected between a current drain terminal of the power semiconductor element and the gate terminal. The power conversion device according to claim 9, further comprising a switch control unit that controls the on/off operation of the switch so that, during an off period of the power semiconductor element in one cycle related to the on/off operation of the power semiconductor element, there is at least an on period of the switch provided in the arm to which the power semiconductor element in the off period belongs. The power conversion device according to claim 10, wherein the on-period of the switch is longer than the on-period of the power semiconductor element provided in the arm different from the arm to which the switch belongs, and shorter than the off-period of the power semiconductor element provided in the arm to which the switch belongs.

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