JP7550656B2 - Method for manufacturing silicon carbide semiconductor device - Google Patents

Description

This disclosure relates to a method for manufacturing a silicon carbide semiconductor device.

For example, Patent Document 1 is an example of prior art related to silicon carbide semiconductor devices. Patent Document 1 describes a method for manufacturing a silicon carbide (hereinafter also referred to as SiC) semiconductor device. In Patent Document 1, first, an n-type epitaxial layer is laminated on an n-type SiC substrate. Next, impurities are implanted into the epitaxial layer by ion implantation to sequentially form a p-type base region, an n-type source region, and an n-type contact region.

A carbon layer is then formed on the epitaxial layer, followed by an annealing process to activate the base region, source region, and contact region. The carbon layer prevents silicon (Si) from escaping from the surface of the epitaxial layer during the annealing process. After the annealing process, the carbon layer is removed, and then a gate insulating film, a gate electrode, a source electrode, and a drain electrode are formed in sequence. This allows the manufacture of a SiC semiconductor device.

JP 2007-281005 A

Ion implantation causes crystal defects in the epitaxial layer, and these crystal defects cause warping in the SiC substrate. If the amount of warping in the SiC substrate is large, the transport device may no longer be able to hold the SiC substrate. In this case, the transport device cannot transport the SiC substrate to the processing device for the next process after the ion implantation process. Alternatively, if the amount of warping in the SiC substrate becomes large, the holding device in the processing device may no longer be able to properly hold the SiC substrate. In this case, the processing device cannot process the SiC substrate. In either case, processing of the SiC substrate cannot continue.

Therefore, the present disclosure aims to provide a technology that can reduce the amount of warping in SiC substrates.

A method for manufacturing a silicon carbide semiconductor device according to the present disclosure includes a first step of injecting a first impurity into a surface of a silicon carbide substrate; a second step of performing a heat treatment on the silicon carbide substrate in a thermal diffusion furnace at a temperature exceeding 459°C and not exceeding 1100°C after the first step; a third step of injecting a second impurity into the surface of the silicon carbide substrate after the second step; a fourth step of forming a carbon protective film on the surface of the silicon carbide substrate after the third step; and a fifth step of performing a heat treatment on the silicon carbide substrate at a temperature of 1600°C or more to activate the first impurity and the second impurity after the fourth step .

According to the present disclosure, the amount of warping of the silicon carbide substrate can be reduced. Moreover, since the heat treatment in the second step is performed at a low temperature of 1100 degrees or less, sublimation of silicon carbide hardly occurs. Therefore, the second step can be performed without forming a carbon protective film in advance on the silicon carbide substrate to suppress silicon loss. Therefore, the amount of warping of the silicon carbide substrate can be reduced with fewer steps.

1A to 1C are diagrams each illustrating an example of a configuration of a SiC substrate in an ion implantation process. 1 is a diagram illustrating an example of the configuration of a SiC substrate from which the resist has been removed. FIG. 1 is a diagram illustrating an example of a configuration of a SiC substrate after a heat treatment is performed. FIG. 1 is a flowchart illustrating an example of a method for manufacturing a SiC device. 3A to 3C are diagrams each illustrating an example of a configuration of a SiC substrate in each manufacturing step. 3A to 3C are diagrams each illustrating an example of a configuration of a SiC substrate in each manufacturing step. 3A to 3C are diagrams each illustrating an example of a configuration of a SiC substrate in each manufacturing step. 3A to 3C are diagrams each illustrating an example of a configuration of a SiC substrate in each manufacturing step. 3A to 3C are diagrams each illustrating an example of a configuration of a SiC substrate in each manufacturing step. 3A to 3C are diagrams each illustrating an example of a configuration of a SiC substrate in each manufacturing step. 3A to 3C are diagrams each illustrating an example of a configuration of a SiC substrate in each manufacturing step. 3A to 3C are diagrams each illustrating an example of a configuration of a SiC substrate in each manufacturing step. 1 is a graph showing an example of a temperature profile in a heat treatment process. 1 is a graph showing an example of a temperature profile in a heat treatment process. 1 is a graph showing an example of a temperature profile in a heat treatment process. FIG. 1 is a diagram illustrating an example of the configuration of a thermal diffusion furnace. 1 is a graph showing an example of the amount of warping of a SiC substrate. 13 is a graph showing the relationship between the set temperature and the amount of warpage reduction.

First, the features of the method for manufacturing a silicon carbide semiconductor device according to the present embodiment will be outlined. Hereinafter, the silicon carbide semiconductor device will also be referred to as a SiC device. This manufacturing method includes an ion implantation step in which various impurities are implanted into a silicon carbide substrate. FIG. 1 is a diagram that shows an example of the configuration of a SiC substrate 100 in the ion implantation step. As shown in FIG. 1, a resist 12 is formed in a predetermined pattern on the upper surface of the epitaxial layer 2 of the SiC substrate 100. Using this resist 12 as a mask, impurities such as boron, aluminum, or nitrogen are implanted into the epitaxial layer 2 by selective ion implantation. The impurities are also called dopants. This ion implantation step can form a p-type or n-type impurity region 13 in the epitaxial layer 2 of the SiC substrate 100.

However, this ion implantation process creates crystal defects 14 in the impurity region 13. The crystal defects 14 are also called implantation defects.

After the ion implantation process, the resist 12 is removed. FIG. 2 is a schematic diagram showing an example of the configuration of the SiC substrate 100 from which the resist 12 has been removed. As shown in FIG. 2, the crystal defects 14 in the impurity region 13 cause a tensile force F1 in the in-plane direction in the SiC substrate 100. This causes the SiC substrate 100 to warp. The tensile force F1 increases as the degree of the crystal defects 14 increases. The degree of the crystal defects 14 can be expressed, for example, by the size and number of the crystal defects 14. The degree of the crystal defects 14 varies depending on various factors such as the area of impurity implantation, the type of impurity, the acceleration voltage, and the amount of impurity implantation, and does not depend much on the type of resist 12.

When different types of impurity regions 13 are formed in the SiC substrate 100, multiple ion implantation steps are performed. Since the number of crystal defects 14 in the SiC substrate 100 increases with each ion implantation step, the amount of warping of the SiC substrate 100 increases as a result of multiple ion implantation steps. If the amount of warping of the SiC substrate 100 is large, it may be difficult to hold the SiC substrate 100. For example, the transport device may not be able to properly hold the SiC substrate 100, and the SiC substrate 100 may not be able to be transported to the processing device. Alternatively, the holding device in the processing device may not be able to properly hold the SiC substrate 100. In these cases, the SiC substrate 100 cannot be processed, and a SiC device cannot be manufactured.

In this embodiment, after the ion implantation process, the SiC substrate 100 is subjected to heat treatment at a temperature of 800 degrees or more and 1100 degrees or less (heat treatment process). FIG. 3 is a diagram showing an example of the configuration of the SiC substrate 100 after the heat treatment. This heat treatment can repair some of the crystal defects 14. Therefore, the degree of the crystal defects 14 can be reduced, and the tensile force F1 of the SiC substrate 100 can be reduced. This reduction in the tensile force F1 can reduce the amount of warping of the SiC substrate 100. Therefore, the SiC substrate 100 can be appropriately held by the conveying device or the holding device in the processing device.

Moreover, in this heat treatment process, the heat treatment is performed at a relatively low temperature of 800 degrees or more and 1100 degrees or less. Therefore, during this heat treatment, there is almost no sublimation of SiC from the SiC substrate 100. Therefore, there is no need to form a carbon protective film (described later) in advance to prevent Si from escaping before the heat treatment process, and the amount of warping of the SiC substrate 100 can be reduced with fewer processes.

Below, a more specific example of a method for manufacturing a SiC device is described. FIG. 4 is a flowchart showing an example of a method for manufacturing a SiC device. Here, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used as a specific example of a SiC device. This SiC device is manufactured by performing various processes described below on a SiC substrate 100.

5 to 12 are diagrams each showing an example of a configuration during manufacturing in each step of a method for manufacturing a SiC device. In the example of FIG. 5, a SiC substrate 100 includes a SiC substrate 1 and an epitaxial layer 2. The SiC substrate 1 is an n ⁺ type SiC substrate having a relatively high impurity concentration. An n ^- type SiC epitaxial layer 2 having a relatively low impurity concentration is laminated on one main surface (hereinafter referred to as the upper surface) of the SiC substrate 1 (see FIG. 2).

In step S1 (ion implantation step: corresponding to step 1), a well region 3 is formed in the epitaxial layer 2 (see also FIG. 6). The well region 3 is a p-type impurity region, and is formed in a predetermined pattern in the epitaxial layer 2. As a more specific formation method, first, a first resist (not shown) is formed on the upper surface of the epitaxial layer 2. This first resist covers the area other than the area where the well region 3 is to be formed, while exposing the area where the well region 3 is to be formed. Next, using the first resist as a mask, ions of a p-type impurity such as boron (B) or aluminum (Al) are implanted. Next, the first resist is removed. This allows the p-type well region 3 to be formed.

The formation of the resist, the ion implantation, and the removal of the resist are performed, for example, by different processing devices. In this case, the SiC substrate 100 is transported between the processing devices by a transport device. The same applies to the various processes described below.

While the well region 3 can be formed by ion implantation, crystal defects 14 (see also FIG. 2) are generated in the well region 3. These crystal defects 14 cause a tensile force F1 in the epitaxial layer 2 within its plane. This causes the SiC substrate 100 to warp such that the periphery is lower than the center. Here, we will describe a case where the amount of warping of the SiC substrate 100 due to the ion implantation process of step S1 is relatively small. In other words, the SiC substrate 100 can be held even after the ion implantation process of step S1.

Next, in step S2 (ion implantation step: corresponding to step 1), a source region 4 is formed in each well region 3. The source region 4 is an n-type impurity region and is formed on the upper side of the well region 3. More specifically, a second resist (not shown) is first formed on the upper surface of the epitaxial layer 2. The second resist covers the area other than the area where the source region 4 is to be formed, while exposing the upper surface of the area where the source region 4 is to be formed. Next, using the second resist as a mask, ions of an n-type impurity such as phosphorus (P) or nitrogen (N) are implanted. Next, the second resist is removed. This allows the n-type source region 4 to be formed.

While the source region 4 is formed by ion implantation of impurities, crystal defects 14 (see also FIG. 2) are also generated in the source region 4. Due to these crystal defects 14, an additional tensile force F1 is generated in the epitaxial layer 2. This causes the amount of warping of the SiC substrate 100 to further increase. In other words, the amount of warping of the SiC substrate 100 increases with each ion implantation process.

Next, the contact region 5 is formed, but in the example of FIG. 4, a heat treatment process (corresponding to the second process) in step S3 is performed before that. This heat treatment is a process for reducing the amount of warping of the SiC substrate 100. That is, here, the amount of warping of the SiC substrate 100 may exceed the allowable amount due to the ion implantation of impurities into the contact region 5, so the amount of warping of the SiC substrate 100 is reduced before the contact region 5 is formed.

Specifically, in step S3, the SiC substrate 100 is subjected to heat treatment at a temperature of 800 degrees or more and 1100 degrees or less. Such heat treatment is performed by a predetermined heating device (e.g., a thermal diffusion furnace). By heating the SiC substrate 100, some of the crystal defects 14 in the epitaxial layer 2 are repaired. This makes it possible to reduce the tensile force F1 caused by the crystal defects 14, and to reduce the amount of warping of the SiC substrate 100.

Next, in step S4 (ion implantation process), the contact region 5 is formed. The contact region 5 is a p-type impurity region, and is formed at a position above the well region 3 and adjacent to the source region 4. Specifically, first, a third resist (not shown) is formed on the upper surface of the epitaxial layer 2. The third resist covers the area other than the area where the contact region 5 is to be formed, while exposing the upper surface of the area where the contact region 5 is to be formed. Next, p-type impurity ions are implanted using the third resist as a mask. Note that impurities may be implanted into the contact region 5 so that the impurity concentration in the contact region 5 is higher than the impurity concentration in the well region 3. Next, the third resist is removed. This allows the contact region 5 to be formed.

The ion implantation process of step S4 also generates crystal defects 14 in the contact region 5, increasing the amount of warping of the SiC substrate 100. However, the heat treatment process of step S3 prior to step S4 reduces the amount of warping of the SiC substrate 100. Therefore, the amount of warping of the SiC substrate 100 after step S4 is smaller than when step S3 is not performed. This makes it possible to hold the SiC substrate 100 even after step S4.

Next, in step S5 (carbon protective film formation process: corresponding to the third process), the carbon protective film 6 is formed (see also FIG. 7). The carbon protective film 6 is a film made of carbon, and covers, for example, the entire SiC substrate 100. Note that the carbon protective film 6 may be formed partially on the surface of the SiC substrate 100, for example, by covering only the front surface of the SiC substrate 100. The carbon protective film 6 is formed by any of various methods, such as a method of drying and carbonizing a resist containing carbon, CVD (Chemical Vapor Deposition), and sputtering.

Next, in step S6 (corresponding to the fourth step), activation annealing is performed. More specifically, the SiC substrate 100 is heat-treated in an atmosphere of an inert gas such as argon (Ar) at a temperature of 1600°C or higher, preferably at a temperature of 1600°C or higher and 1800°C or lower.

The temperature in the activation annealing process (step S6) is higher than the temperature in the heat treatment process (step S3). This activation annealing process can activate the well region 3, the source region 4, and the contact region 5. Because the carbon protective film 6 is formed prior to this activation annealing process, it is possible to suppress the loss of Si from the surface of the SiC substrate 100 during the activation annealing process. This makes it possible to suppress the roughness of the surface due to the loss of Si.

In addition, the activation annealing process repairs the crystal defects 14 in the epitaxial layer 2, so the amount of warping of the SiC substrate 100 is reduced again. Because the activation annealing process uses a high temperature, the warping of the SiC substrate 100 is almost completely eliminated.

Next, in step S7, the carbon protective film 6 is removed. For example, the carbon protective film 6 is removed by an ashing process using plasma.

Next, in step S8, a gate insulating film 7 (see also FIG. 8) is formed on the upper surface of the epitaxial layer 2. The gate insulating film 7 is, for example, a silicon dioxide (SiO ₂ ) film, and is formed by, for example, a thermal oxidation method.

Next, in step S9, a gate electrode film 8 is formed on the upper surface of the gate insulating film 7 (see also FIG. 9). The gate electrode film 8 is, for example, a polysilicon film, and is formed on the upper surface of the gate insulating film 7 so as to straddle the two well regions 3. For example, a polysilicon film is formed by CVD on the upper surface of the gate insulating film 7, a fourth resist (not shown) is formed on the upper surface of the polysilicon film, and the polysilicon film is dry-etched or wet-etched using the fourth resist as a mask, thereby forming the gate electrode film 8. The fourth resist is then removed.

Next, in step S10, the interlayer insulating film 9 is formed (see also FIG. 10). The interlayer insulating film 9 is, for example, a silicon dioxide film, and is formed so as to cover the gate electrode film 8. For example, a silicon dioxide film is formed on the upper surface of the gate insulating film 7 by CVD using TEOS (TetraEthOxySilane) gas, and a fifth resist (not shown) is formed on the upper surface of the silicon dioxide film. Then, the silicon dioxide film is dry-etched or wet-etched using the fifth resist as a mask, thereby forming the interlayer insulating film 9. This etching also etches the gate insulating film 7. The etching of the gate insulating film 7 exposes a part of the upper surface of the contact region 5 and the upper surface of the source region 4.

Next, in step S11, a source electrode film 10 is formed on the interlayer insulating film 9 and the exposed source region 4 and contact region 5 (see also FIG. 11). The source electrode film 10 is a conductive film made of, for example, aluminum (Al) or an alloy of aluminum and silicon. For example, the source electrode film 10 is formed by sputtering.

Next, in step S12, a drain electrode film 11 is formed on the lower surface of the SiC substrate 1 (see also FIG. 12). The drain electrode film 11 is a conductive film made of, for example, aluminum, an alloy of aluminum and silicon, titanium (Ti), or nickel (Ni). For example, the drain electrode film 11 is formed by sputtering.

In this manner, a SiC device 200, which is a MOSFET, can be manufactured.

Moreover, according to the manufacturing method of this embodiment, the warping of the SiC substrate 100 caused by the ion implantation process (e.g., steps S1 and S2) is mitigated by the heat treatment process (step S3). Therefore, the SiC substrate 100 can be more appropriately transported between devices after the heat treatment process. Alternatively, in steps after the heat treatment process, the holding device in each processing device can appropriately hold the SiC substrate 100.

Moreover, in the above example, the heat treatment step (step S3) is performed before the step of forming the carbon protective film 6 (step S5). In other words, the heat treatment step is performed in a state where the carbon protective film 6 has not been formed. This is because the heat treatment step is performed at a temperature of 1100 degrees or less, which is lower than the temperature of the activation annealing treatment, and therefore there is almost no sublimation of SiC on the surface of the SiC substrate 100, and the carbon protective film 6 is not required. Conversely, by adopting a temperature in the heat treatment step where there is almost no sublimation of SiC, the heat treatment can be performed even in a state where the carbon protective film 6 has not been formed.

This technique of performing heat treatment without forming the carbon protective film 6 is related to the sublimation of SiC, which is unique to the SiC substrate 100. In other words, in this embodiment, the heat treatment is performed on the SiC substrate 100, which may be sublimated by heating, by adopting a temperature range that does not cause the sublimation. This allows the heat treatment process to be performed without performing the process of forming the carbon protective film before the heat treatment process. In other words, the amount of warping of the SiC substrate 100 can be reduced with fewer processes. This allows productivity to be improved.

An example of the experimental results of the heat treatment process will be described below. Figures 13 to 15 are graphs that outline an example of a temperature profile in the heat treatment process (step S3). Here, the SiC substrate 100 was carried into a thermal diffusion furnace 300 in which the furnace temperature was set to 800 degrees, and the heat treatment process was performed in a nitrogen ( _N2 ) gas atmosphere.

Figure 16 is a diagram showing an example of the configuration of a thermal diffusion furnace 300. The thermal diffusion furnace 300 is, for example, a vertical thermal diffusion furnace, and includes a quartz tube 310 and a heating section 320. A plurality of SiC substrates 100 are carried into the quartz tube 310. The quartz tube 310 accommodates a plurality of SiC substrates 100 arranged in a vertical direction. A heating section 320 is provided around the quartz tube 310 to heat the inside of the quartz tube 310. As a result, the plurality of SiC substrates 100 accommodated in the quartz tube 310 are heated and heat-treated. The heating section 320 may be capable of heating, but may also be a heater with a temperature sensor such as a thermocouple (symbol 320 on the left side of Figure 16), or a temperature sensor and a heater may be separately attached (symbol 320 on the right side of Figure 16). The temperature sensor may monitor the heater temperature (reference number 320 on the left side of FIG. 16), may monitor the furnace temperature (reference number 320 on the right side of FIG. 16), or may monitor both.

16, the quartz tube 310 is connected to a supply pipe 330 for supplying various gases to the inside of the quartz tube 310 and an exhaust pipe 340 for exhausting gas from the inside of the quartz tube 310. In the example of FIG. 16, the thermal diffusion furnace 300 can supply hydrogen gas, oxygen gas, and nitrogen gas to the quartz tube 310 through the supply pipe 330. By supplying an inert gas such as nitrogen to the inside of the quartz tube 310, the oxygen concentration can be reduced, and therefore oxidation of the SiC substrate 100 can be suppressed. In this embodiment, it is not necessary to supply hydrogen gas and oxygen gas into the quartz tube 310. In short, it is sufficient to use a heating device that can heat the SiC substrate 100 to a temperature of 800 degrees or more and 1100 degrees or less.

Hereinafter, the temperature in the heat treatment process is referred to as the set temperature. Figure 13 shows the temperature profile of the temperature inside the furnace when the set temperature is 800 degrees. The temperature inside the furnace here refers to the temperature of the space surrounding the SiC substrate 100, that is, the temperature of the internal space of the quartz tube 310. Figure 14 shows the temperature profile when the set temperature is 950 degrees. Figure 15 shows the temperature profile when the set temperature is 1100 degrees.

In the example of FIG. 13, the thermal diffusion furnace 300 performs heat treatment on the SiC substrate 100 for a period of 40 minutes after the SiC substrate 100 is carried in. The SiC substrate 100 is removed from the thermal diffusion furnace 300 after the heat treatment is completed. In the example of FIG. 14, the thermal diffusion furnace 300 increases the temperature inside the furnace from the standby temperature to 950 degrees at a heating rate of 5 degrees/minute after the SiC substrate 100 is carried in, and performs heat treatment on the SiC substrate 100 at 950 degrees for a period of 30 minutes. After the heat treatment is completed, the thermal diffusion furnace 300 decreases the temperature inside the furnace from 950 degrees to the standby temperature at a heating rate of 2.5 degrees/minute. The SiC substrate 100 is removed after the temperature inside the furnace reaches the standby temperature. In the example of FIG. 15, after the SiC substrate 100 is carried in, the thermal diffusion furnace 300 increases the temperature inside the furnace from the standby temperature to 1100°C at a heating rate of 5°C/min, and performs heat treatment on the SiC substrate 100 at 1100°C for a period of 30 minutes. After the heat treatment is completed, the thermal diffusion furnace 300 decreases the temperature inside the furnace from 1100°C to the standby temperature at a heating rate of 2.5°C/min. The SiC substrate 100 is removed after the temperature inside the furnace reaches the standby temperature. Note that if the heating rate is increased too much, crystal defects (slip) will occur in the SiC substrate 100, so an appropriate value must be used.

The heating time at 800 degrees is longer than the heating times at 950 degrees and 1100 degrees for the following reason. That is, when the SiC substrate 100 is carried into the thermal diffusion furnace 300, the temperature inside the furnace may temporarily drop from the standby temperature. In other words, the heating time at 800 degrees is made longer than 30 minutes so that the heat treatment at 800 degrees can be performed more reliably over a period of 30 minutes.

Figure 17 is a graph showing an example of the amount of warping of the SiC substrate 100. In the example of Figure 17, the amount of warping of the SiC substrate 100 before the ion implantation process (hereinafter referred to as the initial amount of warping), the amount of warping of the SiC substrate 100 after the ion implantation process, and the amount of warping of the SiC substrate 100 after the heat treatment process are shown. Here, an experiment was performed by implanting aluminum as an impurity into the epitaxial layer 2. In addition, in the experiment, three SiC substrates 100 produced from the same ingot were used so that the difference in mechanical properties, such as Young's modulus and Poisson's ratio, between the three SiC substrates 100 was small.

In Figure 17, the amount of warping for the SiC substrate 100 subjected to the heat treatment process at 800 degrees is plotted with black circles, the amount of warping for the SiC substrate 100 subjected to the heat treatment process at 950 degrees is plotted with black triangles, and the amount of warping for the SiC substrate 100 subjected to the heat treatment process at 1100 degrees is plotted with black squares.

In the example of FIG. 17, the initial warpage of all three SiC substrates 100 is approximately -25.0 μm. As can be seen from FIG. 17, the warpage of the SiC substrates 100 increases from the initial warpage due to the ion implantation process. In the example of FIG. 17, the warpage of each SiC substrate 100 after the ion implantation process varies within a range of 130 μm to 150 μm.

It can be seen that by subjecting these SiC substrates 100 to a heat treatment process, the amount of warping of the SiC substrates 100 approaches the initial amount of warping. Here, the amount of warping of the SiC substrates 100 was reduced from 150 μm to 46.7 μm by heat treatment at 800 degrees. In other words, the amount of warping was reduced by about 60% compared to the amount of warping after the ion implantation process. Also, the amount of warping of the SiC substrates 100 was reduced from 133 μm to 6.86 μm by heat treatment at 950 degrees. In other words, the amount of warping was reduced by about 80%. Also, the amount of warping of the SiC substrates 100 was reduced from 140 μm to -13.2 μm by heat treatment at 1100 degrees. In other words, the amount of warping was reduced by about 90%. For ease of explanation, the percentage by which the amount of warping was reduced (for example, the above-mentioned values of approximately 60%, approximately 80%, and approximately 90% by which the amount of warping was reduced) will be referred to as the warping reduction degree below.

As described above, the higher the set temperature in the heat treatment process, the closer the amount of warpage of the SiC substrate 100 is to the initial amount of warpage. This is thought to be because the higher the set temperature, the more crystal defects 14 are repaired. The set temperature in the heat treatment process may be set in consideration of the maximum amount of warpage of the SiC substrate 100 that can be held by the transport device and the holding device of the processing device, but a high set temperature in the heat treatment process is desirable in that the amount of warpage can be reduced. The set temperature is preferably, for example, greater than 850 degrees and less than or equal to 1100 degrees, and more preferably greater than or equal to 950 degrees and less than or equal to 1100 degrees. In particular, if the set temperature is greater than or equal to 950 degrees and less than or equal to 1100 degrees, the amount of warpage of the SiC substrate 100 can be reduced to zero or less, and the amount of warpage can be brought closer to the initial amount of warpage. Therefore, the transport device can easily transport the SiC substrate 100 to the processing device for the next process of the ion implantation process. FIG. 18 is a graph showing the relationship between the set temperature and the amount of warpage reduction. FIG. 18 plots the warpage reduction degree at the three set temperatures of 800°C, 950°C, and 1100°C, and shows an exponential approximation curve (dotted line) for showing the tendency of the warpage reduction effect. The approximation curve is calculated using the above three points and is expressed by the formula: set temperature = 459e ^{0.0093 x warpage reduction degree} . According to this, it can be seen that the warpage reduction effect disappears at a set temperature of 459°C or less. As the reason for the disappearance of the warpage reduction effect, since SiC is composed of four covalent bonds and has a melting point of about 2000°C, it is presumed that the temperature at which crystallization begins is about 500°C, at which one covalent bond begins. And, since defects are restored by crystallization and warpage is reduced, it has been found from the experimental results that a set temperature exceeding at least 459°C is necessary to obtain the effect of reducing the amount of warpage.

In the above example, the heat treatment step S3 is performed after the ion implantation steps S1 and S2. However, the timing of the heat treatment step may be changed as necessary. For example, the heat treatment step S3 may be performed between steps S1 and S2.

Also, the SiC device is not necessarily limited to a MOSFET. This embodiment is applicable to all SiC devices manufactured by a manufacturing method that includes an ion implantation process for implanting impurities into the SiC substrate 100, and specific examples of the present invention include various SiC devices such as SBDs (Schottky Barrier Diodes), IGBTs (Insulated Gate Bipolar Transistors), and PN junction diodes.

The embodiments and variations can be freely combined, and each embodiment and variation can be modified or omitted as appropriate.

100 SiC substrate, 200 SiC device, 6 carbon protective film, S1, S2 first process (step), S3 second process (step), S5 third process (step), S6 fourth process (step).

Claims (3)

A method for manufacturing a silicon carbide semiconductor device, comprising:
A first step of implanting a first impurity into a surface of a silicon carbide substrate;
a second step of performing a heat treatment on the silicon carbide substrate in a thermal diffusion furnace at a temperature exceeding 459° C. and not exceeding 1100° C. after the first step;
a third step of implanting a second impurity into the surface of the silicon carbide substrate after the second step;
A fourth step of forming a carbon protective film on a surface of the silicon carbide substrate after the third step;
a fifth step of, after the fourth step, performing a heat treatment on the silicon carbide substrate at a temperature of 1600° C. or more to activate the first impurity and the second impurity . A method for manufacturing a silicon carbide semiconductor device, comprising:
A first step of implanting a first impurity into a surface of a silicon carbide substrate;
a second step of performing a heat treatment on the silicon carbide substrate at a temperature of 800° C. or more and 1100° C. or less after the first step;
a third step of implanting a second impurity into the surface of the silicon carbide substrate after the second step;
A fourth step of forming a carbon protective film on a surface of the silicon carbide substrate after the third step;
a fifth step of, after the fourth step, performing a heat treatment on the silicon carbide substrate at a temperature of 1600° C. or more to activate the first impurity and the second impurity . The method for manufacturing a silicon carbide semiconductor device according to claim 1 or 2, wherein the second step is performed in a state where a carbon protective film is not formed on the silicon carbide substrate.

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