JP7551582B2 - Inverter device, method for measuring offset voltage of inverter device, and program for measuring offset voltage of inverter device - Google Patents

Description

The present invention relates to technology for converting direct current to alternating current.

Patent document 1 discloses an inverter that converts direct current to alternating current. This inverter has three transistor pairs connected in series between a high-voltage line (Vpp) that supplies a high voltage direct current and a low-voltage line that supplies a low voltage direct current, and outputs three-phase alternating current to a motor by the switching operation of each transistor pair. Specifically, each transistor in the inverter switches between the on and off states in response to a pulse whose duty ratio is controlled by PWM (Pulse Width Modulation).

In an ideal inverter, when all of the transistor pairs of each phase are in the off state and no AC is being output from each AC output terminal, which is the midpoint of each transistor pair, the voltages of the AC output terminals are equal. For example, in an inverter that outputs three-phase AC, the voltage of the U-phase output terminal of the U-phase transistor pair, which are all in the off state, the voltage of the V-phase output terminal of the V-phase transistor pair, which are all in the off state, and the voltage of the W-phase output terminal of the W-phase transistor pair, which are all in the off state, would ideally be equal to each other.

However, in reality, the voltage difference between each AC output terminal when no AC is being output, measured by the voltage sensor, does not become zero due to manufacturing errors in the transistor pairs of each phase, individual differences in the voltage sensors that measure the interphase voltages between UV phases, VW phases, WU phases, etc., and the effects of the operational amplifier and ADC (analog-to-digital converter) provided downstream of the voltage sensor. This voltage difference (interphase voltage between each AC output terminal when no AC is being output) is called the offset voltage. In order to eliminate the effects of this offset voltage, it is possible to measure the offset voltage between each phase in advance using a voltage sensor. Then, when using the interphase voltages measured in real time by the voltage sensor in feedback control of the inverter when AC is being output, the offset voltage measured in advance is subtracted from it.

JP 2010-63303 A

A protective diode element is often provided in parallel with the current path of the transistor of each phase. The protective diode element is provided so that current flows only in the direction from the low voltage line to the high voltage line, but when the transistor is in the off state, leakage current can occur in the direction from the high voltage line to the low voltage line. When this leakage current flows through the protective diode element, a voltage is generated, which can become a source of error when the voltage sensor measures the offset voltage between each phase.

The present invention was made in consideration of these circumstances, and its purpose is to provide an inverter device etc. that can measure offset voltage with high accuracy.

In order to solve the above problems, an inverter device according to one embodiment of the present invention includes an inverter that outputs multiphase AC by the switching operation of multiple transistors connected in parallel between a high-voltage line that supplies a high DC voltage and a low-voltage line that supplies a low DC voltage, multiple pulse supply units that supply pulses for the switching operation to the control terminals of each transistor, a phase-to-phase voltage measurement unit that measures the phase-to-phase voltage between the AC output terminals of each transistor, and a pulse control unit that causes each pulse supply unit to supply a pulse with a duty ratio greater than 0 and less than 1 to the control terminal of each transistor while the phase-to-phase voltage measurement unit is measuring an offset voltage, which is the phase-to-phase voltage when the inverter is not outputting multiphase AC.

In this embodiment, while the phase-to-phase voltage measuring unit is measuring the offset voltage, a pulse with a duty ratio greater than 0 and less than 1 is supplied to the control terminal of each transistor, causing each transistor to be intermittently turned on and current to flow intermittently through the current path, thereby preventing leakage current from flowing through protective diode elements, etc.

Another aspect of the present invention is a method for measuring the offset voltage of an inverter device. This method is a method for measuring the offset voltage of an inverter device that includes an inverter that outputs multiphase AC by switching operations of multiple transistors connected in parallel between a high-voltage line that supplies a high DC voltage and a low-voltage line that supplies a low DC voltage, and multiple pulse supply units that supply pulses for switching operations to the control terminals of each transistor, and includes a step of causing each pulse supply unit to supply a pulse with a duty ratio greater than 0 and less than 1 to the control terminal of each transistor while measuring the offset voltage, which is the phase-to-phase voltage between the AC output terminals of each transistor when the inverter is not outputting multiphase AC.

In addition, any combination of the above components, and any transformation of the present invention into a method, device, system, recording medium, computer program, etc., are also valid aspects of the present invention.

The present invention makes it possible to measure the offset voltage in an inverter device with high accuracy.

1 shows a schematic diagram of an inverter device that supplies polyphase AC to a motor. 3A and 3B show schematic output voltage waveforms at AC output terminals of the U, V and W phases when the inverter is outputting three-phase AC. The equivalent circuit of an induction motor is shown. 1 shows a control device in an inverter device. Schematically shows the pulses that each driver applies to the gates of each transistor pair when measuring the offset current and offset voltage of the inverter. 4 shows an example of the measurement results of the offset voltage.

Below, the embodiments for implementing the present invention will be described in detail with reference to the drawings. In the description and drawings, the same or equivalent components, members, and processes are given the same reference numerals, and duplicated explanations will be omitted. The scale and shape of each part shown in the drawings are set for convenience in order to facilitate explanation, and should not be interpreted as being limiting unless otherwise specified. The embodiments are illustrative and do not limit the scope of the present invention in any way. All features and combinations thereof described in the embodiments are not necessarily essential to the invention.

The inverter device of the present invention can be applied to any device that operates on polyphase AC, but in this embodiment, an example of a drive device or motor device equipped with an electric motor or motor that operates based on polyphase AC supplied by the inverter device is described. FIG. 1 shows a schematic diagram of an inverter device 10 of this embodiment that supplies polyphase AC to a motor 20. The inverter device 10 includes a converter 11 that rectifies three-phase AC of R, S, and T phases supplied from a commercial power source or the like and converts it into DC (pulsating current), a capacitor 12 that smooths the DC converted by the converter 11 to shape the waveform, and an inverter 13 that converts the DC smoothed by the capacitor 12 into AC.

Converter 11 is equipped with diodes 111 to 116 that rectify three-phase (R, S, T) AC supplied from a commercial power source or the like in a fixed direction (from bottom to top in the figure). Diode 111 passes current when the R-phase AC voltage is positive, diode 112 passes current when the R-phase AC voltage is negative, diode 113 passes current when the S-phase AC voltage is positive, diode 114 passes current when the S-phase AC voltage is negative, diode 115 passes current when the T-phase AC voltage is positive, and diode 116 passes current when the T-phase AC voltage is negative. These diodes 111 to 116 connected in a bridge form cause a pulsating current with a fixed direction and fluctuating magnitude to appear between the output terminals of converter 11. Capacitor 12 supplies DC that has been smoothed from the pulsating current obtained by converter 11 to inverter 13.

Hereinafter, the DC voltage input between high voltage input terminal 131 and low voltage input terminal 132 of inverter 13 via converter 11 and capacitor 12 will be represented as V _DC . If the voltage of the high voltage line to which high voltage input terminal 131 is connected is V _dd and the voltage of the low voltage line to which low voltage input terminal 132 is connected is V _ss , then V _DC = V _dd - V _ss .

The inverter 13 outputs three-phase AC by switching operations of three-phase transistor pairs of U-phase, V-phase, and W-phase, which are connected in parallel between a high-voltage line supplying a high _DC voltage _Vdd and a low-voltage line supplying a low DC voltage Vss. In other words, the inverter 13 generates three-phase AC based on a _DC voltage VDC input between a high-voltage input terminal 131 and a low-voltage input terminal 132. Specifically, a U-phase inverter 13U that generates a U-phase AC based on the _DC voltage VDC, a V-phase inverter 13V that generates a V-phase AC based on _{the DC} voltage VDC, and a W-phase inverter 13W that generates a W-phase AC based on _{the DC} voltage VDC are provided in parallel. Since the inverters 13U, 13V, and 13W of each phase have a common configuration, they will be collectively referred to as inverter 13 as appropriate below for explanation.

The inverter 13 includes a high voltage input terminal 131 to which a high DC power supply voltage _Vdd is input, a low voltage input terminal 132 to which a low DC power supply voltage _Vss is input, and an AC output terminal 133 that is provided between a high voltage line to which the high voltage input terminal 131 is connected and a low voltage line to which the low voltage input terminal 132 is connected and outputs an AC voltage that fluctuates between _Vdd and _Vss . A high-voltage side transistor 134H is connected between the high voltage line and the AC output terminal 133, and a low-voltage side transistor 134L is connected between the low voltage line and the AC output terminal 133.

The high-voltage side transistor 134H performs a switching operation in which the conduction state of the current path is switched in response to a pulse supplied from the high-voltage side driver 135H, which serves as a pulse supply unit connected to its control terminal. The low-voltage side transistor 134L performs a switching operation in which the conduction state of the current path is switched in response to a pulse supplied from the low-voltage side driver 135L, which serves as a pulse supply unit connected to its control terminal. Hereinafter, the high-voltage side transistor 134H and the low-voltage side transistor 134L will be collectively referred to as transistor 134 or transistor pair 134, and the high-voltage side driver 135H and the low-voltage side driver 135L will be collectively referred to as driver 135 or driver pair 135. In the following description, "H" meaning "high-voltage side" and "L" meaning "low-voltage side" will be omitted as appropriate, but "H" and "L" will be added to the end of the symbols as necessary in the drawings.

Transistor 134 is an insulated gate bipolar transistor (IGBT) having a gate 31 as a control terminal, a collector 32 as a high-voltage terminal connected to the high-voltage line side, and an emitter 33 as a low-voltage terminal connected to the low-voltage line side. Transistor 134 may be a field effect transistor (FET) having a gate as a control terminal, a drain as a high-voltage terminal, and a source as a low-voltage terminal, or a bipolar transistor having a base as a control terminal, a collector as a high-voltage terminal, and an emitter as a low-voltage terminal.

In the high-voltage side transistor 134H, the gate 31H is connected to the high-voltage side driver 135H, the collector 32H is connected to the high-voltage input terminal 131 or the high-voltage line, and the emitter 33H is connected to the AC output terminal 133 and the collector 32L of the low-voltage side transistor 134L. In the low-voltage side transistor 134L, the gate 31L is connected to the low-voltage side driver 135L, the collector 32L is connected to the AC output terminal 133 and the emitter 33H of the high-voltage side transistor 134H, and the emitter 33L is connected to the low-voltage input terminal 132 or the low-voltage line. In the above configuration, the connection point between the emitter 33H of the high-voltage side transistor 134H and the collector 32L of the low-voltage side transistor 134L forms the AC output terminal 133.

Each transistor 134 further includes a protective diode 34 as a protective diode element formed in parallel with the current path or channel between the collector 32 and the emitter 33, whose conductive state is switched in response to a pulse supplied from each driver 135 to the gate 31. The protective diode 34 may be a discrete element separate from the transistor 134, or may be formed integrally or monolithically with the transistor 134 in the semiconductor manufacturing process for manufacturing the transistor 134. The protective diode 34 is provided so that a current flows only in the direction from the low voltage line side to the high voltage line side, but as described later, when the transistor 134 is in the off state (the channel is in a non-conducting state), leakage current may occur in the direction from the high voltage line side to the low voltage line side.

The driver 135, which is configured as an integrated circuit (IC), constitutes a pulse supplying unit that supplies a pulse for switching operation to the gate 31 of the transistor 134. Specifically, the driver 135 applies a pulse whose duty ratio is controlled by PWM to the gate 31 of the transistor 134. The transistor 134 performs switching operation between an on state and an off state depending on the presence or absence of a pulse. Specifically, while a pulse is applied to the gate 31, the transistor 134 is in an on state, and the channel between the collector 32 and the emitter 33 is in a conductive state. Meanwhile, while a pulse is not applied to the gate 31, the transistor 134 is in an off state, and the channel between the collector 32 and the emitter 33 is in a non-conductive state.

2 shows output voltage waveforms _VU , _VV , _VW of AC output terminals 133U, 133V, 133W of each of the UVW phases when inverter 13 outputs three-phase AC, together with pulses applied to gate 31 of transistor pair 134 by high-voltage side driver 135H and low-voltage side driver 135L of each of the UVW phases. Each of AC output terminals 133U, 133V, 133W outputs AC voltages _VU , VV, _VW of sinusoidal waveforms fluctuating between high voltage _Vdd and low voltage _Vss . In three-phase AC, the phases of AC voltage waveforms _VU , _{VV , VW} of each phase differ by 120 degrees or 2/3π. In the following description, the average value of high voltage _Vdd and low voltage _Vss is set to 0.

During the period when each of AC output terminals 133U, 133V, and 133W outputs a positive voltage, high-voltage side driver 135H applies a pulse whose duty ratio changes stepwise between 0 and 1 to gate 31H of high-voltage side transistor 134H, while low-voltage side driver 135L does not apply a pulse to gate 31L of low-voltage side transistor 134L (duty ratio is 0). When high-voltage side driver 135H applies a pulse whose duty ratio is 1 to gate 31H of high-voltage side transistor 134H, the channel of high-voltage side transistor 134H is almost completely conductive with the high voltage line, so that a high voltage approximately equal to _Vdd appears at AC output terminal 133.

During the period when each of AC output terminals 133U, 133V, 133W outputs a negative voltage, low-voltage side driver 135L applies a pulse whose duty ratio changes stepwise between 0 and 1 to gate 31L of low-voltage side transistor 134L, while high-voltage side driver 135H does not apply a pulse to gate 31H of high-voltage side transistor 134H (duty ratio is 0). When low-voltage side driver 135L applies a pulse whose duty ratio is 1 to gate 31L of low-voltage side transistor 134L, the channel of low-voltage side transistor 134L is almost completely conductive with the low voltage line, so that a low voltage approximately equal to _Vss appears at AC output terminal 133.

As described above, during normal operation when inverter 13 is outputting three-phase AC, in inverters 13U, 13V, and 13W of each of the UVW phases, a pulse with a stepwise changing duty ratio is applied to only one of high-voltage side transistor 134H and low-voltage side transistor 134L, and no pulse is applied to the other of high-voltage side transistor 134H and low-voltage side transistor 134L (duty ratio is 0). The state of the pulse during such normal operation is significantly different from the state of the pulse applied to each transistor 134 when measuring the offset voltage, which will be described later.

The three-phase AC generated by the inverter 13 is supplied to the motor 20, which generates rotational power. The motor 20 is a three-phase brushless motor equipped with three-phase coils 20U, 20V, and 20W of U, V, and W phases. The U-phase coil 20U receives a U-phase current from the AC output terminal 133U of the U-phase inverter 13U, the V-phase coil 20V receives a V-phase current from the AC output terminal 133V of the V-phase inverter 13V, and the W-phase coil 20W receives a W-phase current from the AC output terminal 133W of the W-phase inverter 13W. The inverters 13U, 13V, and 13W of each phase generate a rotating magnetic field by applying three-phase AC of different phases to the coils 20U, 20V, and 20W of each phase based on the rotational position of the rotor detected by the hall elements H1, H2, and H3 of the motor 20. The desired rotational power is obtained from the rotor that rotates due to this rotating magnetic field. The number of phases of the motor 20 is not limited to three, but may be any natural number greater than or equal to two.

The motor 20 can be of any type as long as it operates based on the multi-phase AC supplied by the inverter 13, but in this embodiment, which allows the offset voltage between each phase to be measured with high precision as described below, it is preferable to use an induction motor or an asynchronous motor, which has more motor constants (described below) to be measured compared to a synchronous motor that uses a permanent magnet in the rotor. In an induction motor, not only does the stator on the primary side have multi-phase coils 20U, 20V, and 20W, but the rotor on the secondary side also has multi-phase coils.

Figure 3 shows an equivalent circuit of induction motor 20. The left side of the figure represents primary side stator 21, and the right side of the figure represents secondary side rotor 22. Stator 21 has the aforementioned three-phase coils 20U, 20V, and 20W, and rotor 22 has three-phase coils 20u, 20v, and 20w. The illustrated parameters represent the following, and among these, those whose numerical values are approximately constant are specifically called motor constants.

_V1 : Primary terminal voltage _I1 : Primary current _I1 ': Primary load current _E1 : Primary induced electromotive force _V2 : Secondary terminal voltage _I2 : Secondary current _E2 : Secondary induced electromotive force

_r1 : Primary resistance _x1 : Primary reactance _r2 : Secondary resistance _x2 : Secondary reactance _g0 : Excitation conductance _b0 : Excitation susceptance

I ₀ : Excitation current I _g : Iron loss current I _b : Magnetization current R ₀ : Equivalent output resistance s : Slip

Figure 4 shows the control device in the inverter device 10 of this embodiment together with the inverter 13 and the motor 20. The control device is composed of an outer current control loop 40 that feedback controls the three-phase AC current applied to the motor 20, and an inner voltage control loop 50 that feedback controls the three-phase AC voltage applied to the motor 20. The current control loop 40 includes a current sensor 41, an amplifier 42, an AD converter 43, an offset current holding unit 44, an offset current subtraction unit 45, and a current control unit 46. The voltage control loop 50 includes a UV interphase voltage sensor 51, a VW interphase voltage sensor 52, an amplifier 53, an AD converter 54, an offset voltage holding unit 55, an offset voltage subtraction unit 56, and a voltage control unit 57.

The current sensor 41 in the current control loop 40 measures the AC current of each UVW phase that is applied to the motor 20 by the AC output terminals 133U, 133V, and 133W of the inverters 13U, 13V, and 13W of the UVW phases. The amplifier 42 is composed of an operational amplifier or the like, and amplifies the AC current of each UVW phase measured by the current sensor 41. The AD conversion unit 43 converts the AC current of each UVW phase amplified by the amplifier 42 from an analog value to a digital value. The offset current holding unit 44 stores and holds the offset current, which is the current difference between each UVW phase when the inverter 13 is not outputting three-phase AC, based on the AC current of each UVW phase converted to a digital value by the AD conversion unit 43. A specific method for measuring the offset current will be described later.

During current feedback control when the inverter 13 is outputting three-phase AC, the offset current subtraction unit 45 subtracts a current equivalent to the offset current between the UVW phases held by the offset current holding unit 44 from the real-time AC current of each UVW phase measured by the current sensor 41. The current control unit 46 compares the real-time AC current of each UVW phase from which the effects of the offset current have been removed by the offset current subtraction unit 45 with the current commands for each UVW phase provided from outside the illustrated control device, and generates a voltage command for the voltage control unit 57 based on the respective deviations.

The UV-phase voltage sensor 51 and the VW-phase voltage sensor 52 in the voltage control loop 50 constitute an interphase voltage measurement unit that measures the voltage difference between the UV phases and the VW phases, respectively. Specifically, the UV-phase voltage sensor 51 measures the UV-phase voltage between the AC output terminal 133U of the U-phase inverter 13U and the AC output terminal 133V of the V-phase inverter 13V, and the VW-phase voltage sensor 52 measures the VW-phase voltage between the AC output terminal 133V of the V-phase inverter 13V and the AC output terminal 133W of the W-phase inverter 13W. Note that the WU-phase voltage between the AC output terminal 133W of the W-phase inverter 13W and the AC output terminal 133U of the U-phase inverter 13U can be calculated from the UV-phase voltage measured by the UV-phase voltage sensor 51 and the VW-phase voltage measured by the VW-phase voltage sensor 52, so there is no need to provide a voltage sensor for measuring this.

The amplifier 53 is composed of an operational amplifier and the like, and amplifies the voltage differences between the UV, VW phases measured by the UV phase-to-phase voltage sensor 51 and the VW phase-to-phase voltage sensor 52. The AD converter 54 converts the voltage differences between the UV, VW phases amplified by the amplifier 53 from analog values to digital values. The offset voltage holding unit 55 stores and holds the offset voltage, which is the voltage difference between the UV, VW phases when the inverter 13 is not outputting three-phase AC, based on the voltage differences between the UV, VW phases converted into digital values by the AD converter 54. A specific method for measuring the offset voltage will be described later.

During voltage feedback control when the inverter 13 is outputting three-phase AC, the offset voltage subtraction unit 56 as an offset subtraction unit subtracts the offset voltage between each of the UVW phases held by the offset voltage holding unit 55 from the real-time inter-phase voltage between each of the UVW phases measured by the UV phase-to-phase voltage sensor 51 and the VW phase-to-phase voltage sensor 52. The voltage control unit 57 compares the real-time voltage difference between each of the UVW phases from which the effect of the offset voltage has been removed by the offset voltage subtraction unit 56 with the voltage command for each of the UVW phases provided by the current control unit 46, and generates a pulse generation command for each driver 135 as a pulse supply unit based on the respective deviations.

During normal operation when the inverter 13 outputs three-phase AC, pulses whose duty ratios are controlled by PWM as shown in FIG. 2 are generated by each driver 135 under the control of the voltage control unit 57. In this way, the voltage control unit 57 constitutes a pulse control unit that feedback controls the duty ratios of the pulses that each driver 135 supplies to the gate 31 of each transistor 134 based on the interphase voltage from which the offset voltage has been subtracted by the offset voltage subtraction unit 56.

Next, the measurement of the offset current and offset voltage of the inverter 13 by the control device of Figure 4 will be described. Figure 5 shows a schematic diagram of the pulses that the high-voltage driver 135H and the low-voltage driver 135L of each UVW phase apply to the gate 31 of each transistor pair 134 when measuring the offset current and offset voltage of the inverter 13.

Figure 5 (A) shows a typical conventional method for measuring offset current and offset voltage. In this measurement method, no pulse is applied to the gates 31 of all six transistors 134 in the inverters 13U, 13V, and 13W of the UVW phases. In other words, the duty ratio of the pulses applied to the gates 31 of all transistors 134 is always 0. At this time, all transistors 134 are in the off state and no current flows through the channel between the collector 32 and the emitter 33, so that the AC output terminals 133U, 133V, and 133W of each UVW phase are electrically insulated from the high voltage line and the low voltage line. With the AC output terminals 133U, 133V, and 133W of each UVW phase in this state as the measurement objects, the current sensor 41 measures the offset current between the UVW phases, and the UV phase-to-phase voltage sensor 51 and the VW phase-to-phase voltage sensor 52 measure the offset voltage between the UVW phases. The measured offset current is stored and held in the offset current holding unit 44, and the measured offset voltage is stored and held in the offset voltage holding unit 55.

In such a conventional method for measuring offset current and offset voltage, the measurement accuracy may be deteriorated due to leakage current of the protective diode 34. The protective diode 34 is provided to pass current only in the direction from the low voltage line to the high voltage line, but when all the transistors 134 are in the off state as shown in FIG. 5(A), leakage current may flow through the protective diode 34 in the direction from the high voltage line to the low voltage line. This leakage current is a cause of error when the offset current is measured by the current sensor 41, and the voltage generated when the leakage current flows through the protective diode 34 is a cause of error when the offset voltage is measured by the UV-phase voltage sensor 51 and the VW-phase voltage sensor 52.

Figure 5 (B) shows a method for measuring offset current and offset voltage that can reduce the influence of leakage current flowing through the protective diode 34. In this measurement method, under the control of the voltage control unit 57 as a pulse control unit, a pulse with a duty ratio greater than 0 and less than 1 is applied to the gates 31 of all six transistors 134 in the inverters 13U, 13V, and 13W of the UVW phases. At this time, all the transistors 134 are intermittently turned on, and current flows intermittently through the channel, resulting in a reduction in the leakage current flowing through the protective diode 34. With the influence of leakage current reduced in this way, the current sensor 41 can measure the offset current between the UVW phases with high accuracy, and the UV phase-to-phase voltage sensor 51 and the VW phase-to-phase voltage sensor 52 can measure the offset voltage between the UVW phases with high accuracy.

The duty ratios of the pulses applied to the gates 31 of the six transistors 134 may be different from each other, but are preferably equal to each other as shown in FIG. 5(B). The duty ratios of the pulses applied to the gates 31 of the six transistors 134 may be changed in a range greater than 0 and less than 1 while the offset current and offset voltage are being measured, but are preferably constant as shown in FIG. 5(B). The phases of the pulses applied to the gates 31 of the six transistors 134 may be different from each other, but are preferably equal to each other as shown in FIG. 5(B) (see also FIG. 5(C) described later).

The duty ratio of the pulses applied to the gates 31 of the six transistors 134 can be set anywhere between 0 and 1, but is preferably set to a value of around 0.5 or 50% as shown in FIG. 5(B). This balances the time each transistor 134 is on and the time each transistor 134 is off, stabilizing the operation of the inverter 13 while measuring the offset current and offset voltage. Specifically, the duty ratio of the pulses applied to the gates 31 of the six transistors 134 is preferably set to a value within the range of 40% to 60%, and more preferably within the range of 45% to 55%.

When the duty ratio of the pulses applied to the gates 31 of the six transistors 134 is set to 0, the measurement is the same as the conventional measurement method of FIG. 5(A). When the duty ratio of the pulses applied to the gates 31 of the six transistors 134 is set to 1, all the transistors 134 are fully conductive, and the power supply voltage of the high voltage line and/or low voltage line appears at each of the AC output terminals 133U, 133V, 133W, so that the offset current and offset voltage cannot be measured. Also, when the duty ratio is 1, the high voltage line and the low voltage line may be short-circuited, causing an excessive current to flow through each transistor 134.

This is also the case in FIG. 5B, where the high-voltage transistor 134H and the low-voltage transistor 134L are simultaneously on (however, the short-circuit time is halved due to the 50% duty ratio). In order to prevent such short-circuit problems, the phases of the pulse applied to the gate 31H of the high-voltage transistor 134H and the pulse applied to the gate 31L of the low-voltage transistor 134L may be shifted from each other as shown in FIG. 5C, thereby reducing the time when the high-voltage transistor 134H and the low-voltage transistor 134L are simultaneously on. In the example of FIG. 5C, by shifting the pulses with a duty ratio of 50% on the high-voltage side and the low-voltage side by the amount of the duty ratio, only one of the transistors 134 is on at any time, preventing a short circuit between the high-voltage line and the low-voltage line.

Also, as shown in FIG. 5(D), a first time period in which a pulse is applied to the gate 31H of the high-voltage side transistor 134H and a second time period in which a pulse is applied to the gate 31L of the low-voltage side transistor 134L may be separated. In the first offset current and first offset voltage measured in the first time period, the effect of the leakage current of the protection diode 34H of the high-voltage side transistor 134H is reduced, and in the second offset current and second offset voltage measured in the second time period, the effect of the leakage current of the protection diode 34L of the low-voltage side transistor 134L is reduced.

Therefore, by taking the average of the first offset current and the second offset current, a highly accurate offset current is obtained in which the effects of the leakage currents of the high-voltage side protection diode 34H and the low-voltage side protection diode 34L are reduced in a well-balanced manner. Similarly, by taking the average of the first offset voltage and the second offset voltage, a highly accurate offset voltage is obtained in which the effects of the leakage currents of the high-voltage side protection diode 34H and the low-voltage side protection diode 34L are reduced in a well-balanced manner.

The first offset current and/or the second offset current, even when used alone, are more accurate than the offset current obtained by the conventional measurement method of FIG. 5(A), and therefore these may be held in the offset current holding unit 44 and used for current feedback control. Similarly, the first offset voltage and/or the second offset voltage, even when used alone, are more accurate than the offset voltage obtained by the conventional measurement method of FIG. 5(A), and therefore these may be held in the offset voltage holding unit 55 and used for voltage feedback control.

Fig. 6 shows an example of the measurement result of the offset voltage by the measurement method shown in Fig. 5. The upper curve in Fig. 6 represents the UV-phase offset voltage V _UV measured by the UV-phase voltage sensor 51, and the lower curve in Fig. 6 represents the VW-phase offset voltage V _VW measured by the VW-phase voltage sensor 52. Both offset voltages V _UV and V _VW are digital values converted from analog values by the AD conversion unit 54. In the time period up to time T, the offset voltages V _UV and V _VW were measured by the conventional measurement method in Fig. 5(A), and in the time period after time T, the offset voltages V _UV and V _VW were measured by the measurement method of this embodiment in Fig. 5(B).

As a result, a difference of 0.39 V was confirmed in the UV-phase offset voltage _VUV between the conventional measurement method and the measurement method of this embodiment, and a difference of 0.45 V was confirmed in the VW-phase offset voltage _VVW between the conventional measurement method and the measurement method of this embodiment. As such, it is understood that with the conventional measurement method, the influence of the leakage current of the protection diode 34, etc., resulted in a measurement error of about 0.4 V. According to the measurement method of this embodiment, this measurement error can be eliminated, so that the offset voltage and offset current can be measured with high accuracy.

The measurement error of the offset voltage and/or offset current as described above has a significant adverse effect, particularly when measuring the motor constant (FIG. 3) of the motor 20. For example, when the voltage when a primary current _I1 of 50 A flows through a primary resistance _r1 of 60 mΩ is measured by the UV-interphase voltage sensor 51 and/or the VW-interphase voltage sensor 52, if there is no measurement error due to leakage current of the protective diode 34, the correct measurement value of 3 V is obtained, and the correct resistance value of _r1 = 3 V/50 A = 60 mΩ is obtained. On the other hand, if there is a measurement error of 0.4 V due to leakage current, etc., the measurement value of the voltage when a primary current _I1 of 50 A flows through _the primary resistance r1 is 3.4 V, and the erroneous resistance value of _r1 = 3.4 V/50 A = 68 mΩ is obtained.

Furthermore, measurement errors in the offset voltage and/or offset current also adversely affect the control of the motor 20. For example, if the primary resistance _r1 of the motor 20 is 100 mΩ, a measurement error of 0.4 V results in an error in the primary current _I1 of 0.4 V/100 mΩ = 4 A, which adversely affects the feedback control in the control device. In particular, when the motor 20 is driven with low torque, the primary current _I1 to be passed becomes small, and the effect of the above error becomes relatively large.

Therefore, according to this embodiment, which can reduce measurement errors of the offset voltage and/or offset current, the motor constant of the motor 20 can be measured with high accuracy, and the motor 20 can be controlled with high accuracy.

The present invention has been described above based on the embodiments. The embodiments are merely examples, and it will be understood by those skilled in the art that various modifications are possible in the combination of each component and each processing process, and that such modifications are also within the scope of the present invention.

The functional configuration of each device described in the embodiments can be realized by hardware resources or software resources, or by the cooperation of hardware and software resources. Processors, ROM, RAM, and other LSIs can be used as hardware resources. Programs such as operating systems and applications can be used as software resources.

10 inverter device, 13 inverter, 20 motor, 31 gate, 34 protection diode, 40 current control loop, 41 current sensor, 44 offset current holding unit, 45 offset current subtraction unit, 46 current control unit, 50 voltage control loop, 51 UV interphase voltage sensor, 52 VW interphase voltage sensor, 55 offset voltage holding unit, 56 offset voltage subtraction unit, 57 voltage control unit, 133 AC output terminal, 134 transistor, 135 driver.

Claims (8)

an inverter that outputs multiphase AC by switching operations of a plurality of transistors that are connected in parallel between a high voltage line that supplies a high DC voltage and a low voltage line that supplies a low DC voltage;
a plurality of pulse supply units for supplying pulses for the switching operation to a control terminal of each of the transistors;
a phase-to-phase voltage measuring unit for measuring a phase-to-phase voltage between the AC output terminals of each of the transistors;
a pulse control unit that causes each of the pulse supply units to supply a pulse having a duty ratio greater than 0 and less than 1 to a control terminal of each of the transistors while the phase-to-phase voltage measurement unit is measuring an offset voltage, which is the phase-to-phase voltage when the inverter is not outputting a polyphase AC current;
An inverter device comprising: The inverter device according to claim 1, wherein the duty ratios of the pulses supplied to the control terminals of the transistors by the pulse control unit are equal to each other while the interphase voltage measurement unit is measuring the offset voltage. The inverter device according to claim 1 or 2, wherein the duty ratio of the pulses supplied to the control terminals of the transistors by the pulse control unit is constant while the interphase voltage measurement unit is measuring the offset voltage. An inverter device according to any one of claims 1 to 3, wherein the phases of the pulses supplied to the control terminals of the transistors by the pulse control unit are equal to each other while the interphase voltage measurement unit is measuring the offset voltage. an offset subtraction unit that subtracts the offset voltage from the phase-to-phase voltage measured by the phase-to-phase voltage measurement unit when the inverter is outputting a polyphase AC;
the pulse control unit feedback-controls a duty ratio of a pulse supplied from each of the pulse supply units to a control terminal of each of the transistors, based on the inter-phase voltage from which the offset voltage has been subtracted.
5. The inverter device according to claim 1. The inverter device according to any one of claims 1 to 5, wherein each of the transistors further comprises a protective diode element formed in parallel with a current path whose conduction state is switched in response to a pulse supplied from the pulse supply unit to the control terminal. 1. A method for measuring an offset voltage of an inverter device comprising: an inverter that outputs a multi-phase AC by switching operations of a plurality of transistors connected in parallel between a high voltage line that supplies a high DC voltage and a low voltage line that supplies a low DC voltage; and a plurality of pulse supplying units that supply pulses for the switching operations to control terminals of the transistors,
a step of causing each of the pulse supplying units to supply a pulse having a duty ratio greater than 0 and less than 1 to a control terminal of each of the transistors while measuring an offset voltage, which is a phase-to-phase voltage between the AC output terminals of each of the transistors when the inverter is not outputting a polyphase AC current;
A method for measuring the offset voltage of an inverter device. 1. An offset voltage measurement program for an inverter device including: an inverter that outputs a polyphase AC by switching operations of a plurality of transistors connected in parallel between a high voltage line that supplies a high DC voltage and a low voltage line that supplies a low DC voltage; and a plurality of pulse supply units that supply pulses for the switching operations to control terminals of the transistors,
a step of causing each of the pulse supplying units to supply a pulse having a duty ratio greater than 0 and less than 1 to a control terminal of each of the transistors while measuring an offset voltage, which is a phase-to-phase voltage between the AC output terminals of each of the transistors when the inverter is not outputting a polyphase AC current;
A program for measuring the offset voltage of inverter devices.

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