JP7552404B2 - Modular multilevel cascade converter and control method thereof - Google Patents

Description

The present invention relates to a modular multilevel cascade converter (MMCC) circuit in which one arm of a dual star chopper cell (DSCC) is replaced with a high-voltage switching element.

Figure 1 shows the main circuit configuration of the modular multilevel cascade converter (MMCC) shown in Figure 14 of Patent Document 1. Patent Document 1 and Non-Patent Document 1 list the features of this circuit as having a small number of parts and being able to reduce conduction loss. The loss reduction effect is shown in Patent Document 1 and Non-Patent Document 1.

A DC voltage source is connected to the left side of Figure 1, but in practice a DC link capacitor is connected. In addition, a power conversion device, which acts as another power source, a load, and DC transmission and distribution lines may also be connected.

Figure 3 is a control block diagram of the circuit shown in Figure 15 of Patent Document 1.

JP 2019-47713 A

Kazunobu Oi, Kenta Takasho, Yugo Tadano, “Modular Multilevel Converter Replaced One Module with High Voltage IGBT”, IPEC201 8 Niigata 22B3-1

The problem with the circuit in Figure 1 is that it requires a large DC link capacitor compared to other configurations. This is because harmonic currents flow into the DC link capacitor when the circuit is operated. This harmonic current is evaluated. Consider the case where the AC phase voltages v _SU , v _SV , and v _SW are expressed by equation (1), and the AC phase currents i _invU , i _invV , and i _invW are expressed by equation (2).

Here, V is the effective value of the AC line voltage, _Id is the d-axis current which is involved in the active power of the input/output power of the circuit, _Iq is the q-axis current which is involved in the reactive power, ω is the angular frequency, and t is the time.

In the circuit of Figure 1, when the phase voltage of a certain phase is higher than the other phases, the high-voltage switching element of the upper arm is turned ON. In equation (1), the period during which the upper arm switching element of the U phase is ON is -π/3<ωt<π/3. For the V phase, it is π/3<ωt<π, and for the W phase, it is -π<ωt<-π/3.

In the DC link, AC phase current i _invU , i _invV , or i _invW of the phase in which the upper arm switching element is ON, and circulating current Ic for charging the cell capacitor of the corresponding phase and keeping the cell capacitor voltage constant flow. In Patent Document 1, the circulating current Ic is set to a constant value. The current i _DC flowing in this DC link is expressed by the following equation (3).

In the period π/3<ωt<π, the current flowing from the DC link to the U phase is zero. However, if the variations in the switching elements and cell losses of each phase are ignored, the waveform of the current flowing from the DC link to the V phase is exactly the same as that of the U phase. In the period -π<ωt<-π/3, a current with the same waveform flows from the DC link to the W phase. Therefore, the current i _DC flowing through the DC link has a waveform with periodicity three times the frequency of the fundamental wave. When the current i _DC flowing through the DC link is expanded into a Fourier series, equation (4) is obtained. Note that k is an integer equal to or greater than 1.

Assuming that all harmonic currents except for the _DC component of the current iDC flowing through the DC link flow into the DC link capacitor, the voltage ripple _ΔvDC of the DC link capacitor is expressed by equation (5), where _CDC is the capacitance of the DC link capacitor.

As described above, when the circuit in Figure 1 is operated, a voltage ripple Δv _DC occurs in the DC link capacitor voltage. The maximum frequency component of the voltage ripple Δv _DC is three times that of the fundamental wave, and in particular, when attempting to output the q-axis current I _q , i.e., reactive power, the voltage ripple Δv _DC becomes three times larger than when effective power is output. If the voltage ripple Δv _DC is large, there is a risk that the operation of the circuit will become unstable. For stable operation, the DC link capacitor voltage V _DC must satisfy equation (6).

If equation (6) is not satisfied and the DC link capacitor voltage _VDC becomes smaller than the AC line voltage peak, an uncontrollable current will flow from the AC side to the DC link. One method to prevent this is to reduce the voltage ripple _ΔvDC , but increasing the capacitance CDC of the _DC link capacitor increases the cost and volume of the device.

If the impedance of other devices and loads connected to the DC link is small, the harmonic current also flows through the other devices and loads, so that the capacitance C _DC of the DC link capacitor can be made small.

However, this method is not suitable for long-distance DC transmission, thyristor converters, and other devices or loads with high impedance. Another method is to increase the DC link capacitor voltage V _DC , but this requires increasing the withstand voltage of the DC link capacitor, which also increases the cost and volume.

Furthermore, when the _DC link capacitor voltage VDC is increased, the cell capacitor voltage must also be increased proportionally, resulting in problems such as increased cost and volume of the cell capacitor, increased switching loss, and increased voltage ripple due to cell switching. Furthermore, Non-Patent Document 1 shows that the circulating current Ic can be made zero when the relationship between the DC link capacitor voltage _VDC and the AC side line voltage effective value V satisfies the following equation (7):

When the DC link capacitor voltage _VDC is increased, the condition of the formula (7) is deviated from, and the circulating current Ic increases, which leads to an increase in the conduction loss.

For the reasons stated above, the challenge in modular multilevel cascade converters is to reduce the voltage ripple of the DC link capacitor and to use a small-capacity capacitor.

The present invention has been devised in view of the above-mentioned problems of the related art, and one aspect of the present invention is a modular multilevel cascade converter having two or more phases, comprising a switching element connected to the positive terminal of a DC link capacitor, a parallel capacitor connected in parallel to the switching element, a cell module having two or more chopper cells or bridge cells cascaded to the negative terminal of the DC link capacitor, and a buffer reactor connected between the switching element and the cell module, the modular multilevel cascade converter generating a voltage command value using a two-arm modulation method, turning on the switching element when the voltage command value of the phase to be controlled is 1 and the voltage detection value of the switching element of the phase to be controlled is 0 or less, and turning off the switching element when the voltage command value of the phase to be controlled is less than 1, and a gate controller for the switching element that outputs a commutation command value, which is usually obtained by adding a fixed value α to the output current detection value, as a cell module output current command value, and controlling the switching element of the phase to be controlled to be a constant current. When the switching element is ON, the device is characterized by having a current command value calculation unit that superimposes harmonics on the charge/discharge current command value obtained by multiplying the deviation between the cell capacitor voltage average value and the cell capacitor voltage command value by a gain Gc for a certain time Δtc and outputs the result as the cell module output current command value; a current control unit that outputs a feedforward term obtained by multiplying the difference between the cell module output current command value a certain time ago Δt and the current cell module output current command value by a gain Gl, a value obtained by multiplying the deviation between the cell module output current command value and the cell module output current detection value by a gain G, and a value obtained by adding 1, as the cell module voltage command value; and a gate signal generation unit that selects the voltage command value when the gate command of the switching element of the controlled phase is OFF and the voltage command value of the controlled phase is less than 1, and selects the cell module voltage command value otherwise, multiplies the selected value by a correction coefficient, and compares the value to which the cell capacitor voltage control command value is added with the carrier triangular wave to generate a cell gate command.

In another aspect, a modular multilevel cascade converter having two or more phases includes a switching element connected to the negative terminal of a DC link capacitor, a parallel capacitor connected in parallel to the switching element, a cell module having two or more chopper cells or bridge cells cascaded to the positive terminal of the DC link capacitor, and a buffer reactor connected between the switching element and the cell module, and generates a voltage command value using a two-arm modulation method, and when the voltage command value of the phase to be controlled is -1 and the voltage detection value of the switching element of the phase to be controlled is greater than 0, turns ON the switching element, and when the voltage command value of the phase to be controlled is greater than -1, turns OFF the switching element, and outputs a commutation command value, which is usually obtained by adding a fixed value α to the output current detection value, as a cell module output current command value, and when the switching element of the phase to be controlled is turned ON, In this case, the device is characterized by having a current command value calculation unit that superimposes harmonics on a charge/discharge current command value obtained by multiplying the deviation between the cell capacitor voltage average value and the cell capacitor voltage command value by a gain -Gc for a certain time Δtc, and outputs the result as the cell module output current command value; a feedforward term that multiplies the difference between the cell module output current command value a certain time ago Δt and the current cell module output current command value by a gain Gl, a value obtained by multiplying the deviation between the cell module output current command value and the cell module output current detection value by a gain G, and outputting a value obtained by adding -1 as the cell module voltage command value; and a gate signal generation unit that selects the voltage command value when the gate command for the switching element of the phase to be controlled is OFF and the voltage command value of the phase to be controlled is greater than -1, and selects the cell module voltage command value otherwise, multiplies the selected value by a correction coefficient, and compares the value to which the cell capacitor voltage control command value has been added with a carrier triangular wave to generate a cell gate command.

In one aspect, the harmonics are determined based on the harmonics in equation (4).

i _DC : current flowing through the DC link k: an integer equal to or greater than 1 Id: d-axis current Iq: q-axis current ω: angular frequency t: time Ic: circulating current.

In one aspect, the method is characterized in that only the third harmonic of equation (11) among the harmonics calculated by equation (4) is superimposed on the charge/discharge current command value.

i _DC1 : Third harmonic of the current flowing through the DC link.

In another aspect, the third harmonic of equation (11) and the sixth harmonic of equation (12) among the harmonics calculated by equation (4) are superimposed on the charge/discharge current command value.

i _DC1 : The third harmonic of the current flowing through the DC link. i _DC2 : The sixth harmonic of the current flowing through the DC link.

In another aspect, the method is characterized in that, among the harmonics calculated by formula (4), higher harmonics are superimposed on the Iq term than on the Id term.

In one embodiment, the harmonics are smaller than those calculated by equation (4), (11), or (12).

The present invention makes it possible to reduce the voltage ripple of the DC link capacitor in a modular multilevel cascade converter and use a small-capacity capacitor.

FIG. 4 is a main circuit configuration diagram of the modular multilevel cascade converter according to the first to third embodiments. FIG. 1 is a circuit diagram showing a chopper cell and a bridge cell. FIG. 1 is a diagram showing a control circuit of Patent Document 1. FIG. 4 is a diagram showing an example of a gate controller of a switching element. FIG. 4 is a diagram showing a carrier triangular wave start signal. FIG. 13 is a diagram showing another example of a gate controller of a switching element. 4 is a time chart showing an output waveform of a gate controller of a switching element. FIG. 2 is a diagram showing a harmonic superimposing unit according to the first embodiment. FIG. 11 is a diagram showing a harmonic superimposing unit according to a second embodiment. FIG. 13 is a diagram showing a harmonic superimposing section according to a third embodiment. FIG. 11 is a diagram showing a simulation waveform when the first embodiment is applied.

Below, embodiments 1 to 3 of the modular multilevel cascade converter of the present invention will be described in detail with reference to Figures 1 to 11.

[Embodiment 1]
The main circuit configuration of a modular multilevel cascade converter (MMCC) is explained based on Fig. 1. The feature of this MMCC circuit is that the lower arm is composed of a cell module 1 in which chopper cells C are cascaded as shown in Fig. 2, and by increasing the number of connected cells, it is possible to handle higher voltages.

In addition, in this embodiment 1, as shown in FIG. 1, high-voltage switching elements Su, Sv, and Sw are connected to the upper arm. Furthermore, parallel capacitors Cu, Cv, and Cw are connected in parallel to the switching elements Su, Sv, and Sw, respectively. That is, the modular multilevel cascade converter in this embodiment 1 includes DC link capacitors DCP and DCN, switching elements Su, Sv, and Sw, parallel capacitors Cu, Cv, and Cw, a cell module 1, buffer reactors Lu, Lv, and Lw, and a filter reactor FL.

The DC link capacitors DCP and DCN may be integrated into one.

The switching elements Su, Sv, and Sw are semiconductor elements with self-extinguishing capabilities and diodes connected in inverse parallel, and are of high voltage resistance, such as 4500V. The switching elements Su, Sv, and Sw are placed between the positive terminal of the DC link capacitor DCP and the AC output terminals u, v, and w. Depending on the magnitude of the AC voltage to be output, multiple switching elements Su, Sv, and Sw may be connected in series. The parallel capacitors Cu, Cv, and Cw are connected in parallel to the switching elements Su, Sv, and Sw.

The cell module 1 is connected to the negative terminal of the DC link capacitor DCN and is made up of multiple chopper cells C connected in cascade. This cell module 1 forms the lower arm of each AC output phase.

Buffer reactors Lu, Lv, and Lw are connected between the cell module 1 and the AC output terminals u, v, and w, respectively. A filter reactor FL is generally connected to the AC output terminals u, v, and w to suppress the outflow of switching noise.

Note that Vpu, Vpv, and Vpw are voltage detection values of the switching elements Su, Sv, and Sw, _VDC is a DC voltage detection value (DC link capacitor voltage), Iz is a cell module output current detection value, Iinv is an output current detection value, and Vs is a system voltage detection value, which are each detected and used in the control circuit in FIG. 3 described later.

As shown in FIG. 2(a), one end of the first switching device S1 is connected to one connection terminal of the chopper cell C. The second switching device S2 is connected between the one connection terminal and the other connection terminal. The cell capacitor Ca is connected between the other end of the first switching device S1 and the other connection terminal.

In addition, instead of the chopper cell C, a bridge cell B may be connected. As shown in FIG. 2(b), one end of the third switching device S3 is connected to one connection terminal of the bridge cell B. One end of the fourth switching device S4 is connected to a common connection point between the third switching device S3 and one connection terminal. A fifth switching device S5 is connected between the other end of the third switching device S3 and the other connection terminal. A sixth switching device S6 is connected between the other end of the fourth switching device S4 and the other connection terminal. A cell capacitor Cb is connected between the common connection point of the third and fifth switching devices S3 and S5 and the common connection point of the fourth and sixth switching devices S4 and S6.

In these circuits, it is assumed that two-arm modulation is applied to the voltage command value as shown in FIG. 2 of Patent Document 1. In period 1, the switching element Su of the upper arm is turned ON to bypass the output current to the upper arm, thereby reducing the conduction loss of the switching element, and during this period, a circulating current is passed through the cell module 1 of the lower arm to charge and discharge the cell capacitor Ca, thereby easily realizing cell capacitor voltage control.

Taking FIG. 1 as an example, the following operations must be performed in period 1.
In order to prevent a short circuit due to residual charge in the parallel capacitor Cu connected in parallel to the switching element Su of the upper arm when the switching element Su is turned ON, an excessive current is output from the lower arm to discharge the charge in the parallel capacitor Cu, and then the anti-parallel diode in the upper arm is made conductive to divert the current.
After checking the commutation, the upper arm switching element Su is turned ON.
A circulating current flows from the DC link capacitors DCP, DCN to the switching element Su of the upper arm and the cell module 1 of the lower arm, charging the cell capacitor Ca.
In order to stop the circulating current and establish zero voltage switching when the switching element Su in the upper arm is turned OFF, an excess current is output from the cell module 1 in the lower arm to discharge the charge in the parallel capacitor Cu, and then the anti-parallel diode in the upper arm is made conductive to commutate the current. This operation makes the voltage detection value Vpu of the switching element Su in the upper arm equal to or less than zero.
After confirming the commutation, the upper arm switching element Su is turned OFF.

To achieve this, very high-speed current control is required.

Figure 3 shows a block diagram of the control unit of embodiment 7 of Patent Document 1. This control unit is intended to be applied to the circuit of Figure 1. Figure 3 is divided into several control blocks. First, the block that calculates the voltage command value V* (hereinafter referred to as voltage command value calculation unit 2) will be explained.

The voltage command value V* can be calculated using feedforward or voltage control, but here we will use current control as an example. The voltage command value calculation unit 2 is configured as follows:

The phase-locked loop PLL inputs the system voltage detection value Vs and outputs the phase θ. Here, it is assumed that a modular multilevel cascade converter (MMCC) is used as the system-connected device, but if it is used as a motor drive device, the phase θ is detected by a rotary encoder provided on the motor.

The dq converter 3 inputs the output current detection value Iinv and phase θ of each converter phase, and converts the output current detection value Iinv into a d-axis current detection value Id and a q-axis current detection value Iq in a rotating coordinate system synchronized with the system frequency. A filter to remove switching ripple and noise may be applied to the output current detection value Iinv (omitted in Figure 3).

The subtractors 4d and 4q calculate the deviation between the d-axis current command value Id* and the q-axis current command value Iq* and the d-axis current detection value Id and the q-axis current detection value Iq. The PI amplifiers 5d and 5q amplify the deviation calculated by the subtractors 4d and 4q and output a voltage command value on the rotating coordinate system synchronized with the system frequency (or the frequency of the motor voltage).

The dq inverse converter 6 performs dq inverse conversion on the voltage command values on the rotating coordinate system, which are the outputs of the PI amplifiers 5d and 5q, based on the phase θ, and outputs the voltage command values on the fixed coordinate system.

The two-arm modulator 7 performs two-arm modulation on the voltage command value on the fixed coordinates, which is the output of the dq inverse transformer 6. The maximum value selection unit 7a selects and outputs the largest value among the three-phase voltage command values on the fixed coordinates that have been inversely transformed by dq. The adder 8a adds a fixed value of 1 to the three-phase voltage command values that have been inversely transformed by dq, and subtracts the output of the maximum value selection unit 7a from the addition result.

The calculation and two-arm modulation process of the voltage command value V* is performed as described above. If the output of the dq inverse converter 6 is a three-phase balanced sine wave, the voltage command value V* after two-arm modulation will have the waveform shown in Figure 2 of Patent Document 1.

The voltage command value V* and the voltage detection values (collector-emitter voltages of the switching elements) Vpu, Vpv, and Vpw of the upper arm switching elements Su, Sv, and Sw are input to the gate controller 9a of the switching elements. Figure 4 shows the configuration of the gate controller 9a of the switching elements in the U phase. The gate controller 9a of the U phase switching elements is configured as follows.

Comparator 10a determines whether the U-phase voltage command value Vu* is equal to 1, and if it is 1, outputs 1, otherwise outputs 0. The output of comparator 10a is input to the lower input terminal of switch SW3, which will be described later, and to OR element 11.

Comparator 12a determines whether the voltage detection value Vpu of the switching element Su in the U phase exceeds 0. The output of comparator 12a becomes the control signal for switch SW3. If Vpu>0, switch SW3 outputs the input signal of the upper input terminal, and if Vpu≦0, switch SW3 outputs the input signal of the lower input terminal. The output signal of switch SW3 becomes the U-phase upper arm gate command as it is.

Buffer 13 receives the output signal of switch SW3, delays it by one calculation time, and outputs it. The output signal of buffer 13 is input to the upper input terminal of switch SW3.

OR element 11 receives the output signal of switch SW3 and the output of comparator 10a, and outputs 1 if at least one of them is 1, and outputs 0 if both are 0. NOT element 14 inverts the output of OR element 11 and outputs it. The output of NOT element 14 becomes the control signal for switch SW2, which will be described later.

The rising edge detector 15 outputs 1 for one calculation time when the output signal of the switch SW3 changes from 0 to 1. If the output of the rising edge detector 15 is 1, the hold device 16 continues to output 1 for a fixed time Δtc. The fixed time Δtc is the time for controlling the charging and discharging of the cell capacitor. A time slightly shorter than period 1 in FIG. 2 of Patent Document 1 is specified. The NOT element 17 inverts the output signal of the hold device 16 and outputs it. The output signal of the NOT element 17 becomes the control signal for the switch SW1, which will be described later.

The switching element gate controller 9a outputs an ON command as the U-phase upper arm gate command when the voltage command value V* of the phase to be controlled is 1, and outputs an OFF command when V*<1. However, ON/OFF switching is performed only when the voltage detection values Vpu, Vpv, Vpw of the upper arm switching elements Su, Sv, Sw of the phase to be controlled are equal to or less than zero.

The control signal of switch SW1 is normally 1. When the gate command for the switching element of the upper arm of the phase to be controlled is turned ON, it becomes 0 for a certain period of time Δtc, and then returns to 1.

The control signal of switch SW2 outputs 0 when either the switching element of the upper arm of the phase to be controlled is ON or the voltage command value V* is equal to 1.

The current command value calculation unit 18a that calculates the lower arm cell module output current command value I* during period 2 will be described. The current command value calculation unit 18a is configured as follows.

The adder 19 adds a fixed value α to the output current detection value Iinv of each converter phase to calculate the commutation command value. The fixed value α is set to approximately 1% to 10% of the rated value of the output current detection value Iinv (current value that allows 100% continuous operation). The commutation command value, which is the output of the adder 19, is input to the upper input terminal of the switch SW1.

Multiplier 20 multiplies the _DC voltage detection value VDC by a fixed value 1+β, divides it by the number of cells n, and outputs a command value for the cell capacitor voltage average value (cell capacitor voltage command value) _VDC (1+β)/n. The fixed value 1+β is set to β=approximately 5% (≈0.05). As a result, the cell capacitor voltage command value _VDC (1+β)/n is obtained by dividing the DC voltage detection value _VDC by the number of cells per phase n and then increasing it by 5%.

The hold device 21 holds the cell capacitor voltage average value Vcavg of each phase at a predetermined timing and continues to output the value at that time. The cell capacitor voltage average value Vcavg is calculated by the following formula (8) where the number of cells per phase is n and the kth cell capacitor voltage detection value is Vck. The predetermined timing is immediately after the gate command for the switching element of the upper arm of the phase to be controlled is turned ON.

The subtractor 22 subtracts the output of the multiplier 20 from the output of the hold unit 21 to obtain the deviation. The multiplier 23a multiplies the deviation by the gain Gc and outputs a charge/discharge current command value for charging the cell capacitor. In Patent Document 1, the charge/discharge current command value, which is the output of the multiplier 23a, is input to the lower input terminal of the switch SW1, but in this embodiment 1, the charge/discharge command value is superimposed with harmonics, which will be described later, and input to the lower input terminal of the switch SW1.

Switch SW1 receives a control signal from the gate controller 9a of the switching element, and if it is 1, it outputs a signal from the upper input terminal, and if it is 0, it outputs a signal from the lower input terminal. That is, switch SW1 normally outputs the commutation command value Iinv+α, and when the gate command for the switching element of the upper arm of the phase to be controlled is turned ON, it switches to outputting the charge/discharge current command value for a certain period of time Δtc, and then returns to outputting the commutation command value Iinv+α.

The following describes the current control unit 24a, which inputs the cell module output current command value I* and determines the cell module voltage command value Vn* for period 2. The current control unit 24a is configured as follows.

The differentiator 25 inputs the cell module output current command value I* and outputs the difference between the current cell module output current command value I* and the cell module output current command value I* a time Δt ago. The differentiator 25 inputs a start-up signal, which will be described later, and operates only at the valley of the maximum value of the carrier triangular wave for n cells. The time Δt is 1/n period of the carrier triangular wave.

The amplifier 26 multiplies the output of the differentiator 25 by a gain Gl and outputs the feedforward term of the voltage command value. The subtractor 27 calculates the deviation between the cell module output current detection value Iz and the cell module output current command value I* for the corresponding phases.

The amplifier 28 multiplies the deviation by the gain G. The adder 29a adds the feedforward term of the voltage command value and a fixed value 1 to the output of the amplifier 28. The output of the adder 29a becomes the cell module voltage command value Vn* of the cell module 1.

We will now explain the gate signal generation unit 30, which generates a gate signal from the voltage command value V* and the cell module voltage command value Vn*.

The voltage command value V* is input to the upper input terminal of switch SW2, and the cell module voltage command value Vn* is input to the lower input terminal of switch SW2. Switch SW2 inputs a control signal from the switching element gate controller 9a, and if it is 1, it outputs the signal from the upper input terminal, and if it is 0, it outputs the signal from the lower input terminal. In other words, if the gate command for the switching element of the phase to be controlled is ON or V*==1, it switches to the output of the lower input terminal, and otherwise it switches to the output of the upper input terminal.

The output of switch SW2 is input to multiplier 31, where the amplitude is corrected. The multiplier of multiplier 31 is calculated as follows:

Divider 32 divides the converter DC voltage detection value _VDC by the number of cells n and calculates the reciprocal of the result, i.e., outputs n/ _VDC . Multiplier 33 calculates the product of the output of divider 32 and the cell capacitor voltage average value Vcavg. The output of multiplier 33 becomes the multiplier of multiplier 31, i.e., the amplitude correction coefficient.

The adder 34 adds each cell capacitor voltage control command value to the amplitude-corrected voltage command value. The cell capacitor voltage control command value is calculated as follows:

The subtractor 35 calculates the deviation between each of the cell capacitor voltage detection values Vc for 3n cells and the average cell capacitor voltage Vcavg for the same phase as the cell to be controlled. The cell capacitor voltage detection value Vc is a signal for n cells per phase, for three phases, for a total of 3n cells.

Amplifier 36 multiplies the deviation by gain Gci. Sign extractor 37 outputs the sign extraction result of the cell module output current detection value Iz. That is, sign extractor 37 outputs 1 if Iz>0, -1 if Iz<0, and 0 if Iz=0. Multiplier 38 calculates the product of the output of amplifier 36 and the sign detection result of the cell module output current detection value Iz of the same phase as the cell to be controlled. The output of multiplier 38 becomes the cell capacitor voltage control command value.

The PWM modulator 39 compares the voltage command value obtained by adding each cell capacitor voltage control command value with the carrier triangular wave to generate a gate signal and add dead time. The carrier triangular wave used for PWM modulation is generated, for example, as follows (in the case of PS [phase shift]):

The delay unit 41 delays the phase of the carrier triangular wave output from the carrier triangular wave generator 40 by 2(k-1)π/n for the kth cell. The delay unit 41 generates n carrier triangular waves with a phase shift of 2π/n each, and in the PWM modulator 39, the kth triangular wave is compared with the voltage command values for the U, V, and W phases and sent to the kth cell of the corresponding phase.

From the carrier triangular wave, an activation signal for the differentiator 25 inside the current control unit 24a is generated as follows. The maximum value selection unit 42a selects and outputs the maximum value from the n carrier triangular waves output from the delay unit 41. The differentiator 43 differentiates the output of the maximum value selection unit 42.

Comparator 44a outputs 1 if the output of differentiator 43 is positive, and 0 if it is below zero. Rising edge detector 45 outputs 1 for one calculation time immediately after the output of comparator 44a changes from 0 to 1. The output of rising edge detector 45 is output to differentiator 25 inside current control unit 24a, and differentiator 25 operates only at the valley of the maximum value of the carrier triangular wave. The carrier triangular wave and the generated start-up signal of differentiator 25 are shown in Figure 5. Point A in Figure 5 corresponds to the valley of the maximum value of the carrier triangular wave.

The voltage command value calculation unit 2 has the same configuration as the current control block of a general inverter. It calculates the output voltage command value based on the deviation between the output current detection value Iinv and the d-axis current command value Id* and q-axis current command value Iq* amplified by a PI amplifier, and then applies two-arm modulation by the two-arm modulator 7.

The gate controller 9a of the switching element will now be described. In the circuit of FIG. 1, the conduction loss of the switching element is reduced by bypassing the converter output current to the upper arm during period 1 shown in FIG. 2 of Patent Document 1.

In period 1, that is, when the voltage command value V* of the corresponding phase is 1, the upper arm switching element is turned ON. However, depending on the sign of the output current, the parallel capacitor may be short-circuited when the switching element is turned ON. This capacitor short-circuit phenomenon is undesirable because it may cause overcurrent destruction of the switching element. Therefore, by detecting the voltage detection values Vpu, Vpv, and Vpw of the switching elements and turning ON the upper arm switching element when the voltage command value V* = 1 and the voltage detection values Vpu, Vpv, and Vpw of the switching elements are zero or below zero taking into account the diode voltage drop, the upper arm switching element is kept on waiting until the lower arm cell module 1 discharges the charge of the parallel capacitor, and the capacitor short-circuit can be avoided.

When the upper arm switching element is turned OFF, the charge remaining in the parallel capacitor due to the element voltage (several volts) while the upper arm switching element is ON is discharged to achieve zero voltage switching when the upper arm switching element is turned OFF. Therefore, after detecting that V*<1 and the voltage of the upper arm switching element is below zero, an OFF command for the upper arm switching element is output.

However, when turning OFF, the current bypasses the parallel capacitor, so the switching loss does not increase significantly. Therefore, the OFF command may be output only when V*<1 without detecting the voltage detection values Vpu, Vpv, and Vpw of the switching elements Su, Sv, and Sw.

The gate controller 9a of the switching element at this time is shown in Figure 6. The comparator 10a judges whether the voltage command value Vu* of the U phase is equal to 1 or not, and outputs 1 if it is 1, and outputs 0 otherwise. The output of the comparator 10a is input to the AND element 65 and the OR element 11, which will be described later.

Comparator 12a determines whether the voltage detection value Vpu of the upper arm switching element Su in the U phase exceeds 0. The output of comparator 12a is inverted and input to OR element 64. AND element 65 inputs the output of comparator 10a and the output of OR element 64, outputs 1 when both are 1, and outputs 0 otherwise. The output of AND element 65 becomes the U phase upper arm gate command.

The OR element 11 receives the output of the comparator 10a and the output of the AND element 65, and outputs 1 when at least one of them is 1, and outputs 0 when both are 0. The output of the OR element 11 is inverted by the NOT element 14 and output as a control signal for the switch SW2.

The buffer 66 receives the output signal of the AND element 65, delays it by one calculation time, and outputs it. The output of the buffer 66 is input to the OR element 64.

The rising edge detector 15 outputs 1 for one calculation time when the output signal of the AND element 65 changes from 0 to 1. If the output of the rising edge detector 15 is 1, the hold element 16 continues to output 1 for a fixed time Δtc. The fixed time Δtc is the time for controlling the charging and discharging of the cell capacitor. It is set to a time slightly shorter than period 1 in FIG. 2 of Patent Document 1. The NOT element 17 inputs the output signal of the hold element 16. The output signal of the NOT element 17 becomes the control signal for the switch SW1 described later.

The current command value calculation unit 18a will now be described. The cell module output current command value I* consists of two types of values: a commutation command value for commutating the upper arm passing current to the lower arm cell module 1, and a charge/discharge current command value for controlling the average cell capacitor voltage of the phase to be controlled to a constant value. The former is input to the upper input terminal of switch SW1, and the latter is input to the lower input terminal, and is switched by switch SW1 depending on the situation and output as the cell module output current command value I*.

The commutation command value is set to a value that exceeds the current output current detection value Iinv by α. α is set to a value of approximately +1% to +10% of the rated value of the output current detection value Iinv (the current value that allows 100% continuous operation). If the cell module output current detection value Iz can be controlled to a current according to the command value, the upper arm passing current becomes Iinv-Iz=-α, and current flows from bottom to top. If there is a charge in the parallel capacitors Cu, Cv, and Cw, the upper arm passing current flows preferentially through the parallel capacitors Cu, Cv, and Cw rather than the anti-parallel diodes of the switching elements, and the parallel capacitors Cu, Cv, and Cw are discharged. When the parallel capacitors Cu, Cv, and Cw have completed discharging, the upper arm passing current passes through the anti-parallel diodes.

At this time, excessive current does not flow to the AC output side. This is because the output current detection value Iinv is controlled by the other two phases. Also, the inductances of the buffer reactors Lu, Lv, Lw and filter reactor FL have the relationship Lu, Lv, Lw > Lz. In this formula, Lu, Lv, Lw refer to the inductance values of the buffer reactors Lu, Lv, Lw. Lz refers to the inductance value per phase of the filter reactor FL.

The filter reactor FL is set to a large inductance value to remove AC output current ripple, and the buffer reactors Lu, Lv, and Lw are set to a small inductance value to quickly charge and discharge the commutation and parallel capacitors Cu, Cv, and Cw.

Because the filter reactor FL prevents abrupt changes in the output current detection value Iinv, most of the increase in the cell module output current detection value Iz passes through the upper arm. When commutation is performed, the distortion of the output current detection value Iinv hardly increases. Increasing α here has the advantage of ensuring that commutation can be performed, but also has the disadvantage of increasing losses. Therefore, the condition for α is kept at around 10%.

The charge/discharge current command value is calculated by first calculating the deviation between the cell capacitor voltage average value Vcavg and the cell capacitor voltage command value _VDC (1+β)/n. The cell capacitor voltage command value _VDC (1+β)/n is the value obtained by dividing the DC voltage detection value _VDC by the number of cells per phase n. However, in order to perform commutation, the sum of the cell capacitor voltages must be in excess of the DC voltage detection value _VDC . Therefore, the excess is set as β here, and the coefficient 1+β is multiplied by _VDC /n. The obtained deviation is multiplied by the gain Gc to obtain the charge/discharge current command value. This gain Gc is expressed by the following equation (9) based on the relational equation between the capacitor voltage and current. In addition, C in equation (9) is the capacitance of the cell capacitor Ca.

The fixed time Δtc is the charge/discharge time of the cell capacitor. The fixed time Δtc is set to about 70-80% of period 1 (1/3 cycle of the fundamental wave), and the remainder is allocated to commutation control.

Switch SW1 switches between the commutation command value and the charge/discharge current command value. Normally, it is input to the upper input terminal and outputs the commutation command value. When the upper arm switching elements Su, Sv, and Sw are turned ON, switch SW1 switches to the output of the lower input terminal for a certain time Δtc and outputs the charge/discharge current command value, controlling the cell capacitor voltage. After the certain time Δtc, switch SW1 returns to the output of the upper input terminal and outputs the commutation command value again, discharging the charge (about several volts) of the parallel capacitors Cu, Cv, and Cw of the upper arm, and zero voltage switching can be achieved when the upper arm switching elements Su, Sv, and Sw are then turned OFF.

The current control unit 24a will now be described. The current control unit 24a is composed of a general current control block and a feedforward term. The general current control block amplifies the deviation between the cell module output current detection value Iz and the cell module output current command value I* using an amplifier 28, and adds the feedforward term described below to this result to determine the cell module voltage command value Vn*.

The feedforward term will now be explained. As mentioned above, this circuit configuration requires high-speed current control. Therefore, the voltage required for the desired current output is calculated from the voltage-current relationship of the buffer reactors Lu, Lv, and Lw, and this is output using feedforward to achieve high speed. The relational equation for the buffer reactors Lu, Lv, and Lw, the gain Gl calculated from this, and the required cell module output voltage Vn can be calculated using the following equation (10).

Here, _vLz represents the applied voltage to the buffer reactors Lu, Lv, and Lw, and Lz represents the inductance of the buffer reactors Lu, Lv, and Lw. The cell module output voltage Vn obtained by the above formula (10) is defined as the cell module voltage command value Vn*.

The current control unit 24a first uses a buffer to hold the cell module output current command value I* from a certain time Δt ago, and calculates ΔI* by calculating the difference between this and the cell module output current command value I*. Here, the certain time Δt is the smallest unit of voltage pulse that the lower arm cell module 1 can output, i.e., 1/n period of the carrier triangular wave.

The ΔI* calculated by the amplifier 26 is multiplied by the gain Gl and output as the voltage command value of the feedforward term. With the above feedforward compensation, even if the cell module output current command value I* changes, the cell module output current detection value Iz can be made approximately equal to the cell module output current command value I* after 1/n period of the carrier triangular wave.

Since the purpose of the amplifier 28 is to correct the discrepancy between the cell module output current detection value Iz and the cell module output current command value I*, the gain G may be small. On the other hand, the gain Gl becomes large due to the minute value (fixed time) Δt of the denominator. Therefore, care must be taken to avoid noise being superimposed on the cell module output current command value I*.

However, although the cell module output current command value I* is a value based on the output current detection value Iinv, the filter reactor FL through which the output current detection value Iinv passes is assumed to have a large inductance value, so the noise superimposed on the output current detection value Iinv is small.

Furthermore, the cell module output current command value I* is also determined from the DC voltage detection value V _DC and the cell capacitor voltage average value Vcavg, but since these are capacitor voltages, noise is less likely to be superimposed.

The adder 29a adds 1 as a feedforward term. This corresponds to the _DC voltage detection value VDC in equation (10) when multiplied by an amplitude correction coefficient described later. The purpose of adding 1 is to make the cell module output current detection value Iz zero by outputting a voltage equal to the _DC voltage detection value VDC from the lower arm cell module 1 when the cell module output current command value I* is constant at zero.

The voltage command value V* calculated by the voltage command value calculation unit 2 and the cell module voltage command value Vn* calculated by the current control unit 24a are appropriately selected by switch SW2 and then multiplied by a correction coefficient nVcavg/ _VDC . This is to align the voltage output by the lower arm cell module 1 when V*=1 with the voltage output when the upper arm switching elements Su, Sv, Sw are ON, i.e., the _DC voltage detection value VDC. As a result, even if the upper arm switching elements Su, Sv, Sw are switched ON and OFF when V*=1, the converter output voltage does not change, and distortion of the output voltage can be suppressed.

After being multiplied by the correction coefficient nVcavg/ _VDC , the cell capacitor voltage control command value is added to the voltage command value. The deviation between the individual cell capacitor voltage detection value Vc and the cell capacitor voltage average value Vcavg is amplified by an amplifier 36.

Next, the output of the amplifier 36 is corrected based on the sign of the cell module output current detection value Iz. For example, consider a case where the capacitor voltage detection value Vc of the cell to be controlled is excessive, the output of the amplifier 36 is positive, and the cell module output current detection value Iz is also positive.

By increasing the target cell output voltage, the effective power output by the cell increases, allowing the cell capacitor Ca to be discharged. To increase the cell output voltage, a positive cell capacitor voltage control command value is added.

Consider the case where the cell module output current detection value Iz is negative under the same conditions. In this case, if the target cell output voltage is reduced, the effective power input to the cell will decrease, and the cell capacitor charge amount can be reduced. To reduce the cell output voltage, a negative cell capacitor voltage control command value should be added.

Finally, the voltage command value is compared with the carrier triangular wave to generate gate commands for each cell. Here, the carrier triangular wave is a phase-shift type, with the phase shifted by 2(k-1)π/n.

For example, if each phase has four cells in series, then n = 4 and k = 1, 2, 3, 4. The first cell has no phase shift. The second cell has a phase shift of 2π/4. The third cell has a phase shift of 4π/4. The fourth cell has a phase shift of 6π/4.

At this time, as shown in FIG. 5, the largest value is extracted from the carrier triangle wave of each cell, and a start-up signal is generated at the valley and input to the differentiator 25 inside the current control unit 24a. This enables the differentiator 25 to calculate and output the difference between the cell module output current command value I* a certain time ago Δt and the current cell module output current command value I*.

The reason for generating the start signal at the valley is explained below. If there is a delay in the start signal generated at the peak, when the voltage command value V* decreases from a state of approximately 1, three or more intersections between the voltage command value V* and the carrier triangle wave will occur in succession, temporarily increasing the number of switching times and resulting in increased losses.

In addition, if the pulse width becomes extremely short, the switching element will operate in the active region, which can cause the element to heat up and shorten its lifespan or even break down. To prevent this, the start signal is generated at the valley.

Figure 5 shows the waveforms of the carrier triangle wave and the start signal. The output signal of the maximum value selection unit 42a is shown in bold. The start signal becomes 1 at the valley of the output signal of the maximum value selection unit 42a, i.e., at point A.

Figure 7 shows the upper arm gate command output from the switching element gate controller 9a and the control signals for switches SW1 and SW2. Based on this, a series of operations will be explained using the U phase as an example. When the voltage command value of the phase to be controlled is Vu*<1, the control signal for switch SW2 is 1, and switch SW2 outputs the signal of the upper input terminal. The upper arm gate command is 0, and the upper arm switching element Su is OFF. General current control is performed, and the lower arm cell module 1 outputs a voltage equivalent to the voltage command value Vu* obtained by current control.

When Vu* = 1, first the control signal of switch SW2 becomes 0 and switch SW2 switches to the output of the lower input terminal. The control signal of switch SW1 remains at 1, and switch SW1 outputs the signal of the upper input terminal.

Therefore, the lower arm cell module 1 performs commutation control by outputting a current slightly larger than the current output current detection value Iinv, and discharges the parallel capacitor Cu of the upper arm switching element Su. When the voltage detection value Vpu of the upper arm switching element Su falls below zero and it is detected that the parallel capacitor Cu has been completely discharged, the upper arm gate command is switched from 0 to 1, and the upper arm switching element Su is turned ON.

The control signal of switch SW1 becomes 0, switch SW1 switches to the output of the lower input terminal, and the lower arm cell module 1 charges and discharges the cell capacitor Ca, controlling the cell capacitor voltage average value Vcavg to the cell capacitor voltage command value V _DC (1+β)/n.

At this time, the converter output current is controlled by the cell modules 1 of the lower arms of the other two phases, so the converter can output current according to the command value even while the U-phase cell capacitor Ca is being charged or discharged.

When switch SW1 switches to the up position after a certain time Δtc has elapsed, the lower arm cell module 1 performs commutation control again. The output current from the lower arm cell module 1 becomes the output current detection value Iinv, and the excess current passes through the anti-parallel diode of the upper arm switching element Su.

In FIG. 7, the upper arm current passes through the switching element Su, and the voltage detection value Vpu of the upper arm switching element Su is slightly positive due to the voltage drop, but the upper arm current reverses and passes through the anti-parallel diode, becoming slightly negative due to the voltage drop, and the upper arm switching element Su is ready to be turned OFF.

When V*<1 and Vpu≦0 are satisfied, the upper arm gate command is switched from 1 to 0 to turn off the upper arm switching element Su, and switch SW2 switches to the output of the upper input terminal, returning to normal current control.

The above control block is intended to be applied to FIG. 1. However, it can also be applied to the main circuits in FIG. 20 and FIG. 21 of Patent Document 1.

As shown in FIG. 28 of Patent Document 1, the present invention can also be applied to a configuration in which switching elements Su, Sv, and Sw are connected to the negative terminals of DC link capacitors DCP and DCN, and a cell module 1 is connected to the positive terminals of DC link capacitors DCP and DCN. In this case, modifications can be made as shown in FIG. 28 of embodiment 13 of Patent Document 1.

The difference in the two-arm modulator 7 is that instead of the maximum value selection unit 7a, a minimum value selection unit is provided, which selects and outputs the smallest value among the three-phase voltage command values that have been inversely dq transformed. The adder 8a adds a fixed value of -1 to the deviation between the three-phase voltage command values and the output of the minimum value selection unit.

The gate controller 9a of the upper arm switching element becomes the gate controller of the lower arm switching element. In the gate controller of the lower arm switching element, comparator 10a determines whether the voltage command value Vu* of the U phase is -1 or not. Comparator 12a determines whether the voltage detector Vnu of the switching element Su in the U phase is greater than 0 or not. The output of switch SW3 becomes the lower arm gate command of the U phase and is output to the lower arm switching element Su.

In the current command value calculation unit 18a, the multiplier 23a inverts the sign of the gain and multiplies it by the gain -Gc.

The cell module output current detection value Iz is positive when it flows from the DC side to the AC side. In a configuration in which switching elements are connected to the positive terminals of the DC link capacitors DCP and DCN, a flow from top to bottom is positive, and in a configuration in which switching elements are connected to the negative terminals of the DC link capacitors DCP and DCN, a flow from bottom to top is positive. This change is made to accommodate this difference in detection direction.

For the current control unit 24a, the adder 29a adds the output of the amplifier 26, the output of the amplifier 28, and -1. The output of the adder 29a becomes the upper arm cell module voltage command value Vp*.

The block that generates the activation signal for the differentiator 25 of the current control unit 24a from the carrier triangular wave has a minimum value selection unit instead of a maximum value selection unit 42a, and selects and outputs the smallest value from the n carrier triangular waves output from the delay unit 41. The comparator 44a outputs 1 if the output of the differentiator 43 is negative, and 0 if it is zero or greater. As a result, the differentiator 25 only operates at the peak of the carrier triangular wave's minimum value.

In this embodiment 1, changes are made to the areas indicated by the dotted circles in FIG. 3. The changes are to superimpose a harmonic (sine wave) on the output signal of multiplier 23a, which multiplies the gain Gc, and input the result to the lower terminal of switch SW1.

Figure 8 shows the harmonic superposition block of this embodiment 1. As shown in Figure 8, the harmonic superposition block is composed of the following:

Multiplier 70 multiplies the d-axis current command value Id* by a gain of 3√3/8π ≒ 0.2067. Multiplier 71 further multiplies the output of multiplier 70 by a gain of G3. Multiplier 72 multiplies the q-axis current command value Iq* by a gain of 9√3/8π ≒ 0.6202. Multiplier 73 further multiplies the output of multiplier 72 by a gain of G3.

Multiplier 74 multiplies the phase θ obtained from the phase locked loop PLL in FIG. 3 by a gain of 3. Adder 75 adds a phase offset φ3 to 3θ, which is the output of multiplier 74, and outputs 3θ+φ3. Tables (cos, sin) 76 and 77 input 3θ+φ3 and output the corresponding cosine wave and sine wave.

Multiplier 78 multiplies the output of table 76, cos(3θ+φ3), by the output of multiplier 71, 3√3/8π×G3×Id*. Multiplier 79 multiplies the output of table 77, sin(3θ+φ3), by the output of multiplier 73, 9√3/8π×G3×Iq*. Adder 80 adds the outputs of multipliers 78 and 79 and inverts the sign.

The adder 81 adds the output signal of the adder 80 to the output signal of the multiplier 23a, which multiplies the gain Gc in FIG. 3. The added signal is the lower input signal of the switch SW1. The upper input signal of the switch SW1 is Iinv+α. The output signal of the switch SW1 is the output current command value I* of the lower arm cell module.

In the first embodiment, an appropriate harmonic current is output from the lower arm cell module 1, and the voltage ripple Δv _DC of the DC link capacitor is suppressed by canceling out the harmonics superimposed on the current i _DC flowing through the DC link.

The operation of the first embodiment will be described. When k=1 (third harmonic) is extracted from the current i _DC flowing through the DC link, the following equation (11) is obtained: _{i DC1} is the third harmonic of the current flowing through the DC link.

Therefore, the cell module 1 of the lower arm of the phase in which the upper arm is ON outputs a current in the opposite direction.

Now let us consider Figure 8. Harmonics are obtained by multiplying the cosine wave or sine wave with a gain as shown in equation (11). The gain in Figure 8 is 1/√2 smaller than that in equation (11), but this is chosen appropriately depending on whether the control system uses the effective value or the amplitude as the reference.

In Figure 8, a further gain G3 is applied because it is assumed that deviations will occur due to the finite current control gain of the downstream lower arm cell module 1. By setting gain G3 to a value slightly greater than 1, it is possible to obtain a current for the lower arm cell module 1 that is close to the expected value even when the gain is low and the deviation is large.

φ3 (fixed value) is added to phase 3θ because it is assumed that there will be a delay in the current control of the lower arm cell module 1. By passing a current command value with a phase slightly more advanced than expected to the current control block, it is possible to obtain a current in the lower arm cell module 1 with a phase close to that expected.

The output signal of the multiplier 23a, which multiplies the gain Gc, is the current command value of the cell module 1 of the lower arm for three phases. The harmonic current obtained is added to the current command value of the cell module 1 of the lower arm for all three phases.

Normally, harmonics should only be added to the lower arm cell module current command value for the phase in which the upper arm is ON, but the switch SW1 in the subsequent stage superimposes harmonics onto the cell module output current command value I* only for the phase in which the upper arm is ON. The cell module output current command value I* for the phase in which the upper arm is OFF becomes equal to Iinv + α, so harmonics are not superimposed.

This allows the parallel capacitors Cu, Cv, and Cw connected in parallel to the switching elements Su, Sv, and Sw to be discharged when the upper arm switching element is turned ON, even when harmonics are superimposed. This prevents increased loss and noise caused by short circuits in the parallel capacitors Cu, Cv, and Cw, and also prevents situations in which the parallel capacitors cannot be detected as being discharged completely and the upper arm cannot be turned ON, resulting in unstable operation.

As described above, according to the first embodiment, the ripple in the DC link capacitor voltage that occurs in the circuit of FIG. 1 can be reduced.

In addition, to keep the voltage ripple at the same level, the application of this embodiment 1 requires an increase in the capacity of the low-voltage, low-cost cell capacitor, but the capacity of the high-voltage, high-cost DC link capacitor can be reduced by more than that, resulting in lower costs.

In addition, if the total harmonic distortion (THD) of the output current is kept at the same level, the DC link capacitor capacity can be reduced and there is no need to increase the cell capacitor capacity, which further reduces costs and allows for miniaturization.

In addition, if the capacitance of the DC link capacitor and cell capacitor is not changed, the rated voltage (the voltage value at which 100% continuous operation is possible) of the DC link capacitor and cell capacitor can be lowered, making it possible to reduce the size and cost of the capacitors. Furthermore, other effects can be obtained, such as reduced switching loss, lower noise, smaller reactor size, and reduced conduction loss due to reduced circulating current.

In addition, the circuit of FIG. 1 can be applied even when the impedance of other devices connected to the DC link is high. In addition, since only the third harmonic, which has the greatest effect on the voltage ripple, is cancelled, the voltage ripple can be effectively reduced with the lowest computational load. [Embodiment 2]
Fig. 9 shows a harmonic superposition block according to the present embodiment 2. Fig. 9 adds the following to Fig. 8.

Multiplier 82 multiplies the d-axis current command value Id* by a gain of 3√3/35π≒0.0473. Multiplier 83 further multiplies the output of multiplier 82 by a gain of G6. Multiplier 84 multiplies the q-axis current command value Iq* by a gain of 18√3/35π≒0.2835. Multiplier 85 further multiplies the output of multiplier 84 by a gain of G6.

Multiplier 86 multiplies θ by a gain of 6. Adder 87 adds a phase offset φ6 to the output 6θ of multiplier 86 to output 6θ+6φ. Tables (cos, sin) 88 and 89 input the output 6θ+φ6 of adder 87 and output the corresponding cosine wave and sine wave.

Multiplier 90 multiplies the output of table 88, cos(6θ+φ6), by the output of multiplier 83, 3√3/35π×G6×Id*. Multiplier 91 multiplies the output of table 89, sin(6θ+φ6), by the output of multiplier 85, 18√3/35π×G6×Iq*.

Adders 92 and 93 add -3√3/8π×G3×Id*×cos(3θ+φ3) and -9√3/8π×G3×Iq*×sin(3θ+φ3) calculated in the first embodiment to the outputs of multipliers 90 and 91. Adder 81 adds the resulting signal to the output signal of multiplier 23a, which is multiplied by gain Gc.

The operation of the second embodiment will be described. In the second embodiment, among the harmonics superimposed on the current i _DC flowing through the DC link, not only the third harmonic but also the sixth harmonic is cancelled. When k=2 (sixth harmonic) is extracted from the current i _DC flowing through the DC link, the following formula (12) is obtained. _{i DC2} is the sixth harmonic of the current flowing through the DC link.

Therefore, a current in the opposite direction is added to the output current command value of the lower arm cell module 1, and currents of -i _DC1 and -i _DC2 are output from the lower arm cell module 1. The calculation method is the same as in embodiment 1, and the gain and phase offset are differentiated taking into account that the delay and deviation of the current control differ from the third harmonic.

In the second embodiment, −i _DC1 and −i _DC2 (third and sixth harmonics) are output from the cell module 1 of the lower arm, but it is also possible to output higher harmonics of k=3 or more.

However, from equation (5), the Id term (active power) of the voltage ripple Δv _DC is approximately inversely proportional to the cube of k, and the Iq term (reactive power) is also approximately inversely proportional to the square of k. Therefore, the higher the order of the harmonics superimposed on the voltage ripple Δv _DC , the smaller it becomes, so sufficient effect can be obtained even if high-order harmonics are ignored, and ignoring them also reduces the calculation load.

Since the voltage ripple due to reactive power (q-axis current) is larger than the voltage ripple due to active power (d-axis current), it is possible to superimpose higher-order harmonics on the Iq term than on the Id term among the harmonics calculated by equation (4). For example, in this embodiment 2, it is possible to simplify the harmonic current output only on the d-axis current by limiting it to third order, or to output ninth-order harmonic current only on the q-axis current.

As described above, according to the second embodiment, the same effect as that of the first embodiment is achieved. In addition, by canceling the sixth harmonic, the voltage ripple can be reduced more than that of the first embodiment.

[Embodiment 3]
Fig. 10 shows a harmonic superposition block according to the third embodiment. Fig. 10 adds the following to Fig. 8.

The deadbands 94 and 95 output zero if the absolute values of the d-axis current command value Id* and the q-axis current command value Iq* are within a set threshold value, and if they exceed the threshold value, output values that bring the d-axis current command value Id* and the q-axis current command value Iq* closer to zero by the threshold value.

The multipliers 70 and 72 multiply the outputs of the dead bands 94 and 95 by gains 3√3/8π and 9√3/8π. The rest of the process is the same as in the first embodiment. In addition, the third embodiment may be applied to the second embodiment.

In the first and second embodiments, harmonics are superimposed on the output current of the lower arm cell module to reduce the voltage ripple Δv _DC of the DC link capacitor. However, because the output current of the lower arm cell module that passes through many cells is increased, there is a problem that the effect of reducing conduction loss, which is an advantage of this circuit, is lost.

Therefore, the harmonics that are actually superimposed are made smaller than those calculated by equation (4), (11), or (12). In this third embodiment, a dead band is set for the d-axis current command value Id* and the q-axis current command value Iq* that are input to the harmonic superimposition block. This makes it possible to realize an operation in which harmonics are not superimposed on the lower arm cell module output current at light loads where the voltage ripple is originally small, and at heavy loads, only a small amount of harmonics are superimposed to suppress the voltage ripple ΔvDC to a level that does not interfere with operation.

An example of a method for setting the dead band will be described. When the voltage ripple Δv _DC is expanded for the largest k=1 (third harmonic), the following equation (13) is obtained.

As a result, since the third-order voltage ripple caused by reactive power (q-axis current) is three times larger than that of active power (d-axis current), it is possible to reduce the dead band of the q-axis current by one-third.

As described above, according to the third embodiment, the same effects as those of the first and second embodiments are achieved. Furthermore, by allowing a certain degree of voltage ripple, the harmonic current superimposed on the lower arm cell module output current can be reduced, and an increase in loss can be suppressed.

The simulation waveform is shown in Figure 11. However, no power source or load is connected to the DC link, and a reactive power (q-axis current) of 1 pu is output from the device as a condition for increasing the voltage ripple Δv _DC . At time 1 second, the first embodiment is enabled. The ripple of the DC link capacitor voltage V _DC at the bottom is reduced to almost half by enabling the first embodiment. On the other hand, the increase in the ripple of the cell capacitor voltage is small, about 1.4 times.

To keep the capacitor voltage ripple at the same level, the capacity of the low-voltage, low-cost cell capacitor needs to be increased by 1.4 times, but the high-cost DC link capacitor to which high voltage is applied can be halved, resulting in cost benefits.

When checking the THD of the output current Iinv, it was reduced from 3.9% to 3.4% after applying embodiment 1. This shows that the DC link capacitor has a greater impact on THD. If the THD is to be kept at the same level, there is no need to increase the cell capacitor capacitance, and the DC link capacitor capacitance can be reduced, allowing for further cost and volume reductions.

The reason why the THD of the output current detection value Iinv is high before the application of the first embodiment is that the minimum value of _{the DC} link capacitor VDC is smaller than the line voltage peak 6.6×√2≈9334 V, which does not satisfy formula (6).

However, after application of embodiment 1, formula (6) can be satisfied even if the rated value of _{the DC} link capacitor voltage VDC (the voltage value at which 100% continuous operation is possible) is reduced from 10 kV to 9.8 kV. By reducing the rated value of the _DC link capacitor voltage VDC (the voltage value at which 100% continuous operation is possible), the rated value of the cell capacitor voltage (the voltage value at which 100% continuous operation is possible) can also be reduced, and switching loss can be reduced. The voltage ripple output from the cells due to switching can also be reduced, and other effects can be obtained, such as lower noise and the miniaturization of the filter reactor FL and buffer reactors Lu, Lv, and Lw.

Furthermore, under these conditions, the condition for making the circulating current Ic zero, according to equation (7), is V _DC = 9774 V. By lowering the rated value of the DC link capacitor voltage V _DC (the voltage value allowing 100% continuous operation), it is possible to approach this value, reduce the circulating current Ic, and reduce the conduction loss.

Although the present invention has been described in detail above only with respect to the specific examples, it will be clear to those skilled in the art that various modifications and alterations are possible within the scope of the technical concept of the present invention, and it goes without saying that such modifications and alterations fall within the scope of the claims.

1...Cell module DCP, DCN...DC link capacitor C...Chopper cell B...Bridge cell Su, Sv, Sw...Switching element u, v, w...AC output terminal FL...Filter reactor Lu, Lv, Lw...Buffer reactor Cu, CV, Cw...Parallel capacitor

Claims (9)

A switching element connected to a positive terminal of the DC link capacitor;
a parallel capacitor connected in parallel to the switching element;
A cell module having two or more chopper cells or bridge cells cascade-connected to the negative terminal of the DC link capacitor;
a buffer reactor connected between the switching element and the cell module;
A modular multilevel cascade converter having two or more phases, comprising:
A voltage command value is generated using a two-arm modulation method;
a gate controller for a switching element that turns on the switching element when the voltage command value of the phase to be controlled is 1 and a voltage detection value of the switching element of the phase to be controlled is equal to or less than 0, and turns off the switching element when the voltage command value of the phase to be controlled is less than 1;
a current command value calculation unit which normally outputs a commutation command value obtained by adding a fixed value α to the output current detection value as a cell module output current command value, and when the switching element of the phase to be controlled is turned ON, outputs as the cell module output current command value a charge/discharge current command value obtained by multiplying the deviation between the cell capacitor voltage average value and the cell capacitor voltage command value by a gain Gc for a certain time Δtc, with harmonics superimposed thereon so as to suppress voltage ripple of the DC link capacitor ;
a current control unit that outputs as a cell module voltage command value a feedforward term obtained by multiplying a difference between the cell module output current command value a certain time ago Δt and the current cell module output current command value by a gain Gl, a value obtained by multiplying a deviation between the cell module output current command value and the cell module output current detection value by a gain G, and a sum of these values;
a gate signal generating unit that selects the voltage command value when a gate command for the switching element of the phase to be controlled is OFF and the voltage command value for the phase to be controlled is less than 1, and otherwise selects the cell module voltage command value, multiplies the selected value by a correction coefficient, and compares the value to which the cell capacitor voltage control command value is added with a carrier triangular wave to generate a cell gate command;
A modular multilevel cascade converter comprising: A switching element connected to a negative terminal of the DC link capacitor;
a parallel capacitor connected in parallel to the switching element;
A cell module having two or more chopper cells or bridge cells cascade-connected to the positive terminal of the DC link capacitor;
a buffer reactor connected between the switching element and the cell module;
A modular multilevel cascade converter having two or more phases, comprising:
A voltage command value is generated using a two-arm modulation method;
a gate controller for a switching element that turns on the switching element when the voltage command value of the phase to be controlled is −1 and a voltage detection value of the switching element of the phase to be controlled is greater than 0, and turns off the switching element when the voltage command value of the phase to be controlled is greater than −1;
a current command value calculation unit which normally outputs a commutation command value obtained by adding a fixed value α to the output current detection value as a cell module output current command value, and when the switching element of the phase to be controlled is turned ON, outputs as the cell module output current command value a charge/discharge current command value obtained by multiplying the deviation between the cell capacitor voltage average value and the cell capacitor voltage command value by a gain -Gc for a certain time Δtc, with harmonics superimposed thereon so as to suppress voltage ripple of the DC link capacitor ;
a current control unit that outputs as a cell module voltage command value a feedforward term obtained by multiplying a difference between the cell module output current command value a certain time ago Δt and the current cell module output current command value by a gain Gl, a value obtained by multiplying a deviation between the cell module output current command value and the cell module output current detection value by a gain G, and a value obtained by adding -1;
a gate signal generating unit that selects the voltage command value when a gate command for the switching element of the phase to be controlled is OFF and the voltage command value for the phase to be controlled is greater than −1, and otherwise selects the cell module voltage command value, multiplies the selected value by a correction coefficient, and compares the value to which the cell capacitor voltage control command value is added with a carrier triangular wave to generate a cell gate command;
A modular multilevel cascade converter comprising: 3. The modular multilevel cascade converter according to claim 1, wherein the harmonics are determined based on the harmonics in equation (4).

i _DC : current flowing through the DC link k: integer equal to or greater than 1 Id: d-axis current Iq: q-axis current ω: angular frequency t: time Ic: circulating current 4. The modular multilevel cascade converter according to claim 3, wherein only a third harmonic of the equation (11) among the harmonics obtained by the equation (4) is superimposed on the charge/discharge current command value.

i _DC1 : Third harmonic of the current flowing through the DC link 4. The modular multilevel cascade converter according to claim 3, wherein a third harmonic of an equation (11) and a sixth harmonic of an equation (12) among the harmonics obtained by the equation (4) are superimposed on the charge/discharge current command value.

i _DC1 : 3rd harmonic of the current flowing through the DC link i _DC2 : 6th harmonic of the current flowing through the DC link The modular multilevel cascade converter according to claim 3, characterized in that, of the harmonics calculated by equation (4), higher harmonics are superimposed for the Iq term than for the Id term. The modular multilevel cascade converter according to any one of claims 3 to 6, characterized in that the harmonics are smaller than those calculated by equation (4), (11), or (12). A switching element connected to a positive terminal of the DC link capacitor;
a parallel capacitor connected in parallel to the switching element;
A cell module having two or more chopper cells or bridge cells cascade-connected to the negative terminal of the DC link capacitor;
a buffer reactor connected between the switching element and the cell module;
A control method for a modular multilevel cascade converter having two or more phases, comprising:
A voltage command value is generated using a two-arm modulation method;
a gate controller turns on the switching element when the voltage command value of the phase to be controlled is 1 and a voltage detection value of the switching element of the phase to be controlled is equal to or less than 0, and turns off the switching element when the voltage command value of the phase to be controlled is less than 1;
the current command value calculation unit normally outputs a commutation command value obtained by adding a fixed value α to the output current detection value as the cell module output current command value, and when the switching element of the phase to be controlled is turned ON, for a certain time Δtc, outputs as the cell module output current command value a charge/discharge current command value obtained by multiplying the deviation between the cell capacitor voltage average value and the cell capacitor voltage command value by a gain Gc, with harmonics superimposed thereon so as to suppress voltage ripple of the DC link capacitor ;
the current control unit outputs, as a cell module voltage command value, a value obtained by multiplying a feedforward term obtained by multiplying a difference between the cell module output current command value a certain time ago Δt and the current cell module output current command value by a gain Gl, a value obtained by multiplying a deviation between the cell module output current command value and the cell module output current detection value by a gain G, and adding 1;
a gate signal generating unit selects the voltage command value when a gate command for the switching element of the phase to be controlled is OFF and the voltage command value for the phase to be controlled is less than 1, and otherwise selects the cell module voltage command value, multiplies the selected value by a correction coefficient, and compares a value to which a cell capacitor voltage control command value has been added with a carrier triangular wave to generate a cell gate command. A switching element connected to a negative terminal of the DC link capacitor;
a parallel capacitor connected in parallel to the switching element;
A cell module having two or more chopper cells or bridge cells cascade-connected to the positive terminal of the DC link capacitor;
a buffer reactor connected between the switching element and the cell module;
A control method for a modular multilevel cascade converter having two or more phases, comprising:
A voltage command value is generated using a two-arm modulation method;
a gate controller turns on the switching element when the voltage command value of the phase to be controlled is −1 and the voltage detection value of the switching element of the phase to be controlled is greater than 0, and turns off the switching element when the voltage command value of the phase to be controlled is greater than −1;
the current command value calculation unit normally outputs a commutation command value obtained by adding a fixed value α to the output current detection value as the cell module output current command value, and when the switching element of the phase to be controlled is turned ON, for a certain time Δtc, outputs as the cell module output current command value a charge/discharge current command value obtained by multiplying the deviation between the cell capacitor voltage average value and the cell capacitor voltage command value by a gain -Gc, and superimposing harmonics so as to suppress voltage ripple of the DC link capacitor ;
the current control unit outputs, as a cell module voltage command value, a value obtained by multiplying a feedforward term obtained by multiplying a difference between the cell module output current command value a certain time ago Δt and the current cell module output current command value by a gain Gl, a value obtained by multiplying a deviation between the cell module output current command value and the cell module output current detection value by a gain G, and -1;
a gate signal generating unit selects the voltage command value when a gate command for the switching element of the phase to be controlled is OFF and the voltage command value for the phase to be controlled is greater than -1, and selects the cell module voltage command value otherwise, multiplies the selected value by a correction coefficient, and compares a value to which a cell capacitor voltage control command value has been added with a carrier triangular wave to generate a cell gate command.

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