JP7554686B2 - Method and apparatus for diagnosing a programmable logic device - Google Patents

Description

The present invention relates to programmable logic device technology.

In the broad sense, a programmable logic device (sometimes referred to as a PLD) is a circuit device in which user logic can be set (configured, in other words, programmed). A PLD, for example, has an array containing multiple logic blocks (sometimes referred to as LBs) as a logic circuit (in other words, a programmable area) in which user logic can be set. A logic block is also configured, for example, with a look-up table (sometimes referred to as a LUT) and a flip-flop (sometimes referred to as a FF). A memory (in other words, a storage device) such as a flash memory stores data for setting user logic in the PLD. The data is loaded from the memory into the logic circuit in the PLD, thereby setting the user logic in the logic circuit of the PLD.

For the above PLDs, manufacturers perform diagnostics (sometimes called scan tests, etc.) to detect any faults or defects and ensure the quality of the product.

An example of prior art related to the diagnosis of the above-mentioned PLD is JP 9-139667 A (Patent Document 1). Patent Document 1 describes how a self-inspection circuit for a programmable logic circuit can perform self-inspection immediately before writing logic information and inspection after mounting on the device, making it easier to isolate faults in a programmable logic integrated circuit. Patent Document 1 also describes how normal logic information and check logic information can be selected and programmed into a programmable logic integrated circuit.

Japanese Patent Application Publication No. 9-139667

Manufacturers of IC devices such as LSIs and FPGAs perform scan tests (diagnoses) on PLDs to detect defects and ensure product quality. Even if there are no problems during the manufacture of a PLD, physical stress on the PLD or deterioration over time may cause the PLD to fail or malfunction. At the manufacturing site where products equipped with PLDs are manufactured, scan tests are performed on the PLD-equipped products before shipping to inspect their quality. Even after the product has been shipped to the user's environment, if a malfunction occurs in the PLD, it is necessary to determine whether the malfunction is due to a physical failure of the PLD or simply a design defect. In such cases, scan tests may be performed on the PLD.

In diagnosing the above PLD, it is desirable to be able to diagnose the programmable area (logic circuit) of the PLD more comprehensively. In a conventional PLD of a certain type, the majority of the area within the device is occupied by logic blocks. These logic blocks are mainly composed of lookup tables and flip-flops. The PLD diagnosis method of the conventional technology example does not achieve comprehensive diagnosis down to the level of the input/output terminals of the lookup tables and flip-flops within the logic blocks.

In particular, the positions of the input/output terminals used by a lookup table change each time depending on the user logic that constitutes the circuit. For this reason, with the PLD diagnostic method of the conventional technology, it is possible that a situation may arise in which all of the input/output terminals used when configuring the user logic, which is the normal operation circuit that should be diagnosed, are not inspected or diagnosed. In other words, for example, if one of the input terminals of a lookup table used in a normal operation circuit has a stuck-at fault (a fault in which the value is fixed at 0 or 1), depending on the configuration of the diagnostic circuit, the stuck-at fault of that input terminal cannot be detected.

For example, in the PLD diagnostic technology of Patent Document 1, only the flip-flop portion in the logic block can be diagnosed due to the configuration of the diagnostic circuit (e.g., a configuration using a shift register, etc.). Conventional PLD diagnostic technology cannot perform comprehensive fault diagnosis for the portion of the logic circuit in which user logic is configured (in other words, the programmable area). In the conventional technology example, within each logic block, which is a logic circuit, only the specific input signal line used by the user logic out of the multiple input signal lines of the lookup table is diagnosed, and other input signal lines are not diagnosed.

Furthermore, conventional PLD diagnostic techniques, including that of Patent Document 1, require the implementation of a dedicated circuit for diagnosis (sometimes referred to as a diagnostic circuit) in the PLD. For example, in order to diagnose the user logic, which is a normal operation circuit, within the PLD, it is necessary to implement a circuit section for generating a diagnostic signal (in other words, a pattern) and a circuit section for determining and outputting the diagnostic result. In this case, it is also necessary to design an efficient diagnostic signal and a circuit for the diagnostic circuit. In addition, in this case, the area that can be used for the original user logic in the programmable region is reduced by the amount of the implementation of the diagnostic circuit.

The object of the present invention is to provide a technology for diagnosing the above-mentioned PLD that can more comprehensively diagnose failures and malfunctions in the PLD.

A representative embodiment of the present invention has the following configuration. The embodiment is a programmable logic device diagnostic method for diagnosing a fault or malfunction of a programmable logic device, the programmable logic device having a plurality of logic blocks in a programmable area, each logic block in the plurality of logic blocks having a lookup table having a plurality of input signal lines and one output signal line, and a flip-flop connected to a stage subsequent to the lookup table, the programmable logic device diagnostic method has a diagnostic step of configuring the diagnostic circuit in the programmable area and executing a diagnosis by loading diagnostic data for configuring a diagnostic circuit into a configuration memory of the programmable logic device at the time of diagnosis, the diagnostic circuit having a diagnostic signal generation circuit that generates a signal that repeats 0 and 1 as a diagnostic signal, and a plurality of logic blocks connected in series, each logic block having one output signal line that is connected to a plurality of input signals of a logic block in a next stage. and a logic block chain connected to a signal line, the diagnostic signal output from the diagnostic signal generation circuit being input to an input signal line of the first logic block of the logic block chain, and the output signal line of the last logic block of the logic block chain being connected to an output terminal of the programmable logic device, and the diagnostic step includes a first step of configuring an equivalent circuit of NAND or NOR in the lookup table of each logic block of the logic block chain, a second step of inputting the diagnostic signal to the first logic block of the logic block chain, a third step of observing an output signal from an output terminal of the programmable logic device, and a fourth step of determining that there is no fault or defect in the logic block chain if the observed signal value is a signal value that repeats 0 and 1, and determining that there is a fault or defect in the logic block chain if the observed signal value is not a signal value that repeats 0 and 1.

According to a representative embodiment of the present invention, the above-mentioned PLD diagnosis technology can diagnose PLD failures and malfunctions more comprehensively. Other issues, configurations, effects, etc. will be described in [Mode for carrying out the invention].

1 shows an example of the configuration of a PLD diagnostic system (including a PLD mounted board) compatible with a PLD diagnostic method according to a first embodiment of the present invention. In the first embodiment, the configuration of a PLD is shown. In the first embodiment, the configuration of a logic block (LB) is shown. 2 shows a flow of a PLD diagnosis method according to the first embodiment. In the first embodiment, a configuration example of a diagnostic signal generating unit in the first method will be described. In a modification of the first embodiment, a configuration example of a diagnostic signal generating section in the second method will be described. In the first embodiment, a more detailed configuration example of a PLD will be shown. In the first embodiment, a more detailed configuration example of a logic block (LB) will be shown. In the first embodiment, an example of the settings of the configuration memory for realizing a NAND or NOR configuration will be shown. In the first embodiment, a configuration example of a logic block (LB) for realizing a NAND or NOR configuration will be shown. In a modification of the first embodiment, a configuration example of a logic block (LB) in a case where other wirings are also diagnosed will be shown.

Below, an embodiment of the present invention will be described in detail with reference to the drawings. In the drawings, the same parts are generally given the same reference numerals, and repeated explanations will be omitted. In the drawings, the depiction of each component may not represent the actual position, size, shape, range, etc., in order to facilitate understanding of the invention, and the present invention is not necessarily limited to the position, size, shape, range, etc., disclosed in the drawings.

<First embodiment>
A PLD diagnostic method according to a first embodiment of the present invention will be described with reference to Figures 1 to 10. The PLD diagnostic method according to the first embodiment shown in Figure 1 and the like is a method in which, in a diagnostic system including a PLD-mounted board 10, a diagnostic configuration (setting of diagnostic circuits) is performed at the time of diagnosis for a PLD 1 that is an object to be diagnosed, and a diagnostic result is obtained from an output signal. The PLD diagnostic device according to the first embodiment corresponds to a system including the PLD-mounted board 10 in Figure 1, and performs operations and processing according to the PLD diagnostic method according to the first embodiment.

[PLD diagnostic system]
1 shows the configuration of a PLD diagnostic system corresponding to the PLD diagnostic method of the first embodiment. In other words, this PLD diagnostic system is a PLD diagnostic device. This PLD diagnostic system has a PLD mounted board 10, which is a board on which a PLD 1 is mounted, and a waveform observation device 16 connected to the PLD mounted board 10, and is operated and used by a user U. The user U is a diagnostician in a company that manufactures and diagnoses the PLD 1, in other words, an operator. This PLD diagnostic system has a function of diagnosing the PLD 1, which is a diagnostic target, by the PLD mounted board 10, which is a board that is a diagnostic execution object (subject). The PLD mounted board 10 executes processing according to the PLD diagnostic method of the first embodiment based on the operation by the user U. The user U operates and uses this PLD diagnostic system to perform diagnostic work on the PLD 1. This PLD diagnostic system accepts operational input (e.g., instructions, settings, etc.) from a user U via an input/output interface (such as an input/output device or user interface), and outputs the diagnostic state, diagnostic results, etc. to the user U.

PLD1 is the object to be diagnosed, and is a PLD of a certain type (i.e., a type that includes an LUT and FFs). In detail, there are various types of PLDs manufactured by various vendors, and the types differ in terms of implementation details, performance, etc. Examples of the types of PLDs from each vendor include differences in the arrangement and size of the logic circuit, the number of input signal lines of the LUT, etc. The PLD diagnosis method of the first embodiment can be similarly applied to these various PLDs. PLD1 includes a configuration memory 1M and a logic block, etc., which will be described later.

The PLD-mounted board 10 is an integrated circuit board on which the PLD 1, which is the object to be diagnosed, is mounted, in other words, an integrated circuit board to which the PLD 1 is connected, and is composed of an LSI, etc. The PLD-mounted board 10 includes the PLD 1, a configuration ROM 11, a circuit data selection switch 12, a clock supplier 13, a display 14 such as an LED, an observation terminal (in other words, an output terminal) 15, and signal lines connecting them, etc.

The configuration ROM 11 stores data for configuring the PLD 1. The data includes normal operation circuit data 11A and diagnostic data 11B. The normal operation circuit data 11A is data for configuring the normal operation circuit (in other words, the user logic). The diagnostic data 11B is data for configuring the diagnostic circuit. The diagnostic data 11B includes NAND version diagnostic circuit data 11C and NOR version diagnostic circuit data 11D. The NAND version diagnostic circuit data 11C is data used when performing a diagnosis in the NAND version (steps S1 to S5 in FIG. 4) described below, and the NOR version diagnostic circuit data 11D is data used when performing a diagnosis in the NOR version (steps S7 to S11 in FIG. 4) described below, and these form one set. The company performing the diagnosis stores diagnostic data 11B in advance in the configuration ROM 11 of the PLD-mounted board 10.

A circuit data selection switch 12 is connected to the configuration ROM 11. The circuit data selection switch 12 switches which of the data in the configuration ROM 11 is used to configure the PLD 1 according to an operation input by the user U. Specifically, the circuit data selection switch 12 is switched so that normal operation circuit data 11A is selected during normal (non-diagnostic) operation, and diagnostic data 11B is selected during diagnosis. The data selected by the circuit data selection switch 12 from the configuration ROM 11 is loaded (in other words, expanded, written, stored) into the configuration memory 1M in the PLD 1 as circuit data (in other words, configuration data) c1 via a signal line.

When normal operation circuit data 11A is selected by circuit data selection switch 12, normal operation circuit data 11A is loaded into configuration memory 1M. This configures a normal operation circuit in the programmable area of PLD1. When diagnostic data 11B (e.g., NAND version diagnostic circuit data 11C) is selected by circuit data selection switch 12, diagnostic data 11B (e.g., NAND version diagnostic circuit data 11C) is loaded into configuration memory 1M. This configures a diagnostic circuit in the programmable area of PLD1.

The user U may directly operate the circuit data selection switch 12, or the user U may indirectly operate and set the circuit data selection switch 12 through operations from a device or computer system such as a PC that is communicatively connected to the PLD-mounted board 10.

The PLD1 may also be supplied with a clock c2 from a clock supplier 13 provided on the PLD-mounted board 10. In one method of the PLD diagnostic method of the first embodiment (see FIG. 5 below), the clock c2 is used to generate a diagnostic signal for diagnosing the PLD1. The PLD-mounted board 10 includes, for example, a quartz oscillator as the clock supplier 13, which is a source of the clock signal. This clock signal c1 is supplied to each part of the PLD-mounted board 10 and each part of the PLD1.

During diagnosis, the PLD1 has a scan-out signal c3 as an output signal. This scan-out signal c3 is output to the display 14 and the observation terminal 15 through a signal line. Either the display 14 or the observation terminal 15 may be used to observe the scan-out signal c3, which is an output signal. The display 14 is, for example, an LED lamp, and displays according to the signal value of the scan-out signal c3. For example, the display 14 is not lit when the signal value of the scan-out signal c3 is 0, and is lit when the signal value is 1. The display state of this LED lamp represents the output signal value. By visually viewing the display state of this display 14, the user U1 can recognize the state of the signal value of the scan-out signal c3, and can distinguish between a 01 repeating signal and a 0 degenerate signal, which will be described later.

A waveform observation device 16 is connected to the observation terminal 15 via a probe (signal line or communication line) outside the PLD-mounted board 10. The waveform observation device 16 is composed of an oscilloscope or the like, and displays the scan-out signal c3 from the observation terminal 15 as a waveform on a screen. By visually viewing the waveform displayed on the screen of the waveform observation device 16, the user U1 can recognize the state of the signal value of the scan-out signal c3.

The observation of the output signal is not limited to the waveform observation device 16, and may be performed using a screen such as a liquid crystal display of a computer system such as a PC that is connected to the PLD-mounted board 10 for communication. A diagnostic graphical user interface (GUI) may be provided on the screen of the waveform observation device 16 or the liquid crystal display of the PC. For example, the GUI on the screen may display not only the signal value and waveform of the scan-out signal c3, but also information such as the ID of the object to be diagnosed, date and time, diagnosis type (e.g., before shipment/after shipment), diagnostician (user U), diagnosis status message (e.g., "diagnosis started"/"diagnosis in progress"/"diagnosis completed"), diagnosis time, and diagnosis result (presence or absence of failure/failure and details).

The display state of the display 14 and waveform observation device 16 changes depending on whether the output signal value is 0 or 1. For example, when the PLD 1 is normal and the output signal value is a repeating signal of 0 and 1, the LED lamp of the display 14 blinks at a constant cycle. If there is a failure or malfunction in the PLD 1, the output signal value becomes, for example, a 0 degenerate signal, and the LED lamp of the display 14 is fixed in an unlit state. Therefore, from the difference in these display states, the user U can determine whether there is a failure or malfunction in the PLD 1.

In addition, in order to deal with the case where the output signal repeats 0 and 1 at high speed, the display output on the display 14 or the like may be adjusted to have a low frequency output signal so that the user U1 can easily visually confirm it. As described above, in this PLD diagnosis method, the user U1 can visually determine the observation and monitoring of the output signal during diagnosis. In particular, when a display 14 such as an LED is used, there is no need to provide an external device on the PLD mounting board 10, and diagnosis can be achieved at low cost.

In the first embodiment, as shown in FIG. 1, a configuration ROM 11 is provided on the PLD mounting substrate 10 in addition to the PLD 1 as a memory for storing configuration data using a flash memory or the like. As a modified example, a memory for storing such configuration data may be provided within the PLD 1.

[Timing of diagnosis]
In the PLD diagnosis method of the first embodiment, the timing for diagnosing the PLD 1 can be, for example, as follows. This diagnosis (in other words, a scan test or the like) can basically be performed at any timing. The state of the PLD-mounted device 10 can be roughly divided into the following phases.

(1) System operation phase: The system operation phase is a phase in which the PLD1 is operated with a normal operation circuit (user logic) configured. The user U sets the circuit data selection switch 12 in advance so that the normal operation circuit data 11A is selected as the configuration data c1 in FIG. 1. When the PLD mounting board 10 is powered on, the normal operation circuit data 11A is loaded from the configuration ROM 11 to the configuration memory 1M of the PLD1 as the configuration data c1 according to the setting of the circuit data selection switch 12. This configures the normal operation circuit in the programmable area of the PLD1. In addition, a clock c2 is supplied to the PLD1 from the clock supplier 13. The normal operation circuit of the PLD1 starts operating based on the clock c2. After the start of operation, if a malfunction occurs in the PLD1 during operation, the system transitions to the following diagnosis phase.

(2) Diagnostic phase: The diagnostic phase is a phase in which diagnosis is performed with a diagnostic circuit configured in the PLD1. After turning off the power to the PLD-mounted board 10, the user U sets the circuit data selection switch 12 so that the diagnostic circuit data 11B (for example, first the NAND version diagnostic circuit data 11C, then the NOR version diagnostic circuit data 11D) is selected as the configuration data c1 in FIG. 1. If observation and diagnosis are to be performed using a waveform observation device 16, the user U connects the waveform observation device 16 to the observation terminal 15 of the PLD-mounted board 10 and sets the device in a state in which the scan-out signal c3 output from the PLD1 can be monitored and observed. If the user U performs observation and diagnosis by visually checking the blinking of the display 14, the waveform observation device 16 is not necessary.

After that, the user U turns on the power supply of the PLD-mounted board 10. This causes the diagnostic circuit data 11B (e.g., NAND version diagnostic circuit data 11C) to be deployed as configuration data c1 from the configuration ROM 11 to the configuration memory 1M of the PLD1, and a diagnostic circuit (e.g., a NAND version diagnostic circuit) is configured in the programmable area. This automatically starts the diagnosis of the PLD1 on the PLD-mounted board 10. The user U observes the diagnostic waveform corresponding to the scan-out signal c3, for example, on the screen of the waveform observation device 16. Then, the user U determines whether there is a malfunction of the PLD1 (particularly the programmable area) or a logic fault in the normal operation circuit, etc., from the state of the diagnostic waveform, and isolates the malfunction. Following the diagnosis of the NAND version, the diagnosis of the NOR version is similarly performed. When the diagnosis of the NAND version and the diagnosis of the NOR version are completed as a set, the diagnosis of the PLD1 is completed.

[PLD]
FIG. 2 shows an outline of the internal configuration of the PLD 1. The PLD 1 has a logic block chain (sometimes referred to as LBC) 110, a diagnostic signal generator 101, and an output terminal 102. The logic block chain (LBC) 110 is configured by a series connection of a plurality of logic blocks (LBs) 100. The LBC 110 is a chain that connects all the LBs 100 to be diagnosed. In the example of FIG. 2, the LBC 110 is configured by a series connection of L LBCs such as LBC#1 to LBC#L.

The diagnostic signal generating unit 101 is a part configured for diagnosis using components in the existing PLD1, and is a part of the diagnostic circuit. Data for configuring the diagnostic signal generating unit 101 is included as part of the diagnostic data 11B. In an example of this PLD diagnostic method, which will be described later, the diagnostic signal generating unit 101 is configured as a diagnostic signal generating circuit using some LBs in the existing PLD1. In this PLD diagnostic method, the diagnostic signal generating unit 101 configured in the PLD1 generates a diagnostic signal d1, which is a signal for diagnosis, and inputs it to the LBC110. The diagnostic signal d1 is a signal (logical value) that alternately inverts 0 and 1 while repeating ("010101..."), and may be described as a 01 repeat signal, an inverted signal, etc., for the sake of explanation. During diagnosis, the diagnostic signal generating unit 101 outputs the generated diagnostic signal d1 to the LBC110 to be diagnosed. The diagnostic signal d1 is input to the first LB100 of the LBC110.

As shown in the figure, each LB100 of the LBC110 has multiple input signal lines 111 and one output signal line 112. One output signal line 112 of a certain LB100 is directly connected to multiple input signal lines 111 of the LB100 in the next stage. Note that the input signal lines correspond to input terminals and input signals, and the output signal lines correspond to output terminals and output signals.

The last LB100 of the LBC100 is connected to the output terminal 102 of the PLD100. The output signal d2 from the LBC100 is output as the scan-out signal c3 in FIG. 1 through the output terminal 102. In other words, the output signal d2 and the scan-out signal c3 are diagnostic output signals, observation signals, etc. This output signal d2 becomes a 01 repeating signal, similar to the contents of the diagnostic signal d1 at the time of input, when the LBC110 is normal, i.e., when there are no failures or defects.

On the other hand, if the LBC 110 is in a state where there is a failure or malfunction, this output signal d2 is no longer a 01 repeating signal. That is, in that case, this output signal d2 is a signal that is fixed to a signal value (logical value) of either 0 or 1 from a certain point in time, in other words, a 0-stuck signal or a 1-stuck signal. Therefore, the user U, who is the diagnostician, can monitor and observe the scan-out signal c3, which is the output signal d2, using a waveform observation device 16 or the like to determine which state the signal content is in, thereby determining whether the target LBC 110 (corresponding PLD 1) is in a failure or malfunction.

If the diagnosis results indicate that there is a fault or defect in the LBC 110 (corresponding PLD 1), the vendor will take action to address the fault or defect. One example of such action would be to replace the PLD 1, or to identify the faulty LB 100 and set the programmable area so that the faulty LB 100 is not used.

As shown in FIG. 2, in the LBC110 configured during diagnosis, one output of the LB100 in a certain stage is branched and connected to all of the multiple inputs of the LB100 in the next stage (multiple inputs of the LUT described below). With such a connection of the LBC110 and the LUT configured with a NAND or NOR as an equivalent circuit described below, the LUT of each LB100 functions as a NOT gate (inversion logic). Each LB100 in all LB100 of the LBC110 outputs a signal (e.g., 1) that is the inversion of a signal (e.g., 0) received from the LB100 in the previous stage every clock cycle. The LBC110 repeatedly inverts the value of the signal (diagnosis signal d1) flowing through the multiple LB100 between 0 and 1 for each LUT.

In an LUT with NAND configured, if even one of the input signals to the multiple input terminals of the LUT degenerates to 0, the signal value will not change to 0 even if a signal value of 1 is received from the previous LB100. Also, in an LUT with NOR configured, if even one of the input signals to the multiple input terminals of the LUT degenerates to 1, the signal value will not change to 1 even if a signal value of 0 is received from the previous LB100.

If there is a stuck-at fault in any of the multiple inputs of the LUT, the LUT of each LB100 will no longer function as a NOT gate. Therefore, the output signal d2 based on the diagnostic signal d1 will be a stuck-at-0 signal or a stuck-at-1 signal. Therefore, by observing the output signal d2, it is possible to determine whether or not there is a failure or malfunction in the LBC110 of the PLD1.

[LB]
3 shows an outline of the configuration of each LB 100 of the LBC 110. The LB 100 includes a look-up table (LUT) 2 whose input side is connected to a plurality of input signal lines 111, a flip-flop (FF) 5 whose input side is connected to one output signal line of the LUT 2, and signal lines connecting them. In other words, the LUT 2 has a plurality of input signal lines 111 and one output signal line. One output signal line of the FF 5 corresponds to one output signal line 112 of the LB 100.

During diagnosis, LUT2 is configured as an equivalent circuit with either NAND21 or NOR22. These are configured with the aforementioned NAND version diagnostic circuit data 11C or NOR version diagnostic circuit data 11D.

[Flow of PLD diagnosis method]
4 shows a flow of the PLD diagnostic method of the first embodiment. This flow includes automatic processing and operations by the PLD diagnostic system of FIG. 1 and operations and operations by a user U who is a diagnostician. This flow is performed at the above-mentioned timing and phase for performing the diagnosis. This flow has steps S1 to S15.

First, in step S1, the user U selects and sets the circuit data selection switch 12 to use the NAND diagnostic circuit 11C. For example, the user U operates the circuit data selection switch 12 to perform this setting. As an example of the operation and implementation of the circuit data selection switch 12, a button or lever may be used to manually switch between normal mode and diagnostic mode.

In step S2, the power supply of the PLD mounted board 10 including the PLD 1 is turned on. For example, the user U turns on the power button of the PLD mounted board 10. This starts up the PLD mounted board 10. In this PLD diagnostic method, the PLD mounted board 10 performs a free-running operation after the power supply is turned on, and automatically executes a diagnosis.

In step S3, the PLD-mounted board 10 loads the NAND version diagnostic circuit data 11C in the configuration ROM 11 as circuit data c1 into the configuration memory 1M of the PLD 1 based on the settings in step S1. This configures a NAND version diagnostic circuit in the programmable area of the PLD 1. That is, at this time, the diagnostic signal generating unit 101 in FIG. 2 is configured, and NAND 21 is configured in LUT 2 in FIG. 3 in each LB 100 in the LBC 110. Based on this configuration, the NAND version diagnostic process is automatically started and executed.

During the diagnosis time, the diagnostic signal d1 generated by the diagnostic signal generation circuit 101 in FIG. 2 is input to the LBC 110, and after passing through each LB 100, the output signal d2 indicating the diagnosis state in the NAND version is output from the last stage, and becomes the scan-out signal c3.

In step S4, the scan-out signal c3 from the observation terminal 15 is monitored and observed for a predetermined time or more from the start of the diagnosis. For example, the diagnostic waveform of the scan-out signal c3 is observed on the screen of the waveform observation device 16. In step S5, it is determined whether the repetition of 0 and 1 is normal for the signal value of the scan-out signal c3, which is the output signal. If it is normal (Y), that is, if the signal value is a repetition of 0 and 1, proceed to step S6. If it is not normal (N), that is, if the signal value is not a repetition of 0 and 1, proceed to step S14. The above-mentioned case of not being normal (N) is, for example, when the signal value becomes a signal value with successive 0s (a 0-degenerate signal) or a signal value with successive 1s (a 1-degenerate signal). As described above, the case of not being normal (N) generally suggests the presence of a failure or malfunction, but the detailed judgment result is given in steps S12 to S14 described later.

In step S6, the power supply to the PLD-mounted board 10 is temporarily turned off. Next, in step S7, the circuit data selection switch 12 is selected and set to use the NOR diagnostic circuit 11D. For example, user U1 operates the circuit data selection switch 12 to make this setting. In step S8, the power supply to the PLD-mounted board 10 is turned on again.

In step S9, based on the settings in step S7, the NOR version diagnostic circuit data 11D in the configuration ROM 11 is loaded as circuit data c1 into the configuration memory 1M of the PLD1. This configures a NOR version diagnostic circuit in the programmable area of the PLD1. That is, the diagnostic signal generating unit 101 in FIG. 2 is configured, and in each LB100 in the LBC110, NOR22 is configured in LUT2 in FIG. 3. Based on this configuration, the NOR version diagnostic process is automatically started and executed.

During the diagnosis time, the diagnosis signal d1 generated by the diagnosis signal generation circuit 101 in FIG. 2 is input to the LBC 110, and the output signal d2 representing the diagnosis state in the NOR version is output from the last stage, becoming the scan-out signal c3.

In step S10, the scan-out signal c3 from the observation terminal 15 is monitored and observed for a period of time equal to or longer than a predetermined time from the start of the diagnosis. In step S11, it is determined whether the signal value of the scan-out signal, which is an output signal, is normal in that it repeats 0 and 1. If it is normal (Y), that is, if the signal value is a repetition of 0 and 1, proceed to step S12. If it is not normal (N), that is, if the signal value is not a repetition of 0 and 1, proceed to step S13.

Step S12 is a diagnostic judgment, and one of the detailed diagnostic results is that there is no device malfunction due to a stuck-at fault in LB100. In other words, this means that no "stuck-at-1 fault" or "stuck-at-0 fault" has occurred in any of the LB100 in the LBC110 of this PLD1. A "stuck-at-1 fault" is a fault in which a signal value becomes fixed (stuck) at 1. A "stuck-at-0 fault" is a fault in which a signal value becomes fixed (stuck) at 0.

Step S13 is a diagnostic judgment, and one of the details of the diagnostic result is that a "stuck-at-1 fault" has occurred in one of the LBs 100. Also, step S14 is a diagnostic judgment, and one of the details of the diagnostic result is that a "stuck-at-0 fault" has occurred in one of the LBs 100.

After steps S12, S13, and S14, the process proceeds to step S15. Step S15 marks the end of the diagnosis, which means that isolation of the malfunction of PLD1 has been completed. As described above, in the PLD diagnosis method of embodiment 1, it is possible to isolate the normality/malfunction of the target PLD1 into diagnosis results (corresponding fault/malfunction states) such as those in steps S12, S13, and S14.

The minimum time required to diagnose the PLD 1 (the predetermined time in steps S4 and S10) can be estimated by multiplying the clock period by the number of LBs in the PLD-mounted board 10 that includes the diagnostic circuit. Note that the above process flow is an example in which a step for diagnosing the NAND version is first provided, followed by a step for diagnosing the NOR version, but this is not limiting and the process flow may be in the reverse order.

[Diagnostic signal generating unit (1)]
5 shows a diagnostic signal generating circuit 101A as a configuration example of the diagnostic signal generating unit 101 in the first embodiment. This configuration example is also referred to as a first method. This configuration example of the first method uses an external clock supply. The diagnostic signal generating circuit 101A receives and uses the clock signal c2 from the clock supplier 13 in FIG. 1 described above, and does not generate a clock signal within the diagnostic signal generating circuit 101A.

This diagnostic signal generating circuit 101A is connected to the front stage of the LB100 at the head of the LBC110. This diagnostic signal generating circuit 101A is mainly composed of one LB501. The LB501 of this diagnostic signal generating circuit 101A includes an LUT502 and an FF505. The LUT502 has a plurality of input signal lines 504, and one output signal line 503 is connected as an input signal line of the FF505. The output signal line 506 of the FF505 outputs the diagnostic signal d1. The LB501 of this diagnostic signal generating circuit 101A is different from each LB100 of the LBC110 in that the output signal line 506 of the FF505 returns to the plurality of input signal lines 504 of the LUT502 and is connected as shown in the figure through a signal line 507 so as to form a loop. FF505 inputs the output signal from output signal line 503 of LUT502 and a clock signal CLK corresponding to clock signal c3 input from the outside at input terminal 508, and holds the signal value.

[Diagnostic signal generating unit (2)]
6 shows a diagnostic signal generating circuit 101B as a configuration example of the diagnostic signal generating unit 101 in a modification of the first embodiment. This configuration example is also referred to as the second method. This configuration example of the second method does not require an external clock supply, and generates a clock signal within this diagnostic signal generating circuit 101A. When this second method is applied, the PLD mount board 10 does not need to have the clock supplier 13.

This diagnostic signal generation circuit 101B is connected to the front stage of the LB 100 at the head of the LBC 110. This diagnostic signal generation circuit 101B is configured as a ring oscillator circuit using an odd number (m) of LUTs. This diagnostic signal generation circuit 101B is mainly configured using a plurality (m) of LBs 601 {601-1 to 601-m}. Each LB 601 of this diagnostic signal generation circuit 101B has an LUT 602. The LUT 602 has a plurality of input signal lines 604 and one output signal line 606, and the one output signal line 606 is connected as an input signal line 604 of the LUT 602 of the LB 601 in the next stage.

The output signal line 606 of the LUT 602 of the LB 601-m in the last stage outputs the diagnostic signal d1 and the clock signal CLK. The output signal line 606 of the LUT 602 of the LB 601-m in the last stage is connected as shown through the signal line 607 so as to return to the multiple input signal lines 604 of the LB 601-1 in the first stage and form a loop.

This diagnostic signal generating circuit 101B can adjust the frequency of the diagnostic signal d1 according to the number of LBs 100 (corresponding LUTs 602) that are connected.

[PLD configuration example]
7 shows a more detailed configuration example of a general PLD, and the PLD 1 of the type to be diagnosed in the first embodiment also has such a basic configuration. As shown in the figure, this PLD has a plurality of LBs 701 (corresponding LBs 100) arranged as a two-dimensional array. Around the LBs 701, wiring 706 (vertical and horizontal rows shown by three lines in this example) is connected through wiring 705 (shown by one line in this example) and a wiring connection box (CB) 704. The wiring 706 (vertical and horizontal rows) through the wiring connection box (CB) 704 are connected to each other via a wiring switch box (SB) 703. In addition, an input/output block (IOB) 702 is also connected to the wiring connection box (CB) 704 on the outer periphery of the wiring on the PLD board 700.

In this PLD, LBs 701 can be connected together like a chain based on wiring control in a wiring connection box (CB) 704 and a wiring switch box (SB) 703 to form an LBC. In this example, an LBC 710 is configured as shown by the arrow. The LBC 110 in Figure 2 is configured based on the mechanism described above.

[LB configuration example]
FIG. 8 shows a more detailed configuration example of a general LB, and the LB 100 having such a configuration is used in the first embodiment. FIG. 8 corresponds to a more detailed configuration example of FIG. 3. The LB 100 in FIG. 8 has an LUT 2, a FF 5, a selector 4, and a signal line (in other words, wiring) connecting them. The LUT 2 has a plurality of input terminals 801 (e.g., a, b, . . ., c) corresponding to a plurality of input signal lines 111 (e.g., a1, a2, . . ., am) of the LB 100. A signal line (e.g., signal y) from an output terminal 802 of the LUT 2 becomes the output signal line 112 of the LB 100, and is also branched to become one input of the selector 4. The selector 4 takes one input signal (e.g., signal d) of the LB 100 as the other input. The selector 4 is an output data selector, and outputs a signal selected from one input (signal y) and the other input (signal d). An output signal 803 (i.e., signal y or signal d) of the selector 4 is one input signal of the FF 5. The clock signal CLK of the input of the LB 100 is also input to the FF 5. An output signal of the FF 5 (e.g., signal q) is another output signal of the output signal line 112 of the LB 100.

[NAND or NOR Settings for LB]
9 and 10 show a more specific example of the configuration when an equivalent circuit of a NAND (negative logical product) 21 or a NOR (negative logical product) 22 is configured in the LB 100 when diagnosing the PLD 1. First, FIG. 9(a) shows the memory setting values when realizing the configuration of NAND 21. This memory corresponds to the configuration memory 1M in FIG. 1 and to the configuration memory 3 (3A) in FIG. 10. In this example, the setting value of this configuration memory 3 (3A) is "11111110" (only the last bit is 0) in the case of 8 bits.

Similarly, FIG. 9(b) shows the setting values of the configuration memory 3 (3A) when realizing the configuration of NOR22. In this example, the setting value of this configuration memory 3 (3A) is "10000000" (only the first bit is 1). These setting values of the configuration memory 3 (3A) are set based on the aforementioned NAND version diagnostic circuit data 11C, etc.

Figure 10 shows an example of the configuration of LB100 when NAND21 is configured based on the memory setting values in Figure 9 (a). This LB100 includes an LUT2, FF5, selector 4 (4A, 4B), configuration memory 3 (3A, 3B), and signal lines (wiring) connecting them. The configuration memory 3 has memory 3A and memory 3B. The selector 4 has selector 4A and selector 4B. Memory 3A is connected to selector 4A of LUT2. Memory 3B is connected to selector 4B before FF5.

The configuration memory 3A corresponds to an LUT configuration table. For example, when the PLD1 is started up, a setting value such as that shown in FIG. 9(a) is loaded and stored in this configuration memory 3A from the external configuration ROM 11 (NAND version diagnostic circuit data 11C). This automatically configures NAND 21 in the LUT2. This setting value is information that defines the configuration of the LUT2, that is, the correspondence between the input value and the output value, in other words, information that determines the truth value that is output using bits based on multiple inputs as an index.

In this example, LUT2 is a three-input LUT (a LUT having three input signal lines/input terminals), and is a circuit that outputs one output value according to a combination of three input values. LUT2 includes memory 3A and selector 4A. A plurality of output signal lines 901 of memory 3A are connected as a plurality of input signal lines of selector 4A. A plurality of input signal lines 801 (three lines indicated by a, b, and c in this example) of LUT2 are connected to the control input terminal of selector 4A. One output signal line 802 of selector 4A and LUT2 becomes one of the output signal lines of LB100 as indicated by signal y, and is connected by branching as one of the two input signal lines of selector 4B. An input signal line 903 indicated by signal d is connected as the other input signal line of selector 4B.

The control input terminal of the selector 4B is supplied with a set value from the memory 3B. For example, 0 is set in the memory 3B in FIG. 9. The selector 4B selects and outputs an output value from two input signals (y, d) according to the set value of the memory 3B connected to the control input terminal. The output data selected by the selector 4B is connected to one input signal line of FF5 via one output signal line 803. FF5 temporarily holds the output data. In addition, the clock signal CLK (supplied from the above-mentioned diagnostic signal generating unit 101) is input to FF5 via one input signal line 904. FF5 outputs a signal q from one output signal line 906, which becomes the other output signal of the output signal line 112.

This LUT2 is a block that selects the setting value data of the configuration memory 3A according to the input value from the input signal line 801 (a, b, c in this example). In the figure, for ease of explanation, an example of the setting of LUT2 in the selector 4A is illustrated as a matrix in a schematic manner. In this selector 4A, an output data value is selected and determined from the setting value of the configuration memory 3A corresponding to the row (input on the signal line 901) according to the combination of values of the column (input on the input signal line 801 side), and output from the output signal line 802. This matrix indicates which value of the setting value of the memory 3A is selected and output according to all combinations (8 in this example) of the values of the LUT2 input (a, b, c). For example, in a NAND21 configuration, when the value of the set of LUT2 inputs (a, b, c) at a certain time is (0, 0, 0), the setting value "1" of the memory 3A corresponding to the first row shown in the figure is selected and output. If the value of the LUT2 input (a, b, c) pair at a given time is (1, 1, 1), the setting value "0" of memory 3A corresponding to the eighth row shown in the figure is selected and output.

The diagnostic mechanism in this PLD diagnostic method is outlined below. During diagnosis, the same value (0 or 1) is input to each input (a, b, c) of the input signal line 801 of LUT2. Therefore, for example, if a value that results in the configuration of NAND21 as shown in FIG. 9(a) above is set in memory 3A, the output signal value of LUT2 under normal conditions will always be a signal that alternates between 0 and 1 on a time series (01 repetition signal).

For example, in the case of the configuration of NAND21 as shown in FIG. 10, consider the case where at least one (one or more) of the multiple inputs (input signal lines 801) of LUT2 is fixed to 0 (described as "stuck at 0"). In this case, as shown in the figure, the combination of LUT2 settings corresponds to one of the seven combinations from the top, and in any case, 0 (a value corresponding to the set (1, 1, 1)) will not be selected as the output value from memory 3A. In other words, only 1 selected from memory 3A will be output as the output of LUT2. Therefore, the output signal of LB100 becomes such a signal value/output data ("1111...", "stuck at 1 signal") that is fixed to 1 and continues to be 1. If such an output signal value is observed during diagnosis, a fault/fault in this LUT2, particularly a "stuck at 0 fault", can be detected. As described above, the configuration of LUT2 in FIG. 10 has a function of outputting 0 only when all inputs are 1, and is therefore a NAND configuration as an equivalent circuit.

The mechanism is basically the same as above when diagnosing with the configuration of NOR22. Although not shown, consider the case where the setting value of memory 3A in the configuration of FIG. 10 is replaced with the setting value "0000...1" in FIG. 9(b). In the case of this configuration of NOR21, if any input value of LUT2 is fixed to 1 (described as "stuck at 1"), the combination of LUT2 settings corresponds to any of the seven combinations from the bottom, and in any case, 1 will not be selected as the output value from memory 3A. In other words, only 0 will be output as the output of LUT2. Therefore, the output signal of LB100 becomes a signal value/output data with continuous 0s fixed to 0 ("0000...", "stuck at 0 signal"). By observing such output signal values, it is possible to detect failures/malfunctions of this LUT2, especially "stuck at 1 failures".

The PLD diagnosis method of the first embodiment performs a set of diagnosis for a "stuck-at-1 fault" in the NAND21 configuration and a diagnosis for a "stuck-at-0 fault" in the NOR22 configuration (Figure 4). This makes it possible to reliably perform a fault diagnosis for the LB100 that includes the target LUT2.

In the configuration of FIG. 10, during diagnosis, selector 4B selects the output of LUT2 (output signal line 802, signal y) by setting the value "0" in memory 3B. In this case, the input of signal d is not selected by selector 4B and is not used for diagnosis.

[Effects, etc.]
As described above, according to the PLD diagnostic method of the first embodiment, the failures and defects of the PLD 1 can be diagnosed more comprehensively. According to the first embodiment, it is not necessary to implement a diagnostic circuit in the PLD 1, and the number of design steps can be reduced. According to the first embodiment, in the programmable area of the logic block 100 of the PLD 1, not only the area in which the user logic is programmed but also the entire programmable area can be diagnosed as comprehensively as possible. According to the first embodiment, it is possible to comprehensively diagnose the input of the multiple input signal lines 801 of the LUT 2 (FIG. 8) regardless of the value. In other words, it is possible to comprehensively diagnose all of the multiple input signal lines of the LUT 2. The PLD diagnostic method of the first embodiment is a method for diagnosing a certain type of PLD (i.e., a type having an LUT and FF) as a diagnostic object, but it can be applied to a certain type of PLD regardless of the vendor or type (for example, differences in array, size, number of LUT input terminals, etc.), and does not require design depending on the vendor or type. According to the first embodiment, even if a defect occurs after the product is shipped, diagnosis can be used to easily determine whether the cause is a physical failure of the PLD device or simply a design flaw, thereby achieving low costs.

In addition, the PLD diagnostic method of the first embodiment has the following advantages. According to the first embodiment, it is not necessary to design or implement a generation circuit for a diagnostic signal (in other words, a pattern) as in the conventional technology example. According to the first embodiment, the diagnosable area (the number of corresponding LBs) in the programmable area is increased. It is assumed that the size of the programmable area is the same constant area in the PLD in the conventional technology example and the PLD in the first embodiment compared thereto. In the conventional technology example, it is necessary to implement a diagnostic circuit (corresponding hardware) for the fault diagnosis function in a part of the programmable area in the PLD. That is, the area in which the user logic can be set among the entire programmable area is the part excluding the diagnostic circuit. On the other hand, in the PLD in the first embodiment, it is not necessary to implement a dedicated diagnostic circuit (corresponding hardware) in the programmable area for the implementation of the fault diagnosis function. Therefore, in the first embodiment, the area in which the user logic can be set among the entire programmable area is the entire area. During diagnosis, the diagnostic circuit described above is temporarily configured in the programmable area of the PLD, but after diagnosis, the user logic (normal operation circuit) can be configured.

[Modification]
The following modifications of the first embodiment are also possible. In the first embodiment, a method for reliably diagnosing the wiring passing through the LUT2 and FF5 including a plurality of input signal lines of the LB100 has been shown. Furthermore, in the modification, other wiring parts in the LB can also be diagnosed, thereby improving comprehensiveness. In this modification, the states of the wiring and switches are set for diagnosis in the PLD of FIG. 7. In general, the LB100 has a configuration as shown in FIG. 8, and depending on the assembly of the LBC110, it is possible to diagnose not only the wiring between LUT2 and FF5 in the same LB100, but also the wiring between LUT2 and FF5 between different LB100.

Figure 11 shows an example of the configuration of LB100 during diagnosis, as an explanatory diagram of a PLD diagnosis method according to a modified example of the first embodiment. A setting value of "1" is set for memory 3B connected to selector 4B in LB100. As a result, selector 4B selects and outputs signal d on input signal line 903 out of two input signals (y, d).

The input of signal d of LB100 is different from the input (a, b, c) of LUT2. This is the following input when explained with the configuration of FIG. 7. In FIG. 7, if we focus on one LB100, for example, four other LB100s are arranged around and adjacent to that LB100, above, below, left and right, via wiring 705 and wiring connection box (CB) 704. Assume that this central LB100 has four inputs from the four neighboring LB100s. The four inputs are, for example, signals a, b, c, and d. Then, three of these inputs are used as the inputs (a, b, c) of the aforementioned LUT2. The remaining input is the input of signal d. The wiring is connected in the PLD of FIG. 7 so as to have such a connection relationship. It is possible to connect various LBC110s, not limited to the LBC710 in FIG. 7.

In a modified example, the diagnostic signal d1 during diagnosis flows in the LBC 110 as follows. For example, consider the first LB and the second LB as inter-LB connections. The diagnostic signal d1 (signal value of 0 or 1 at a certain point in time) is first input to the input signal line 801 (a, b, c) of the LUT 2 of the first LB of the LBC 110 as shown in FIG. 11, and the output value of the LUT 2 is output as a signal y on the output signal line 802. The output of the signal y is input to the input signal line 903 of the signal d of the next second LB based on the wiring connection between the LBs 100. The input of the signal d is selected and output by the selector 4B, input to the FF5, and becomes the output of the signal q on the output signal line 906 from the FF5. The output of the signal q is input to the input signal line 801 (a, b, c) of the LUT 2 of the next LB 100, and so on.

In the PLD diagnosis method of this modified example, as described above, in multiple LBs 100, diagnostic signals flow in both the signal line of signal y and the signal line of signal d in the same way, so by observing these output signals, it is possible to determine a failure or malfunction using the same mechanism as described above (whether or not it is a 01 repeating signal). In other words, according to this modified example, other wiring (signal line 903, etc.) within LB 100 can also be diagnosed as targets, improving the comprehensiveness of the diagnosis.

The present invention has been specifically described above based on the embodiments, but the present invention is not limited to the above-mentioned embodiments and can be modified in various ways without departing from the gist of the invention.

1...PLD, 1M...configuration, 10...PLD mounting board, 11...configuration ROM, 11A...normal operation circuit data, 11B...diagnosis data, 11C...NAND version diagnostic circuit data, 11D...NOR version diagnostic circuit data, 12...circuit data selection switch, 13...clock supplier, 14...display, 15...observation terminal, 16...waveform observation device, 100...LB, 101...diagnosis signal generator, 102...output terminal, 110...LBC, 111...input signal line, 112...output signal line, d1...diagnosis signal, d2...output signal.

Claims (6)

A programmable logic device diagnostic method for diagnosing a fault or malfunction of a programmable logic device, comprising:
The programmable logic device includes a plurality of logic blocks in a programmable area;
Each of the plurality of logic blocks includes a lookup table having a plurality of input signal lines and one output signal line, and a flip-flop connected to a subsequent stage of the lookup table;
The programmable logic device diagnostic method includes:
a diagnostic step of configuring the diagnostic circuit in the programmable area by loading diagnostic data for configuring a diagnostic circuit into a configuration memory of the programmable logic device at the time of diagnosis, and executing a diagnosis;
The diagnostic circuitry includes:
a diagnostic signal generating circuit for generating a signal that repeats 0 and 1 as a diagnostic signal;
A logic block chain in which the plurality of logic blocks are connected in series and one output signal line of each logic block is connected to a plurality of input signal lines of a logic block in a next stage;
having
The diagnostic signal output from the diagnostic signal generation circuit is input to an input signal line of a first logic block of the logic block chain, and an output signal line of a last logic block of the logic block chain is connected to an output terminal of the programmable logic device;
The diagnosis step includes:
A first step in which a NAND or NOR is configured as an equivalent circuit in the lookup table of each logical block of the logical block chain;
a second step of inputting the diagnostic signal to a first logical block of the logical block chain;
a third step of observing an output signal from an output terminal of the programmable logic device;
A fourth step of determining that there is no fault or defect in the logical block chain if the observed signal value is a signal value that repeats 0 and 1, and determining that there is a fault or defect in the logical block chain if the observed signal value is not a signal value that repeats 0 and 1;
23. A programmable logic device diagnostic method comprising: 2. The programmable logic device diagnostic method according to claim 1, further comprising:
The diagnosis step includes:
configuring a NAND as an equivalent circuit in the lookup table and performing diagnosis;
and configuring a NOR as an equivalent circuit in the lookup table to perform diagnosis.
In the diagnosis of the NAND, in the fourth step, if the observed signal value becomes a signal value fixed to 1 , it is determined that a stuck-at -0 fault in which a signal value is stuck to 0 has occurred in any one of the logic blocks of the logic block chain,
In the diagnosis using the NOR, if the observed signal value becomes a signal value fixed to 0 in the fourth step, it is determined that a stuck-at -1 fault in which the signal value is stuck to 1 has occurred in any one of the logic blocks of the logic block chain.
A method for diagnosing a programmable logic device. 2. The programmable logic device diagnostic method according to claim 1, further comprising:
The diagnostic signal generating circuit includes:
an output terminal of a flip-flop in one logic block is connected in a loop back to all of a plurality of input terminals of a look-up table;
a clock signal from outside the programmable logic device is input to generate the diagnostic signal;
A method for diagnosing a programmable logic device. 2. The programmable logic device diagnostic method according to claim 1, further comprising:
The diagnostic signal generating circuit includes:
an output terminal of a last logic block in an odd number of logic blocks is connected in a loop so as to return to all of the plurality of input terminals of the look-up table of the first logic block, and an output signal line of each intermediate logic block is connected to the plurality of input signal lines of a logic block in a next stage;
generating a clock signal and said diagnostic signal;
A method for diagnosing a programmable logic device. 2. The programmable logic device diagnostic method according to claim 1, further comprising:
a step of switching between configuring the normal operation circuit in the programmable area by loading normal operation circuit data for configuring a normal operation circuit from a configuration memory outside the programmable logic device to a configuration memory of the programmable logic device based on a selection setting of a circuit data selection switch outside the programmable logic device, and configuring the diagnostic circuit by loading the diagnostic data.
A method for diagnosing a programmable logic device. A programmable logic device diagnostic apparatus for diagnosing a fault or malfunction of a programmable logic device, comprising:
a substrate on which the programmable logic device is mounted;
A configuration ROM provided on the substrate;
Equipped with
The programmable logic device includes a plurality of logic blocks in a programmable area;
Each of the plurality of logic blocks includes a lookup table having a plurality of input signal lines and one output signal line, and a flip-flop connected to a subsequent stage of the lookup table;
During diagnosis, diagnostic data for configuring a diagnostic circuit is loaded from the configuration ROM to a configuration memory of the programmable logic device, thereby configuring the diagnostic circuit in the programmable area and executing a diagnosis;
The diagnostic circuitry includes:
a diagnostic signal generating circuit for generating a signal that alternates between 0 and 1 as a diagnostic signal;
A logic block chain in which the plurality of logic blocks are connected in series and one output signal line of each logic block is connected to a plurality of input signal lines of a logic block in a next stage;
having
The diagnostic signal output from the diagnostic signal generation circuit is input to an input signal line of a first logic block of the logic block chain, and an output signal line of a last logic block of the logic block chain is connected to an output terminal of the programmable logic device;
In the diagnosis,
The lookup table of each logical block of the logical block chain is configured with a NAND or NOR as an equivalent circuit,
inputting the diagnostic signal into a first logical block of the logical block chain;
Observing an output signal from an output terminal of the programmable logic device;
If the observed signal value is a signal value that repeats 0 and 1, it is determined that there is no fault or defect in the logical blockchain, and if the signal value is not a signal value that repeats 0 and 1, it is determined that there is a fault or defect in the logical blockchain.
Programmable logic device diagnostic equipment.

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