JP7555697B2 - Photoelectric conversion device, method for manufacturing photoelectric conversion device, and method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a photoelectric conversion device, a method for manufacturing a photoelectric conversion device, and a method for manufacturing a semiconductor device.

For CCD and amplified solid-state imaging devices used in digital still cameras and camcorders, a stacked structure has been proposed in which multiple semiconductor chips with different functions are bonded together and electrically connected. A solid-state imaging device (hereinafter referred to as a photoelectric conversion device) formed with this stacked structure can form optimal processes and circuits for each semiconductor chip, making it easy to increase the functionality of the device. It has also been proposed that in photoelectric conversion devices, measurements are performed using an inspection circuit before the semiconductor chips are bonded together, and that wafers can be selected, rejected, or repaired for redundancy based on these measurements.

International Publication No. 2015/159766

The inventor discovered that if the input or output potential in the inspection circuit is unstable, the operation of the inspection circuit may become unstable, causing voltage fluctuations. The inventor discovered that this effect causes a noise signal to be superimposed on the operation of the photoelectric conversion device (sensor) via capacitive coupling.

In contrast, in Patent Document 1, in addition to the power supply that provides a potential (power supply potential) to the inspection circuit, the input/output terminals (electrodes; pads) of the inspection circuit are connected to external connection pads via stacked connections, so the input or output potential of the inspection circuit is stable.

However, in this patent document 1, an external connection pad is required to stabilize the potential of the input or output of the inspection circuit, which reduces the integration density of the semiconductor chip. Furthermore, patent document 1 does not describe a method (treatment) for stabilizing the potential of an inspection circuit that is not connected to an external connection pad. In other words, it is not possible to achieve both improved integration density and reduced noise in a photoelectric conversion device having an inspection circuit.

The present invention aims to provide a photoelectric conversion device having an inspection circuit, which is highly integrated and has low noise.

The first aspect of the present invention is a method for producing a cellular membrane comprising the steps of:
A first substrate having pixel circuits including photoelectric conversion elements;
A second substrate having a signal processing circuit that drives the pixel circuit or processes a signal from the pixel circuit;
a connection portion that electrically connects the first substrate and the second substrate;
A test circuit;
having
the inspection circuit is formed on one of the first substrate and the second substrate, and a wiring for supplying a first potential on the one substrate is connected to a power supply connection terminal of the inspection circuit ;
a second potential is supplied to at least one of an input terminal and an output terminal of the inspection circuit, the input terminal and the output terminal being different from the power supply connection terminal;
The connection portion is connected to at least one of the input terminal and the output terminal.
The photoelectric conversion device is characterized in that

A second aspect of the present invention is a method for producing a composition comprising the steps of:
providing a first substrate having pixel circuits including photoelectric conversion elements;
providing a second substrate having a signal processing circuit for driving the pixel circuit or for processing a signal from the pixel circuit;
a bonding step of forming a connection portion that electrically connects the first substrate and the second substrate,
one of the first substrate and the second substrate includes an inspection circuit having a power supply connection terminal connected to a wiring for supplying a first potential in the one substrate;
The joining step includes:
forming the connection portion using an input terminal or an output terminal of the inspection circuit other than the power supply connection terminal;
connecting the input terminal or the output terminal of the inspection circuit to a wiring for supplying a second potential;
Including,
The present invention relates to a method for producing a photoelectric conversion device.

A third aspect of the present invention is a method for producing a composition comprising the steps of:
1. A method for manufacturing a semiconductor device having a second substrate for bonding to a first substrate, comprising the steps of:
forming a second substrate having a second circuit for driving a first circuit disposed on the first substrate or for processing a signal from the first circuit, and a test circuit for testing the second circuit;
an inspection step of inspecting the second circuit by contacting a probe with at least one of an input terminal and an output terminal of the inspection circuit;
having
In the forming step, at least one of an input terminal and an output terminal of the inspection circuit is configured to be connected to a wiring for supplying a predetermined potential on the first substrate.
The present invention relates to a method for manufacturing a semiconductor device.

A fourth aspect of the present invention is a method for producing a composition comprising the steps of:
providing a first substrate having pixel circuits including photoelectric conversion elements;
providing a second substrate having a signal processing circuit for driving the pixel circuit or for processing a signal from the pixel circuit;
supplying a first potential from one of the first and second substrates to a power supply connection terminal of an inspection circuit formed on the one substrate;
an inspection step of contacting a probe with at least one of an input terminal and an output terminal of the inspection circuit, the input terminal and the output terminal being different from the power supply connection terminal;
a bonding step of electrically connecting at least one of the input terminal and the output terminal to a wiring for supplying a second potential by bonding the first substrate and the second substrate with a bonding portion;
having
The joining step includes:
a step of forming an oxide film on the one substrate on which the inspection circuit is formed and planarizing the oxide film after the probe is brought into contact in the inspection step;
forming the joint at a terminal of the inspection circuit with which the probe is in contact;
Including,
The present invention relates to a method for producing a photoelectric conversion device.

A fifth aspect of the present invention is a method for producing a composition comprising the steps of:
providing a first substrate having pixel circuits including photoelectric conversion elements;
providing a second substrate having a signal processing circuit for driving the pixel circuit or for processing a signal from the pixel circuit;
supplying a first potential from one of the first and second substrates to each of power supply connection terminals of a plurality of inspection circuits formed on the one substrate;
an inspection step of contacting a probe with at least one of an input terminal and an output terminal of a first inspection circuit among the plurality of inspection circuits, the input terminal and the output terminal being different from the power supply connection terminal;
a bonding step of electrically connecting at least one of the input terminal and the output terminal to a wiring for supplying a second potential by bonding the first substrate and the second substrate with a bonding portion;
having
The joining step includes:
a step of forming an oxide film on the one substrate on which the plurality of inspection circuits are formed and planarizing the oxide film after the probe is brought into contact in the inspection step;
forming the joint on a terminal of a second inspection circuit that is not in contact with the probe among the plurality of inspection circuits;
Including,
the first inspection circuit and the second inspection circuit are electrically connected to one of the substrates on which the plurality of inspection circuits are formed.
The present invention relates to a method for producing a photoelectric conversion device.
A sixth aspect of the present invention is a method for producing a composition comprising the steps of:
providing a first substrate having pixel circuits including photoelectric conversion elements;
providing a second substrate having a signal processing circuit for driving the pixel circuit or for processing a signal from the pixel circuit;
supplying a first potential from one of the first and second substrates to a power supply connection terminal of an inspection circuit formed on the one substrate;
an inspection step of contacting a probe with at least one of a first input terminal and a first output terminal of the inspection circuit, the inspection circuit including a plurality of terminals different from the power supply connection terminals that are connected to each other;
a bonding step of electrically connecting at least one of the first input terminal and the first output terminal to a wiring for supplying a second potential by bonding the first substrate and the second substrate with a bonding portion;
having
The joining step includes:
forming an oxide film on one of the first substrate and the second substrate after a probe is brought into contact with at least one of the first input terminal and the first output terminal in the inspection step;
planarizing the oxide film ;
forming the joints at a second input terminal different from the first input terminal and at a second output terminal different from the first output terminal of the plurality of terminals of the inspection circuit;
Including,
The present invention relates to a method for producing a photoelectric conversion device.

The present invention provides a photoelectric conversion device having an inspection circuit, which is highly integrated and has low noise.

1 is a cross-sectional view showing a schematic diagram of a solid-state imaging device according to a first embodiment; 1 is a circuit diagram illustrating a solid-state imaging device according to a first embodiment of the present invention; FIG. 11 is a cross-sectional view illustrating a solid-state imaging device according to a second embodiment. FIG. 11 is a circuit diagram illustrating a solid-state imaging device according to a second embodiment. 4 is a flowchart of a method for manufacturing a solid-state imaging device according to an embodiment. FIG. 11 is a circuit diagram illustrating a solid-state imaging device according to a third embodiment. FIG. 13 is a diagram illustrating an example of the configuration of an imaging system according to a sixth embodiment. FIG. 13 is a diagram illustrating an example of the configuration of an imaging system and a moving object according to a seventh embodiment. FIG. 11 is a cross-sectional view illustrating a solid-state imaging device according to a fourth embodiment. 10A to 10C are cross-sectional views showing a manufacturing process of a solid-state imaging device according to a fourth embodiment. 10A to 10C are cross-sectional views showing a manufacturing process of a solid-state imaging device according to a fourth embodiment. FIG. 13 is a cross-sectional view illustrating a solid-state imaging device according to a fifth embodiment. 13A to 13C are cross-sectional views showing a manufacturing process of a solid-state imaging device according to a fifth embodiment. 13A to 13C are cross-sectional views showing a manufacturing process of a solid-state imaging device according to a fifth embodiment.

The following describes an embodiment of the present invention with reference to the attached drawings, but the present invention is not limited to the following embodiment (embodiment).

Example 1
In the first embodiment of the present invention, in a photoelectric conversion device in which two semiconductor substrates are stacked, a potential (power supply potential) is supplied to an inspection circuit formed on one of the semiconductor substrates, and the inspection circuit is further connected to another potential on the other semiconductor substrate via a stacked connection portion. This makes it possible to stabilize the potential (voltage) in the inspection circuit even when the supplied potential changes, thereby suppressing the generation of noise. Furthermore, in this embodiment, an external connection pad is not used to connect to the other potential, thereby improving the integration degree of the photoelectric conversion device.

Below, a solid-state imaging device 100, which is a photoelectric conversion device (stacked sensor; semiconductor device) according to this embodiment, will be described with reference to Figures 1, 2(A), and 2(B).

[Cross-sectional configuration of solid-state imaging device]
1 shows a cross-sectional view of a solid-state imaging device 100. The solid-state imaging device 100 is configured with a stacked structure in which two semiconductor substrates, a semiconductor substrate 101 and a semiconductor substrate 102, are bonded together (joined). Here, the semiconductor substrates 101 and 102 are electrically connected by a stacked connection portion 130. Therefore, it can be said that the stacked connection portion 130 is not included in either the semiconductor substrate 101 or the semiconductor substrate 102, or that it is included in both.

The semiconductor substrate 101 has a sensor function. More specifically, the semiconductor substrate 101 has a pixel circuit 110 having a photoelectric conversion element composed of a photodiode 110-1, a selection transistor 110-2, etc., and a peripheral circuit 111.

In addition, the semiconductor substrate 101 is formed with an external connection pad 220, which is an electrode for connecting to the outside. Here, the external connection pad 220 can be wire-bonded via a TSV (Through-Silicon Via) 225 formed in the semiconductor substrate 101.

The semiconductor substrate 102 has a logic circuit (logic circuit; signal processing circuit) 112 for driving the pixel circuit 110 (photoelectric conversion element; sensor). Alternatively, the logic circuit 112 may include a memory, a vertical signal line, etc., and process a signal output by the photoelectric conversion element. The process of driving the pixel circuit 110 can also be considered to be included in the signal processing. The peripheral circuit 111 may have part of the configuration of such a logic circuit 112. In order to perform the above-mentioned signal processing, the logic circuit 112 is electrically connected to the pixel circuit 110 by another stack connection part having a configuration similar to that of the stack connection part 130.

In addition, in this embodiment, the semiconductor substrate 102 is formed with an inspection circuit 120 that is electrically connected to the same power supply (power supply wiring) as the logic circuit 112. Here, the inspection circuit 120 is connected to an input/output terminal 130-2 that is used for input/output (connection) with the outside when inspecting the semiconductor substrate 102. Therefore, it can be said that the inspection circuit 120 has a power supply connection part (not shown) that is electrically connected to the same power supply as the logic circuit 112, and an input/output terminal 130-2. Note that in this embodiment, the power supply connection part (power supply connection terminal) and the input/output terminal 130-2 are different nodes (configurations) in the inspection circuit 120. Note that the input/output terminal 130-2 in this embodiment is described as having both an input terminal and an output terminal, but may have either an input terminal or an output terminal.

Here, there are inspection circuits 120 that perform measurements even after the two semiconductor substrates are bonded together, and those that do not perform measurements after bonding. For example, the inspection circuit 120 that inspects the yield of the vertical signal lines in the pixels and the logic circuit 112 such as the memory does not perform measurements after bonding. In this way, the inspection circuit 120 that does not perform inspection after bonding does not need to be connected to anything other than the same potential (power supply potential) as the logic circuit 112, so there is a high possibility that the potential will change to an unstable state and noise will occur. Therefore, the noise suppression in this embodiment is more effectively exerted. Note that, when the inspection circuit 120 is formed on the semiconductor substrate 101, it may be a circuit that inspects the yield of the pixel circuit 110 and the peripheral circuit 111.

[Circuit configuration of solid-state imaging device]
Next, the circuit configuration of the solid-state imaging device 100 will be described with reference to FIGS.

2A is a schematic circuit diagram of the semiconductor substrate 102 before the two semiconductor substrates are bonded together. As described above, the semiconductor substrate 102 has the logic circuit 112 and the inspection circuit 120. Here, the semiconductor substrate 102 can be operated by applying a potential and an operating pulse for operating the logic circuit 112 and the inspection circuit 120 to pads (not shown) provided on the semiconductor substrate 102. At this time, the inspection circuit 120 (power supply connection portion of the inspection circuit 120) and the logic circuit 112 are connected to the same power supply (wiring), and the potential supplied to the inspection circuit 120 from the power supply (power supply wiring) is the potential VDD3, which is a potential common to the logic circuit 112. Here, after the semiconductor substrate 102 starts operating, the semiconductor substrate 102 can be inspected by contacting the measurement probe 140 with at least one of the input terminal and the output terminal of the input/output terminal 130-2 of the inspection circuit 120. This makes it possible to select whether the semiconductor substrate 102 is good or bad.

Here, when bonding to form the stacked structure is performed on a chip-by-chip basis, defective chips can be eliminated by performing the above-mentioned inspection, and defects after the stacked structure is formed can be prevented in advance. This makes it possible to reduce the cost of forming the solid-state imaging device 100. Also, when bonding is performed on a semiconductor substrate-by-substrate basis, defects after the stacked structure is formed can be prevented in advance by eliminating wafers with an extremely large number of defective chips.

Furthermore, locations where there is a high risk of chip defects on the semiconductor substrate 101 side may be determined based on data from visual inspection of the semiconductor substrate 101 for foreign matter and defects, etc., and in-line data such as film thickness distribution. Furthermore, by bonding together chips determined to be defective on the semiconductor substrate 102 side and chips on the semiconductor substrate 101 side that are highly likely to be defective, it is also possible to reduce the defect rate after the formation of the stacked structure.

2B is a circuit diagram showing the electrical connection of two semiconductor substrates in the solid-state imaging device 100 according to the first embodiment. Here, the potential VDD1 is the potential of the power supply of the pixel circuit 110, and the potential VDD2 is the potential of the power supply of the peripheral circuit 111. At least one of the input terminal and the output terminal of the input/output terminal 130-2 of the inspection circuit 120 is electrically connected to the input/output terminal 130-1 formed on the semiconductor substrate 101 to form the stacked connection section 130. The input of the inspection circuit 120 is electrically connected to the potential (fixed potential) of the semiconductor substrate 101 via the stacked connection section 130. More specifically, in this embodiment, the input (input terminal) of the inspection circuit 120 is electrically connected to a predetermined power supply (power supply wiring) that supplies the potential. Note that the potential of the semiconductor substrate 101 to which the input of the inspection circuit 120 is connected (supplied to the input) can utilize the potential VDD2 of the power supply used in the peripheral circuit 111. At this time, if the potential given to the stacked connection portion 130 is such that the output of the inspection circuit 120 is fixed, the hot carrier injection phenomenon (hot carrier light emission phenomenon) of the inspection circuit 120 can be suppressed. Note that the inspection circuit 120 is not limited to being connected to the power supply potential VDD2 of the peripheral circuit 111 via the stacked connection portion 130, but may be connected to the output potential of the peripheral circuit 111, for example. Also, not limited to the input of the inspection circuit 120, the output (output terminal) of the inspection circuit 120 may be electrically connected to the potential of the semiconductor substrate 101 via the stacked connection portion 130. In other words, it is sufficient that at least one of the input terminal and the output terminal of the input/output terminal 130-2 of the inspection circuit 120 is electrically connected to the potential (fixed potential) of the semiconductor substrate 101.

[Issues and Effects]
Here, the problem to be solved by this embodiment will be described in detail. The potential (power supply potential) supplied to the inspection circuit 120 is common to the logic circuit 112, so when a potential is supplied to drive the logic circuit 112, the potential is also supplied to the inspection circuit 120. Therefore, when the supply starts, the potential of the inspection circuit 120 may change unstably, and the current value flowing through the inspection circuit 120 may not be controlled to a desired value. This may cause a hot carrier light emission phenomenon, and a pseudo signal (noise) may be superimposed on the output signal of the solid-state imaging device 100.

In contrast, in the first embodiment, the input or output of the inspection circuit 120 formed on the semiconductor substrate 102 is further connected to the potential on the semiconductor substrate 101 via the stacked connection portion 130. This allows the potential on the semiconductor substrate 101 to be supplied to the inspection circuit 120, stabilizing the potential of the inspection circuit 120, thereby making it possible to reduce noise caused by the inspection circuit 120 without increasing the number of external connection pads.

Example 2
In the solid-state imaging device according to the first embodiment, the inspection circuit is formed on the same semiconductor substrate as the logic circuit, but in the solid-state imaging device (photoelectric conversion device) according to the present embodiment, the inspection circuit is formed on the same semiconductor substrate as the pixel circuit and the peripheral circuit. A solid-state imaging device 100 according to the second embodiment will be described below with reference to Figures 3, 4(A), 4(B), and 5. Note that the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[Cross-sectional configuration of solid-state imaging device]
3 shows a cross-sectional view of the solid-state imaging device 100. Here, similarly to the first embodiment, the pixel circuit 110 and the peripheral circuit 111 are formed on the semiconductor substrate 101, and the inspection circuit 112 (not shown) is formed on the semiconductor substrate 102. In this embodiment, in addition to the logic circuit 112, the logic circuit 113 is formed on the semiconductor substrate 102. Meanwhile, in the solid-state imaging device 100 according to this embodiment, unlike the first embodiment, the inspection circuit 121 is formed on the semiconductor substrate 101. In addition, the external connection pad 221 is formed on the semiconductor substrate 102, and the external connection pad 221 can be wire-bonded via the TSV 225 formed on the semiconductor substrate 101.

[Circuit configuration of solid-state imaging device]
Next, the circuit configuration of the solid-state imaging device 100 according to this embodiment will be described with reference to FIGS.

FIG. 4A is a circuit diagram showing a schematic diagram of the semiconductor substrate 101 before the two semiconductor substrates are bonded together. The semiconductor substrate 101 has a pixel circuit 110, a peripheral circuit 111, and an inspection circuit 121. Here, the semiconductor substrate 101 can be operated by applying a potential and an operating pulse for operating the pixel circuit 110, the peripheral circuit 111, and the inspection circuit 121 to a pad (not shown) provided on the semiconductor substrate 101 side. At this time, the power supply potential of the pixel circuit 110 is VDD1, and the potential supplied to the inspection circuit 121 is common to the power supply potential VDD2 of the peripheral circuit 111. In other words, the power supply connection part of the inspection circuit 121 is electrically connected to the same power supply (power supply wiring) as the peripheral circuit 111. Here, after the operation of the semiconductor substrate 101 starts, the measurement probe 140 contacts either the input terminal or the output terminal of the input/output terminal 130-1 of the inspection circuit 121, thereby inspecting the semiconductor substrate 101 side.

FIG. 4B is a circuit diagram showing the electrical connection of two semiconductor substrates in the solid-state imaging device 100 according to the second embodiment. At least one of the input terminal and the output terminal of the input/output terminal 130-1 of the inspection circuit 121 is electrically connected to the input/output terminal 130-2 formed on the semiconductor substrate 102 to form the stacked connection section 130. In the second embodiment, the input of the inspection circuit 121 is electrically connected to the potential (fixed potential) of the semiconductor substrate 102 through the stacked connection section 130. For example, the potential VDD4 used by the logic circuit 113 can be used as the potential of the semiconductor substrate 102. In this case, if the potential given to the stacked connection section 130 is such that the output of the inspection circuit 121 is fixed, the AC (alternating current) voltage fluctuation of the inspection circuit 121 can be suppressed. Depending on the layout constraints, etc., the inspection circuit 121 may be configured to be connected to other potentials, such as the potential VDD3 of the power supply of the logic circuit 112.

[effect]
In the second embodiment, the input or output of the inspection circuit 121 present on the same substrate as the pixel circuit 110 is connected to the potential of another substrate via the stacked connection portion 130. This can prevent the inspection circuit 121 from causing a hot carrier light emission phenomenon when the solid-state imaging device 100 starts to operate (when driven), as in the first embodiment, and can prevent a false signal from being superimposed on the output signal of the solid-state imaging device 100. Furthermore, when the inspection circuit 121 is present on the same substrate as the pixel circuit 110, there is a risk that a false signal is superimposed on the output signal of the solid-state imaging device 100 through capacitive coupling due to AC voltage fluctuations of the inspection circuit 121, but this can also be prevented according to this embodiment. In other words, according to this embodiment, it is possible to reduce noise caused by the inspection circuit 121 without increasing the number of external connection pads.

[Method of manufacturing a solid-state imaging device]
A method for manufacturing the solid-state imaging device 100 according to the second embodiment will be described with reference to the flowchart shown in Fig. 5. At the start of this flowchart, two semiconductor substrates that do not have wiring formed of a semiconductor layer (silicon) or the like are prepared.

(S1001: Substrate formation step)
First, the semiconductor substrate 101 and the semiconductor substrate 102 are formed by forming elements, wiring, and an insulating film layer on each of the two semiconductor substrates. Here, the elements refer to, for example, the pixel circuit 110, the peripheral circuit 111, and the inspection circuit 121. The inspection circuit 121 is formed so as to be connected to the same power supply (electric potential; power supply wiring) as the peripheral circuit 111. Note that the method of forming the gate electrodes, element isolation, semiconductor regions, wiring layers, and the like constituting these circuits can be manufactured by a general process, so detailed explanations are omitted. Here, at least one of the input terminal and the output terminal of the input/output terminal 130-1 of the inspection circuit 121 is configured so as to be connected to a power supply (power supply wiring) for supplying a potential in the semiconductor substrate 102 when the two semiconductor substrates are joined in S1003. In other words, the input/output terminal 131-1 of the semiconductor substrate 101 and the input/output terminal 131-2 of the semiconductor substrate 102 are formed at positions such that they are in physical contact with each other when the two semiconductor substrates are stacked. Note that the semiconductor substrate 101 and the semiconductor substrate 102 may be ones that have been prepared in advance. That is, S1001 may be a step of preparing the semiconductor substrate 101 and the semiconductor substrate 102.

(S1002; Inspection step)
Next, as shown in FIG. 4A, the semiconductor substrate 101 is measured (inspected) using the inspection circuit 121 by utilizing the input/output terminal 130-1 formed on the semiconductor substrate 101. For example, the semiconductor substrate 101 is operated by applying a potential (power supply potential) and an operating pulse for driving the pixel circuit 110, the peripheral circuit 111, and the inspection circuit 121 to the semiconductor substrate 101. Thereafter, the circuit characteristics (inspection results) of the pixel circuit 110 can be obtained via the inspection circuit 121 by contacting the measurement probe 140 with at least one of the input terminal and the output terminal of the input/output terminal 130-1. Therefore, it is possible to select whether the semiconductor substrate 101 is good or bad before bonding the two semiconductor substrates together. Here, for example, only when the semiconductor substrate 101 is determined to be "good" in S1002, the processing step is performed at S1003.
may transition to

If necessary, after performing the above measurements, any needle marks that occur on the input/output terminal 130-1 during measurement by the measurement probe 140 may be flattened. For example, the needle marks can be removed by wet etching, dry etching, or CMP.

(S1003; Bonding step)
Thereafter, the semiconductor substrate 101 and the semiconductor substrate 102 are bonded. At this time, the input/output terminal 130-1 of the inspection circuit 121 and the input/output terminal 130-2 formed on the semiconductor substrate 102 are electrically connected to form the stacked connection section 130. As a result, the potential (power supply; power supply wiring) in the semiconductor substrate 102 and the inspection circuit 121 are electrically connected via the stacked connection section 130. Note that in S1001, the formation and inspection of the semiconductor substrate 101 for bonding are completed, so the bonding is not essential, for example. In other words, S1001 to S1002 and S1003 may be performed by different users, and this embodiment can also be applied as a manufacturing method for forming the semiconductor substrate 101 (semiconductor device) at the time when the process of S1002 is completed.

It is preferable that the input/output terminals 130-1 are larger than the needle marks that will be generated on the input/output terminals 130-1. In this way, even if the input/output terminals 130-1 are excessively scraped off in the process of removing the needle marks, making it difficult to establish an electrical connection by bonding them together, it may be possible to ensure connectivity by other methods by expanding the effective area of the input/output terminals.

The above shows an example of a manufacturing method that makes it possible to suppress AC voltage fluctuations in the inspection circuit 121 by connecting the input or output of the inspection circuit 121 to the potential of the semiconductor substrate 102 via the stacked connection portion 130. Note that in Example 1 as well, by forming the semiconductor substrate 102 having the inspection circuit 120, it is possible to manufacture a stacked structure in the same process as the above-mentioned manufacturing method.

Example 3
In the solid-state imaging device of Example 2, one inspection circuit is formed on one semiconductor substrate, but in the solid-state imaging device of the present embodiment, two inspection circuits are formed on one semiconductor substrate.

In such a case, as in the first and second embodiments, if the input or output potentials of the two inspection circuits are not stable when the solid-state imaging device is in operation (driven), this may cause the hot carrier light emission phenomenon, resulting in a false signal being superimposed on the output signal of the solid-state imaging device. In addition, if the two inspection circuits are on the same substrate as the pixel circuit, AC voltage fluctuations in the two inspection circuits may be capacitively coupled, resulting in a false signal being superimposed on the output signal of the solid-state imaging device.

In addition, when there are multiple inspection circuits, applying the configurations of Examples 1 and 2 makes it necessary to connect the inputs and outputs of the inspection circuits to different potentials via separate stacked connection parts. In such cases, there is a possibility that layout constraints and yield losses due to stacked connections may occur.

In this embodiment, therefore, a solid-state imaging device 100 is described in which two enable switches are used to connect two inspection circuits to a potential via one stacked connection section, thereby stabilizing the input/output potentials of the two inspection circuits. Below, the solid-state imaging device 100 according to the third embodiment is described using the circuit diagram of the electrical connections shown in FIG. 6.

In the solid-state imaging device 100 according to this embodiment, in addition to the configuration in the second embodiment, a second inspection circuit, inspection circuit 122, is formed on the semiconductor substrate 101. At this time, the power supply potential of the pixel circuit 110 is VDD1, and the power supply potential of the peripheral circuit 111 is VDD2. Also, the power supply potential of the logic circuit 112 is VDD3, and the power supply potential of the logic circuit 113 is VDD4. In this embodiment, the input/output terminal 131-1 is shared by the inspection circuit 121 and the inspection circuit 122.

Here, in this embodiment, the inspection circuit 121 is supplied with a potential VDD2, and the inspection circuit 122 is supplied with a potential VDD5. The inspection circuits 121 and 122 are electrically connected to the corresponding enable switches 141 and 142, respectively. The gates of the enable switches 141 and 142 are shared and electrically connected to a potential that turns the switches off via the stacked connection portion 131. In other words, it can be said that the gates of the enable switches 141 and 142 are connected to each other. Here, the enable switches 141 and 142 switch between a state in which each inspection circuit is connected to a potential that turns the switch off and a state in which the two are electrically separated (cut off). This allows the inspection circuits 121 and 122 to be connected to a stable potential. For example, the potential VDD4 used by the logic circuit 113 can be used as the potential that turns the switch off.

In addition, the inspection circuits 121 and 122 may be grounded via a high-resistance pull-down resistor so that a floating node is not created in the inspection circuits 121 and 122 when the enable switches 141 and 142 are turned off.

[effect]
According to the third embodiment, when a plurality of inspection circuits are formed, the number of electrical connections to potentials via the stacked connection portion 131 can be reduced by using an enable switch with a shared gate. This makes it possible to reduce the chip area and reduce yield loss due to stacked connections. Also, as in the first and second embodiments, AC voltage fluctuations in the inspection circuits can be suppressed. Therefore, it is possible to reduce noise caused by the inspection circuits without increasing the number of external connection pads.

Example 4
In the solid-state imaging device according to the second embodiment, as shown in Fig. 3, the input/output terminal 130-1 of the inspection circuit 121 of the semiconductor substrate 101 is directly connected to the input/output terminal 130-2 formed on the semiconductor substrate 102. In contrast, in the present embodiment, as shown in Fig. 9, a solid-state imaging device 100 will be described in which a bonding portion 320 is formed on the input/output terminal 130-1 and the semiconductor substrates are connected to each other via the bonding portion 320.

Here, after the inspection, a needle mark is formed on the input/output terminal of the inspection circuit due to contact with the measurement probe. Therefore, if an input/output terminal with a needle mark is used for bonding, the unevenness of the needle mark may reduce the connectivity of the two semiconductor substrates, resulting in a decrease in yield. Therefore, a removal process (flattening process) for removing the needle mark by wet etching or dry etching may be added to suppress the decrease in yield. In this embodiment, by forming (manufacturing) the joint 320, it is possible to suppress the decrease in yield in the solid-state imaging device without adding such a removal process.

[Method of manufacturing a solid-state imaging device]
A method for manufacturing a solid-state imaging device 100 according to the fourth embodiment will be described with reference to the flowchart shown in Fig. 5. Here, the flow chart starts with two semiconductor substrates having no wiring formed of a semiconductor layer (silicon) or the like. Note that the same components as those in the second embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

(S1001: Substrate formation step)
First, elements, wiring, and an insulating film layer are formed on each of the two semiconductor substrates to form the semiconductor substrate 101 and the semiconductor substrate 102. Here, the elements refer to, for example, the pixel circuit 110, the peripheral circuit 111, and the inspection circuit 121. Note that detailed explanations of the methods for forming the gate electrodes, element isolation, semiconductor regions, wiring layers, and the like that constitute these circuits will be omitted because they can be manufactured by general processes.

Figure 10 (A) shows a cross-sectional view of the wiring layer of the semiconductor substrate 101 after completion of S1001. On the surface of the semiconductor substrate 101, an input/output terminal 130-1 is formed from a top metal, and the input/output terminal 130-1 is covered with an oxide film 300.

(S1002; Inspection step)
10B, a part of the oxide film 300 formed on the semiconductor substrate 101 is removed to open the input/output terminal 130-1. A measurement probe 140 (probe needle) is brought into contact with the input/output terminal 130-1, and the semiconductor substrate 101 is measured (inspected) using the inspection circuit 121. At this time, a needle mark 310 is formed on the input/output terminal 130-1 by the contact of the measurement probe 140 (probe needle).

(S1003; Bonding step)
Next, an oxide film is formed and planarized. For example, an oxide film 301 is deposited by CVD (Chemical Vapor Deposition), and then the surface of the oxide film 301 is planarized by CMP (Chemical Mechanical Polishing). This makes it possible to eliminate irregularities in the oxide film 300, as shown in FIG. 11A. Furthermore, the oxide film 301 also penetrates into the needle mark 310 formed in the input/output terminal 130-1, so that the needle mark 310 is also planarized.

Next, the bonding portion 320 is formed. As shown in FIG. 11(B), the bonding portion 320 is formed on the input/output terminal 130-1. The bonding portion 320 is conductive and is, for example, a microbump whose main component is copper. The bonding portion 320 is formed, for example, using a general dual damascene process. At this time, multiple bonding portions 320 may be formed on the input/output terminal 130-1.

Then, the semiconductor substrate 101 and the semiconductor substrate 102 are bonded. For example, as shown in FIG. 11C, the bonding portion 320 is used to bond to a bonding portion 321 similarly formed on the other semiconductor substrate 102. After inspection, a solid-state imaging device having a structure in which the semiconductor substrate 101 and the semiconductor substrate 102 are bonded can be manufactured using the input/output terminal 130-1. As a result, similar to the second embodiment, the inspection circuit 121 is connected to the wiring that supplies the potential in the semiconductor substrate 101 via the bonding portion 320.

The bonding is not limited to bonding between the bonding portions 320, but may be bonding between the bonding portion 320 of the semiconductor substrate 101 and the input/output terminal 130-2 of the semiconductor substrate 102. In addition, in this embodiment, a solid-state imaging device in which the inspection circuit 121 is formed on the semiconductor substrate 101 has been described, but this embodiment can also be applied to a solid-state imaging device in which the inspection circuit 120 is formed on the semiconductor substrate 102.

[effect]
As described above, in the method for manufacturing a solid-state imaging device, it is possible to suppress a decrease in yield without adding a step of removing needle marks. This embodiment is a method for manufacturing a solid-state imaging device that includes a step of forming an oxide film, planarizing, and forming a junction after an inspection step of at least one of the semiconductor substrates. This makes it possible to suppress a decrease in yield due to needle marks during inspection without adding a removal step.

Example 5
In the method for manufacturing a solid-state imaging device according to Example 4, a bond 320 is formed on the input/output terminal 130-1 of the inspection circuit 121 of the semiconductor substrate 101 with which the probe is in contact. In this example, a method for manufacturing a solid-state imaging device 100 is shown in which a bond 322 is formed on the input/output terminal 132 of the inspection circuit 121 with which the probe is not in contact, as shown in Fig. 12. This example also makes it possible to suppress a decrease in yield without adding a step for removing needle marks.

A method for manufacturing a solid-state imaging device 100 according to a fifth embodiment will be described with reference to the flowchart shown in FIG. 5. At the start of this flowchart, two semiconductor substrates that do not have wiring formed of a semiconductor layer (silicon) or the like are prepared.

(S1001: Substrate formation step)
In S1001, similarly to the fourth embodiment, a semiconductor substrate 101 and a semiconductor substrate 102 are formed. Here, a plurality of inspection circuits 121 are formed in the semiconductor substrate 101. In this embodiment, as shown in Fig. 13A, the semiconductor substrate 101 has an input/output terminal 130-1 of the inspection circuit 121 and an input/output terminal 132 of the inspection circuit 121. Note that in the semiconductor substrate 101, the input/output terminal 130-1 and the input/output terminal 132 are electrically connected.

(S1002; Inspection step)
13B, in a manner similar to that of the fourth embodiment, the measurement probe 140 is brought into contact with the input/output terminal 130-1, and the semiconductor substrate 101 is measured (inspected) using the inspection circuit 121. At this time, a needle mark 310 is formed on the input/output terminal 130-1 by the contact of the measurement probe 140.

(S1003; Bonding step)
In step S1003, first, as shown in FIG. 13C, an oxide film is formed and planarized in the same manner as in the fourth embodiment.

Next, as shown in FIG. 14(A), a joint 322 is formed on the input/output terminal 132 electrically connected to the input/output terminal 130-1. Here, the measurement probe 140 is not in contact with the input/output terminal 132. The joint 322 is conductive and is, for example, a microbump whose main component is copper. The joint 322 is formed, for example, using a general dual damascene. Note that multiple joints 322 may be formed on the input/output terminal 132.

Then, the semiconductor substrate 101 and the semiconductor substrate 102 are bonded. For example, as shown in FIG. 14B, the bonding portion 322 is used to bond to the bonding portion 321, which is connected to a power source (power source wiring) not shown in the figure for supplying the potential formed on the other semiconductor substrate 102. This makes it possible to manufacture a solid-state imaging device having a structure in which the input/output terminal 130-1 of the inspection circuit 121 is electrically connected to the potential of the other semiconductor substrate 102 after the inspection is performed.

In the above-mentioned Examples 1 to 5, a photoelectric conversion device formed with a two-layer semiconductor substrate is shown, but the concept of the present invention is not limited to two layers, and can also be applied to a photoelectric conversion device with three or more layers. In this case, the inspection circuit may be formed on any substrate, or may be formed on multiple substrates.

Furthermore, the potential of the input/output of the inspection circuit and the gate of the enable switch can be electrically connected to a predetermined potential via multiple stacked connections. In addition, in the third embodiment, two inspection circuits are illustrated, but this is not limiting, and three or more inspection circuits may be present. In that case, it is sufficient to use a number of enable switches corresponding to the number of inspection circuits.

Example 6
An image pickup system according to a sixth embodiment of the present invention will be described with reference to Fig. 7. Fig. 7 is a block diagram showing a schematic configuration of the image pickup system according to this embodiment.

The solid-state imaging device 100 described in the above embodiments 1 to 5 can be applied to various imaging systems. Applicable imaging systems are not particularly limited, but examples include various devices such as digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, observation satellites, and medical cameras. Camera modules equipped with an optical system such as a lens and an imaging device (photoelectric conversion device) are also included in imaging systems. Figure 7 shows a block diagram of a digital still camera as an example of these.

As shown in FIG. 7, the imaging system 2000 includes a solid-state imaging device 100, an imaging optical system 2002, a CPU 2010, a lens control unit 2012, an imaging device control unit 2014, and an image processing unit 2016. The imaging system 2000 further includes an aperture shutter control unit 2018, a display unit 2020, an operation switch 2022, and a recording medium 2024.

The imaging optical system 2002 is an optical system for forming an optical image of a subject, and includes a lens group, an aperture 2004, etc. The aperture 2004 has a function of adjusting the amount of light during shooting by adjusting its opening diameter, and also functions as a shutter for adjusting the exposure time when shooting still images. The lens group and aperture 2004 are held so that they can move forward and backward along the optical axis, and their linked operation realizes a variable magnification function (zoom function) and a focus adjustment function. The imaging optical system 2002 may be integrated into the imaging system, or may be an imaging lens that can be attached to the imaging system.

The solid-state imaging device 100 is arranged so that its imaging surface is located in the image space of the imaging optical system 2002. The solid-state imaging device 100 is the solid-state imaging device described in Examples 1 to 5, and is configured to include a CMOS sensor (pixel section) and its peripheral circuit (peripheral circuit area). The solid-state imaging device 100 has pixels having multiple photoelectric conversion sections arranged two-dimensionally, and color filters are arranged for these pixels to form a two-dimensional single-plate color sensor. The solid-state imaging device 100 photoelectrically converts the subject image formed by the imaging optical system 2002, and outputs it as an image signal or a focus detection signal.

The lens control unit 2012 controls the forward and backward movement of the lens group of the imaging optical system 2002 to perform variable magnification operations and focus adjustment, and is composed of circuits and processing devices configured to realize this function. The aperture shutter control unit 2018 adjusts the amount of light for shooting by changing the aperture diameter of the aperture 2004 (variable aperture value), and is composed of circuits and processing devices configured to realize this function.

The CPU 2010 is a control device within the camera that handles various controls of the camera body, and includes an arithmetic unit, a ROM, a RAM, an A/D converter, a D/A converter, a communication interface circuit, etc. The CPU 2010 controls the operation of each unit within the camera in accordance with a computer program stored in the ROM or the like, and executes a series of photographing operations such as AF, imaging, image processing, recording, etc., including detection of the focus state of the imaging optical system 2002 (focus detection). The CPU 2010 also functions as a signal processing unit (signal processing device).

The imaging device control unit 2014 controls the operation of the solid-state imaging device 100, and A/D converts signals output from the solid-state imaging device 100 and transmits them to the CPU 2010. The imaging device control unit 2014 is configured to realize these functions by circuits and control devices. The solid-state imaging device 100 may have the A/D conversion function. The image processing unit 2016 is a processing device that performs image processing such as gamma conversion and color interpolation on the A/D converted signal to generate an image signal, and is configured to realize these functions by circuits and control devices. The display unit 2020 is a display device such as a liquid crystal display device (LCD), and displays information about the camera's shooting mode, a preview image before shooting, a confirmation image after shooting, a focus state during focus detection, and the like. The operation switch 2022 is configured by a power switch, a release (shooting trigger) switch, a zoom operation switch, a shooting mode selection switch, and the like. The recording medium 2024 is for recording shot images, and may be built into the imaging system or may be a removable device such as a memory card.

In this way, by configuring the imaging system 2000 to which the solid-state imaging device 100 according to the first to fifth embodiments is applied, a high-performance imaging system can be realized.

Example 7
An imaging system and a moving object according to a seventh embodiment of the present invention will be described with reference to Fig. 8(A) and Fig. 8(B). Fig. 8(A) and Fig. 8(B) are diagrams showing the configurations of the imaging system and the moving object according to this embodiment.

Figure 8 (A) shows an example of an imaging system 2100 related to an in-vehicle camera. The imaging system 2100 has an imaging device 2110. The imaging device 2110 is any one of the solid-state imaging devices described in the above-mentioned embodiments 1 to 5. The imaging system 2100 has an image processing unit 2112, which is a processing device that performs image processing on multiple image data acquired by the imaging device 2110. Furthermore, the imaging system 2100 has a parallax acquisition unit 2114, which is a processing device that calculates parallax (phase difference of parallax images) from multiple image data acquired by the imaging device 2110. The imaging system 2100 also has a distance acquisition unit 2116, which is a processing device that calculates the distance to an object based on the calculated parallax, and a collision determination unit 2118, which is a processing device that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 2114 and the distance acquisition unit 2116 are examples of information acquisition means that acquire information such as distance information to an object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 2118 may determine the possibility of a collision using any of these pieces of distance information. The above-mentioned processing device may be realized by dedicated hardware, or may be realized by general-purpose hardware that performs calculations based on software modules. The processing device may also be realized by a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or the like. The processing device may also be realized by a combination of these.

The imaging system 2100 is connected to a vehicle information acquisition device 2120, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 2100 is also connected to a control ECU 2130, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 2118. That is, the control ECU 2130 is an example of a mobile body control means that controls a mobile body based on distance information. The imaging system 2100 is also connected to an alarm device 2140 that issues an alarm to the driver based on the judgment result of the collision judgment unit 2118. For example, when the judgment result of the collision judgment unit 2118 indicates that there is a high possibility of a collision, the control ECU 2130 applies the brakes, releases the accelerator, suppresses the engine output, and performs vehicle control to avoid the collision and reduce damage. The alarm device 2140 issues an alarm to the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

In this embodiment, the surroundings of the vehicle, for example the front or rear, are imaged by the imaging system 2100. FIG. 8(B) shows the imaging system 2100 when imaging the area in front of the vehicle (imaging range 2150). The vehicle information acquisition device 2120 sends an instruction to operate the imaging system 2100 to perform imaging. By using the solid-state imaging device 100 according to the above-described embodiments 1 to 5 as the imaging device 2110, the imaging system 2100 of this embodiment can further improve the accuracy of distance measurement.

In the above explanation, an example of control to avoid collision with other vehicles was described, but the system can also be applied to automatic driving control to follow other vehicles, automatic driving control to avoid going out of lanes, etc. Furthermore, the imaging system is not limited to vehicles such as automobiles, but can be applied to moving bodies (transportation equipment) such as ships, aircraft, and industrial robots. The moving devices in moving bodies (transportation equipment) are various types of drive sources such as engines, motors, wheels, and propellers. In addition, the system can be applied not only to moving bodies, but also to a wide range of equipment that uses object recognition, such as intelligent transport systems (ITS).

Other Examples
The configurations and processes described in the above-described embodiments and modifications of the present invention can be used in any combination.

100: solid-state imaging device, 101: semiconductor substrate, 102: semiconductor substrate 101: pixel circuit, 112: logic circuit, 120: inspection circuit, 130: stacked connection portion

Claims (17)

A first substrate having pixel circuits including photoelectric conversion elements;
A second substrate having a signal processing circuit that drives the pixel circuit or processes a signal from the pixel circuit;
a connection portion that electrically connects the first substrate and the second substrate;
A test circuit;
having
the inspection circuit is formed on one of the first substrate and the second substrate, and a wiring for supplying a first potential on the one substrate is connected to a power supply connection terminal of the inspection circuit;
a second potential is supplied to at least one of an input terminal and an output terminal of the inspection circuit, the input terminal and the output terminal being different from the power supply connection terminal;
The connection portion is connected to at least one of the input terminal and the output terminal.
A photoelectric conversion device comprising: The inspection circuit is a circuit for inspecting the pixel circuit or the signal processing circuit.
2. The photoelectric conversion device according to claim 1. the inspection circuit is connected to a power supply wiring common to a circuit other than the inspection circuit on the one of the substrates on which the inspection circuit is formed, thereby supplying the first potential;
3. The photoelectric conversion device according to claim 1 or 2. the inspection circuit is connected to a power supply wiring common to a circuit in one of the first substrate and the second substrate on which the inspection circuit is not provided, via the connection portion, so that the second potential is supplied thereto;
4. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction. the first substrate has a peripheral circuit separate from the pixel circuit,
the inspection circuit is formed on the second substrate,
the inspection circuit is connected to a power supply wiring common to the signal processing circuit, and thereby the first potential is supplied to the inspection circuit; and the inspection circuit is connected to a power supply wiring common to the peripheral circuit, via the connection portion, and thereby the second potential is supplied to the inspection circuit.
5. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction. the first substrate has a peripheral circuit separate from the pixel circuit,
the inspection circuit is formed on the first substrate,
the inspection circuit is connected to a power supply wiring common to the peripheral circuit, and thereby the first potential is supplied to the inspection circuit; and the inspection circuit is connected to a power supply wiring common to the signal processing circuit, via the connection portion, and thereby the second potential is supplied to the inspection circuit.
5. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction. a second connection portion that electrically connects the pixel circuit of the first substrate and the signal processing circuit of the second substrate;
7. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction. The photoelectric conversion device according to any one of claims 1 to 7 ,
a signal processing device for processing a signal output from the photoelectric conversion device;
An imaging system comprising: A mobile object,
The photoelectric conversion device according to any one of claims 1 to 7 ,
A mobile device;
a processing device that acquires information from a signal output from the photoelectric conversion device;
a control device that controls the moving device based on the information;
A moving object comprising: providing a first substrate having pixel circuits including photoelectric conversion elements;
providing a second substrate having a signal processing circuit for driving the pixel circuit or for processing a signal from the pixel circuit;
a bonding step of forming a connection portion that electrically connects the first substrate and the second substrate,
one of the first substrate and the second substrate includes an inspection circuit having a power supply connection terminal connected to a wiring for supplying a first potential in the one substrate;
The joining step includes:
forming the connection portion using an input terminal or an output terminal of the inspection circuit other than the power supply connection terminal;
connecting the input terminal or the output terminal of the inspection circuit to a wiring for supplying a second potential;
Including,
A method for producing a photoelectric conversion device comprising the steps of: an inspection step of inspecting the one substrate on which the inspection circuit is formed, before the bonding step;
The inspection step includes a step of contacting a probe with the input terminal or the output terminal of the inspection circuit.
The method for producing a photoelectric conversion device according to claim 10 . 1. A method for manufacturing a semiconductor device having a second substrate for bonding to a first substrate, comprising the steps of:
forming a second substrate having a second circuit for driving a first circuit disposed on the first substrate or for processing a signal from the first circuit, and a test circuit for testing the second circuit;
an inspection step of inspecting the second circuit by contacting a probe with at least one of an input terminal and an output terminal of the inspection circuit;
having
In the forming step, at least one of an input terminal and an output terminal of the inspection circuit is configured to be connected to a wiring for supplying a predetermined potential on the first substrate.
4. A method for manufacturing a semiconductor device comprising the steps of: The method further includes a bonding step of connecting at least one of the input terminal and the output terminal of the inspection circuit to a wiring for supplying a predetermined potential in the first substrate after the inspection step.
13. The method for manufacturing a semiconductor device according to claim 12 . providing a first substrate having pixel circuits including photoelectric conversion elements;
providing a second substrate having a signal processing circuit for driving the pixel circuit or for processing a signal from the pixel circuit;
supplying a first potential from one of the first and second substrates to a power supply connection terminal of an inspection circuit formed on the one substrate;
an inspection step of contacting a probe with at least one of an input terminal and an output terminal of the inspection circuit, the input terminal and the output terminal being different from the power supply connection terminal;
a bonding step of electrically connecting at least one of the input terminal and the output terminal to a wiring for supplying a second potential by bonding the first substrate and the second substrate with a bonding portion;
having
The joining step includes:
a step of forming an oxide film on the one substrate on which the inspection circuit is formed and planarizing the oxide film after the probe is brought into contact in the inspection step;
forming the joint at a terminal of the inspection circuit with which the probe is in contact;
Including,
A method for producing a photoelectric conversion device comprising the steps of: providing a first substrate having pixel circuits including photoelectric conversion elements;
providing a second substrate having a signal processing circuit for driving the pixel circuit or for processing a signal from the pixel circuit;
supplying a first potential from one of the first and second substrates to each of power supply connection terminals of a plurality of inspection circuits formed on the one substrate;
an inspection step of contacting a probe with at least one of an input terminal and an output terminal, which is different from the power supply connection terminal, of a first inspection circuit among the plurality of inspection circuits;
a joining step of electrically connecting at least one of the input terminal and the output terminal to a wiring for supplying a second potential by joining the first substrate and the second substrate with a joint portion;
having
The joining step includes:
a step of forming an oxide film on the one substrate on which the plurality of inspection circuits are formed and planarizing the oxide film after the probe is brought into contact in the inspection step;
forming the joint on a terminal of a second inspection circuit that is not in contact with the probe among the plurality of inspection circuits;
Including,
the first inspection circuit and the second inspection circuit are electrically connected to one of the substrates on which the plurality of inspection circuits are formed.
A method for producing a photoelectric conversion device comprising the steps of: providing a first substrate having pixel circuits including photoelectric conversion elements;
providing a second substrate having a signal processing circuit for driving the pixel circuit or for processing a signal from the pixel circuit;
supplying a first potential from one of the first and second substrates to a power supply connection terminal of an inspection circuit formed on the one substrate;
an inspection step of contacting a probe with at least one of a first input terminal and a first output terminal of the inspection circuit, the inspection circuit including a plurality of terminals different from the power supply connection terminals that are connected to each other;
a joining step of electrically connecting at least one of the first input terminal and the first output terminal to a wiring for supplying a second potential by joining the first substrate and the second substrate with a joint portion;
having
The joining step includes:
forming an oxide film on one of the first substrate and the second substrate after a probe is brought into contact with at least one of the first input terminal and the first output terminal in the inspection step;
planarizing the oxide film ;
forming the joints at a second input terminal different from the first input terminal and at a second output terminal different from the first output terminal of the plurality of terminals of the inspection circuit;
Including,
A method for producing a photoelectric conversion device comprising the steps of: the second input terminal and the second output terminal are not in contact with the probe at least during the inspection step;
The method for producing a photoelectric conversion device according to claim 16 .

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