JP7556201B2 - Communication device and multi-layer board - Google Patents

Description

The present invention relates to a communication device and a multi-layer board, for example, a small multi-function board that mounts multiple chips, such as bare chips for high-frequency analog and silicon photo chips for optical communication, on a printed circuit board.

In conventional high-frequency transmission boards, it was common to construct high-speed transmission paths with a layout on the surface of the board only. Furthermore, by improving the accuracy of through-hole models and improving the through-holes themselves (back drilling, etc.), it has become possible to use through-holes even for high-speed transmission. For example, it is possible to mount daughter boards equipped with multiple IC chips and different functions, such as multi-chip packages and multi-chip modules, on a mother board. In particular, Patent Documents 1, 2, and 3 disclose boards with half-through holes on the side.

JP 2008-034672 A (Abstract, Figure 2) JP 2014-229722 A (FIG. 1(b)) JP-A-10-229142 (FIG. 2)

The half through holes described in Patent Documents 1, 2, and 3 have limitations on the thickness of the core material and the precision of wiring fabrication. This causes problems such as signal reflection due to mismatch in characteristic impedance, reducing high-frequency characteristics.

The present invention was made to solve these problems, and aims to provide a communication device and a multilayer board that can improve high-frequency characteristics.

In order to achieve the above object, the present invention provides a communication device (200) having a daughter board (100) on which a high frequency device (3) is mounted and a mother board (7) on which one or more daughter boards are mounted, the daughter board has a first through hole (side wall portion 1b, signal line through hole) that connects its front surface (11) and back surface (6a), the intermediate layers (21, 22, 23, 24) constituting a ground electrode of the daughter board have equal intervals between their end faces (21a, 22a, 23a, 24a) and the first through hole, the first through hole is a half through hole connected to a signal line and formed in a semicircular notch shape at an end of the daughter board, the planar shape of the end face is a straight line parallel to the end of the daughter board, and the end faces are connected by second through holes. Here, the intermediate layers constituting the ground electrode of the daughter board may have end faces in the vicinity of the first through hole aligned in the thickness direction. It should be noted that the symbols and letters in parentheses are symbols and the like given in the embodiments and do not limit the present invention.

The present invention can improve high-frequency characteristics.

1 is an overall configuration diagram of a communication device according to a first embodiment of the present invention; 2 is a partial cross-sectional view of a daughter board of a communication device according to a first embodiment of the present invention; FIG. FIG. 2 is a rear view of the daughter board of the communication device according to the first embodiment of the present invention. FIG. 2 is an external view of a half through hole. FIG. 6 is a partial cross-sectional view of a daughter board of a communication device according to a second embodiment of the present invention. FIG. 11 is a rear view of a daughter board of a communication device according to a second embodiment of the present invention. 11 is a partial cross-sectional view of a daughter board of a communication device according to a third and fourth embodiment of the present invention. FIG. FIG. 13 is a rear view of a daughter board of a communication device according to a third embodiment of the present invention. FIG. 13 is a rear view of a daughter board of a communication device according to a fourth embodiment of the present invention. 13A and 13B are diagrams illustrating electric field distributions on a daughter board of communication devices according to third and fourth embodiments of the present invention.

Below, an embodiment of the present invention (hereinafter referred to as "embodiment") will be described in detail with reference to the drawings. Note that each figure is merely a schematic illustration to allow a sufficient understanding of the present invention. In addition, in each figure, common or similar components are given the same reference numerals, and duplicate explanations thereof will be omitted.

First Embodiment
FIG. 1 is a diagram showing the overall configuration of a communication device according to a first embodiment of the present invention.
Communication device 200 is a high-frequency analog communication device including daughter board 100 having bare chip 3 for high-frequency analog communication mounted thereon, and mother board 7 on which daughter board 100 is mounted. Bare chip 3 may be a Si photochip having light receiving elements and light emitting elements for optical communication mounted thereon as high-frequency devices. In this case, communication device 200 is configured as an optical communication device.

The mother board 7 is formed with, for example, a ground 6b and a transmission line 5b. The ground 6b is formed with a joint 4 for joining the daughter board 100. The daughter board 100 is formed with, for example, a ground 6a and a transmission line 5a. At the end of the ground 6a, a plurality of half-through holes 1 and a plurality of through holes 2 arranged near each half-through hole 1 are formed. The half-through holes 1 are used for electrical connection between the daughter board 100 and the mother board 7. The ground 6a and the transmission line 5a are electrically connected to the bare chip 3 by wires.

Fig. 2 is a partial cross-sectional view of the daughter board of the communication device according to the first embodiment of the present invention, Fig. 3 is a rear view thereof, and Fig. 4 is an external view of a half through hole.
The daughter board 100 is a multi-layer board (e.g., a six-layer board) in which multiple layers (e.g., three layers) of core material 8, multiple layers (e.g., two layers) of prepreg 9, intermediate layers 21, 22, 23, and 24 interposed therebetween, and outer layers 20 and 25 are laminated. The outer layers 20 and 25 are plated and function as a ground 6a, a signal line 11, etc. The intermediate layers 21, 22, 23, and 24 are generally used as low-speed transmission lines, DC lines, and ground layers as appropriate.

The intermediate layers 21, 22, 23, 24 and the outer layers 20, 25 are metallic layers made of copper (Cu), and the core material 8 and prepreg 9 are dielectrics. The thickness of the intermediate layers 21, 22, 23, 24 is generally about 18 μm, but may be as much as 35 μm depending on the substrate used. The thickness of the core material 8 and prepreg 9 also conforms to that of the substrate used. Generally, the more layers in the substrate used, the thinner the core material 8 and prepreg 9 will be, at around 0.1 to 0.2 mm, but if the total thickness of the substrate is important, the intermediate layers may be thicker.

The child board 100 has a half through hole 1 and a through hole 2 arranged near the half through hole 1. In addition, through holes 2c, 2c are formed on both sides of the through hole 2. In other words, the child board 100 has a half through hole 1 and a plurality of through holes 2 arranged in a lattice pattern near the half through hole 1.

The half through hole 1 is composed of an arc portion 1a and a side wall portion 1b. The arc portion 1a is formed in a semicircular notch shape, and is a band-shaped arc with an inner radius (hole diameter r1) and an outer radius (land diameter r2) (r2>r1). The side wall portion 1b is a semicircular eaves gutter shape in cross section of the hole diameter r1. The half through hole 1 is formed by joining the inner diameter side of the arc portion 1a and the side wall portion 1b. The half through hole 1 can be made by forming a V-groove on the front and back sides of a through hole made in a substrate, and then cleaving it.

The adjacent through holes 2c, 2, 2c are inner through holes having a side wall portion 2a and a bottom surface portion 2b. The side wall portion 2a electrically connects the intermediate layers 21, 22, 23 to the outer layer 20, and the bottom surface portion 2b is bonded to the surface of the intermediate layer 23. The side wall portion 1b of the half through hole 1 and the side wall portion 2a of the through hole 2 face each other in the vicinity.

The outer layer 20 is plated and functions as the ground 6a. Therefore, the multiple through holes 2c, 2, 2c are maintained at ground potential and each functions as a linear ground. The multiple through holes 2c, 2, 2c arranged in a lattice form function as a virtual ground surface as a whole. The side wall portion 1b of the half through hole 1 and the virtual ground surface approximately form a microstrip line.

The intermediate layers 21, 22, and 23 are electrically connected at the side wall 2a. The end faces 21a, 22a, and 23a of the intermediate layers 21, 22, and 23 are located in the same plane. In other words, the positions of the end faces 21a, 22a, and 23a are the same in the thickness direction of the daughter board 100. This plane is used as a virtual ground plane 29, and a microstrip line is formed between the side wall 1b of the half through hole 1.

Therefore, the line in sidewall portion 1b (the line of signal line 11) is maintained at a predetermined characteristic impedance. This improves the high-frequency characteristics in the Z direction until the signal of signal line 11 reaches mother board 7 (FIG. 1). Therefore, half through hole 1 is suitable as a through hole for a signal line.

Second Embodiment
Although the daughter board 100 of the first embodiment has the through holes 2c, 2, 2c arranged in a lattice pattern, this may be replaced by a rectangular parallelepiped cavity structure.

FIG. 5 is a partial cross-sectional view of a daughter board for a communication device according to a second embodiment of the present invention, and FIG. 6 is a rear view of the daughter board.
Like the daughter board 100 of the first embodiment, the daughter board 101 is mounted on the mother board 7 (FIG. 1). Like the daughter board 100, the daughter board 101 has a half through hole 1 formed therein, but differs from the daughter board 100 in that a cavity structure 41 (side wall surface 41a, bottom surface 41b) is formed near the half through hole 1. The cavity structure 41 is formed by subjecting the side wall of a rectangular parallelepiped opening to electrical continuity.

The cavity structure 41 is electrically connected to the outer layer 20 and multiple intermediate layers 21, 22, and 23 by plating in a rectangular shape in a plan view, and is maintained at ground potential. As a result, the side wall portion 1b of the half through hole 1 forms a complete microstrip line with the side wall surface 41a of the cavity structure 41. Therefore, the line of the side wall portion 1b (the line of the signal line 11) is maintained at a predetermined characteristic impedance. This improves the high-frequency characteristics until the signal of the signal line 11 reaches the mother board 7 (Figure 1). In addition, since a complete microstrip line is formed, it is easy to control the characteristic impedance. In addition, the distance d between the outer diameter side of the arc portion 1a of the half through hole 1 and the side wall surface 41a can be made large, improving ease of manufacture.

In addition, in the child board 101, like the child board 100, the end faces 21a, 22a, and 23a of the multiple intermediate layers 21, 22, and 23 are located in the same plane. This plane is used as a virtual ground plane 29, and a microstrip line is formed between the side wall portion 1b of the half through hole 1. Here, the shorter the distance between the end faces 21a, 22a, and 23a and the side wall surface 41a of the cavity structure 41, the better.

Third Embodiment
In the first embodiment, a plurality of through holes 2c, 2, 2c are arranged in a lattice pattern, and in the second embodiment, a cavity structure 41 (side wall surface 41a, bottom surface 41b) is formed, but it is also acceptable to simply arrange the end surfaces 21a, 22a, 23a of a plurality of intermediate layers 21, 22, 23 in the same plane.

FIG. 7 is a partial cross-sectional view of a daughter board of a communication device according to third and fourth embodiments of the present invention, and FIG. 8 is a rear view of the daughter board.
Substrate 102 is mounted on mother substrate 7, similar to substrate 100 (FIG. 1) of the first embodiment. Substrate 102 has half through-hole 1 formed therein, which is composed of arc portion 1a and side wall portion 1b. Multiple intermediate layers 21, 22, 23, and 24 are maintained at ground potential by through-holes (inner through-holes) not shown.

The end faces 21a, 22a, 23a, and 24a of the multiple intermediate layers 21, 22, 23, and 24 are located in the same plane and form a virtual ground plane 29. The distance between the side wall portion 1b of the half through hole 1 and the end faces 21a, 22a, 23a, and 24a is a distance d at the shortest point. The end face 20a of the outer layer 20 is not necessarily located in the same plane as the end faces 21a, 22a, 23a, and 24a, but it does not matter if they are located in the same plane.

This also allows the side wall 1b of the half through hole 1 to form a microstrip line together with the virtual ground plane 29. Therefore, the line of the side wall 1b (the line of the signal line 11) is maintained at a predetermined characteristic impedance. This reduces reflection of the signal of the signal line 11 until it reaches the mother board 7 (FIG. 1).

Fourth Embodiment
In the third embodiment, the end faces 21a, 22a, 23a, and 24a of the multiple intermediate layers 21, 22, 23, and 24 are located in the same plane, but they may be curved surfaces as long as the distance d to the side wall portion 1b of the half through hole 1 is consistent.

Figure 9 is a rear view of a daughter board of a communication device according to a fourth embodiment of the present invention. Note that the partial cross-sectional view is the same as that of Figure 7.

The daughter board 103 is mounted on the mother board 7, similar to the daughter boards 100, 101, and 102 of the above-mentioned embodiments. The daughter board 103 has a half through hole 1 formed with an arc portion 1a and a side wall portion 1b. The intermediate layers 21, 22, 23, and 24 are maintained at ground potential by through holes (inner through holes) not shown. The distance between the end faces 21a, 22a, 23a, and 24a of the intermediate layers 21, 22, 23, and 24 and the side wall portion 1b of the half through hole 1 is maintained at a distance d. In other words, the end faces 21a, 22a, 23a, and 24a are arc-shaped, and the radius (land diameter r3) is r3 ≒ (r1 + d) when the hole diameter of the side wall portion 1b is r1. In addition, end faces 21a, 22a, 23a, and 24a are located within a curved surface that is semicircular in cross section and forms a virtual ground surface 29 (Figure 7).

FIG. 10 is a diagram showing the electric field distribution on the daughter board of the communication device according to the third and fourth embodiments of the present invention.
The daughter boards 102 and 103 are formed with a half through hole 1 having an arc portion 1a and a side wall portion 1b, outer layers 20 and 25, and intermediate layers 21, 22, 23 and 24. The intermediate layers 21, 22, 23 and 24 are maintained at ground potential, and a high frequency voltage is applied or generated to the half through hole 1.

Except for the vicinity of the end face 24a, between the outer layer 25 and the intermediate layer 24, the electric field lines leave the outer layer 25 at equal intervals and reach the intermediate layer 24 while remaining parallel. In other words, the electric field is uniform between the outer layer 25 and the intermediate layer 24 in the signal transmission direction. In other words, the signal line 11 and the intermediate layer 24 form an almost complete microstrip line, except for the vicinity of the end face 24a.

On the other hand, the electric field lines coming out at equal intervals from the side wall portion 1b, which is at an equipotential, head toward the end faces 21a, 22a, 23a, and 24a of the multiple intermediate layers 21, 22, 23, and 24. In the vicinity of the multiple end faces 21a, 22a, 23a, and 24a, the density of the electric field lines is high and the electric field is strong. However, since there are multiple end faces 21a, 22a, 23a, and 24a, the inclination of the electric field lines is small. In other words, in the signal transmission direction (Z direction), the electric field is almost uniform in the vicinity of the side wall portion 1b. Therefore, the side wall portion 1b of the half through hole 1 forms an approximate microstrip line together with the virtual ground plane 29 formed by the multiple end faces 21a, 22a, 23a, and 24a.

However, in reality, since the ground is not flat, the characteristic impedance transitions to a higher impedance side than the theoretical value with respect to the distance d. In high-density, highly multi-layer boards, it approaches the theoretical value. The characteristic impedance varies depending on the layer structure (configuration, number of layers, and base material), but it is possible to match it empirically. In other words, by using a virtual ground plane 29, the characteristic impedance can be easily matched in the third embodiment (Figure 8), and a value close to the theoretical value can be obtained by the fourth embodiment (Figure 9).

(Modification)
The present invention is not limited to the above-described embodiment, and various modifications are possible, for example, as follows.
(1) In the child board 100 of the first embodiment, the through hole 2 is formed near the half through hole 1, but two through holes may be provided on either side. In this case, it is possible to form a virtual ground plane without providing through holes 2c, 2c on either side of the through hole 2. Also, although the through hole 2 in the first embodiment is hollow, it may be filled with plating or the like.

(2) In the second embodiment, a rectangular recess is formed in the substrate, and the cavity structure 41 is formed by plating, but a structure in which a metal block is inserted in the same position is also possible. The cavity structure 41 is rectangular, but it may be curved (see FIG. 9).

1 Half through hole (first through hole, through hole for signal line)
2, 2c Through hole (second through hole)
3. Bare chip (high frequency device)
7 Mother substrate 20, 25 Outer layer 21, 22, 23, 24 Intermediate layer (ground electrode)
20a, 21a, 22a, 23a, 24a End face 28 Planar space 29 Ground surface 31 Inner through hole 41 Cavity structure 100, 101, 102, 103 Substrate (laminated substrate)
200 Communication device

Claims (8)

A communication device having a daughter board on which a high-frequency device is mounted and a mother board on which one or more of the daughter boards are mounted,
the daughter board has a first through hole that electrically connects its front surface to its back surface,
the intermediate layers constituting the ground electrode of the child board have end faces spaced equally from the first through holes;
the first through hole is a half through hole connected to a signal line and formed in an end portion of the daughter board in a semicircular notch shape,
the end surface has a planar shape that is a straight line parallel to an end of the child board,
The end faces are connected to each other by second through holes.
A communication device comprising: 2. The communication device according to claim 1, wherein the high-frequency device is one or both of a light receiving element for optical communication and a light emitting element for optical communication. 2. The communication device according to claim 1 ,
A communication device, characterized in that the multiple end faces are connected by a metal wall surface. 4. The communication device according to claim 3 ,
The communication device, wherein the metal wall surface has a cavity structure that is rectangular in a plan view. 2. The communication device according to claim 1 ,
A communication device, characterized in that the end face has a planar shape that is a semicircle whose distance from the central axis of the semicircle is longer than the radius of the half through hole. 6. The communication device according to claim 5 ,
A communication device, characterized in that the multiple end faces are connected by a metal wall surface. A communication device having a daughter board on which a high-frequency device is mounted and a mother board on which one or more of the daughter boards are mounted,
the daughter board has a first through hole that electrically connects its front surface to its back surface,
the intermediate layers constituting the ground electrodes of the child board have end faces in the vicinity of the first through holes aligned in a thickness direction;
the first through hole is a half through hole connected to a signal line and formed in an end portion of the daughter board in a semicircular notch shape,
the end surface has a planar shape that is a straight line parallel to an end of the child board,
The end faces are connected to each other by second through holes.
A communication device comprising: A multilayer substrate having an outer layer and a plurality of intermediate layers and carrying a high-frequency device,
A through hole for a signal line is provided to electrically connect the front surface and the back surface,
the intermediate layers constituting the ground electrode have end faces spaced equally from the signal line through holes, and end faces of the intermediate layers in the vicinity of the signal line through holes are aligned in a thickness direction;
the signal line through hole is a half through hole connected to a signal line and having a semicircular notch at one end,
The end surface has a planar shape that is a straight line parallel to the end portion,
The end faces are connected to each other by second through holes.
A multilayer substrate comprising:

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