JP7558424B2 - Semiconductor integrated circuit device - Google Patents

Description

The present disclosure relates to a semiconductor integrated circuit device.

In ICs (Integrated Circuits), such as semiconductor integrated circuits, checking whether the correct voltage is being output from the analog circuit to the internal node is an important element in detecting faults. The simplest way to do this is to provide an external terminal for monitoring voltage, and connect the internal node to be measured to this external terminal, thereby measuring the voltage of the internal node via the external terminal. In this case, by connecting the external terminal to multiple internal nodes in sequence, the external terminal can be shared to measure the voltages of multiple internal nodes.

As ICs become larger, the number of internal nodes whose voltages need to be checked increases, and so does the test time required to check the voltages of the internal nodes. As a technique for making such tests more efficient, Japanese Patent Application Laid-Open No. 2006-234577 (Patent Document 1) describes a configuration in which a voltage comparator is provided inside an IC to determine whether the DC voltage of a specific circuit node of an analog integrated circuit is within a certain range and the result of this determination is output outside the IC.

JP 2006-234577 A

In Patent Document 1, when there are a large number of internal nodes to be measured, a configuration in which a changeover switch (selection circuit) is placed between multiple internal nodes and the voltage comparator, and the voltage comparator is shared by multiple internal nodes, is required in terms of chip size.

However, in this configuration, when the internal node connected to the voltage comparator is switched by the changeover switch, it takes time for the input voltage to the voltage comparator to settle in order to obtain an accurate judgment result. As a result, there is a concern that the test time will be longer if there are many objects to be measured.

In addition, because the standard value, i.e., the voltage range that should be judged as normal, differs for each internal node, it becomes necessary to switch the reference voltage that is compared with the voltage of the internal node on the voltage comparator side. As a result, there are concerns that the circuit size will increase due to the addition of a configuration for switching the reference voltage, and that the test time will be further extended because a settling time is required for switching the reference voltage.

This disclosure has been made to solve these problems, and the purpose of this disclosure is to speed up the determination of whether the voltage of an internal node of a semiconductor integrated circuit device is normal using a simple circuit configuration.

In one aspect of the present disclosure, a semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a plurality of voltage-current conversion circuits, a reference current source, and a current comparator. Each voltage-current conversion circuit performs voltage-to-current conversion on a measurement voltage according to a first conversion gain, the measurement voltage being in accordance with the voltage of at least one measurement node inside the semiconductor integrated circuit device, to generate at least one output current. The reference current source outputs a predetermined reference current. The current comparator outputs at least one determination signal in accordance with a comparison result between the reference current and each of at least one output current input from a voltage-to-current conversion circuit selected from the plurality of voltage-to-current conversion circuits.

According to the present disclosure, the measured voltage can be compared with a judgment voltage by using a current comparator to compare the output current obtained by voltage-current conversion of the measured voltage with a reference current, and when switching between multiple voltage-current converters, the time required for the output current input to the current comparator to settle can be shortened. As a result, the normality judgment of the voltage of an internal node of a semiconductor integrated circuit device can be accelerated with a simple circuit configuration.

1 is a block diagram showing a configuration of a semiconductor integrated circuit device according to a first embodiment; FIG. 2 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 1 . FIG. 2 is a circuit diagram for explaining an internal configuration of each block shown in FIG. 1 according to a first modification of the first embodiment. 1 is a circuit diagram illustrating a configuration of a voltage-current conversion circuit according to a first modification of the first embodiment. FIG. FIG. 11 is a circuit diagram illustrating a configuration of a reference current source according to a first modification of the first embodiment. FIG. 11 is a block diagram showing a configuration of a semiconductor integrated circuit device according to a second embodiment. FIG. 7 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 6. FIG. 11 is a block diagram showing a configuration of a semiconductor integrated circuit device according to a third embodiment. FIG. 9 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 8 . FIG. 13 is a block diagram showing a configuration of a semiconductor integrated circuit device according to a fourth embodiment. FIG. 11 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 10 . FIG. 13 is a block diagram showing a configuration of a semiconductor integrated circuit device according to a fifth embodiment. FIG. 13 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 12 . FIG. 13 is a block diagram showing a configuration of a semiconductor integrated circuit device according to a sixth embodiment. FIG. 15 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 14. FIG. 23 is a signal waveform diagram for explaining the operation of a semiconductor integrated circuit device according to a sixth embodiment. 11 is a table illustrating the operation of the abnormality detection configuration with respect to the determination results of the first and second internal circuits. FIG. 23 is a block diagram showing a configuration of a semiconductor integrated circuit device according to a seventh embodiment. FIG. 13 is a circuit diagram illustrating a configuration of a voltage-current conversion circuit according to a seventh embodiment. FIG. 23 is a circuit diagram illustrating a configuration of a voltage-current conversion circuit according to a modification of the seventh embodiment.

Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings will be given the same reference numerals, and in principle, their description will not be repeated.

Embodiment 1.
FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit device 5a according to a first embodiment.

With reference to Figure 1, semiconductor integrated circuit device 5a includes N (N: an integer of 2 or more) internal circuits 10, N voltage-current conversion circuits 20, a selection circuit 30, a reference current source 40, and a current comparator 50. In the following, an example where N = 4 is described, so that semiconductor integrated circuit device 5a includes four internal circuits 10a to 10d and voltage-current conversion circuits 20a to 20d.

The internal circuits 10a to 10d generate voltages at internal nodes NTa to NTd. That is, the internal nodes NTa to NTd are "measurement nodes," and the current comparator 50 outputs a binary judgment signal Sjd according to the comparison result between the voltage of the measurement node (in FIG. 1, the output voltage Vout of the internal circuit 10a) and a predetermined judgment voltage Vto. In the first embodiment, the judgment signal Sjd indicates whether the output voltage Vout is included in a range higher or lower than the predetermined judgment voltage. The judgment voltage Vto can be set to the boundary value of the normal range of the output voltage (measurement voltage) Vout.

Figure 2 shows a circuit diagram to explain the internal configuration of each block shown in Figure 1. Since the measurement configurations for internal circuits 10a to 10d (internal nodes NTa to NTd) are similar, in Figure 2, the configuration corresponding to internal circuit 10a (internal node NTa) is representatively shown with the subscript a, but similar configurations are arranged corresponding to internal circuits 10b to 10d.

Furthermore, in the following, when elements corresponding to the internal circuits 10a to 10d are to be collectively described without distinction, the subscripts a to d will be omitted, and they will be described, for example, as internal circuit 10, internal node NT, and voltage-current conversion circuit 20.

Figure 2 shows an example in which voltage-to-current conversion circuit 20a is selected from voltage-to-current conversion circuits 20a to 20d, and the output current Iout generated by voltage-to-current conversion circuit 20a is input to current comparator 50. At this time, output voltage Vout from internal circuit 10a appears at internal node NTa, which is the measurement node. In the following, the voltage compared with the judgment voltage is referred to as the measurement voltage. Therefore, in the following, output voltage Vout is also referred to as the measurement voltage Vout.

The voltage-current conversion circuit 20a includes an N-type MOS (Metal-oxide Semiconductor) transistor (hereinafter, referred to as an NMOS transistor) 201a and a resistive element 202a. The NMOS transistor 201a is connected between a node N1a and the resistive element 202a. The resistive element 202a is connected between the NMOS transistor 201a and a ground line NL that transmits a ground voltage GND. The resistive element 202a has an electrical resistance value RO.

The gate of the NMOS transistor 201a is connected to the internal node NTa, which is the measurement node. That is, the measurement voltage Vout is input to the gate of the NMOS transistor 201a.

The selection circuit 30 has switches 301a to 301d. The switches 301a to 301d are connected between the nodes N1a to N1d and the node N2 of the current comparator 50, respectively. The nodes N1a to N1d are connected to the internal nodes NTa to NTd via the voltage-current conversion circuits 20a to 20d, respectively, as shown in FIG. 1. The voltage-current conversion circuits 20b to 20d are also configured in the same manner as the voltage-current conversion circuit 20a, and have a series circuit of an NMOS transistor and a resistive element between the nodes N1b to N1c and the ground line NL.

The current comparator 50 includes two pairs of current mirrors, P-type MOS transistors (hereinafter referred to as PMOS transistors) 501 and 502 and NMOS transistors 503 and 504. The PMOS transistor 501 is connected between a power supply line NP that transmits a power supply voltage VDD and a node N2, and the PMOS transistor 502 is connected between the power supply line NP and a node N3. The PMOS transistors 501 and 502 form a current mirror by commonly connecting their gates to the node N2 (i.e., the drain of the PMOS transistor 501). The current ratio of the current mirror is assumed to be 1:1.

NMOS transistor 503 is connected between node N3 and the ground line NL, and NMOS transistor 504 is connected between node N4 and the ground line NL. NMOS transistors 503 and 504 configure a current mirror by having their gates commonly connected to node N4 (i.e., the drain of NMOS transistor 504). In the following, the current ratio of the current mirror is assumed to be 1:1.

The reference current source 40 has resistive elements 401, 402, and 404, an NMOS transistor 403, and PMOS transistors 405 and 406.

The PMOS transistor 406 is connected between the power supply line NP and node N4, and the PMOS transistor 405 is connected between the power supply line NP and node N5. The PMOS transistors 405 and 406 configure a current mirror by having their gates commonly connected to node N5 (i.e., the drain of the PMOS transistor 405). The current ratio of the current mirror is assumed to be 1:1.

The NMOS transistor 403 is connected between the node N5 and the node N7, and the resistive element 404 is connected between the node N7 and the ground line NL. The resistive element 404 has an electrical resistance value RP.

Resistance element 401 is connected between the power supply line NP and node N6, and resistance element 402 is connected between the ground line NL and node N6. Therefore, a reference voltage Vref is generated at node N6 by dividing the power supply voltage VDD by resistance elements 401 and 402.

Next, the operation of the circuit shown in FIG. 2 will be described.
The selection circuit 30 turns on one of the switches 301a to 301d that corresponds to the internal node to be measured, and turns off the remaining switches. In the example of Fig. 2, the switch 301a is turned on. This creates a path for the output current Iout from the power supply line NP to the ground line NL, including the PMOS transistor 501, the switch 301a (node N1a), the NMOS transistor 201a, and the resistor element 202a.

The output current Iout is expressed by the following formula (1) using the measured voltage Vout, the electrical resistance value RO of the resistive element 202a, and the gate-source voltage Vgs2 of the NMOS transistor 201a. That is, the voltage-current conversion circuit 20 converts the measured voltage Vout into the output current Iout according to the conversion gain according to formula (1). In formula (1), (1/RO) corresponds to one example of the "first conversion gain".

Iout=(Vout-Vgs2)/RO...(1)
The output current Iout is copied by a current mirror (current ratio 1:1) formed by PMOS transistors 501 and 502. As a result, in the current comparator 50, a current equivalent to the output current Iout is supplied to the node N3 by the PMOS transistor 502. Supplied.

In contrast, in the reference current source 40, a path for the reference current Iref is generated from the power supply line NP to the ground line NL, the path including the PMOS transistor 405, the NMOS transistor 403, and the resistive element 404.

The reference current Iref is expressed by the following equation (2) using the reference voltage Vref at node N6, the electrical resistance value RP of the resistive element 404, and the gate-source voltage Vgs4 of the NMOS transistor 403. That is, the reference current source 40 converts the reference voltage Vref into the reference current Iref according to the conversion gain according to equation (2). In equation (2), (1/RP) corresponds to one example of the "second conversion gain".

Iref=(Vref-Vgs4)/RP...(2)
The reference current Iref is copied by a current mirror formed by PMOS transistors 405 and 406 (current ratio 1:1) and a current mirror formed by NMOS transistors 504 and 503 (current ratio 1:1). In this case, a current equivalent to the reference current Iref is drawn from the node N3 by the NMOS transistor 503.

As a result, in the current comparator 50, a voltage V3 is generated at node N3, which is the amplified current difference between the output current Iout and the reference current Iref. Specifically, when Iout>Iref, the voltage V3 becomes a high-level voltage (hereinafter also simply referred to as "H level") equivalent to the power supply voltage VDD. On the other hand, when Iout<Iref, the voltage V3 becomes a low-level voltage (hereinafter also simply referred to as "L level") equivalent to the ground voltage GND. The voltage V3 at node N3 is output as a judgment signal Sjd to a terminal 6 that can be contacted from outside the semiconductor integrated circuit device 5a.

In this case, the judgment can be made faster by using a judgment voltage Vto to be compared with the measured voltage Vout and designing it so that when Vout = Vto, Iout = Iref.

From equations (1) and (2), such conditions can be obtained by solving the following equation (3).

(Vto-Vgs2)/RO=(Vref-Vgs4)/RP...(3)
Therefore, by determining the electrical resistance value RO of the resistive element 202a according to equation (4) obtained by modifying equation (3), it is possible to make Iout=Iref when Vout=Vto.

RO=(Vto-Vgs2)/(Vref-Vgs4)・RP...(4)
In this way, the semiconductor integrated circuit device according to the first embodiment can compare the measurement voltage Vout with the determination voltage Vto by comparing the output current Iout obtained by current-converting the measurement voltage Vout with the reference current Iref. can.

Since the input of the current comparator 50 has an inherently low impedance characteristic, in this embodiment, the settling time of the voltage at node N3 when the selection circuit 30 switches the measurement voltage Vout is significantly shortened compared to the settling time of the input voltage of the voltage comparator circuit that compares voltages in Patent Document 1. In particular, in a configuration in which the circuit size is suppressed by sharing the current comparator 50 between multiple internal nodes, the effect of shortening the test time is significant.

Furthermore, as can be understood from the formula (4), by changing the electric resistance value RO of the resistive element 202a, the fixed reference current Iref in the reference current source 40 can be used to equivalently change the judgment voltage Vto to be compared with the measured voltage Vout. That is, by changing the conversion gain according to the electric resistance value RO of the resistive element 202a in the voltage-current conversion circuit 20, the reference current Iref can be fixed, and the judgment voltage Vto can be freely changed in accordance with the normal range of the measured voltage Vout at each internal node NT. That is, the electric resistance value RO (i.e., the conversion gain) in the voltage-current conversion circuit 20 is determined to reflect at least the judgment voltage Vto, and is preferably set according to the formula (4). This makes it possible to realize switching of the judgment voltage for a plurality of measured voltages with a simple configuration. As a result, the manufacturing cost of the semiconductor integrated circuit device can be reduced.

In addition, in formulas (1) to (4), Vgs2 and Vgs4 can be made to have equivalent values by matching the ratio of the current and the transistor size (W/L) between NMOS transistor 201a and NMOS transistor 403. With this, when Iout = Iref, with electrical resistance values RO and RP determined according to formula (4), it is possible to compare the measured voltage Vout with the above-mentioned determination voltage Vto with Vgs2 = Vgs4.

However, there is a concern that the judgment result may be affected if Vgs2 and Vgs4 fluctuate due to manufacturing variations in transistors (mainly threshold voltage variations) and temperature changes. Therefore, it is preferable to use elements whose threshold voltages (Vth) are sufficiently smaller than the judgment voltage Vto and the reference voltage Vref for the NMOS transistors 201a and 403 used in the voltage-current conversion circuit 20 and the reference current source 40. For example, it is preferable to configure the NMOS transistors 201a and 403 using native MOSs, which in principle have Vth = 0 (V).

2 shows an example of configuring the voltage-current conversion circuit 20 using NMOS transistors, but it is also possible to configure the voltage-current conversion circuit 20 using PMOS transistors. In particular, when the determination voltage Vto is low, it is preferable to increase the voltage applied to the resistive element 202a (electrical resistance value RO) in order to reduce the effect of Vgs2 in equation (1).

(Variation 1)
3 shows a circuit diagram illustrating the internal configuration of each block in FIG. 1 according to a modified example in which voltage-to-current conversion is performed using PMOS transistors. In FIG. 3, the configuration corresponding to the internal circuit 10a is representatively shown with the subscript a, but similar configurations are arranged corresponding to each internal circuit 10.

Referring to Figure 3, in variant example 1, the voltage-current conversion circuit 20a, current comparator 50, and reference current source 40 in Figure 2 are replaced with a voltage-current conversion circuit 20pa, a current comparator 50p, and a reference current source 40p.

The voltage-current conversion circuit 20pa has a PMOS transistor 201pa and a resistive element 202a. The resistive element 202a (electrical resistance value RO) is connected between the power supply line NP and the PMOS transistor 201pa. The PMOS transistor 201pa is connected between the resistive element 202a and a node N1a. The gate of the PMOS transistor 201pa is connected to the internal node NTa to be measured, similar to the NMOS transistor 201 (Figure 2). The configuration of the selection circuit 30 is the same as that of Figure 2.

The current comparator 50p includes two current mirrors, NMOS transistors 501p and 502p and PMOS transistors 503p and 504p. The NMOS transistor 501p is connected between the node N2 and the ground line NL, and the NMOS transistor 502p is connected between the node N3 and the ground line NL. The NMOS transistors 501p and 501n form a current mirror in the same way as the PMOS transistors 501 and 502 (FIG. 2).

As a result, when switch 301a is turned on, a path for output current Iout is generated from power supply line NP to ground line NL, including resistor element 202a, PMOS transistor 201pa, switch 301a (node N1a), and NMOS transistor 501p. Output current Iout is obtained by converting measured voltage Vout into a voltage-current according to the following equation (5) instead of equation (1) in FIG. 2. From equation (5), the conversion gain of voltage-current conversion circuit 20pa is also (1/RO).

Iout=(VDD-Vout-Vgs2)/RO...(5)
The reference current source 40 includes resistance elements 401, 402, and 404, a POS transistor 403p, and NMOS transistors 405p and 406p. The NMOS transistor 406p is connected between the ground line NL and a node N4. , connected between the ground line NL and node N7. The NMOS transistors 405p and 406p form a current mirror in the same manner as the PMOS transistors 405 and 406 (FIG. 2). The PMOS transistor 403p is connected between the node N5 and the node N7. A resistor element 404 (with an electrical resistance value RP) is connected between the node N5 and the power supply line NP.

As a result, in the reference current source 40p, a path of the reference current Iref corresponding to the reference voltage Vref is generated from the power supply line NP to the ground line NL, including the resistive element 404, the PMOS transistor 403p, and the NMOS transistor 405p.

The reference current Iref is expressed by the following equation (6) instead of equation (2) in Figure 2. From equation (6), the conversion gain of the reference current source 40p is also (1/RP).

Iref=(VDD-Vref-Vgs4)/RP...(6)
3, the reference current Iref is copied by a current mirror (current ratio 1:1) formed by PMOS transistors 503p and 504p. As a result, the PMOS transistor 503p, contrary to FIG. A current equivalent to Iref is supplied to node N3.

On the other hand, the output current Iout generated in the voltage-current conversion circuit 20p is copied by a current mirror (current ratio 1:1) formed by NMOS transistors 501p and 502p. As a result, in the current comparator 50p, a current equivalent to the output current Iout is drawn from node N3 by NMOS transistor 502p.

Therefore, in the current comparator 50p, a voltage V3 is generated at N3 by amplifying the current difference between the output current Iout and the reference current Iref. Specifically, the polarity is opposite to that of the current comparator 50 (Figure 2), and when Iref>Iout, the voltage V3 becomes H level (VDD). On the other hand, when Iout>Iref, the voltage V3 becomes L level (GND). The voltage V3 at node N3 is output from the current comparator 50p as a judgment signal Sjd.

As can be understood from the above equations (5) and (6), in the modified example of Figure 3, in order to design Iout = Iref when Vout = Vto using the judgment voltage Vto relative to the measurement voltage Vout, the ratio of the electrical resistance value RO of resistor element 202a and the electrical resistance value RP of resistor element 404 is determined according to the following equation (7).

RO=(VDD-Vto-Vgs2)/(VDD-Vref-Vgs4)・RP...(7)
In this manner, in the configuration of the first modification, the positions of the power supply line NP and the ground line NL are swapped, and the NMOS transistors and PMOS transistors are swapped, so that the PMOS transistors are not used. This makes it possible to perform voltage-to-current conversion.

As with the configuration of Fig. 2, the configuration of the modified example 1 also makes it possible to compare the measurement voltage Vout with the judgment voltage Vto by comparing the output current Iout, which is a current conversion of the measurement voltage Vout, with the reference current Iref. As a result, when the judgment voltage Vto is low, the same effect as that described in Fig. 2 can be obtained by using the modified example of Fig. 3.

(Variation 2)
Furthermore, a modified example for canceling the influence of Vgs2 and Vgs4 in the expressions (1), (2) and the like will be described.

FIG. 4 is a circuit diagram illustrating a modification of the voltage-current conversion circuit 20a shown in FIG.
Voltage-to-current converter circuit 20a# according to the second modification in FIG. 4 further includes an operational amplifier buffer 230a in addition to an NMOS transistor 201a and a resistive element 202a similar to those in voltage-to-current converter circuit 20a (FIG. 2).

The operational amplifier buffer 230a has PMOS transistors 2033a and 2034a, NMOS transistors 2031a, 2032a, and 2035a, and current sources 2036a and 2037a.

The PMOS transistors 2033a and 2034a are connected between the power supply line NP and the node N10 and between the node N11 and the node N12, respectively. The current source 2036a is connected between the node N12 and the ground line NL. Furthermore, the gates of the PMOS transistors 2033a and 2034a are connected to the node N10.

In this way, a current mirror type differential amplifier is configured by the PMOS transistors 2033a and 2034a, the NMOS transistors 2031a and 2032a, and the current source 2036a. The gate of the NMOS transistor 2031a is connected to the internal node NTa, which corresponds to the measurement node.

Furthermore, NMOS transistor 2035a is connected between the power supply line NP and node N13, which is connected to the gate of NMOS transistor 2032a. Current source 2037a is connected between node N13 and ground line NL. The gate of NMOS transistor 2035a is connected to node N11. Note that NMOS transistor 2035a, NMOS transistor 201a, and NMOS transistor 403 (reference current source 40) are designed to have the same characteristics (transistor size).

As a result, in the operational amplifier buffer 230a, the gate voltage of the NMOS transistor 2032a becomes equal to the gate voltage of the NMOS transistor 2031a, i.e., the measurement voltage Vout. Furthermore, when the current of the current source 2037a is set equal to the reference current Iref, the gate-source voltage of the NMOS transistor 2035a becomes equal to Vgs4 in FIG. 2. Therefore, the gate voltage of the NMOS transistor 2035a, i.e., the voltage of the node N11, becomes equal to Vout+Vg4.

On the other hand, the NMOS transistor 201a generates a gate-source voltage Vgs2 similar to that in Figure 2. As a result, it can be understood that the voltage applied to the resistance element 202a is Vout + Vgs4 - Vg2.

Furthermore, in the second modification, a similar operational amplifier buffer is also disposed on the reference current source side.
FIG. 5 is a circuit diagram illustrating a modification of the reference current source 40 shown in FIG.

The reference current source 40# of variant example 2 of Figure 5 differs from the reference current source 40 (Figure 2) in that it further includes an operational amplifier buffer 407 between node N6, which is the connection point of resistance elements 401 and 402, and the gate of NMOS transistor 403.

The operational amplifier buffer 407 is configured similarly to the operational amplifier buffer 230a of FIG. 4, and has NMOS transistors 4071, 4072, and 4075, NMOS transistors 4073 and 4074, and current sources 4076 and 4077.

The gate of the NMOS transistor 4071 is connected to a node N6 where a reference voltage Vref is generated. The NMOS transistor 4075 is connected between the power supply line NP and a node N14, and the current source 4077 is connected between the node N14 and a ground line NL. The gate of the NMOS transistor 4075 is connected to a node N15 which is the connection point of the PMOS transistor 4074 and the NMOS transistor 4072. The gate of the NMOS transistor 403 is also connected to the node N15. The NMOS transistor 4075 is designed to have the same characteristics (transistor size and threshold voltage) as the NMOS transistor 403 (reference current source 40).

As a result, in the operational amplifier buffer 407, the gate voltage of the NMOS transistor 4072 becomes equivalent to the gate voltage of the NMOS transistor 4071, i.e., the reference voltage Vref. Furthermore, if the current of the current source 4077 is made equivalent to the current flowing through the resistive element 404, i.e., the reference current Iref, the gate-source voltage of the NMOS transistor 4075 becomes equivalent to the gate-source voltage Vgs4 of the NMOS transistor 403. Therefore, the gate voltage of the NMOS transistor 4075, i.e., the voltage of the node N15, becomes equivalent to Vout+Vg4.

As a result, it can be understood that the voltage applied to the resistive element 404 is equivalent to the reference voltage Vref. Therefore, the reference current Iref is expressed as Iref = Vref/RS.

As described above, in the voltage-current conversion circuit 20a#, the voltage applied to the resistive element 202a is Vout + Vgs4 - Vg2. Therefore, if the output current Iout and the reference current Iref are designed to be equal when the measurement voltage Vout is the judgment voltage Vto (Vout = Vto), then Vgs4 = Vgs2, and the output current Iout is expressed as Iout = Vout / RO.

Therefore, in a modified example that uses a voltage-to-current conversion circuit 20a# including an operational amplifier buffer and a reference current source 40#, in order to design Iout=Iref when Vout=Vto using a judgment voltage Vto relative to a measurement voltage Vout, the ratio of the electrical resistance value RO of the resistive element 202a and the electrical resistance value RP of the resistive element 404 can be determined according to the following formula (8). Note that formula (8) also holds true in the voltage-to-current conversion circuits 20 and 20p of Figures 2 and 3 by setting Vgs2=Vgs4.

RO=(Vto/Vref)・RP...(8)
As can be seen from equation (8), by using an operational amplifier buffer, even if manufacturing variations in transistors (mainly threshold voltage variations) and temperature changes occur, As a result, the comparison between the measurement voltage Vout and the determination voltage Vto can be performed with high accuracy.

Note that the op-amp buffer 230a (FIG. 4) and the op-amp buffer 407 (FIG. 5) can also be applied to the voltage-to-current conversion circuit 20pa and the reference current source 40p in the modified example 1 shown in FIG. 3. In this case, it is necessary to swap the positions of the power supply line NP and the ground line NL, and to swap the NMOS transistors and PMOS transistors in each of the op-amp buffer 230a and the op-amp buffer 407, in the same manner as in the arrangement from FIG. 2 to FIG. 3.

Embodiment 2.
FIG. 6 is a block diagram showing a configuration of a semiconductor integrated circuit device 5b according to the second embodiment.

As shown in Figure 6, the semiconductor integrated circuit device 5b differs from the semiconductor integrated circuit device 5a according to the first embodiment in that it has N voltage-current conversion circuits 21 instead of the N voltage-current conversion circuits 20, and in that it has a selection circuit 31 instead of the selection circuit 30. Figure 6 also shows an example configuration for N=4.

Each selection circuit 21 has a node that generates two output currents with different conversion gains for the measurement voltage Vout at the internal node NT that corresponds to the measurement node of the corresponding internal circuit 10. In response to this, the selection circuit 31 is configured to select one of the (2×N) nodes of the N voltage-current conversion circuits 21 and connect it to the current comparator 50.

In the second embodiment, the measured voltage Vout can be compared with two types of judgment voltages. For example, by comparing the measured voltage Vout with a judgment voltage Vtl corresponding to the lower limit of the normal range of the measured voltage Vout and a judgment voltage Vtu corresponding to the upper limit of the normal range, it is possible to determine whether the measured voltage Vout is within the normal range.

Figure 7 shows a circuit diagram for explaining the internal configuration of each block shown in Figure 6. In Figure 7, the configuration corresponding to internal circuit 10a is representatively shown with the subscript a, but similar configurations are arranged corresponding to each internal circuit 10.

7, the voltage-current conversion circuit 21a includes NMOS transistors 203a and 205a and resistor elements 204a and 206a. The gates of the NMOS transistors 203a and 205a are commonly connected to the internal node NTa. That is, the gate voltages of the NMOS transistors 203a and 205a are the measurement voltage Vout.

The NMOS transistor 203a is connected between the node N1ax and the resistive element 204a, and the resistive element 204a is connected between the NMOS transistor 203a and the ground line NL. The resistive element 204a has an electrical resistance value RU.

Similarly, the NMOS transistor 205a is connected between the node N1ay and the resistive element 206a, and the resistive element 206a is connected between the NMOS transistor 205a and the ground line NL. The resistive element 206a has an electrical resistance value RL.

In the voltage-current conversion circuit 21a, two "voltage-current conversion units" corresponding to the series circuit of the NMOS transistor 201a and the resistive element 202a in Fig. 2 are provided, and the number of nodes at which the output current Iout is generated, corresponding to the node N1a in Fig. 2, increases to two, nodes N1xa and N1ya. Since the electrical resistance values of the resistive elements 204a and 206a are different, the two voltage-current conversion units convert the common measurement voltage Vout into output currents with different conversion gains.

The voltage-current conversion circuits 21b to 21d are configured in the same manner as the voltage-current conversion circuit 21a, and in each voltage-current conversion circuit 21, a series circuit (voltage-current conversion unit) of an NMOS transistor and a resistive element is arranged between two nodes and the ground line NL.

The selection circuit 31 has switches 302a to 302d and 303a to 303d. The switches 303a to 303d are each connected between one of the two nodes of the voltage-current conversion circuit 21 (node N1ax in FIG. 7) and node N2. The switches 302a to 302d are each connected between the other of the two nodes of the voltage-current conversion circuit 21 (node N1ay in FIG. 7) and node N2.

In embodiment 2, the configuration downstream of node N2, i.e., the current comparator 50 and the reference current source 40, is the same as that in Figure 2, so detailed description will not be repeated.

In the semiconductor integrated circuit device 5b according to the second embodiment, the selection circuit 31 turns on one of the switches 302a to 302d and 303a to 303d while turning off the remaining switches. By sequentially turning on one of the two switches corresponding to the internal circuit (internal node) to be measured, the output current (Iou) generated at the node N1ax and the output current (Iol) generated at the node N1ay are input one by one to the current comparator 50. This allows the measurement voltage Vout to be compared with the two determination voltages Vtu and Vtl in sequence.

First, switch 302a is turned on while the remaining switches are turned off. This creates a path for output current Iol from power supply line NP to ground line NL, including PMOS transistor 501, switch 302a (node N1ay), NMOS transistor 205a, and resistive element 206a, similar to the path for output current Iout in FIG. 2. At this time, in current comparator 50, the current mirror formed by PMOS transistors 501 and 502 makes output current Iout supplied by PMOS transistor 502 to node N3 equal to output current Iol (Iout = Iol).

Next, switch 303a is turned on while the remaining switches are turned off. A path of output current Iou including PMOS transistor 501, switch 303a (node N1ax), NMOS transistor 203a, and resistive element 204a from power supply line NP to ground line NL is generated in the same manner as the path of output current Iout in FIG. 2. At this time, in current comparator 50, output current Iout supplied to node N3 by PMOS transistor 502 becomes equal to output current Iou (Iout = Iou).

In this way, the voltage-current conversion circuit 21 can generate multiple output currents Iol and Iou with different conversion gains for a common measurement voltage Vout. The conversion gains of the output currents Iol and Iou for the measurement voltage Vout are adjusted by the electrical resistance values RL and RL.

For the judgment voltage Vtl corresponding to the lower limit of the normal range of the measurement voltage Vout described above, when Vout = Vtl, the electrical resistance value RU for making Iout = Iol = Iref is given by the following equation (9), which is a modification of equation (4). Vgs22 in equation (9) indicates the gate-source voltage of the NMOS transistor 205a.

RO=(Vtl-Vgs22)/(Vref-Vgs4)・RP...(9)
For a reference voltage Vtu corresponding to the upper limit of the normal range of the measured voltage Vout, when Vout=Vtu, the electrical resistance value RU for making Iout=Iou=Iref is given by the following equation (4) 10), where Vgs21 represents the gate-source voltage of the NMOS transistor 203a.

RO=(Vtu-Vgs21)/(Vref-Vgs4)・RP...(10)
2, in the current comparator 50, a current equivalent to the reference current Iref is drawn from the node N3 by the NMOS transistor 503. Therefore, at the node N3, when the switch 302a is on, the output current Iol and the reference current On the other hand, when the switch 303a is on, a voltage V3 is generated by amplifying the current difference between the output current Iou and the reference current Iref. Depending on the magnitude of the set output current Iout and the reference current Iref, the determination signal Sjd generated at the node N3 is set to H level or L level.

Therefore, when switch 302a is on, if Vout>Vtl, Iout=Iou>Iref, and so the judgment signal Sjd is set to H level. On the other hand, when switch 303a is on, if Vout<Vtu, Iout=Iol<Iref, and so the judgment signal Sjd is set to L level. In this way, it can be determined whether or not the measured voltage Vout is within a predetermined voltage range (normal range) Vtu<Vout<Vtl.

As described above, according to the semiconductor integrated circuit device of the second embodiment, in addition to the effects described in the first embodiment, the measurement voltage Vout can be compared with a plurality of determination voltages while suppressing an increase in the circuit size by using one set of the reference current source 40 and the current comparator 50. This makes it possible to efficiently determine whether the measurement voltage Vout is within the normal range by comparing it with the lower limit and upper limit of the normal range.

In addition, the first and second modifications described in the first embodiment can also be applied to the second embodiment. That is, in the voltage-current conversion circuit 21, the current comparator 50, and the reference current source 40, the positions of the power supply line NP and the ground line NL are swapped, and the NMOS transistors and PMOS transistors are swapped, so that the voltage-current conversion can be performed using PMOS transistors. Alternatively, by adding an operational amplifier buffer (FIGS. 4 and 5) to the voltage-current conversion circuit 21 and the reference current source 40, the effects of MOS transistor variation and temperature fluctuations can be suppressed, and the accuracy of the judgment can be improved.

Embodiment 3.
In the third embodiment, similarly to the second embodiment, another example of the configuration for comparing the measurement voltage Vout with a plurality of determination voltages will be described.

FIG. 8 is a block diagram showing a configuration of a semiconductor integrated circuit device 5c according to the third embodiment.
8, the semiconductor integrated circuit device 5c differs from the semiconductor integrated circuit device 5a according to the first embodiment in that it includes N voltage-current conversion circuits 22 instead of the N voltage-current conversion circuits 20. A control signal Schg for switching the conversion gain is input to each voltage-current conversion circuit 22.

On the other hand, the selection circuit 30, the reference current source 40, and the current comparator 50 have the same configuration as in the first embodiment. FIG. 8 also shows an example of the configuration when N=4. In the third embodiment, too, a configuration for comparing the measurement voltage Vout with the determination voltages Vtl and Vtu similar to those in the second embodiment will be described.

Figure 9 shows a circuit diagram for explaining the internal configuration of each block shown in Figure 8. In Figure 9, the configuration corresponding to internal circuit 10a is representatively shown with the subscript a, but similar configurations are arranged corresponding to each internal circuit 10.

9, the voltage-current conversion circuit 22a includes an NMOS transistor 201a, resistive elements 209a and 210a, and a transistor switch 208a. The resistive element 209a has an electrical resistance value RO1, and the resistive element 210a has an electrical resistance value RO2.

Compared to the voltage-current conversion circuit 20a in Fig. 2, the voltage-current conversion circuit 22a has a configuration in which, instead of the resistance element 202a, series-connected resistance elements 209a and 201a are connected between the source of the NMOS transistor 201a and the ground line NL. The transistor switch 208a is connected in parallel to the resistance element 210a. The transistor switch 208a is turned on when the control signal Schg is at H level, and turned off when the control signal Schg is at L level.

In embodiment 3, the configuration downstream of nodes N1a to N1d, i.e., the selection circuit 30, the current comparator 50, and the reference current source 40, are the same as those in Figure 2, so detailed description will not be repeated.

In the semiconductor integrated circuit device 5c according to the third embodiment, the selection circuit 30 turns on the switch 301a corresponding to the measurement node, as in Fig. 2. This creates a path for the output current Iout from the power supply line NP to the ground line NL, including the PMOS transistor 501, the switch 301a (node N1a), and the NMOS transistor 201a, as in Fig. 2.

In the voltage-current conversion circuit 22a, the electrical resistance between the source of the NMOS transistor 201a and the ground line NL, which are included in the path of the output current Iout, is switched according to the control signal Schg. Specifically, when the control signal Schg is at H level, the output current Iout bypasses the resistive element 210a, so the electrical resistance is RO1. On the other hand, when the control signal Schg is at L level, the output current Iout passes through both the resistive elements 209a and 210a, so the electrical resistance is RO1+RO2.

As a result, in the voltage-current conversion circuit 22a, similar to the voltage-current conversion circuit 21a of embodiment 2 (Figure 7), the conversion gain of the output current Iout relative to the measured voltage Vout can be set in two stages. The respective conversion gains correspond to 1/RO1 and 1/(RO1+RO2). In the current comparator 50, the output current Iout supplied to node N3 by the PMOS transistor 502 is switched according to the control signal Schg input to the transistor switch 208a. That is, one example of a "gain switching mechanism" can be configured by the transistor switch 208a.

For the same judgment voltage Vtl (lower limit side) as in embodiment 2, when Vout = Vtl, the electrical resistance value RO1 for making Iout = Iref is given by the following equation (11), which is a modification of equation (4).

RO1=(Vtl-Vgs2)/(Vref-Vgs4)・RP...(11)
Similarly, for the determination voltage Vtu (upper limit side), when Vout=Vtu, the electrical resistance value RO1+RO2 for making Iout=Iref is given by the following equation (12), which is a modification of equation (4).

RO1+RO2=(Vtu-Vgs2)/(Vref-Vgs4)・RP...(12)
2, in the current comparator 50, a current equivalent to the reference current Iref is drawn from the node N3 by the NMOS transistor 503. Therefore, at the node N3, an output whose conversion gain is switched in response to the control signal Schg is generated. A voltage V3 is generated by amplifying the current difference between the current Iout and the reference current Iref.

Therefore, when the control signal Schg is at H level (when the transistor switch 208a is on), if Vout<Vtl, then Iout>Iref, and the judgment signal Sjd is set to H level. On the other hand, when the control signal Schg is at L level (when the transistor switch 208a is off), if Vout<Vtu, then Iout<Iref, and the judgment signal Sjd is set to L level. In this way, it can be determined whether the measured voltage Vout is within a predetermined voltage range (normal range) Vtu<Vout<Vtl.

As described above, according to the semiconductor integrated circuit device of the third embodiment, as in the second embodiment, the measurement voltage Vout can be compared with a plurality of determination voltages while suppressing an increase in the circuit size by using one set of the reference current source 40 and the current comparator 50. This makes it possible to efficiently determine whether the measurement voltage Vout is within the normal range by comparing it with the lower limit and upper limit of the normal range.

Furthermore, according to the configuration of the third embodiment, it is possible to execute the same judgment of the measured voltage Vout as in the second embodiment without using the selection circuit 31, which has twice the number of switches. In other words, it is possible to obtain the same effect as in the second embodiment, and to reduce the circuit scale compared to the second embodiment.

In addition, the first and second modifications described in the first embodiment can also be applied to the third embodiment. That is, in the voltage-current conversion circuit 22, the current comparator 50, and the reference current source 40, the positions of the power supply line NP and the ground line NL are swapped, and the NMOS transistors and PMOS transistors are swapped, so that the voltage-current conversion can be performed using PMOS transistors. Alternatively, by adding an operational amplifier buffer (FIGS. 4 and 5) to the voltage-current conversion circuit 22 and the reference current source 40, the effects of MOS transistor variation and temperature fluctuations can be suppressed, and the accuracy of the judgment can be improved.

Embodiment 4.
In the fourth embodiment, a configuration will be described in which the comparison of the measurement voltage Vout with a plurality of determination voltages (for example, Vtu, Vtl) described in the second and third embodiments can be performed at the same time.

Figure 10 is a block diagram showing the configuration of a semiconductor integrated circuit device 5d relating to embodiment 4.

As shown in Figure 10, the semiconductor integrated circuit device 5d differs from the semiconductor integrated circuit device 5b (Figure 6) according to the second embodiment in that a selection circuit 32 is provided instead of the selection circuit 31, a current comparator 51 is provided instead of the current comparator 50, and a decision logic circuit 60 is further provided. On the other hand, the voltage-current conversion circuit 21 and the reference current source 40 are the same as those in the second embodiment (Figure 6).

Figure 11 shows a circuit diagram for explaining the internal configuration of each block shown in Figure 10. In Figure 11, the configuration corresponding to internal circuit 10a is representatively shown with the subscript a, but similar configurations are arranged corresponding to each internal circuit 10.

11, the selection circuit 32 has switches 304a to 304d and 305a to 305d. The current comparator 51 is configured to simultaneously generate output currents Ioutx and Iouty at nodes N2x and N2x.

Therefore, node N1ax of voltage-current conversion circuit 21a is connected to node N2x of current comparator 51 via switch 305a of selection circuit 32, and node N1ay of voltage-current conversion circuit 21a is connected to node N2y of current comparator 51 via switch 304a of selection circuit 32. In this way, selection circuit 32 is controlled to connect two nodes (corresponding to Niax and N1ay) of one voltage-current conversion circuit 21 of voltage-current conversion circuits 21a to 21d to nodes N2x and N2y of current comparator 51, respectively.

The current comparator 51 has four current mirrors: PMOS transistors 505 to 508 and NMOS transistors 509 to 511.

The PMOS transistors 505 and 506 are connected between the power supply line NP and the nodes N2x and N3x, respectively. The PMOS transistors 505 and 506 are connected in common to the gates of the node N2x (i.e., the drain of the PMOS transistor 505), forming a current mirror (current ratio is 1:1).

The PMOS transistors 507 and 508 are connected between the power supply line NP and the nodes N2y and N3y, respectively. The PMOS transistors 507 and 508 are connected in common to the gates of the node N2y (i.e., the drain of the PMOS transistor 507), forming a current mirror (current ratio is 1:1).

NMOS transistor 509 is connected between node N3x and the ground line NL, and NMOS transistor 510 is connected between node N3y and the ground line NL. NMOS transistor 511 is connected between node N4 and the ground line NL, similar to NMOS transistor 504 in Fig. 7. A reference current Iref is supplied to node N4 from a reference current source 40 similar to that in Fig. 2.

The gates of NMOS transistors 509 to 511 are commonly connected to node N4 (the drain of NMOS transistor 511). This forms a current mirror of NMOS transistors 511 and 509 (current ratio is 1:1), and a current mirror of NMOS transistors 511 and 510 (current ratio is 1:1).

Next, the operation of the circuit shown in Fig. 11 will be described. In the example of Fig. 11, the operation will be described when the internal node NTa of the internal circuit 10a is selected and the switches 304a and 305a are turned on in the selection circuit 32.

When the switch 305a is turned on, a path for the output current Ioutx is generated from the power supply line NP to the ground line NL, including the PMOS transistor 505, the switch 305a (node N1ax), the NMOS transistor 203a, and the resistive element 204a. The output current Ioutx is equal to the output current Iou in FIG.

Similarly, when the switch 304a is turned on, a path for the output current Iouty is generated from the power supply line NP to the ground line NL, including the PMOS transistor 507, the switch 304a (node N1ay), the NMOS transistor 205a, and the resistive element 206a. The output current Iouty is equivalent to the output current Iol in FIG. 7. In this way, in the current comparator 52 of the fourth embodiment, the output currents Ioutx and Iouty corresponding to the output currents Iou and Iol in FIG. 7 are generated simultaneously. That is, the current comparator 50 receives in parallel a plurality of output currents Ioutx and Iouty having different conversion ratios generated by the voltage-current conversion circuit 22.

The output current Ioutx is copied by a current mirror (current ratio 1:1) formed by PMOS transistors 505 and 506. Similarly, the output current Iouty is copied by a current mirror (current ratio 1:1) formed by PMOS transistors 507 and 508. As a result, in the current comparator 52, a current equivalent to the output current Ioutx is supplied to node N3x by PMOS transistor 506, and a current equivalent to the output current Iouty is supplied to node N3y by PMOS transistor 508.

On the other hand, the reference current Iref supplied from the reference current source 40 to the node N4 is copied by a current mirror (current ratio 1:1) formed by NMOS transistors 511 and 509, and a current mirror (current ratio 1:1) formed by NMOS transistors 511 and 510. As a result, a current equivalent to the reference current Iref is drawn from the node N3x by the PMOS transistor 509. Similarly, a current equivalent to the reference current Iref is drawn from the node N3y by the PMOS transistor 510.

As a result, a voltage V3x is generated at node N3x by amplifying the current difference between the output current Ioutx (Ioutx=Iou) and the reference current Iref. This is equivalent to the voltage V3 generated at node N3 when switch 303a is on in FIG. 7. Therefore, voltage V3x is set to a voltage level indicating the comparison result between the measurement voltage Vout and the judgment voltage Vtu (upper limit side). As in FIG. 7, when Vout<Vtu, Iout<Iref, so the judgment signal Sidx corresponding to voltage V3x is set to the L level.

On the other hand, a voltage V3y is generated at node N3y by amplifying the current difference between the output current Iouty (Iouty=Iou) and the reference current Iref. This is equivalent to the voltage V3 generated at node N3 when switch 302a is on in FIG. 7. Therefore, voltage V3y is set to a voltage level indicating the comparison result between measurement voltage Vout and judgment voltage Vtl (lower limit side). As in FIG. 7, when Vout>Vtl, Iout=Iol>Iref, so the judgment signal Sidy corresponding to voltage V3y is set to H level.

The decision logic circuit 60 has an inverter 601 and a NAND (negative AND) gate 602. The inverter 601 inverts and outputs the decision signal Sidx. The output voltage of the inverter 610 and the decision signal Sidy are input to the NAND gate 602, which outputs the decision signal Sjd. In the configuration of FIG. 11, the decision signal Sjd from the decision logic circuit 60 can be output to a terminal 6 that can be contacted from outside the semiconductor integrated circuit device 5f.

Therefore, when both Vout<Vtu (V3x=L level) and Vout>Vtl (V3y=H level) are satisfied and the measured voltage Vout is within the voltage range of Vtl<Vout<Vtu (normal range), the judgment signal Sjd is set to L level. On the other hand, when the measured voltage Vout is not within the voltage range of Vtl<Vout<Vtu (normal range), neither Vout<Vtu nor Vout>Vtl is satisfied, so the judgment signal Sjd is set to H level.

As described above, in the semiconductor integrated circuit device of embodiment 4, the current comparator 52 can simultaneously compare the measured voltage Vout with the judgment voltage Vtl (lower limit side) and compare the measured voltage Vout with the judgment voltage Vtu (upper limit side).

In contrast, in the configurations of embodiments 2 and 3, the measured voltage Vout can be compared with only one judgment voltage, so the judgment of whether the measured voltage Vout is within the normal range defined by the upper and lower limit values must be performed using the judgment signal Sjd at different timings.

As a result, according to the configuration of the fourth embodiment, the comparison of the measured voltage Vout with a plurality of determination voltages, for example, the determination of whether the measured voltage Vout is within the normal range by comparing it with the lower and upper limits of the normal range, can be performed faster than in the second embodiment. That is, in the semiconductor integrated circuit device according to the fourth embodiment, in addition to the effects described in the second embodiment, the test time can be further shortened.

In addition, the first and second modifications described in the first embodiment can also be applied to the fourth embodiment. That is, in the voltage-current conversion circuit 21, the current comparator 51, and the reference current source 40, the positions of the power supply line NP and the ground line NL are swapped, and the NMOS transistors and PMOS transistors are swapped, so that the voltage-current conversion can be performed using PMOS transistors. Alternatively, by adding an operational amplifier buffer (FIGS. 4 and 5) to the voltage-current conversion circuit 21 and the reference current source 40, the effects of MOS transistor variation and temperature fluctuations can be suppressed, and the accuracy of the judgment can be improved.

Embodiment 5.
In the fifth embodiment, a circuit configuration for omitting the placement of the selection circuit 32 in the fourth embodiment will be described.

Figure 12 is a block diagram showing the configuration of a semiconductor integrated circuit device 5e relating to embodiment 5.

As shown in FIG. 12, the semiconductor integrated circuit device 5e differs from the semiconductor integrated circuit device 5d (FIG. 10) according to the fourth embodiment in that the selection circuit 32 is omitted and that a voltage-current conversion circuit 23 is arranged instead of the voltage-current conversion circuit 21. An enable signal EN is input to each voltage-current conversion circuit 21. FIG. 12 also shows a configuration of N=4, in which individual enable signals ENa-ENd are input to the voltage-current conversion circuits 23a-23d arranged corresponding to the internal circuits 10a-10d, respectively. One of the enable signals ENa-ENd is set to H level to select the internal nodes NTa-NTd of the internal circuits 10a-10d as the measurement target. On the other hand, the remaining three enable signals ENa-ENd are set to L level.

Figure 13 shows a circuit diagram for explaining the internal configuration of each block shown in Figure 12. In Figure 13, the configuration corresponding to internal circuit 10a is representatively shown with the subscript a, but similar configurations are arranged corresponding to each internal circuit 10.

13, the voltage-current conversion circuit 23a further includes an enable switch 207a connected in series to each of the resistive elements 204a and 206a between the resistive elements 204a and 206a and the ground line NL, in comparison with the voltage-current conversion circuit 21a of FIG. 11. The enable switch 207a is turned on and off in response to an enable signal ENa.

Furthermore, in the fifth embodiment, since the selection circuit 32 in FIG. 11 is not provided, the two nodes of each voltage-current conversion circuit 23 are connected to the nodes N2x and N2y of the current comparator 51, respectively, without a switch. For example, the nodes N1ax and N1ay of the voltage-current conversion circuit 23a are connected to the nodes N2x and N2y of the current comparator 51, respectively, without a switch.

When the enable signal ENa is set to the H level and the enable switch 207a is turned on, the voltage-current conversion circuit 23a is connected to the nodes N2x and N2y of the current comparator 51 in the same circuit state as the voltage-current conversion circuit 21a. Therefore, the voltage-current conversion circuit 23a can input the output currents Ioutx and Iouty similar to those in FIG. 11 to the current comparator 51. This makes it possible to generate a judgment signal Sjd based on a comparison between the measurement voltage Vout and the judgment voltages Vlu and Vtl, similar to the fourth embodiment.

On the other hand, when the enable signal ENa is set to the L level and the enable switch 207a is turned off, the paths of the output currents Ioutx and Iouty are cut off in the voltage-current conversion circuit 23a. As a result, in the same way as when the switches 304a and 305a of the selection circuit 32 are turned off in FIG. 11, the output currents Ioutx and Iouty according to the measurement voltage Vout of the internal node NTa are not generated in the current comparator 51. In this case, one of the other voltage-current conversion circuits 23 (voltage-current conversion circuits 23b to 23d in FIG. 12) is selected, and the corresponding enable signal EN is set to the H level. Then, in the current comparator 51, the output currents Ioutx and Iouty according to the measurement voltage Vout input to the selected voltage-current conversion circuit 23 are generated and compared with the reference current Iref.

In this way, in the semiconductor integrated circuit device according to the fifth embodiment, the arrangement of the selection circuit 32 can be omitted, and judgment can be performed by comparing the measurement voltage Vout with a plurality of judgment voltages Vtu and Vyl, similar to the semiconductor device according to the fourth embodiment. Therefore, in addition to the effect of the semiconductor integrated circuit device according to the fourth embodiment, the effect of miniaturization of the circuit can be further enjoyed.

In addition, the first and second modifications described in the first embodiment can also be applied to the fifth embodiment. That is, in the voltage-current conversion circuit 22, the current comparator 50, and the reference current source 40, the positions of the power supply line NP and the ground line NL are swapped, and the NMOS transistors and PMOS transistors are swapped, so that the voltage-current conversion can be performed using PMOS transistors. Alternatively, by adding an operational amplifier buffer (FIGS. 4 and 5) to the voltage-current conversion circuit 22 and the reference current source 40, the effects of MOS transistor variation and temperature fluctuations can be suppressed, and the accuracy of the judgment can be improved.

Furthermore, the fifth embodiment can be combined with the first to third embodiments, and with a configuration in which the first to third embodiments are combined with the first and/or second variations. Specifically, the fifth embodiment can be combined with the first embodiment or the first variation, by connecting the enable switch 207a in series with the resistive element 202a in the voltage-current conversion circuit 20a (FIG. 2) and the voltage-current conversion circuit 20a# (FIG. 4). Similarly, the fifth embodiment can be combined with the first embodiment or the second variation, by connecting the enable switch 207a in series with the resistive element 202pa in the voltage-current conversion circuit 20pa (FIG. 3).

In addition, in the voltage-current conversion circuit 21a (FIG. 7), by connecting the enable switch 207a between the resistor elements 204a and 206a and the ground line NL in the same manner as in FIG. 13, it is possible to combine the second and fifth embodiments. In addition, in the voltage-current conversion circuit 22a (FIG. 9), by connecting the enable switch 207a in series with the resistor elements 209a and 210a and so as to be removed from the short-circuit path caused by the transistor switch 208a, it is also possible to combine the third and fifth embodiments.

Embodiment 6.
In the sixth embodiment, a configuration for dealing with an abnormality using the determination results in the fourth and fifth embodiments will be described.

Figure 14 is a block diagram showing the configuration of a semiconductor integrated circuit device 5f relating to embodiment 6.

As shown in FIG. 14, the semiconductor integrated circuit device 5f has N internal circuits 10 each configured with an internal circuit (hereinafter also referred to as a "first internal circuit") 11 and an internal circuit (hereinafter also referred to as a "second internal circuit") 12 having the same function, and each internal circuit 10 is equipped with an abnormality response configuration that switches to the second internal circuit 12 when a fault is detected in the first internal circuit 11.

Figure 14 also shows an example where N = 4. That is, the internal circuit 10a has a first internal circuit 11a and a second internal circuit 12a, the internal circuit 10b has a first internal circuit 11b and a second internal circuit 12b, the internal circuit 10c has a first internal circuit 11c and a second internal circuit 12c, and the internal circuit 10d has a first internal circuit 11d and a second internal circuit 12d.

The semiconductor integrated circuit device 5f includes, in addition to the voltage-current conversion circuits 21a-21d, selection circuit 32, reference current source 40, current comparator 51, and judgment logic circuit 60 similar to those of the semiconductor integrated circuit device 5d (Figure 10), selection circuits 15a-15d, judgment result selection circuit 70, recording devices 80a-80d, and control logic circuits 9a-9d for the above-mentioned abnormality response configuration.

Figure 15 shows a circuit diagram for explaining the internal configuration of each block shown in Figure 14. In Figure 15, the configuration corresponding to internal circuit 10a is also shown with the subscript a, but similar configurations are arranged corresponding to each internal circuit 10.

The selection circuit 15 has switches 1001a to 1004a. The switches 1001a and 1002a are connected between the first internal circuit 11a and the second internal circuit 12a and another real circuit (not shown) mounted on the semiconductor integrated circuit device 5f, which receives the output voltage of the internal circuit 10a as an input. The switch 1001a is turned on and off in response to a control signal Aa, while the switch 1001a is turned on and off in response to a control signal /Aa (an inverted signal of Aa). As a result, the output voltage of one of the first internal circuit 11a and the second internal circuit 12a is input to the real circuit.

The switch 1003a is connected between an internal node NT1a corresponding to the output node of the first internal circuit 11a and the voltage-current conversion circuit 21a. The switch 1004a is connected between an internal node NT2a corresponding to the output node of the second internal circuit 12a and the voltage-current conversion circuit 21a.

When the switch 1003a is on, the voltage of the internal node NT1a, i.e., the output voltage of the first internal circuit 11a, is input to the voltage-current conversion circuit 21a as the measurement voltage Vout. On the other hand, when the switch 1004a is on, the voltage of the internal node NT2a, i.e., the output voltage of the second internal circuit 12a, is input to the voltage-current conversion circuit 21a as the measurement voltage Vout.

By controlling the switches 1003a and 1004a, a determination signal Sjd indicating whether the output voltage (Vout) of the first internal circuit 11a is within the range Vtl<Vout<Vtu (normal range) can be obtained at the node N20 for each of the output voltages of the first internal circuit 11a and the second internal circuit 12a, as described in the fifth embodiment.

The judgment result selection circuit 70 has switches 701a to 701d and 702a to 702d. The recording device 80a corresponding to the internal circuit 10a has a first latch circuit 801a, a second latch circuit 802a, and a NAND gate 803a.

The switch 701a is connected between the node N20 and the first latch circuit 801a. The first latch circuit 801a is arranged to store the judgment signal Sjd for the first internal circuit 11a included in the internal circuit 10a. Therefore, the switch 701a is provided with an on period in conjunction with the switch 1003a.

Similarly, the switch 702a is connected between the node N20 and the second latch circuit 802a. The second latch circuit 802a is arranged to store the judgment signal Sjd for the second internal circuit 12a included in the internal circuit 10a. Therefore, the switch 702a is provided with an on period in conjunction with the switch 1004a.

Although not shown in the figure, each of the recording devices 80b to 80d arranged corresponding to the internal circuits 10b to 10d includes a first latch circuit 801 that stores the judgment result of the first internal circuit 11, and a second latch circuit 802 that stores the judgment result of the second internal circuit 12. Furthermore, in the judgment result selection circuit 70, a switch 701 leading to the first latch circuit and a switch 702 leading to the second latch circuit are arranged between the recording devices 80b to 80d and node N20 at which the judgment signal Sjd is output from the judgment logic circuit 60.

The NAND gate 803a receives the latch data S11a of the first latch circuit 801a and the latch data S12a of the second latch circuit 802a as inputs and outputs the internal circuit normal signal /Ea.

The control logic circuit 9a has a NAND gate 901a and an inverter 902a. The NAND gate 901a receives latch data S11a and the inverted data of latch data S12a, and outputs a control signal Aa for the switch 1001a. The inverter 902a inverts the output signal of the NAND gate 901a and outputs a control signal /Aa for the switch 1002a.

FIG. 16 shows a signal waveform diagram for illustrating the operation of the semiconductor integrated circuit device 5f.
Referring to FIG. 16, at the test timing of the internal circuit 10a for determining the output voltages of the first internal circuit 11a and the second internal circuit 12a, the switches 304a, 305a of the selection circuit 32 are turned on, and the voltage-current conversion circuit 21a corresponding to the internal circuit 10a is connected to the current comparator 51.

At the test timing of the internal circuit 10a, the output voltage of the first internal circuit 11a and the output voltage of the second internal circuit 12a are judged in sequence. First, by turning on the switches 1003a and 701a, a judgment signal Sjd indicating whether the output voltage (Vout) of the first internal circuit 11a is within the range Vtl<Vout<Vtu (normal range) is input to the first latch circuit 801a. If the judgment result of the first internal circuit 11a is normal, the latch data S11a of the first latch circuit 801a becomes L level.

Next, by turning on the switches 1004a and 702a, a judgment signal Sjd indicating whether the output voltage (Vout) of the second internal circuit 12a is within the range of Vtl<Vout<Vtu (normal range) is input to the second latch circuit 802a. If the judgment result of the first internal circuit 11a is normal, the latch data S12a of the second latch circuit 802a becomes L level.

The first latch circuit 801a corresponds to an example of a "first memory circuit", and the latch data S11a corresponds to an example of "first information". The second latch circuit 802a corresponds to an example of a "second memory circuit", and the latch data S12a corresponds to an example of "second information". In addition, an example of a "measurement selection circuit" can be configured by the switches 1003a and 1004a of the selection circuit 15a.

When the determination of the output voltages of the first internal circuit 11a and the second internal circuit 12a is completed, the test timing of the internal circuit 10a is terminated and the test timing of the internal circuit 10b is set. In the test timing of the internal circuit 10b, the switches 1003b, 1004b, 304b, 305b, 701b, and 702b corresponding to the internal circuit 10b are turned on and off in the same manner as the switches 1003a, 1004a, 304a, 305a, 701a, and 702a in the test timing of the internal circuit 10a so as to determine the output voltages of the first internal circuit 11b and the second internal circuit 12b in sequence.

Figure 17 shows a diagram explaining the operation of the anomaly detection configuration for the judgment results of the first and second internal circuits. As shown in Figure 17, there are Case 1 to Case 4 for combinations of the judgment results of the first and second internal circuits.

In case 1, the output voltage (Vout) of both the first internal circuit 11a and the second internal circuit 12a is normal (S11a = S12a = L). At this time, the control signal Aa is set to H level, while the control signal /Aa is set to L level. That is, the output of the first internal circuit 11a is transmitted to the actual circuit by the switch 1001a. Also, the internal circuit abnormality signal /Ea is set to H level.

In case 2, the output voltage of the first internal circuit 11a is normal (S11a=L), while the output voltage of the second internal circuit 12a is abnormal (S12a=H), and the second internal circuit 12a is faulty. In this case, as in case 1, the control signal Aa is set to H level, while the control signal /Aa is set to L level. That is, the output of the first internal circuit 11a is transmitted to the actual circuit by the switch 1001a. Also, the internal circuit abnormality signal /Ea is set to H level.

In case 3, contrary to case 2, the output voltage of the second internal circuit 12a is normal (S12a=L), while the output of the first internal circuit 11a is abnormal (S11a=H), and the first internal circuit 11a is faulty. In this case, the control signal Aa is set to L level, while the control signal /Aa is set to H level. That is, the output of the second internal circuit 12a is transmitted to the actual circuit by the switch 1002a. Also, the internal circuit abnormality signal /Ea is set to H level. In this way, one embodiment of an "output selection circuit" can be configured by the switches 1001a and 1002a of the selection circuit 15a.

In case 4, the output voltages of both the first internal circuit 11a and the second internal circuit 12a are abnormal (S11a = S12a = L), and both the first internal circuit 11a and the second internal circuit 12a are faulty. In this case, the internal circuit abnormality signal /Ea is set to the L level, unlike cases 1 to 3. The control signals Aa and /Aa are set in the same way as in cases 1 and 2.

In this way, the first internal circuit 11a is set as the default circuit for actual use, and when the first internal circuit 11a fails, the second internal circuit 12a for backup is automatically switched to the circuit for actual use, provided that the determination result is normal. This allows the semiconductor integrated circuit device 5e to continue operating even when an internal circuit fails.

In addition, if both the first internal circuit 11a and the second internal circuit 12a fail, the internal circuit abnormality signal /Ea is set to an L level to indicate that the internal circuit 10a is unusable.

The test timing of the internal circuit 10 shown in Figure 16 can be set when the power supply of the semiconductor integrated circuit device 5f is turned on, and periodically at a time that does not affect the circuit operation.

As described above, the semiconductor integrated circuit device according to the sixth embodiment can automatically detect a failure in the internal circuit 10 and switch to a backup circuit when a failure occurs, thereby improving the reliability of continued circuit operation in addition to the effects described in the fourth embodiment. Also, by monitoring the control signals Aa, /Aa and the internal circuit abnormality signal /Ea from outside the semiconductor integrated circuit device 5f, the failure state of each internal circuit 10 can be grasped. That is, the control signals Aa, /Aa and the internal circuit abnormality signal /Ea can be output to a terminal (not shown) that can be contacted from outside the semiconductor integrated circuit device 5f, similar to the terminal 6.

In addition, in Figure 15, an example is described in which the abnormality response configuration in embodiment 6 is applied to the semiconductor integrated circuit device of embodiment 4, but it is also possible to combine embodiment 6 with the other embodiments 1 to 3 and 5 in addition to applying modifications 1 and 2. In this case, the number of latch circuits in the recording device 80 and the contents of the logical operation in the control logic circuit 9 can be appropriately changed as necessary.

As an example, in embodiments 1 to 3, in order to determine normality and ≧ using the judgment results relating to the same voltage range (Vtl<Vout<Vtu) as in embodiment 4, four latch circuits are required in each recording device 80 to hold the judgment signal Sjd in comparison with each of the judgment voltages Vtl and Vtu, and it is necessary to modify the logical operation in the control logic circuit 9 so that the latch data of the four latch circuits is used to obtain control signals Aa, /Aa and internal circuit abnormality signal /Ea similar to those in Figure 17 for normal and abnormal combinations (cases 1 to 4) of the first internal circuit 11a and the second internal circuit 12a.

Embodiment 7.
In the seventh embodiment, a configuration will be described in which the difference between two voltages (voltage difference) related to the measurement nodes of the internal circuit is used as the measurement voltage, that is, the subject of judgment.

Figure 18 is a block diagram showing the configuration of a semiconductor integrated circuit device 5g relating to embodiment 7.

18, the semiconductor integrated circuit device 5g differs from the semiconductor integrated circuit device 5b (FIG. 10) according to the fourth embodiment in that two voltages, a first voltage Vout1 and a second voltage Vout2, are output from the internal circuit 10a, and that a voltage-current converter circuit 24a is provided instead of the voltage-current converter circuit 21a. Furthermore, an upper peak detector 13a and a lower peak detector 14a are provided for the internal node NTa (output voltage Vout) of the internal circuit 10a, which corresponds to the "measurement node."

The upper peak detector 13a extracts the maximum value (upper peak value) of the output voltage Vout and outputs it as the first voltage Vout1. The lower peak detector 14a extracts the minimum value (lower peak value) of the output voltage Vout and outputs it as the second voltage Vout2. For example, when an AC voltage is output to the internal node NTa, Vout1-Vout2 indicates the peak-to-peak value of the AC voltage.

The first voltage Vout1 and the second voltage Vout2 are input to the voltage-current conversion circuit 24a. The voltage-current conversion circuit 24a converts the voltage difference (Vout1-Vout2) between the first voltage Vout1 and the second voltage Vout2 into output currents Ioutx and Iouty in FIG. 11 with different conversion gains.

On the other hand, the selection circuit 32, the current comparator 50, the reference current source 40, and the decision logic circuit 60 shared by the N internal circuits 10 are the same as those in the fourth embodiment (FIG. 10). In FIGS. 18 and 19, the configuration corresponding to the internal circuit 10a is representatively shown with the subscript a, but the same configuration is arranged corresponding to each internal circuit 10.

Figure 19 shows a circuit diagram illustrating the configuration of a voltage-current conversion circuit related to embodiment 7, i.e., the voltage-current conversion circuit 24a of Figure 18.

19, the voltage-current conversion circuit 24a is connected to the selection circuit 32 (FIG. 11) via nodes N1ax and N1ay. The voltage-current conversion circuit 24a has NMOS transistors 2031a, 2035a, and 2308a, PMOS transistors 2304a, 2307a, and 2310a, resistive elements 2306a and 2309a, and current sources 2302a and 2303a.

The NMOS transistor 2301a is connected between the power supply line NP and the node N31, and the current source 2302a is connected between the node N31 and the ground line NL. The second voltage Vout2 is input to the gate of the NMOS transistor 2301a.

The current source 2303a is connected between the power supply line NP and the node N32, and the PMOS transistor 2304a is connected between the node N32 and the ground line NL. The first voltage Vout1 is input to the gate of the PMOS transistor 2304a.

The NMOS transistor 2305a is connected between the node N1ax and the node N33. The resistive element 2306a is connected between the node N33 and the PMOS transistor 2307a, which is connected between the resistive element 2306a and the ground line NL. The resistive element 2306a has an electrical resistance value RDU.

The NMOS transistor 2308a is connected between the node N1ay and the node N34. The resistive element 2309a is connected between the node N34 and the PMOS transistor 2310a, which is connected between the resistive element 2309a and the ground line NL. The resistive element 2309a has an electrical resistance value RDL.

The gates of NMOS transistors 2305a and 23038a are commonly connected to node N32. The gates of PMOS transistors 2307a and 2310a are commonly connected to node N31.

The voltage V32 at node N32 is expressed as V32 = Vout1 + Vgs14 using the gate-source voltage Vgs14 of PMOS transistor 2304a. Similarly, the voltage V31 at node N31 is expressed as V31 = Vout2 - Vgs11 using the gate-source voltage Vgs11 of NMOS transistor 2301a.

Therefore, the voltage difference applied across the resistor element 2306a is expressed as (V32-Vgs15)-(V31+Vgs17) by further using the gate-source voltage Vgs15 of the NMOS transistor 2305a and the gate-source voltage Vgs17 of the NMOS transistor 2307a. As a result, the output current Ioutx is expressed by the following equation (13).

Ioutx=((Vout1+Vgs14-Vgs15)-(Vout2-Vgs11+Vgs17))/RDU
=(Vout1-Vout2+Vgs14-Vgs15+Vgs11-Vgs17)/RDU...(13)
Similarly, the voltage difference applied across the resistor element 2309a is (V32-Vgs18)-(V31+Vgs20) by further using the gate-source voltage Vgs18 of the NMOS transistor 2308a and the gate-source voltage Vgs20 of the NMOS transistor 2310a. As a result, the output current Iouty is expressed by the following equation (14).

Iouty=((Vout1+Vgs14-Vgs18)-(Vout2-Vgs11+Vgs20))/RDL
=(Vout1-Vout2+Vgs14-Vgs18+Vgs11-Vgs20)/RDL...(14)
In this way, the output currents Ioutx and Iouty are obtained by performing voltage-to-current conversion on the measurement voltage (Vout1-Vout2) using different conversion gains.

By setting judgment voltages Vdu and Vdl corresponding to the lower and upper limits of the normal range of the measured voltage Vout = Vout1 - Vout2, it is possible to determine whether the voltage difference (Vout1 - Vout2) is within the normal range by comparing each of the judgment voltages Vdu and hVdl with the voltage difference (Vout1 - Vout2).

As in embodiment 1, when Vout = Vout1 - Vout2 = Vdu, the electrical resistance value RDU for making Ioutx = Iref is expressed by the following equation (15) using the electrical resistance value RS (reference current source 40) that determines the reference current Iref.

RDU=(Vdu+Vgs14-Vgs15+Vgs11-Vgs17)/(Vref-Vgs4)・RP...(15)
Similarly, when Vout=Vout1-Vout2=Vdl, the electric resistance value RDL for making Iouty=Iref is expressed by the following equation (16) using the electric resistance value RS (reference current source 40). can be.

RDL=(Vdl+Vgs14-Vgs18+Vgs11-Vgs20)/(Vref-Vgs4)・RP...(16)
By determining the electric resistance value RDU of the resistor element 2306a and the electric resistance value RDL of the resistor element 2309a according to the equations (15) and (16), the voltage difference (Vout1-Vout2 ) can be used as a measurement voltage Vout and compared with each of the determination voltages Vdu and Vdl. As a result, the voltage difference between the two voltages related to the measurement node of the internal circuit is within the normal range determined by the determination voltages Vdu and Vdl. It is possible to determine whether or not the information is included.

As in the first and third embodiments, even in a configuration in which a single node N1a is connected to the current comparator 50 via the selection circuit 30 (FIG. 2 or FIG. 9), it is possible to compare the voltage difference between the first voltage Vout1 and the second voltage Vout2 as the measurement voltage Vout with a single judgment voltage Vdt. In this case, in the voltage-current conversion circuit 24a of FIG. 19, the arrangement of the NMOS transistor 2308a, the resistive element 2309a, and the PMOS transistor 2310a is omitted, and the NMOS transistor 2305a is connected between the node N1a and the node N33, so that the above voltage comparison can be performed. The electrical resistance value of the resistive element 2306a in this case can be obtained by replacing the judgment voltage Vtu with the judgment voltage Vdt in the formula (15).

In addition, in the example of Figure 18, the first voltage Vout1 and the second voltage Vout2 related to the measurement node of the internal circuit 10 are two voltages at the same node at different times, but it is also possible to set the voltages of two different nodes of the internal circuit 10 as the first voltage Vout1 and the second voltage Vout2, and to set the voltage difference between the two internal nodes as the measurement voltage Vout.

In the semiconductor integrated circuit device of embodiment 7, the circuit downstream of nodes N1ax and N1ay (or node N1a) can be the same as any of embodiments 1 to 6. This makes it possible to perform a determination of the difference between the two voltages (voltage difference) related to the internal circuit 10 in the same manner as embodiments 1 to 6, or to perform an abnormality response configuration based on the determination result.

(Modification)
18 and 19, an example in which the first voltage Vout1 and the second voltage Vout2 are the upper limit peak voltage and the lower limit peak voltage of the same node has been described, and therefore an example configuration of the voltage-current conversion circuit 24a assuming that both the determination voltage Vtu (upper limit side) and the determination voltage (lower limit side) are positive voltages has been described. In FIG. 20, as a modified example, an example configuration of the voltage-current conversion circuit 25a for dealing with the case in which the determination voltage Vtu (upper limit side) is a positive voltage while the determination voltage (lower limit side) is a negative voltage will be described with reference to FIG.

As shown in FIG. 20, the voltage-current conversion circuit 25a differs from the voltage-current conversion circuit 24a shown in FIG. 19 in that it further includes a PMOS transistor 2312a, an NMOS transistor 2313a, and current sources 2311a and 2314a, and in that the connection destinations of the gates of the NMOS transistor 2308a and the PMOS transistor 2310a are changed.

The current source 2311a is connected between the power supply line NP and the node N35, and the PMOS transistor 2312a is connected between the node N35 and the ground line NL. The second voltage Vout2 is input to the gate of the PMOS transistor 2312a in common with the gate of the NMOS transistor 2301a.

The NMOS transistor 2313a is connected between the power supply line NP and the node N36, and the current source 2314a is connected between the node N36 and the ground line NL. The first voltage Vout1 is input to the gate of the NMOS transistor 2313a in common with the gate of the PMOS transistor 2304a.

The gate of NMOS transistor 2308 is connected to node N35 where a voltage according to the second voltage Vout2 is generated, and the gate of PMOS transistor 2310a is connected to node N36 where a voltage according to the first voltage Vout1 is generated. Therefore, a voltage according to the voltage difference (Vout2-Vout1) is applied to both ends of resistor element 2309a. As a result, output current Iouty becomes a current obtained by converting the voltage difference (Vout2-Vout1) by a conversion gain according to the electrical resistance value RDL.

20, the polarity (positive/negative) of the conversion gain of the output current Iouty is inverted with respect to the voltage-current conversion circuit 24a. Therefore, overall, it can be understood that the polarity (positive/negative) of the judgment voltage Vdl can be inverted and compared with the voltage difference (Vout1-Vout2) compared to the case where the voltage-current conversion circuit 24a is used.

In this way, by using the voltage-current conversion circuit 25a shown in Figure 20, even if the lower limit of the normal range of the voltage difference (Vout1-Vout2) is a negative voltage, the voltage difference between the first voltage Vout1 and the second voltage Vout2 can be used as the measurement voltage Vout and compared with the judgment voltage, as in embodiments 1 to 6.

This disclosure describes various exemplary embodiments and examples, and the various features, aspects, and functions described in one or more embodiments are not limited to application to a particular embodiment, but may be applied to the embodiments alone or in various combinations.

Therefore, countless variations not illustrated are contemplated within the scope of the technology of this disclosure. For example, this includes modifying, adding, or omitting at least one component, and further including extracting at least one component and combining it with a component of another embodiment.

In addition, in the second and subsequent embodiments, a configuration example has been described in which the measurement voltage Vout is converted into two output currents with different conversion gains and compared with two judgment voltages, but in principle, it is also possible to configure the measurement voltage Vout to be compared with three or more judgment voltages by comparing three or more output currents with different conversion gains with a reference current. For example, in each voltage-current conversion circuit 21, 22, such a configuration can be realized by increasing the number of voltage-current conversion units arranged in parallel as in FIG. 7, or the number of resistor elements and switches (gain switching mechanisms) as in FIG. 9.

In addition, in the above embodiment, the current ratio of each current mirror is 1:1, but other current ratios are also possible. In this case, it is necessary to multiply the electric resistance value RO of the formula (4) by (A/B) using the current ratio A of the output current Iout generated in the current comparator 50 transistor, 51 (nodes N3, N3x, N3y) to the output currents Iout, Ioutx, Iouty of the voltage-current conversion circuit 20, etc., and the current ratio B of the reference current Iref generated in the current comparators 50 to 52, 51 (node N4) to the reference current Iref in the reference current source 40.

In this case, in order to balance Vgs2 and Vgs4 in equation (4), it is preferable to adjust the current and transistor size ratio between NMOS transistor 201a and NMOS transistor 403 in FIG. 2 by adjusting the transistor size. As an example, when (A/B) = 0.5, the electrical resistance value RO is halved and the current flowing through NMOS transistor 201a is doubled, so it is preferable that the transistor size of NMOS transistor 201a is twice that of NMOS transistor 403. For example, by connecting two NMOS transistors having the same transistor size as NMOS transistor 403 in parallel to configure NMOS transistor 201a, the current and transistor size ratio between NMOS transistor 201a and NMOS transistor 403 can be adjusted.

The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is indicated by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

5a to 5g semiconductor integrated circuit device, 9a to 9d control logic circuit, 10a to 10d internal circuit, 11a to 11d first internal circuit, 12a to 12d second internal circuit, 13a upper peak detector, 14a lower peak detector, 15a to 15d, 21, 30, 31, 32 selection circuit, 20a to 20d, 20pa, 21a to 21d, 22a to 22d, 23a to 23d, 24a, 25a voltage-current conversion circuit, 40, 40p reference current source, 50, 50p, 51, 52 current comparator, 60 decision logic circuit, 70 decision result selection circuit, 80a, 80b, 80d recording device, 207a enable switch, 208a transistor switch, 230a, 407 operational amplifier buffer, 801a first latch circuit, 802a second latch circuit, Aa, /Aa, Schg control signals, ENa to ENDd enable signals, GND ground voltage, Iol, Iou, Iout, Ioutx, Iouty output current, Iref reference current, NL ground line, NP power supply line, S11a, S12a latch data, Sjd judgment signal, VDD power supply voltage, Vout measurement voltage, Vout1 first voltage, Vout2 second voltage, Vref reference voltage.

Claims (14)

A plurality of voltage-current conversion circuits are provided,
each of the plurality of voltage-current conversion circuits is configured to perform voltage-to-current conversion of a measurement voltage corresponding to a voltage of at least one measurement node inside the semiconductor integrated circuit device in accordance with a first conversion gain reflecting a determination voltage to be compared with the measurement voltage, to generate at least one output current;
A reference current source that outputs a predetermined reference current;
a current comparator that outputs at least one determination signal according to a comparison result between the at least one output current input from a voltage-to-current conversion circuit selected from the plurality of voltage-to-current conversion circuits and the reference current. Each of the voltage-current conversion circuits includes a plurality of voltage-current conversion units each having a different first conversion gain,
the plurality of voltage-to-current conversion units convert the measurement voltages according to the respective first conversion gains to generate the plurality of output currents;
The plurality of output currents generated by the plurality of voltage-to-current conversion units of the selected voltage-to-current conversion circuit are input one by one in sequence to the current comparator;
2. The semiconductor integrated circuit device according to claim 1, wherein the current comparator is configured to output the determination signal according to a result of comparison between one of the plurality of output currents input from the selected voltage-to-current conversion circuit and the reference current. Each of the voltage-current conversion circuits includes:
a gain switching mechanism for switching the first conversion gain between a plurality of gains;
the selected voltage-current conversion circuit sequentially outputs the plurality of output currents, each of which corresponds to the plurality of first conversion gains switched by the gain switching mechanism, one by one;
2. The semiconductor integrated circuit device according to claim 1, wherein the current comparator is configured to output the determination signal according to a result of comparison between one of the plurality of output currents input from the selected voltage-to-current conversion circuit and the reference current. Each of the voltage-current conversion circuits includes a plurality of voltage-current conversion units each having a different first conversion gain,
the plurality of voltage-to-current conversion units convert the measurement voltages according to the respective first conversion gains to generate the plurality of output currents;
The output currents generated by the voltage-to-current conversion units are input in parallel to the current comparator;
2. The semiconductor integrated circuit device according to claim 1, wherein said current comparator is configured to output a plurality of said determination signals according to a result of comparing each of said plurality of output currents input from said plurality of voltage-to-current conversion units with said reference current. The semiconductor integrated circuit device of claim 4, further comprising a decision logic circuit that generates a signal indicating a logical operation result of the plurality of decision signals. A semiconductor integrated circuit device according to any one of claims 1 to 5, wherein the voltage-to-current conversion circuit generates the at least one output current using the voltage of one of the measurement nodes as the measurement voltage. A semiconductor integrated circuit device according to any one of claims 1 to 5, wherein the voltage-to-current conversion circuit generates the at least one output current using the voltage difference between a first voltage and a second voltage at one of the measurement nodes at different timings as the measurement voltage. The semiconductor integrated circuit device of claim 7, wherein the first voltage and the second voltage are a maximum peak value and a minimum peak value of the voltage of the one measurement node. A semiconductor integrated circuit device according to any one of claims 1 to 5, wherein the voltage-current conversion circuit generates the at least one output current using the voltage difference between the two measurement nodes as the measurement voltage. the reference current source is configured to generate the reference current by performing voltage-to-current conversion on a predetermined reference voltage in accordance with a second predetermined conversion gain;
10. The semiconductor integrated circuit device according to claim 1, wherein the first conversion gain in each of the voltage-to-current conversion circuits is determined using a ratio between the determination voltage and the reference voltage, and the second conversion gain. A semiconductor integrated circuit device according to any one of claims 1 to 9, wherein the first conversion gain is set so that the output current and the reference current are equivalent when the measurement voltage is equivalent to the determination voltage. The semiconductor integrated circuit device is
a selection circuit having a plurality of switches connected between the plurality of voltage-to-current conversion circuits and the current comparator;
12. The semiconductor integrated circuit device according to claim 1, wherein in the selection circuit, a part of the plurality of switches connected between the selected voltage-to-current conversion circuit and the current comparator is selectively turned on. Each of the plurality of voltage-to-current conversion circuits has an enable switch connected in a path of the at least one output current,
12. The semiconductor integrated circuit device according to claim 1, wherein the enable switch is turned on in the selected voltage-to-current conversion circuit. The semiconductor integrated circuit device is
a first internal circuit having a predetermined function;
a second internal circuit having the same function as the first internal circuit;
a measurement selection circuit for selectively inputting one of the measurement voltage related to the first internal circuit and the measurement voltage related to the second internal circuit to the voltage-current conversion circuit;
a first storage circuit for storing first information related to the determination signal output from the current comparator when the measurement voltage related to the first internal circuit is input to the voltage-current conversion circuit by the measurement selection circuit;
a second storage circuit for storing second information related to the determination signal output from the current comparator when the measurement voltage related to the second internal circuit is input to the voltage-current conversion circuit by the measurement selection circuit;
The semiconductor integrated circuit device according to any one of claims 1 to 13, further comprising an output selection circuit for operating the semiconductor integrated circuit device using the output of the second internal circuit when a fault occurs in the first internal circuit, based on the first information and the second information stored in the first memory circuit and the second memory circuit, and for operating the semiconductor integrated circuit device using the output of the first internal circuit when a fault occurs in the second internal circuit.

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