JP7563285B2 - Semiconductor Device - Google Patents

Description

This disclosure relates to a semiconductor device.

A power module may include a circuit board on which electronic components are mounted, a heat sink for removing heat from the circuit board, and a casing with the circuit board sandwiched between the heat sink (see, for example, Patent Document 1). The casing includes a support member that supports the heat sink, and a casing body that holds the support member. According to Patent Document 1, a first screw insertion hole formed in the support member and a second screw insertion hole formed in the casing body are aligned on the same axis to facilitate attachment to a mating material.

JP 2018-163914 A

During the manufacture of a semiconductor device, terminals (bus bars) are joined to the circuit pattern of the substrate. If the joining between the terminals and the circuit pattern is insufficient, or if excessive stress is applied to the components that make up the semiconductor device during joining, this will ultimately result in a decrease in the reliability of the semiconductor device.

Therefore, one of the objectives is to provide a semiconductor device that can improve reliability.

The semiconductor device according to the present disclosure includes a base plate having a first through hole penetrating in the thickness direction and including a first surface located on one side in the thickness direction, a substrate including a circuit pattern and disposed on the first surface, a semiconductor chip disposed on the circuit pattern, a frame body including a second surface opposite to the first surface and disposed on the first surface so as to surround the outer periphery of the substrate, and a terminal attached to the frame body and electrically connected to the circuit pattern. The frame body has a second through hole penetrating in the thickness direction of the base plate and disposed so as to coincide with the position of the first through hole when disposed on the first surface. The frame body includes a metal ring-shaped member attached to the second through hole and having a third through hole penetrating in the thickness direction of the base plate. The ring-shaped member includes a first region disposed in the second through hole and a second region protruding from the second surface. The outer diameter of the second region becomes smaller as it approaches the tip. The minimum diameter _D2 of the outer diameter surface of the second region is smaller than the diameter _D1 of the first through hole. The maximum diameter _D3 of the outer diameter surface of the second region is larger than the diameter _D1 of the first through hole. In the thickness direction of the base plate, the end of the first side wall surface constituting the first through hole on the first surface side is in contact with the outer diameter surface of the second region. The end of the annular member on the first surface side is within the first through hole.

The above semiconductor device can improve reliability.

FIG. 1 is a schematic perspective view of a semiconductor device according to a first embodiment. FIG. 2 is a schematic plan view of the semiconductor device shown in FIG. 1 as viewed in the thickness direction of the base plate. FIG. 3 is an exploded perspective view of the semiconductor device shown in FIG. 1 before assembly. FIG. 4 is an exploded side view of the semiconductor device shown in FIG. 1 before assembly. FIG. 5 is a schematic cross-sectional view showing a part of the semiconductor device shown in FIG. FIG. 6 is an enlarged cross-sectional view of the annular member. FIG. 7 is a flow chart showing typical steps of a method for manufacturing the semiconductor device according to the first embodiment shown in FIG. FIG. 8 is a schematic cross-sectional view showing a part of the frame placed on the base plate. FIG. 9 is a graph showing the relationship between the force required for press-fitting and the amount of press-fitting. FIG. 10 is a schematic cross-sectional view showing a part of a semiconductor device in the second embodiment.

[Description of the embodiments of the present disclosure]
First, the embodiments of the present disclosure will be listed and described. The semiconductor device according to the present disclosure includes a base plate having a first through hole penetrating in the thickness direction and including a first surface located on one side in the thickness direction, a substrate including a circuit pattern and disposed on the first surface, a semiconductor chip disposed on the circuit pattern, a frame body including a second surface opposite to the first surface and disposed on the first surface so as to surround the outer periphery of the substrate, and a terminal attached to the frame body and electrically connected to the circuit pattern. The frame body has a second through hole penetrating in the thickness direction of the base plate and disposed so as to coincide with the position of the first through hole when disposed on the first surface. The frame body includes a metal ring-shaped member attached to the second through hole and having a third through hole penetrating in the thickness direction of the base plate. The ring-shaped member includes a first region disposed in the second through hole and a second region protruding from the second surface. The outer diameter of the outer diameter surface of the second region becomes smaller as it approaches the tip. The minimum diameter _D2 of the outer diameter surface of the second region is smaller than the diameter _D1 of the first through hole. The maximum diameter _D3 of the outer diameter surface of the second region is larger than the diameter _D1 of the first through hole. In the thickness direction of the base plate, the end of the first side wall surface constituting the first through hole on the first surface side is in contact with the outer diameter surface of the second region. The end of the annular member on the first surface side is within the first through hole.

In manufacturing a semiconductor device, a method may be adopted in which a frame body to which terminals are attached and a base plate to which a substrate having a circuit pattern on which a semiconductor chip is mounted is first prepared, the frame body is attached to the base plate, and then the terminals and the circuit pattern are joined. In particular, when a high reliability of a semiconductor device is required, such as for in-vehicle use, it is necessary to reliably join the terminals and the circuit pattern, and ultrasonic joining may be adopted. When performing this ultrasonic joining, when pressing an ultrasonic joining tool against the area where the terminals and the circuit pattern contact each other, it is necessary to appropriately set the positional relationship between the terminals and the circuit pattern, especially the positional relationship regarding height. In other words, it is required to position the distance between the terminals and the circuit pattern with high accuracy. If the accuracy of this distance is low, the joining strength may be weakened or excessive stress may be applied to the base plate or the frame body. This may lead to a decrease in the joining strength between the terminals and the circuit pattern, and a decrease in the reliability of the semiconductor device due to the stress applied to the base plate or the frame body. Here, each component constituting the semiconductor device has a dimensional error, and as each component is attached, the error accumulates. Furthermore, when considering the effects of warping of the base plate during ultrasonic bonding, it is difficult to achieve high-precision positioning using a method that requires precise finishing of the dimensions of each component.

According to the semiconductor device of the present disclosure, an annular member including a first region disposed in the second through hole and a second region protruding from the second surface is attached to the frame body. The outer diameter of the second region is smaller as it approaches the tip. The minimum diameter _D2 of the outer diameter of the second region is smaller than the diameter _D1 of the first through hole. The maximum diameter _D3 of the outer diameter of the second region is larger than the diameter _D1 of the first through hole. Therefore, with the second region of the annular member in the first through hole of the base plate, the frame body is pressed against the base plate and pressed in, making it easy to set the distance between the terminal and the circuit pattern to an appropriate distance. In this case, since the outer diameter of the outer diameter of the second region is smaller as it approaches the tip, the amount of press-in can be adjusted to accurately position the terminal and the circuit pattern before bonding. Then, the terminal and the circuit pattern are bonded to each other, and the terminal and the circuit pattern can be appropriately bonded to each other while suppressing excessive stress from being applied to the base plate and the frame body. As a result, the reliability of such a semiconductor device can be improved.

In the above semiconductor device, the outer diameter surface of the second region may be tapered. This makes it possible to more reliably press the annular member into the first through hole and reliably bond the terminal to the circuit pattern.

In the semiconductor device, the difference between the diameter _D1 of the first through hole and the minimum diameter _D2 of the outer diameter surface of the second region may be 0.5 mm or more and 1 mm or less. By doing so, during the manufacture of the semiconductor device, interference between the outer diameter surface of the second region and the side wall surface constituting the first through hole can be suppressed, making it easier to insert the annular member including the protruding second region into the first through hole. Therefore, the semiconductor device can be manufactured more easily.

In the semiconductor device, the difference between the diameter _D1 of the first through hole and the maximum diameter _D3 of the outer diameter surface of the second region may be 2 mm or more. This makes it easier for the end of the sidewall surface constituting the first through hole on the first surface side to come into contact with the outer diameter surface of the second region. Therefore, the semiconductor device can be manufactured more reliably.

In the above semiconductor device, the circuit pattern may be joined to the terminal by melting a portion of the terminal. Such joining can be performed, for example, by ultrasonic joining. Therefore, the terminal and the circuit pattern can be reliably electrically connected without using adhesives or joining materials.

In the above semiconductor device, the semiconductor chip may include a semiconductor layer made of at least one of SiC (silicon carbide), GaN (gallium nitride), and Si (silicon). By including a semiconductor layer made of SiC or GaN, the semiconductor chip can be used as a wide band gap semiconductor chip. Furthermore, by including a semiconductor layer made of Si, the semiconductor chip can be made highly versatile.

In the above semiconductor device, the base plate may be rectangular when viewed in the thickness direction. Four first through holes may be provided corresponding to the four corners of the rectangular base plate. Four second through holes may be provided corresponding to the four first through holes. Four annular members may be attached corresponding to the four second through holes. In this way, in a semiconductor device including a rectangular base plate, the four annular members, the four first through holes, and the four second through holes can more appropriately bond the terminals and the circuit pattern. Therefore, a more reliable semiconductor device can be obtained.

In the above semiconductor device, the four annular members may protrude from the second surface by an equal amount. In this way, each annular member can be press-fitted evenly.

In the above semiconductor device, the amount of protrusion from the second surface of at least one of the four annular members may be different from the amount of protrusion from the second surface of the other annular members. By doing so, after placing the most protruding annular member in the corresponding first through hole, it becomes easy to use this as a reference to place the other annular members in the other first through holes. Therefore, the above semiconductor device can be manufactured more easily.

[Details of the embodiment of the present disclosure]
Next, an embodiment of a semiconductor device according to the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference characters and their description will not be repeated.

(Embodiment 1)
The configuration of a semiconductor device in a first embodiment of the present disclosure will be described. FIG. 1 is a schematic perspective view of the semiconductor device in the first embodiment. FIG. 2 is a schematic plan view of the semiconductor device shown in FIG. 1 when viewed in the thickness direction of a base plate. FIG. 3 is an exploded perspective view of the semiconductor device shown in FIG. 1 before assembly. FIG. 4 is an exploded side view of the semiconductor device shown in FIG. 1 before assembly. FIG. 5 is a schematic cross-sectional view showing a part of the semiconductor device shown in FIG. 1. FIG. 5 is a schematic cross-sectional view taken along line V-V in FIG. 2, and is a schematic cross-sectional view of a region including an annular member described later.

1, 2, 3, 4 and 5, the semiconductor device 11a in the first embodiment includes a base plate 12, a frame 13 arranged on the base plate 12, substrates 17a and 17b arranged on the base plate 12, plate-shaped terminals (bus bars) 19a, 19b, 19c and 19d, capacitors 18a and 18b, semiconductor chips 21a, 21b, 21c, 21d, 21e, 21f, 22a, 22b, 22c, 22d, 22e and 22f, and press-fit pins 26a, 26b, 26c, 26d, 26e, 26f, 26g and 26h. The base plate 12 and the frame 13 form a case 20 provided in the semiconductor device 11a. A space 30 in the case 20 formed by the base plate 12 and the frame 13 is filled with resin (not shown). The type of resin selected may be, for example, epoxy resin, silicone gel, or urethane resin.

The base plate 12 is made of metal. The base plate 12 is made of copper, for example. The surface of the base plate 12 may be plated with nickel or the like. The outer shape of the base plate 12 is a rectangle with the long side extending in the X direction and the short side extending in the Y direction when viewed in the thickness direction. The substrates 17a and 17b are each joined to the first surface 12a located on one side of the thickness direction of the base plate 12 by solder or the like (not shown). For example, a heat dissipation fin (not shown) for efficient heat dissipation may be attached to the back surface 12b located on the other side of the thickness direction of the base plate 12. The thickness direction of the base plate 12 and the thickness directions of the substrates 17a and 17b are the Z direction. The height direction of the semiconductor device 11a is indicated by the Z direction.

The base plate 12 has four first through holes 12c, 12d, 12e, and 12f that penetrate the base plate 12 in the thickness direction. The first through holes 12c, 12d, 12e, and 12f are provided in the portions close to the four corners of the rectangular base plate 12. The first side wall surfaces 12g, 12h, 12i, and 12j that constitute the first through holes 12c, 12d, 12e, and 12f each have a straight shape extending along the Z direction. That is, the first through holes 12c, 12d, 12e, and 12f are each formed so as to penetrate straight through the regions close to the four corners of the base plate 12 in the Z direction. The first through holes 12c, 12d, 12e, and 12f, together with the annular members 41a, 41b, 41c, and 41d having the second through holes 32a, 32b, 32c, and 32d and the third through holes 42a, 42b, 42c, and 42d described below, are effectively used when mounting the semiconductor device 11a at a specified installation location, for example by accommodating the body of a bolt (not shown) in the third through holes 42a, 42b, 42c, and 42d.

The substrate 17a has an insulating plate 14a having insulating properties and a circuit pattern 16a having electrical conductivity. The circuit pattern 16a is disposed on the insulating plate 14a. The substrate 17a is configured by stacking the circuit pattern 16a on the insulating plate 14a. The circuit pattern 16a is composed of a plurality of circuit boards. In this embodiment, the circuit pattern 16a includes a first circuit board 15a, a second circuit board 15b, a third circuit board 15c, a fourth circuit board 15d, a fifth circuit board 15e, and a sixth circuit board 15f. In this embodiment, the circuit pattern 16a is copper wiring. Like the substrate 17a, the substrate 17b has an insulating plate 14b having insulating properties and a circuit pattern 16b which is copper wiring. The circuit pattern 16b includes a seventh circuit board 15g, an eighth circuit board 15h, a ninth circuit board 15i, a tenth circuit board 15j, and an eleventh circuit board 15k.

Capacitor 18a includes one electrode and the other electrode. One electrode is joined to fifth circuit board 15e, and the other electrode is joined to sixth circuit board 15f. Capacitor 18b similarly includes one electrode and the other electrode, and one electrode is joined to tenth circuit board 15j, and the other electrode is joined to eleventh circuit board 15k.

The semiconductor chips 21a, 21b, 21c, 22a, 22b, and 22c are arranged on the first circuit board 15a. The semiconductor chips 21d, 21e, 21f, 22d, 22e, and 22f are arranged on the seventh circuit board 15g. The semiconductor chips 21a, 21b, 21c, 21d, 21e, 21f, 22a, 22b, 22c, 22d, 22e, and 22f are wide band gap semiconductor chips. A wide band gap semiconductor chip is a semiconductor chip having a semiconductor layer made of a material whose band gap is larger than that of silicon as an operating layer. The wide band gap semiconductor chip has a semiconductor layer made of, for example, silicon carbide, gallium nitride, or gallium oxide as an operating layer. Such a wide band gap semiconductor chip has a high breakdown voltage and can reduce the resistance of the drift layer, thereby reducing the on-resistance. The semiconductor chips 21a, 21b, 21c, 21d, 21e, and 21f are, for example, Schottky barrier diodes (SBDs). The semiconductor chips 22a, 22b, 22c, 22d, 22e, and 22f are, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs).

The frame body 13 rises from the first surface 12a of the base plate 12 and is attached to the base plate 12 so as to surround the outer periphery of the substrates 17a and 17b when viewed in the thickness direction of the base plate 12. The frame body 13 includes a second surface 13e that faces the first surface 12a. The frame body 13 is fixed to the base plate 12 by, for example, an adhesive. That is, the first surface 12a of the base plate 12 and the second surface 13e of the frame body 13 are bonded together.

The frame body 13 includes a first wall portion 13a, a second wall portion 13b, a third wall portion 13c, and a fourth wall portion 13d. The first wall portion 13a and the second wall portion 13b are arranged opposite each other in a direction (Y direction) corresponding to the short side of the base plate 12 when viewed in the thickness direction of the base plate 12. The third wall portion 13c and the fourth wall portion 13d are arranged opposite each other in a direction (X direction) corresponding to the long side of the base plate 12 when viewed in the thickness direction of the base plate 12. The first wall portion 13a, the second wall portion 13b, the third wall portion 13c, and the fourth wall portion 13d included in the frame body 13 each rise in a direction intersecting the first surface 12a. Specifically, the first wall portion 13a, the second wall portion 13b, the third wall portion 13c, and the fourth wall portion 13d each rise perpendicularly to the first surface 12a. The frame 13 includes an inner wall surface 27a of the first wall portion 13a, an inner wall surface 27b of the third wall portion 13c that faces the inner wall surface 27a, an inner wall surface 27c of the second wall portion 13b that is continuous with the inner wall surface 27a and the inner wall surface 27b, and an inner wall surface 27d of the fourth wall portion 13d that is continuous with the inner wall surface 27a and the inner wall surface 27b and faces the inner wall surface 27c.

The frame 13 is made of a material with high insulating properties and strength, such as PPS (Polyphenylene Sulfide) resin. This type of resin is a thermoplastic resin that has good moldability, excellent insulating properties, moisture resistance, and heat resistance, and is also strong. Alternatively, PBT (Poly Butylene Terephthalate) resin may be used as the material for the frame 13. The specific configuration of the frame 13 will be described in detail later.

The terminals (bus bars) 19a, 19b, 19c, and 19d are each plate-shaped and made of metal. The terminals 19a, 19b, 19c, and 19d are each attached to the frame 13. Specifically, the terminals 19a and 19b are attached to the third wall 13c. The terminals 19c and 19d are attached to the fourth wall 13d. In this embodiment, the terminals 19a, 19b, 19c, and 19d are attached to the frame 13 by insert molding. The terminals 19a, 19b, 19c, and 19d each have a curved belt-like shape. In this embodiment, the terminals 19a, 19b, 19c, and 19d are each formed by bending a belt-shaped copper plate, for example. The semiconductor device 11a ensures electrical connection to the outside through the terminals 19a, 19b, 19c, and 19d.

The terminal 19a and the first circuit board 15a are directly joined by ultrasonic bonding. The terminal 19b and the second circuit board 15b are directly joined by ultrasonic bonding. The terminal 19c and the seventh circuit board 15g are directly joined by ultrasonic bonding. The terminal 19d and the seventh circuit board 15g are directly joined by ultrasonic bonding. An example of the areas 23a, 23b, 23c, and 23d against which the ultrasonic bonding tool is pressed when joining the terminals 19a, 19b, 19c, and 19d is shown by the dashed lines in FIG. 2.

The semiconductor chip 21a and the semiconductor chip 22a are connected by wire 24a. The semiconductor chip 21b and the semiconductor chip 22b are connected by wire 24b. The semiconductor chip 21c and the semiconductor chip 22c are connected by wire 24c. The semiconductor chip 21d and the semiconductor chip 22d are connected by wire 24d. The semiconductor chip 21e and the semiconductor chip 22e are connected by wire 24e. The semiconductor chip 21f and the semiconductor chip 22f are connected by wire 24f. The semiconductor chip 22a and the fourth circuit board 15d are connected by wire 25a. The semiconductor chip 22b and the fourth circuit board 15d are connected by wire 25b. The semiconductor chip 22c and the fourth circuit board 15d are connected by wire 25c. The semiconductor chip 22d and the eighth circuit board 15h are connected by wire 25d. The semiconductor chip 22e and the eighth circuit board 15h are connected by wire 25e. The semiconductor chip 22f and the eighth circuit board 15h are connected by wire 25f.

The second circuit board 15b and the eighth circuit board 15h are connected by wire 29a. The fourth circuit board 15d and the seventh circuit board 15g are connected by wire 29b. The semiconductor chips 22a, 22b, and 22c are each connected to the third circuit board 15c by wire 28a, and the semiconductor chips 22d, 22e, and 22f are each connected to the ninth circuit board 15i by wire 28b. The wires may be thick aluminum wires or ribbon wires.

The press-fit pins 26a, 26b, 26c, 26d, 26e, 26f, 26g, and 26h are provided to ensure electrical connection with the outside. The press-fit pins 26a, 26b, 26c, 26d, 26e, 26f, 26g, and 26h are each conductive and rod-shaped. The press-fit pins 26a, 26b, 26c, 26d, 26e, 26f, 26g, and 26h are attached to the circuit patterns 16a and 16b so as to rise from the circuit patterns 16a and 16b, respectively. Specifically, one end of the press-fit pin 26a is joined to the third circuit board 15c. One end of the press-fit pin 26b is joined to the fourth circuit board 15d. One end of the press-fit pin 26c is joined to the fifth circuit board 15e. One end of the press-fit pin 26d is joined to the sixth circuit board 15f. One end of the press-fit pin 26e is joined to the ninth circuit board 15i. One end of the press-fit pin 26f is joined to the eighth circuit board 15h. One end of the press-fit pin 26g is joined to the tenth circuit board 15j. One end of the press-fit pin 26h is joined to the eleventh circuit board 15k. The press-fit pins 26a, 26b, 26c, and 26d joined to the circuit pattern 16a are spaced apart from each other in the X direction. The press-fit pins 26e, 26f, 26g, and 26h joined to the circuit pattern 16b are spaced apart from each other in the X direction. The other end of each of the press-fit pins 26a, 26b, 26c, 26d, 26e, 26f, 26g, and 26h is a free end and is in a free state. The extension direction of the press-fit pins 26a, 26b, 26c, 26d, 26e, 26f, 26g, and 26h is the Z direction.

Next, the specific configuration of the frame body 13 will be described. The frame body 13 includes a first flat plate portion 31a, a second flat plate portion 31b, a third flat plate portion 31c, and a fourth flat plate portion 31d. The first flat plate portion 31a and the second flat plate portion 31b are provided in a continuous manner with the third wall portion 13c. The first flat plate portion 31a is provided on the outside of the third wall portion 13c, that is, on the opposite side to the side where the space 30 is located in the X direction, and is provided in a continuous manner with the first wall portion 13a. The second flat plate portion 31b is provided on the outside of the third wall portion 13c, that is, on the opposite side to the side where the space 30 is located in the X direction, and is provided in a continuous manner with the second wall portion 13b. The third flat plate portion 31c and the fourth flat plate portion 31d are provided in a continuous manner with the fourth wall portion 13d. The third flat plate portion 31c is provided on the outside of the fourth wall portion 13d, i.e., on the opposite side in the X direction from the side where the space 30 is located, and is connected to the second wall portion 13b. The fourth flat plate portion 31d is provided on the outside of the fourth wall portion 13d, i.e., on the opposite side in the X direction from the side where the space 30 is located, and is connected to the first wall portion 13a. The frame body 13 includes a surface 13f located on the opposite side to the second surface 13e in the thickness direction of the base plate 12. The surface 13f is provided on the first flat plate portion 31a, the second flat plate portion 31b, the third flat plate portion 31c, and the fourth flat plate portion 31d.

The frame body 13 has four second through holes 32a, 32b, 32c, 32d that penetrate the base plate 12 in the thickness direction. The second through holes 32a, 32b, 32c, 32d are provided in the first flat plate portion 31a, the second flat plate portion 31b, the third flat plate portion 31c, and the fourth flat plate portion 31d, respectively. The second side wall surfaces 33a, 33b, 33c, 33d that constitute the second through holes 32a, 32b, 32c, 32d are each straight in shape extending along the Z direction. The second through holes 32a, 32b, 32c, 32d are formed so as to penetrate the first flat plate portion 31a, the second flat plate portion 31b, the third flat plate portion 31c, and the fourth flat plate portion 31d, respectively, in the Z direction. The second through holes 32a, 32b, 32c, and 32d are positioned so as to coincide with the positions of the first through holes 12c, 12d, 12e, and 12f when the frame body 13 is placed on the first surface 12a.

The frame body 13 includes four metal ring-shaped members 41a, 41b, 41c, and 41d having third through holes 42a, 42b, 42c, and 42d penetrating in the thickness direction of the base plate 12. The third through holes 42a, 42b, 42c, and 42d are provided in the ring-shaped members 41a, 41b, 41c, and 41d, respectively. The third side wall surfaces 43a, 43b, 43c, and 43d constituting the third through holes 42a, 42b, 42c, and 42d are each straight in shape extending along the Z direction. The four ring-shaped members 41a, 41b, 41c, and 41d are each solid cylindrical. The four ring-shaped members 41a, 41b, 41c, and 41d are attached to the second through holes 32a, 32b, 32c, and 32d, respectively. The third through holes 42a, 42b, 42c, and 42d are formed so as to penetrate straight in the Z direction when attached to the second through holes 32a, 32b, 32c, and 32d, respectively. The annular members 41a, 41b, 41c, and 41d are also called collars.

The configuration of the annular member 41a will now be described. The configurations of the annular members 41b, 41c, and 41d are similar to that of the annular member 41a, and therefore will not be described. Figure 6 is an enlarged cross-sectional view of the annular member 41a. The cross-section shown in Figure 6 corresponds to the cross-section shown in Figure 5. To facilitate understanding, the second surface 13e is indicated by a dashed line.

Referring also to FIG. 6, the annular member 41a includes a first region 44a disposed within the second through-hole 32a and a second region 45a protruding from the second surface 13e. An end 46a on one side of the annular member 41a disposed on the base plate 12 side protrudes from the second surface 13e. In addition, in the Z direction, the position of the end 47a on the other side of the annular member 41a is aligned with the position of the surface 13f located on the opposite side to the second surface 13e in the thickness direction. In the Z direction, the position of the end 47a is the same as the position of the surface 13f. In this embodiment, both the ends 46a and 47a are planes parallel to the X-Y plane.

The annular member 41a includes an outer diameter surface 51a of the first region 44a and an outer diameter surface 52a of the second region 45a. The outer diameter surface 51a of the first region 44a includes a straight shape. That is, the outer diameter surface 51a of the first region 44a includes a shape that extends straight in the Z direction. The outer diameter surface 52a of the second region 45a has a smaller outer diameter as it approaches the tip. In this embodiment, the outer diameter surface 52a of the second region 45a is tapered. The angle θ between the outer diameter surface 51a of the first region 44a and the outer diameter surface 52a of the second region 45a is 30°. Note that this angle θ can be any value equal to or less than 45°. The boundary 53a between the straight shape and the tapered shape is located in the first region 44a.

The minimum diameter _D2 of the outer diameter surface 52a of the second region 45a is smaller than the diameter _D1 of the first through hole 12c. The maximum diameter _D3 of the outer diameter surface 52a of the second region 45a is larger than the diameter of the first through hole 12c. In the thickness direction of the base plate 12, the end 12k on the first surface 12a side of the first side wall surface 12g constituting the first through hole 12c is in contact with the outer diameter surface 52a of the second region 45a. The end 46a on the first surface 12a side of the annular member 41a is inside the first through hole 12c. In the thickness direction of the base plate 12, the end 46a on the first surface 12a side of the annular member 41a is located closer to the back surface 12b than the first surface 12a.

The difference between the diameter _D1 of the first through hole 12c and the minimum diameter _D2 of the outer diameter surface 52a of the second region 45a is 0.5 mm or more and 1 mm or less. In this embodiment, specifically, the difference between the diameter _D1 of the first through hole 12c and the minimum diameter _D2 of the outer diameter surface 52a of the second region 45a is 0.5 mm. The difference between the diameter _D1 of the first through hole and the maximum diameter _D3 of the outer diameter surface of the second region is 2 mm or more. Specifically, the difference between the diameter _D1 of the first through hole and the maximum diameter _D3 of the outer diameter surface of the second region is 2 mm.

Next, an example of a method for manufacturing such semiconductor device 11a will be briefly described. Figure 7 is a flow chart showing typical steps of the method for manufacturing semiconductor device 11a in embodiment 1 shown in Figure 1. Referring to Figure 7, in the method for manufacturing semiconductor device 11a in embodiment 1, a frame and base plate preparation step is first carried out as step (S10). In this step (S10), first, the base plate 12 having the above-described configuration is prepared, in which the substrates 17a, 17b, capacitors 18a, 18b, semiconductor chips 21a, 21b, 21c, 21d, 21e, 21f, 22a, 22b, 22c, 22d, 22e, 22f, wires 24a, 24b, 24c, 24d, 24e, 24f, 25a, 25b, 25c, 25d, 25e, 25f, 28a, 28b, 29a, 29b and press-fit pins 26a, 26b, 26c, 26d, 26e, 26f, 26g, 26h are attached and the four first through holes 12c, 12d, 12e, 12f are provided. In addition, a frame 13 having the above configuration is prepared, in which four second through holes 32a, 32b, 32c, and 32d are provided and terminals 19a, 19b, 19c, and 19d and annular members 41a, 41b, 41c, and 41d are attached. That is, the manufacturing method of the semiconductor device 11a includes a step of preparing the frame 13 and the base plate 12.

Next, as a step (S20), a frame body placing step is performed. Fig. 8 is a schematic cross-sectional view showing a part of the state in which the frame body 13 is placed on the base plate 12. In Fig. 8, from the viewpoint of facilitating understanding, the state in which the frame body 13 is placed on the base plate 12 is shown on the left side, and the state shown in Fig. 5 is shown on the right side. With reference to Fig. 8 as well, in this step (S20), the frame body 13 is placed on the base plate 12. Here, the frame body 13 is placed on the base plate 12 so that the second regions 45a of the annular members 41a, 41b, 41c, and 41d are disposed in the first through holes 12c, 12d, 12e, and 12f. At this time, the outer diameter surface 52a of each of the second regions 45a of the annular members 41a, 41b, 41c, and 41d contacts the end portions 12k of the first through holes 12c, 12d, 12e, and 12f on the first surface 12a side, and the other portions are not in contact. In this case, since the dimensional relationship of the diameters _D1 , _D2 , and _D3 is as described above, the semiconductor device 11a can be easily placed as described above. Here, in the Z direction, a gap _S1 is formed between the terminal 19a and the circuit pattern 16a, specifically, between the terminal 19a and the third circuit board 15c of the circuit pattern 16a. The length _G1 of this gap _S1 in the Z direction may be increased or decreased depending on the dimensional relationship of each component constituting the semiconductor device 11a, manufacturing errors, etc. That is, the manufacturing method of the semiconductor device 11a includes a process of placing the frame 13 on the base plate 12 after the above-mentioned preparation process.

After that, a frame press-in process is carried out as a process (S30). In this process (S30), the frame 13 is pushed toward the base plate 12, and the second regions 45a of the annular members 41a, 41b, 41c, and 41d are pressed into the first through holes 12c, 12d, 12e, and 12f. In this case, with the base plate 12 fixed in the Z direction, the frame 13 is pushed in the direction opposite to the direction indicated by the arrow Z. Then, the annular members 41a, 41b, 41c, and 41d are pushed forward, and the second regions 45a gradually enter the first through holes 12c, 12d, 12e, and 12f. That is, the manufacturing method of the semiconductor device 11a includes a process of pressing in the frame 13 after the above-described placing process.

FIG. 9 is a graph showing the relationship between the force required for press-in and the amount of press-in. In FIG. 9, the vertical axis shows the force required for press-in, and the horizontal axis shows the stroke, which is the amount of press-in. In FIG. 9, as the force required for press-in is applied, the amount of press-in increases. Then, until the intersection point of pressure P ₁ and stroke L ₁ is reached, the pressure increases in proportion to the stroke. Then, when the intersection point M is reached, the force required to push forward by the same stroke becomes large. Here, it can be understood that the force becomes large because the terminal 19a and the circuit pattern 16a come into contact with each other. That is, it can be understood that the terminal 19a and the circuit pattern 16a are in an appropriate contact state. At this point, the frame body press-in process is completed.

Next, a bonding step is carried out as step (S40). In this step (S40), the terminal 19a and the circuit pattern 16a are bonded. In this case, the terminal 19a and the circuit pattern 16a are bonded by ultrasonic bonding. The other terminals 19b, 19c, and 19d and the circuit patterns 16a and 16b are also ultrasonically bonded. In other words, the manufacturing method of the semiconductor device 11a includes a step of bonding the terminals 19a, 19b, 19c, and 19d and the circuit patterns 16a and 16b after the above-mentioned press-fitting step.

After that, a resin injection step is carried out as step (S50). In this step (S50), a thermosetting resin is poured into the space 30 formed by the frame body 13 and the base plate 12. That is, the manufacturing method of the semiconductor device 11a includes a step of injecting the resin after the above-mentioned joining step. Next, a resin hardening step is carried out as step (S60). In this step (S60), the injected resin is hardened by heating or the like. Then, the space 30 surrounded by the base plate 12 and the frame body 13 is sealed. That is, the manufacturing method of the semiconductor device 11a includes a step of hardening the resin after the above-mentioned injection step. In this manner, the semiconductor device 11a is manufactured.

In the semiconductor device 11a, annular members 41a, 41b, 41c, and 41d including a first region 44a disposed in the second through holes 32a, 32b, 32c, and 32d and a second region 45a protruding from the second surface 13e are attached to the frame 13. The outer diameter of the outer surface 52a of the second region 45a decreases toward the tip. The minimum diameter _D2 of the outer surface 52a of the second region 45a is smaller than the diameter _D1 of the first through holes 12c, 12d, 12e, and 12f. The maximum diameter _D3 of the outer surface 52a of the second region 45a is larger than the diameter _D1 of the first through holes 12c, 12d, 12e, and 12f. Therefore, with the second regions 45a of the annular members 41a, 41b, 41c, 41d in the first through holes 12c, 12d, 12e, 12f of the base plate 12, the frame 13 is pressed against the base plate 12 and press-fitted, making it easy to set the distance between the terminals 19a, 19b, 19c, 19d and the circuit patterns 16a, 16b to an appropriate distance. In this case, since the outer diameter surface 52a of the second region 45a has a smaller outer diameter approaching the tip, the amount of press-fitting can be adjusted to accurately position the terminals 19a, 19b, 19c, 19d and the circuit patterns 16a, 16b before joining. Thereafter, the terminals 19a, 19b, 19c, and 19d are bonded to the circuit patterns 16a and 16b, thereby making it possible to appropriately bond the terminals 19a, 19b, 19c, and 19d to the circuit patterns 16a and 16b while preventing excessive stress from being applied to the base plate 12 and the frame body 13. As a result, the reliability of the semiconductor device 11a can be improved.

In this embodiment, the outer diameter surface 52a of the second region 45a is tapered. Therefore, the annular members 41a, 41b, 41c, and 41d can be more reliably pressed into the first through holes 12c, 12d, 12e, and 12f, and the terminals 19a, 19b, 19c, and 19d can be more reliably joined to the circuit patterns 16a and 16b.

In this embodiment, the difference between the diameter _D1 of the first through holes 12c, 12d, 12e, and 12f and the minimum diameter _D2 of the outer diameter surface 52a of the second region 45a is 0.5 mm or more and 1 mm or less. Therefore, during the manufacturing of the semiconductor device 11a, the interference between the outer diameter surface 52a of the second region 45a and the first side wall surfaces 12g, 12h, 12i, and 12j constituting the first through holes 12c, 12d, 12e, and 12f is suppressed, and the annular members 41a, 41b, 41c, and 41d including the protruding second region 45a can be easily inserted into the first through holes 12c, 12d, 12e, and 12f. Therefore, the semiconductor device can be manufactured more easily.

In this embodiment, the difference between the diameter _D1 of the first through holes 12c, 12d, 12e, and 12f and the maximum diameter _D3 of the outer diameter surface 52a of the second region 45a is 2 mm or more. This makes it easier for the end portions 12k of the first side wall surfaces 12g, 12h, 12i, and 12j constituting the first through holes 12c, 12d, 12e, and 12f on the first surface 12a side to come into contact with the outer diameter surface 52a of the second region 45a. This makes it possible to manufacture the semiconductor device 11a more reliably.

In this embodiment, the circuit patterns 16a and 16b are joined to the terminals 19a, 19b, 19c, and 19d by melting a portion of the terminals. Such joining can be performed, for example, by ultrasonic joining. Therefore, the terminals 19a, 19b, 19c, and 19d can be reliably electrically connected to the circuit patterns 16a and 16b without using adhesives or joining materials.

In this embodiment, the base plate 12 is rectangular when viewed in the thickness direction. Four first through holes 12c, 12d, 12e, and 12f are provided corresponding to the four corners of the rectangular base plate 12. Four second through holes 32a, 32b, 32c, and 32d are provided to correspond to the four first through holes 12c, 12d, 12e, and 12f. Four annular members 41a, 41b, 41c, and 41d are attached to correspond to the four second through holes 32a, 32b, 32c, and 32d. Therefore, in the semiconductor device 11a including the rectangular base plate 12, the four annular members 41a, 41b, 41c, 41d, the four first through holes 12c, 12d, 12e, 12f, and the four second through holes 32a, 32b, 32c, 32d can more appropriately bond the terminals 19a, 19b, 19c, 19d to the circuit patterns 16a, 16b. This makes it possible to obtain a more reliable semiconductor device 11a.

(Embodiment 2)
Next, another embodiment, that is, embodiment 2, will be described. Fig. 10 is a schematic cross-sectional view showing a part of a semiconductor device in embodiment 2. The semiconductor device in embodiment 2 differs from embodiment 1 in that the outer diameter surface of the second region includes a curved surface.

Referring to FIG. 10, the annular member 61a attached to the frame included in the semiconductor device according to the second embodiment includes an outer diameter surface 51a of the first region 44a and an outer diameter surface 62a of the second region 45a. The outer diameter surface 62a of the second region 45a is a curved surface. Specifically, the outer diameter surface 62a of the second region 45a is configured so that the rate at which the maximum diameter decreases increases as it approaches the end 47a. This also makes it easy to make the end of the first surface side of the annular member inside the first through hole while contacting the end of the first surface side of the side wall surface constituting the first through hole with the outer diameter surface 62a of the second region 45a. Note that the outer diameter surface 62a of the second region 45a may be an arc surface.

Other Embodiments
In the above embodiment, ultrasonic bonding is used to bond the terminals and the circuit pattern, but the present invention is not limited to this, and the terminals and the circuit pattern may be electrically bonded using a conductive adhesive, bonding material, solder, etc. Also, some parts may be ultrasonically bonded and the rest may be bonded with a bonding material.

In addition, in the above embodiment, the end of the annular member is a flat surface, but this is not limited thereto. For example, the tip of the tapered outer diameter surface may directly constitute the end of the annular member.

In the above embodiment, the semiconductor chip includes a semiconductor layer made of SiC, but the present invention is not limited to this, and the semiconductor chip may include a semiconductor layer made of GaN. That is, the semiconductor chip may include a semiconductor layer made of SiC or GaN. In this way, the semiconductor chip can be used as a wide band gap semiconductor chip. The semiconductor chip may also include a semiconductor layer made of Si. In this way, the semiconductor chip can be made highly versatile. That is, the semiconductor chip may include a semiconductor layer made of SiC, GaN, or Si.

In addition, in the above embodiment, an annular member having the above configuration is attached inside each second through hole, but this is not limited to the above, and an annular member having the above configuration may be attached to at least one of the four second through holes.

In the above embodiment, it is desirable that the amount of protrusion of the four annular members from the second surface is uniform. In this way, each annular member can be pressed in evenly. In this case, it is preferable to position the base plate and the frame body using another member. Also, the amount of protrusion from the second surface of at least one of the four annular members may be different from the amount of protrusion from the second surface of the other annular members. In this way, after placing the most protruding annular member in the corresponding first through hole, it becomes easy to place the other annular members in the other first through holes using this as a reference. Therefore, the above semiconductor device can be manufactured more easily.

It should be understood that the embodiments disclosed herein are illustrative in all respects and are not limiting in any respect. The scope of the present invention is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

The semiconductor device disclosed herein can be particularly advantageously applied in cases where improved reliability is required.

11a semiconductor device 12 base plate 12a first surface 12b back surface 12c, 12d, 12e, 12f first through holes 12g, 12h, 12i, 12j first side wall surface 13 frame body 13a first wall portion 13b second wall portion 13c third wall portion 13d fourth wall portion 13e second surface 13f surface 14a, 14b insulating plate 15a first circuit board 15b second circuit board 15c third circuit board 15d fourth circuit board 15e fifth circuit board 15f sixth circuit board 15g seventh circuit board 15h eighth circuit board 15i ninth circuit board 15j tenth circuit board 15k eleventh circuit board 16a, 16b circuit patterns 17a, 17b substrate 18a, 18b capacitors 19a, 19b, 19c, 19d terminal 20 Cases 21a, 21b, 21c, 21d, 21e, 21f, 22a, 22b, 22c, 22d, 22e, 22f Semiconductor chips 23a, 23b, 23c, 23d Regions 24a, 24b, 24c, 24d, 24e, 24f, 25a, 25b, 25c, 25d, 25e, 25f, 28a, 28b, 29a, 29b Wires 26a, 26b, 26c, 26d, 26e, 26f, 26g, 26h Press-fit pins 27a, 27b, 27c, 27d Inner wall surface 31a First flat plate portion 31b Second flat plate portion 31c Third flat plate portion 31d Fourth flat plate portion 32a, 32b, 32c, 32d Second through holes 33a, 33b, 33c, 33d Second side wall surfaces 41a, 41b, 41c, 41d, _61a Annular members 42a, 42b, 42c, 42d Third through holes 43a, 43b, 43c, 43d Third side wall surface 44a First region 45a Second region 46a, 47a Ends 51a, 52a, 62a Outer diameter surface 53a Boundaries _D1 , D2, _D3 Diameter _G1 Length _L1 Stroke M Intersection _P1 Pressure _S1 Gap

Claims (9)

A base plate having a plate shape, a first through hole penetrating in a thickness direction, and including a first surface located on one side in the thickness direction;
a substrate including a circuit pattern and disposed on the first surface;
a semiconductor chip disposed on the circuit pattern;
a frame including a second surface facing the first surface and disposed on the first surface so as to surround an outer periphery of the substrate;
a terminal attached to the frame and electrically connected to the circuit pattern;
the frame has a second through hole that penetrates the base plate in a thickness direction and is arranged to coincide with a position of the first through hole when the frame is disposed on the first surface;
the frame includes a metal annular member attached to the second through hole and having a third through hole passing through the base plate in a thickness direction;
The annular member is
A first region disposed within the second through hole;
a second region protruding from the second surface,
The outer diameter of the second region becomes smaller as it approaches the tip,
The minimum diameter _D2 of the outer diameter surface of the second region is smaller than the diameter _D1 of the first through hole,
The maximum diameter _D3 of the outer diameter surface of the second region is larger than the diameter _D1 of the first through hole,
In a thickness direction of the base plate, an end portion of a first side wall surface constituting the first through hole on the first surface side is in contact with an outer diameter surface of the second region,
A semiconductor device, wherein an end portion of the annular member on the first surface side is located within the first through hole. The semiconductor device according to claim 1, wherein the outer diameter surface of the second region is tapered. 3 . The semiconductor device according to claim 1 , wherein a difference between a diameter D ₁ of the first through hole and a minimum diameter D ₂ of an outer diameter surface of the second region is 0.5 mm or more and 1 mm or less. 4 . The semiconductor device according to claim 1 , wherein a difference between a diameter D ₁ of the first through hole and a maximum diameter D ₃ of an outer diameter surface of the second region is 2 mm or more. The semiconductor device according to any one of claims 1 to 4, wherein the circuit pattern is joined to the terminal by melting a portion of the terminal. The semiconductor device according to any one of claims 1 to 5, wherein the semiconductor chip includes a semiconductor layer made of at least one of SiC, GaN, and Si. The base plate has a rectangular shape when viewed in a thickness direction,
The first through holes are provided in four locations corresponding to four corners of the rectangular base plate,
the second through holes are provided in a number of four so as to correspond to the four first through holes,
The semiconductor device according to claim 1 , wherein four of the annular members are attached so as to correspond to four of the second through holes. The semiconductor device according to claim 7, wherein the four annular members protrude from the second surface by equal amounts. 8. The semiconductor device according to claim 7, wherein a protruding amount of at least one of said four annular members from said second surface is different from a protruding amount of the other annular members from said second surface.

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