JP7563369B2 - Electronic Circuit Module - Google Patents

Description

The present invention relates to an electronic circuit module.

Patent document 1 describes a noise reduction device for an integrated circuit in which a bypass capacitor is connected between one or more pairs of idle input/output ports whose outputs are fixed to H level and L level.

Patent document 2 describes a semiconductor device in which a first semiconductor chip and a second semiconductor chip on which an RC filter is formed are stacked, and the RC filter of the second semiconductor chip is connected to the terminals of the first semiconductor chip.

Patent document 3 describes an information processing device in which, when the control device is reset, a first terminal that goes into a floating state and is required to keep the signal of the terminal of the connected controlled device high is pulled up by a first pull-up resistor, and, when the control device is reset, a second terminal that goes into a floating state and is required to keep the signal of the terminal of the connected controlled device low is pulled down by a first pull-down resistor.

Patent document 4 describes a sensing device in which, in a first mode, a first signal is received at a first terminal and a second signal representing the capacitance of the sensing device is output on a second terminal, and an induction coil and a first capacitor are coupled in parallel between a first node and ground, and, in a second mode, a third signal is received at the first terminal and a fourth signal representing the inductance of the sensing device is output on the second terminal.

Japanese Patent Application Publication No. 6-175758 JP 2005-252123 A JP 2020-109553 A Special Publication No. 2020-512625

The bypass capacitor described in Patent Document 1, which is connected between one or more pairs of vacant input/output ports whose outputs are fixed to H level and L level, is effective in suppressing differential noise, but is ineffective in suppressing common noise. Common noise propagated to a power supply line or ground line may propagate to a GPIO (General Purpose Input/Output) terminal. In that case, the bypass capacitor connected to the GPIO terminal cannot induce the common noise to the ground. Therefore, the common noise affects the inside of the semiconductor device. Furthermore, in the technology described in Patent Document 1, the integrated circuit requires two terminals for respectively connecting the two terminals of the bypass capacitor.

Patent documents 2 to 4 describe GPIO terminals used for transmitting and receiving signals, but do not describe unused GPIO terminals. If an unused GPIO terminal is left open, noise propagated to the power supply line or ground line may propagate to the unused GPIO terminal. In that case, since the unused GPIO terminal is open, the noise affects the inside of the semiconductor device.

The present invention was made in consideration of the above, and aims to improve immunity.

An electronic circuit module according to one aspect of the present invention includes a semiconductor device having an unused terminal that is not connected to a power supply potential, is not connected to a reference potential, does not receive a signal, and does not output a signal, and a resistor or inductance element electrically connected between the unused terminal and the reference potential.

The present invention makes it possible to improve immunity.

FIG. 1 is a diagram showing a configuration of an electronic circuit module according to a first embodiment. FIG. 2 is a diagram showing an internal configuration of the semiconductor device of the electronic circuit module according to the first embodiment. FIG. 3 is a diagram showing a configuration of an input buffer of the electronic circuit module according to the first embodiment. FIG. 4 is a diagram showing a configuration of an output buffer of the electronic circuit module according to the first embodiment. FIG. 5 is a diagram showing a configuration of an electronic circuit module according to the second embodiment. FIG. 6 is a diagram showing a configuration of an electronic circuit module according to the third embodiment. FIG. 7 is a diagram showing a configuration of an electronic circuit module according to the fourth embodiment.

Below, embodiments of the electronic circuit module of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to these embodiments. Each embodiment is merely an example, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible.

First Embodiment
(composition)
1 is a diagram showing the configuration of an electronic circuit module according to a first embodiment. The electronic circuit module 1 has a plurality of electronic components mounted on a substrate 10. The substrate 10 may be made up of a plurality of substrates.

The electronic circuit module 1 is a wireless communication module that performs wireless communication, but the present disclosure is not limited to this. The electronic circuit module 1 is exemplified as being mounted on a vehicle, but the present disclosure is not limited to this.

The electronic circuit module 1 includes a substrate 10, a semiconductor device 11, a matching circuit 21, an antenna 22, and a resistor 23.

The semiconductor device 11 may be enclosed in a package or may be a bare chip.

The antenna 22 may be located outside the substrate 10.

Substrate 10 has terminals 10a to 10c. Semiconductor device 11 has terminals 11a to 11e.

One end of the matching circuit 21 is electrically connected to the terminal 11a. The other end of the matching circuit 21 is electrically connected to the antenna 22. In other words, the terminal 11a is a high-frequency signal input/output terminal. The matching circuit 21 is a circuit that performs impedance matching between the antenna 22 and the semiconductor device 11.

Terminal 11b is electrically connected to the power supply potential Vcc via terminal 10a. Power supplied from the power supply potential Vcc to terminal 11b is supplied to each circuit inside the semiconductor device 11.

Terminal 11c is electrically connected to a reference potential via terminal 10b. The reference potential is exemplified by a ground potential, but the present disclosure is not limited thereto. Terminal 11c is electrically connected to each circuit inside semiconductor device 11.

Terminal 11d is a GPIO (General Purpose Input/Output) terminal, and is electrically connected to external circuit 2 via terminal 10c. External circuit 2 transmits and receives signals to and from each circuit inside semiconductor device 11 via terminal 10c and terminal 11d. Digital signals are exemplified as signals, but the present disclosure is not limited thereto.

Terminal 11e is an unused GPIO terminal. An unused GPIO terminal is a GPIO terminal that is not connected to the power supply potential Vcc, is not connected to a reference potential, does not receive a signal, and does not output a signal.

Terminal 11e corresponds to an example of an "unused terminal" in this disclosure.

The electronic circuit module 1 of the first embodiment uses terminal 11e, an unused GPIO terminal, to suppress noise.

To suppress noise, one end of resistor 23 is electrically connected to terminal 11e. The other end of resistor 23 is electrically connected to the reference potential via terminal 10b.

Figure 2 is a diagram showing the internal configuration of the semiconductor device of the electronic circuit module of the first embodiment. Note that in Figure 2, the substrate 10 and terminals 10a to 10c are omitted.

The semiconductor device 11 includes a switch 41, a preamplifier 42, and a power amplifier 43. The power amplifier 43 is an amplifier that amplifies a high-frequency transmission signal. The preamplifier 42 is an amplifier that amplifies a high-frequency reception signal.

The preamplifier 42 and the power amplifier 43 are electrically connected to the power supply potential Vcc via the power supply potential line 44 and the terminal 11b, and are electrically connected to the reference potential via the reference potential line 45 and the terminal 11c. The preamplifier 42 and the power amplifier 43 operate using power supplied from the power supply potential Vcc via the terminal 11b and the power supply potential line 44.

When transmitting a high-frequency transmission signal to the matching circuit 21, the power amplifier 43 amplifies the high-frequency transmission signal input from a preceding circuit (not shown) and outputs the amplified signal to the switch 41. When transmitting a high-frequency transmission signal to the matching circuit 21, the switch 41 electrically connects the terminal 11a to the output terminal of the power amplifier 43.

When the switch 41 receives a high-frequency reception signal from the matching circuit 21, it electrically connects the terminal 11a to the input terminal of the preamplifier 42. The preamplifier 42 amplifies the high-frequency reception signal input from the switch 41 and outputs it to a downstream circuit (not shown).

The semiconductor device 11 includes general-purpose input/output circuits 51 and 52. The general-purpose input/output circuits 51 and 52 are electrically connected to terminals 11d and 11e, respectively.

The general-purpose input/output circuit 51 includes a first protection diode 61, a second protection diode 62, a pull-up resistor 63, a first switch 64, a pull-down resistor 65, a second switch 66, an input buffer 67, and an output buffer 68.

The input buffer 67 and the output buffer 68 are electrically connected to the power supply potential Vcc via the power supply potential line 44 and the terminal 11b, and are electrically connected to the reference potential via the reference potential line 45 and the terminal 11c. The input buffer 67 and the output buffer 68 operate using power supplied from the power supply potential Vcc via the terminal 11b and the power supply potential line 44.

The cathode of the first protection diode 61 is electrically connected to the power supply potential Vcc via the power supply potential line 44 and the terminal 11b. The anode of the first protection diode 61 is electrically connected to the terminal 11d.

The cathode of the second protection diode 62 is electrically connected to the terminal 11d. The anode of the second protection diode 62 is electrically connected to the reference potential via the reference potential line 45 and the terminal 11c.

One end of the pull-up resistor 63 is electrically connected to the terminal 11d. The other end of the pull-up resistor 63 is electrically connected to one end of the first switch 64. The other end of the first switch 64 is electrically connected to the power supply potential Vcc via the power supply potential line 44 and the terminal 11b. The pull-up resistor 63 pulls up the terminal 11d when the first switch 64 is in the on state.

The pull-up resistor 63 and the first switch 64 may be realized by a P-channel MOS transistor with a high on-resistance.

One end of the pull-down resistor 65 is electrically connected to terminal 11d. The other end of the pull-down resistor 65 is electrically connected to one end of the second switch 66. The other end of the second switch 66 is electrically connected to the reference potential via the reference potential line 45 and terminal 11c. The pull-down resistor 65 pulls down terminal 11d when the second switch 66 is in the on state.

The pull-down resistor 65 and the second switch 66 may be realized by an N-channel MOS transistor with a high on-resistance.

The input terminal of the input buffer 67 is electrically connected to the terminal 11d. The input buffer 67 outputs the signal received from the external circuit 2 via the terminal 11d to a downstream circuit (not shown).

Figure 3 shows the configuration of the input buffer of the electronic circuit module of the first embodiment.

The input buffer 67 includes a P-channel transistor 81 and an N-channel transistor 82.

The source of transistor 81 is electrically connected to the power supply potential Vcc via terminal 67a. The drain of transistor 81 is electrically connected to the drain of transistor 82. The source of transistor 82 is electrically connected to the reference potential via terminal 67b.

The gates of transistors 81 and 82 are electrically connected to terminal 67c. Signal 83 is input to terminal 67c. The drains of transistors 81 and 82 are electrically connected to terminal 67d. Signal 84 is output from terminal 67d.

When signal 83 is at a high level, transistor 81 is turned off and transistor 82 is turned on. Therefore, signal 84 is at a low level.

When signal 83 is at a low level, transistor 81 is turned on and transistor 82 is turned off. Therefore, signal 84 is at a high level.

Referring again to FIG. 2, the output terminal of the output buffer 68 is electrically connected to the terminal 11d. The output buffer 68 outputs a signal received from a previous circuit (not shown) to the external circuit 2 via the terminal 11d.

Figure 4 shows the configuration of the output buffer of the electronic circuit module of the first embodiment.

The output buffer 68 includes an output control circuit 91, a P-channel transistor 92, and an N-channel transistor 93.

A signal 94 is input to the input terminal of the output control circuit 91 via terminal 68c.

The source of transistor 92 is electrically connected to the power supply potential Vcc via terminal 68a. The drain of transistor 92 is electrically connected to the drain of transistor 93. The source of transistor 93 is electrically connected to the reference potential via terminal 68b.

The gates of transistors 92 and 93 are electrically connected to two output terminals of the output control circuit 91, respectively. The drains of transistors 92 and 93 are electrically connected to terminal 68d. A signal 95 is output from terminal 68d.

The output control circuit 91 controls one of the transistors 92 and 93 to the on state in response to the signal 94.

When transistor 92 is controlled to the off state and transistor 93 is controlled to the on state, signal 95 becomes low level.

When transistor 92 is controlled to the on state and transistor 93 is controlled to the off state, signal 95 becomes high level.

Referring again to FIG. 2, the general-purpose input/output circuit 52 includes a first protection diode 71, a second protection diode 72, a pull-up resistor 73, a first switch 74, a pull-down resistor 75, a second switch 76, an input buffer 77, and an output buffer 78.

The connection relationships between the circuit elements in the general-purpose input/output circuit 52 are similar to the connection relationships between the circuit elements in the general-purpose input/output circuit 51, so a description thereof will be omitted.

The circuit configuration of input buffer 77 is similar to the circuit configuration of input buffer 67 (see Figure 3), so the explanation is omitted.

The circuit configuration of the output buffer 78 is similar to the circuit configuration of the output buffer 68 (see Figure 4), so a description is omitted.

The terminal 11d is the GPIO terminal in use. Therefore, the first switch 64 and the second switch 66 are controlled to be in an on or off state depending on the operating status of the semiconductor device 11.

Terminal 11e is an unused GPIO terminal. Therefore, the first switch 64 and the second switch 66 are always controlled to the off state.

(effect)
For example, noise 31 (see FIGS. 1 and 2 ) may enter the connection between the matching circuit 21 and the antenna 22. Note that the location where the noise 31 enters is merely an example, and the present disclosure is not limited thereto. Also, the noise 31 is an example of common noise, and the present disclosure is not limited thereto.

The noise 31 propagates to the power supply potential line 44 or the reference potential line 45 via the matching circuit 21, the terminal 11a, the switch 41, and the preamplifier 42 or the power amplifier 43. Each transistor inside the semiconductor device 11 is made of an oxide film of Si (silicon), and acts as a capacitance of several pF (picofarads) against the noise 31. Therefore, the noise 31 propagated to the power supply potential line 44 or the reference potential line 45 propagates inside the semiconductor device 11, and there is a possibility that the semiconductor device 11 may malfunction.

As a countermeasure, it is possible to add a capacitor to the matching circuit 21, which electrically connects between the line through which the high-frequency transmission signal and the high-frequency reception signal pass and the reference potential. However, doing so is not preferable because it causes the matching circuit 21 to lose the impedance matching between the antenna 22 and the semiconductor device 11.

Therefore, in the electronic circuit module 1 of the first embodiment, one end of the resistor 23 is electrically connected to the terminal 11e. The other end of the resistor 23 is electrically connected to the reference potential.

For example, noise 31 propagated to the power supply potential line 44 flows out to the reference potential via the first protection diode 71, terminal 11e, and resistor 23. Also, for example, noise 31 propagated to the reference potential line 45 flows out to the reference potential via the second protection diode 72, terminal 11e, and resistor 23.

As a result, the electronic circuit module 1 can suppress the noise 31 from propagating to elements inside the semiconductor device 11. As a result, the electronic circuit module 1 can suppress malfunction of the semiconductor device 11, improving immunity. Furthermore, the electronic circuit module 1 can maintain impedance matching between the antenna 22 and the semiconductor device 11. Furthermore, the electronic circuit module 1 only needs one unused GPIO terminal, and does not need a pair of unused GPIO terminals.

Second Embodiment
Among the components of the electronic circuit module of the second embodiment, the same components as those of the first embodiment are given the same reference numerals and the description thereof will be omitted.

Figure 5 shows the configuration of an electronic circuit module in the second embodiment.

Compared to the electronic circuit module 1 of the first embodiment (see FIG. 1), the electronic circuit module 1A includes an inductance element 24 instead of a resistor 23.

An example of the inductance element 24 is a ferrite bead, but the present disclosure is not limited thereto.

One end of the inductance element 24 is electrically connected to the terminal 11e. The other end of the inductance element 24 is electrically connected to the reference potential via the terminal 10b.

Noise 31 propagated to the power supply potential line 44 (see FIG. 2) flows out to the reference potential via the first protection diode 71, terminal 11e, and inductance element 24. Also, for example, noise 31 propagated to the reference potential line 45 (see FIG. 2) flows out to the reference potential via the second protection diode 72, terminal 11e, and inductance element 24.

As a result, electronic circuit module 1A achieves the same effects as electronic circuit module 1.

Third Embodiment
Among the components of the electronic circuit module of the third embodiment, the same components as those of the other embodiments are given the same reference numerals and the description thereof will be omitted.

Figure 6 shows the configuration of an electronic circuit module according to the third embodiment.

Compared to the electronic circuit module 1 of the first embodiment (see FIG. 1), the electronic circuit module 1B further includes an inductance element 24 in addition to the resistor 23.

One end of the inductance element 24 is electrically connected to the terminal 11e. The other end of the inductance element 24 is electrically connected to the reference potential via the terminal 10b.

In other words, the resistor 23 and the inductance element 24 are connected in parallel.

Noise 31 propagated to the power supply potential line 44 (see FIG. 2) flows out to the reference potential via the first protection diode 71, terminal 11e, resistor 23, and inductance element 24. Also, for example, noise 31 propagated to the reference potential line 45 (see FIG. 2) flows out to the reference potential via the second protection diode 72, terminal 11e, resistor 23, and inductance element 24.

As a result, electronic circuit module 1B achieves the same effects as electronic circuit module 1.

<Fourth embodiment>
Among the components of the electronic circuit module of the fourth embodiment, the same components as those of the other embodiments are given the same reference numerals and the description thereof will be omitted.

Figure 7 shows the configuration of an electronic circuit module according to the fourth embodiment.

Compared to the electronic circuit module 1 of the first embodiment (see FIG. 1), the electronic circuit module 1C further includes an inductance element 24 in addition to the resistor 23.

One end of the inductance element 24 is electrically connected to the other end of the resistor 23. The other end of the inductance element 24 is electrically connected to the reference potential via the terminal 10b.

In other words, the resistor 23 and the inductance element 24 are connected in series.

Noise 31 propagated to the power supply potential line 44 (see FIG. 2) flows out to the reference potential via the first protection diode 71, terminal 11e, resistor 23, and inductance element 24. Also, for example, noise 31 propagated to the reference potential line 45 (see FIG. 2) flows out to the reference potential via the second protection diode 72, terminal 11e, resistor 23, and inductance element 24.

As a result, the electronic circuit module 1C achieves the same effects as the electronic circuit module 1.

In the fourth embodiment, one end of the resistor 23 is electrically connected to the terminal 11e, the other end of the resistor 23 is electrically connected to one end of the inductance element 24, and the other end of the inductance element 24 is electrically connected to the reference potential, but the present disclosure is not limited to this. One end of the inductance element 24 may be electrically connected to the terminal 11e, the other end of the inductance element 24 may be electrically connected to one end of the resistor 23, and the other end of the resistor 23 may be electrically connected to the reference potential.

<Additional Notes>
(1)
In each embodiment, the case where there is one unused GPIO terminal (terminal 11e) has been described, but the present disclosure is not limited to this. There may be two or more unused GPIO terminals. In this case, a resistor, an inductance element, a parallel circuit of a resistor and an inductance element, or a series circuit of a resistor and an inductance element may be connected between each unused GPIO terminal and the reference potential.

(2)
In each embodiment, the resistor 23 and the inductance element 24 are mounted on the substrate 10, but the present disclosure is not limited to this. Each of the resistor 23 and the inductance element 24 may be formed in the substrate 10 using wiring or the like.

The above-described embodiment is intended to facilitate understanding of the present invention, and is not intended to limit the present invention. The present invention may be modified or improved without departing from the spirit of the present invention, and equivalents thereof are also included in the present invention.

1, 1A, 1B, 1C Electronic circuit module 10 Substrate 10a, 10b, 10c, 11a, 11b, 11c, 11d, 11e Terminal 11 Semiconductor device 21 Matching circuit 22 Antenna 23 Resistor 24 Inductance element 41 Switch 42 Preamplifier 43 Power amplifier 51, 52 General-purpose input/output circuit 61, 71 First protection diode 62, 72 Second protection diode 63, 73 Pull-up resistor 64, 74 First switch 65, 75 Pull-down resistor 66, 76 Second switch 67, 77 Input buffer 68, 78 Output buffer 81, 82, 92, 93 Transistor 91 Output control circuit

Claims (5)

a semiconductor device having: an unused terminal that is not connected to a power supply potential, is not connected to a reference potential, and to which no signal is input or output ; a first diode having an anode electrically connected to the unused terminal and a cathode electrically connected to a power supply potential line; and a second diode having a cathode electrically connected to the unused terminal and an anode electrically connected to a reference potential line ;
a resistor or inductance element electrically connected between the unused terminal and a reference potential;
Including ,
the first diode passes common noise propagated on the power supply potential line to the unused terminal;
the second diode passes common noise propagated to the reference potential line to the unused terminal;
The resistor or the inductance element passes common noise propagated to the unused terminal to a reference potential.
Electronic circuit module. 2. The electronic circuit module according to claim 1,
a parallel circuit of a resistor and an inductance element electrically connected between the unused terminal and a reference potential,
Electronic circuit module. 2. The electronic circuit module according to claim 1,
a series circuit of a resistor and an inductance element electrically connected between the unused terminal and a reference potential,
Electronic circuit module. 4. The electronic circuit module according to claim 1,
The semiconductor device includes:
Further comprising a high frequency signal input/output terminal for inputting and outputting a high frequency signal.
Electronic circuit module. 5. The electronic circuit module according to claim 4,
An antenna for transmitting and receiving radio waves;
a matching circuit electrically connected between the antenna and the high-frequency signal input/output terminal, for performing impedance matching between the antenna and the semiconductor device;
Further comprising:
Electronic circuit module.

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