JP7565814B2 - Stacked semiconductor device and its manufacturing method - Google Patents

Description

The present invention relates to a stacked semiconductor device and a manufacturing method thereof, and more particularly to a stacked semiconductor device that can be used in, for example, solid-state imaging devices and a manufacturing method thereof.

In recent years, research has been conducted into stacked semiconductor devices in which circuit boards containing transistors are stacked in order to increase the integration and functionality of solid-state imaging elements such as CMOS image sensors. A widely known method of stacking is the use of through silicon vias (TSV) (Non-Patent Document 1). TSVs are formed by drilling holes (vias) in silicon chips such as ICs and LSIs, providing conductors that penetrate the front and back surfaces, and connecting the chips together using electrodes on both sides of the conductor.

On the other hand, there is also a method in which fine electrodes connected to internal circuits such as transistors are formed on the front or back surface of a substrate, and the electrodes are connected to one another to stack the substrates in multiple layers (Patent Document 1, Non-Patent Documents 2 and 3). With this stacked semiconductor device in which front or back electrodes are connected, multiple electrode connections can be used to transmit many signals simultaneously between substrates. When applied to solid-state imaging devices, signal processing can be performed for each pixel by connecting multiple layers of circuits to each pixel, making this an effective technology for increasing density.

In addition, a stacked solid-state imaging element has been proposed that has a stepped light receiving structure in which multiple imaging element chips with photodiodes at the ends are stacked and slightly shifted (Patent Document 2).

Special Publication No. 5-39345 Patent No. 3867124

Seiichi Denda, "Development Trends of Through-Silicon Via (TSV) for 3D Chip Stacking", Surface Technology, Vol.58, No.12, (2007), pp.712-718 M. Goto, et al. “3-D Silicon-on-Insulator Integrated Circuits With NFET and PFET on Separate Layers Using Au/SiO2 Hybrid Bonding”, IEEE Trans. Electron Devices, Vol. 61, No. 8, (2014) , pp.2886-2892 M. Goto, et al. “Pixel-Parallel 3-D Integrated CMOS Image Sensors With Pulse Frequency Modulation A/D Converters Developed by Direct Bonding of SOI Layers”, IEEE Trans. Electron Devices, Vol. 62, No. 11, ( 2015), pp.3530-3535

However, since TSVs are usually formed on a silicon substrate, it is necessary to cover the surface of the hole formed in the silicon substrate with an insulating layer and then fill it with a conductor, making the formation process complicated. In addition, the size of a TSV is generally 3 μm or more, which is larger than the size of a typical transistor, so TSVs are usually placed outside the light-receiving area, and one TSV is connected to each column or block having many pixels, and signal processing circuits such as A/D (analog/digital) conversion circuits are performed for each column.

In addition, stacked semiconductor devices with connected front or back electrodes can realize highly integrated, high-performance stacked semiconductor devices, but since it is necessary to align and connect the multi-layered electrodes, there are concerns that an increase in the number of layers can lead to a decrease in yield and an increase in costs.

Since the light receiving surface of a stepped stacked solid-state imaging element is not flat, there are concerns about problems such as the occurrence of insensitive areas, non-uniform sensitivity between pixels, and asymmetric incidence angle dependency. Also, special fiberglass is required for implementation, which increases costs.

Therefore, the object of the present invention, which has been made in consideration of the above problems, is to provide a stacked semiconductor device with a flat surface and good characteristics, as well as a manufacturing method thereof, while reducing the number of steps in the manufacturing process and improving the yield.

In order to solve the above problems, the stacked semiconductor device according to the present invention is a stacked semiconductor device formed by stacking a plurality of signal processing circuit layers, the signal processing circuit layers having input/output pads at the ends of the signal processing circuits, the signal processing circuit layers being stacked such that the upper signal processing circuits are shifted by one block in the planar direction relative to the lower signal processing circuits so that the positions of the input/output pads do not overlap, and the stacked signal processing circuit layers are characterized in that they have connection electrodes embedded in through holes that reach the input/output pads of each signal processing circuit layer from the surface of the uppermost signal processing circuit layer.

The stacked semiconductor device further includes a photoelectric conversion element layer having a plurality of photoelectric conversion elements on the surface of the uppermost signal processing circuit layer, and the pixel electrodes of the photoelectric conversion elements are preferably connected to the connection electrodes.

The stacked semiconductor device preferably further includes a photoelectric conversion film layer on the surface of the uppermost signal processing circuit layer, and the regions of the photoelectric conversion film layer connected to the connection electrodes are each a pixel region.

Furthermore, it is preferable that the stacked semiconductor device has one block corresponding to one or more pixels.

Furthermore, in the stacked semiconductor device, it is preferable that the signal processing circuit is a pixel signal processing circuit in parallel with the pixels, and that the pixel signal processing circuit that processes the signal of one pixel is shared by multiple pixels.

Furthermore, it is preferable that the stacked semiconductor device has a portion of the connection electrode as an output electrode of the signal processing circuit.

In order to solve the above problems, the method for manufacturing a stacked semiconductor device according to the present invention is a method for manufacturing a stacked semiconductor device formed by stacking multiple signal processing circuit layers, and is characterized by comprising the steps of forming the signal processing circuit layer with input/output pads at the ends of the signal processing circuit, stacking the signal processing circuit layers by shifting the upper signal processing circuit by one block at a time in the planar direction relative to the lower signal processing circuit so that the positions of the input/output pads do not overlap, simultaneously forming multiple through holes that reach the input/output pads of each signal processing circuit layer from the surface of the uppermost signal processing circuit layer, and filling the multiple through holes with a conductive material to form connection electrodes.

The manufacturing method of the stacked semiconductor device preferably further includes a step of stacking a photoelectric conversion element layer having a plurality of photoelectric conversion elements on the surface of the uppermost signal processing circuit layer, and connecting the pixel electrodes of the photoelectric conversion elements to the connection electrodes, respectively.

The manufacturing method of the stacked semiconductor device preferably further includes a step of forming a photoelectric conversion film layer on the surface of the uppermost signal processing circuit layer, and forming the regions of the photoelectric conversion film layer connected to the connection electrodes into pixel regions.

The stacked semiconductor device and manufacturing method of the present invention can reduce the number of steps in the manufacturing process, improve yields, and achieve good element characteristics.

FIG. 1 is a diagram showing an example of a cross-sectional view of a stacked semiconductor device according to a first embodiment; FIG. 1 is a diagram showing an example of a plan view of a stacked semiconductor device according to a first embodiment; 3A to 3C are diagrams illustrating an example of a manufacturing process of the stacked semiconductor device according to the first embodiment; 3A to 3C are diagrams illustrating an example of a manufacturing process of the stacked semiconductor device according to the first embodiment; 3A to 3C are diagrams illustrating an example of a manufacturing process of the stacked semiconductor device according to the first embodiment; 3A to 3C are diagrams illustrating an example of a manufacturing process of the stacked semiconductor device according to the first embodiment; 3A to 3C are diagrams illustrating an example of a manufacturing process of the stacked semiconductor device according to the first embodiment; 3A to 3C are diagrams illustrating an example of a manufacturing process of the stacked semiconductor device according to the first embodiment; 3A to 3C are diagrams illustrating an example of a manufacturing process of the stacked semiconductor device according to the first embodiment; 3A to 3C are diagrams illustrating an example of a manufacturing process of the stacked semiconductor device according to the first embodiment; 3A to 3C are diagrams illustrating an example of a manufacturing process of the stacked semiconductor device according to the first embodiment; 3A to 3C are diagrams illustrating an example of a manufacturing process of the stacked semiconductor device according to the first embodiment; 3A to 3C are diagrams illustrating an example of a manufacturing process of the stacked semiconductor device according to the first embodiment; 3A to 3C are diagrams illustrating an example of a manufacturing process of the stacked semiconductor device according to the first embodiment; 3A to 3C are diagrams illustrating an example of a manufacturing process of the stacked semiconductor device according to the first embodiment; 3A to 3C are diagrams illustrating an example of a manufacturing process of the stacked semiconductor device according to the first embodiment; FIG. 1 is a diagram illustrating an example of a perspective view of a stacked semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view of a stacked semiconductor device according to a first modified example of the first embodiment. FIG. 2 is a plan view of a stacked semiconductor device according to a first modified example of the first embodiment; FIG. 13 is a plan view of a stacked semiconductor device according to a second modified example of the first embodiment; FIG. 13 is a plan view of a stacked semiconductor device according to a third modified example of the first embodiment; FIG. 13 is a plan view of a stacked semiconductor device according to a fourth modified example of the first embodiment; FIG. 13 is a diagram showing an example of a cross-sectional view of a stacked semiconductor device according to a second embodiment; FIG. 13 is a diagram showing an example of a plan view of a stacked semiconductor device according to a second embodiment; FIG. 13 is a diagram illustrating an example of a perspective view of a stacked semiconductor device according to a second embodiment; FIG. 13 is a cross-sectional view of a stacked semiconductor device according to a first modified example of the second embodiment. FIG. 13 is a plan view of a stacked semiconductor device according to a first modified example of the second embodiment; FIG. 13 is a plan view of a stacked semiconductor device according to a second modified example of the second embodiment; FIG. 13 is a plan view of a stacked semiconductor device according to a third modified example of the second embodiment; FIG. 13 is a plan view of a stacked semiconductor device according to a fourth modified example of the second embodiment;

The following describes an embodiment of the present invention with reference to the drawings.

(First embodiment)
An example of a stacked semiconductor device according to a first embodiment of the present invention is shown in Figures 1 and 2. Figure 1 is an example of a cross-sectional view of the stacked semiconductor device 100 according to the first embodiment. Also, Figure 2 is an example of a plan view of the stacked semiconductor device 100 according to the first embodiment. The stacked semiconductor device 100 according to the first embodiment constitutes a solid-state imaging element, and includes a photoelectric conversion element (photodiode) formed on a semiconductor substrate as its light receiving portion.

The stacked semiconductor device 100 comprises a photoelectric conversion element layer 60, a first signal processing circuit layer 10 from the surface side, a second signal processing circuit layer 20, a third signal processing circuit layer 30, and a support layer 40. Note that in this embodiment, the signal processing layer is composed of three layers, but this is just one example, and any number of signal processing circuit layers may be stacked as long as there are multiple layers. Note that for the purposes of explanation, the support layer 40 side of the stacked semiconductor device 100 in FIG. 1 will be referred to as the lower side, and the photoelectric conversion element layer 60 side will be referred to as the upper side or surface side.

The support layer 40 is a layer that supports the stacked semiconductor device 100, and may be, for example, a semiconductor substrate such as silicon. It may also be a glass substrate, a sapphire substrate, or the like, and any substrate (layer) having a thickness and hardness capable of supporting the stacked semiconductor device 100 can be used.

Each signal processing circuit layer 10, 20, 30 includes, for example, buried insulating layers (BOX: Buried Oxide) 12, 22, 32, semiconductor elements 13, 23, 33 such as MOS transistors, electrodes/wirings 14, 24, 34, input/output pads 15, 25, 35, insulating layers 16, 26, 36, etc. In this embodiment, the input/output pads 15, 25, 35 are input terminals of the signal processing circuit of each layer, and are arranged at the ends of the signal processing circuit in each layer.

Each signal processing circuit layer 10, 20, 30 is stacked with the upper signal processing circuit shifted (displaced) in the planar direction (leftward in FIG. 1) by one block (in this embodiment, an area corresponding to one pixel) relative to the lower signal processing circuit so that the positions of the input/output pads 15, 25, 35 of each layer do not overlap. Note that the arrangement and connection of the transistors in each signal processing circuit layer shown in the figure are merely examples and do not mean a specific processing circuit. In this embodiment, each signal processing circuit layer 10, 20, 30 is provided with a signal processing circuit (e.g., an amplifier circuit, an A/D (analog/digital) conversion circuit, a correlated double sampling circuit, etc.) that processes pixel signals from the photoelectric conversion element layer 60. Note that, as described later, this signal processing circuit may be a pixel signal processing circuit in parallel with the pixels.

The stacked semiconductor device 100 also includes connection electrodes 51, 52, and 53 that penetrate and connect from the surface of the uppermost signal processing circuit layer 10 to the input/output pads 15, 25, and 35 of each layer. In this embodiment, the connection electrodes 51, 52, and 53 have the function of transmitting pixel signals from the photoelectric conversion element layer 60 to the corresponding signal processing circuit layers. As described below, the connection electrodes can be formed after stacking each signal processing circuit layer.

The photoelectric conversion element layer 60 includes, for example, an insulating layer 62, a semiconductor layer 63, a photodiode 64 consisting of a pn junction region, a transfer gate 65, an FD (Floating Diffusion) 66, an electrode/wiring 67, an insulating layer 68, and a pixel electrode 69 from the surface side, and constitutes each pixel 60A, 60B, and 60C. The pixel electrode 69 is connected to the connection electrodes 51, 52, and 53, respectively. The signal charge generated by the photodiode (photoelectric conversion element) 64 is transferred to the FD 66 by the transfer gate 65, and is transmitted to the signal processing circuit of each layer via the electrode/wiring 67, the pixel electrode 69, and the connection electrodes 51, 52, and 53. Here, an amplifier circuit may be inserted between the FD 66 and the electrode/wiring 67 to amplify the signal voltage before transmitting it to the signal processing circuit of each layer.

The stacked semiconductor device 100 of this embodiment is a solid-state imaging element, and signal processing for each pixel can be performed in a different layer. That is, the pixel signal generated in pixel 60A is transmitted from the surface to the first-layer signal processing circuit layer 10 via the connection electrode 51, and the signal is processed in the signal processing circuit layer 10 and output. Similarly, the pixel signal generated in pixel 60B is transmitted to the second-layer signal processing circuit layer 20 via the connection electrode 52, and the signal is processed in the signal processing circuit layer 20 and output. Also, the pixel signal generated in pixel 60C is transmitted to the third-layer signal processing circuit layer 30 via the connection electrode 53, and the signal is processed in the signal processing circuit layer 30 and output.

Figure 2 shows an example of a pixel array of the stacked semiconductor device 100 of the first embodiment. Pixels 60A, 60B, and 60C in the plan view correspond to pixels 60A, 60B, and 60C in the cross-sectional view of Figure 1. In Figure 2, dashed lines indicate the boundaries of each pixel, and the position of the photodiode of each pixel is conceptually depicted as a rectangle.

In the stacked semiconductor device 100, the signal charges of multiple pixels 60A aligned in the x direction (row direction) in the plan view of FIG. 2 are processed by the signal processing circuit layer 10, the first layer from the front side. In addition, the signal charges of multiple pixels 60B aligned in the x direction are processed by the signal processing circuit layer 20, the second layer, and the signal charges of multiple pixels 60C aligned in the x direction are processed by the signal processing circuit layer 30, the third layer. Note that although four pixels are drawn in the x direction in FIG. 2, any number of pixels can be formed in the x direction.

In this embodiment, each column of the stacked semiconductor device in FIG. 2 has the same structure and circuit. That is, each pixel is provided with an independent pixel signal processing circuit, enabling pixel-parallel signal processing. Each signal processing circuit layer processes each pixel signal in a signal processing circuit arranged in the y direction, and outputs the signal to the outside from an external input/output pad 80 provided at an arbitrary position (for example, the upper direction in the plan view). This external input/output pad 80 can be formed in the same manner as forming the connection electrode described below. The external input/output pad 80 may be provided for each signal processing circuit layer, or may be shared by multiple signal processing circuit layers.

According to the stacked semiconductor device 100 of this embodiment, since fine connection electrodes 51, 52, and 53 are used, interlayer connection can be performed within the pixel region for each pixel. In addition, since the connection electrodes 51, 52, and 53 are formed after stacking the signal processing circuit layers 10, 20, and 30 as described below, it is not necessary to perform strict alignment between the electrodes when stacking the signal processing circuit layers, and a large number of layers can be easily stacked. Furthermore, each pixel can be formed in a flat photoelectric conversion element layer 60, and various problems caused by the light receiving surface not being flat, such as the occurrence of insensitive regions, uneven sensitivity between pixels, and asymmetric incidence angle dependency, can be eliminated. In addition, the lens focus can be aligned for each pixel, and incident light at a wide angle can be handled.

Next, an example of a method for manufacturing the stacked semiconductor device 100 of the first embodiment will be described. Figures 3A to 3N are cross-sectional views showing each step of an example of a method for manufacturing the stacked semiconductor device 100 of Figure 1.

(a) A signal processing circuit is formed on a first substrate, and a first-layer signal processing circuit layer 10 is fabricated from the surface side. The first substrate is an SOI (Silicon on Insulator) substrate having a support layer (e.g., a silicon layer) 11, a buried insulating layer (e.g., a silicon oxide film) 12, and a semiconductor layer on the buried insulating layer 12. The SOI substrate may be manufactured by any method. In this embodiment, each element (MOS transistor) is formed in an independent semiconductor island region, and it is preferable to fabricate the signal processing circuit on a fully-depleted SOI (FDSOI: Fully-Depleted Silicon on Insulator) substrate having a relatively thin semiconductor layer. FIG. 3A shows an example of the completed state of the first-layer signal processing circuit layer 10. In the present invention, the signal processing circuit layer 10 does not have a well structure, and only the formation region of each element (MOS transistor, etc.) 13 has a semiconductor region, and an insulating layer (e.g., a silicon oxide film) 16 is formed in the region other than the element formation region.

An example of the manufacturing process of the signal processing circuit layer 10 will be described. Impurities are introduced into the semiconductor layer on the buried insulating layer 12 to form a plurality of MOS transistors 13 having source/drain/gate electrodes. Any semiconductor element other than MOS transistors may be formed. After covering the MOS transistors 13 with an interlayer insulating layer (e.g., silicon oxide film) 16, a conductive layer (metal, polysilicon, etc.) is formed and patterned to form electrodes/wiring 14. At the end of the signal processing circuit, an input/output pad 15 is placed to connect to the input (or output) of the signal processing circuit. In this embodiment, the input/output pad is formed from the same metal layer as the electrodes/wiring, but as described later, the input/output pad can be formed from any material layer that is conductive and has high etching resistance. An insulating layer (e.g., silicon oxide film) 16 for surface protection is further formed on the electrodes/wiring 14 and the input/output pad 15. In this way, the signal processing circuit layer 10 is completed.

As an example, if the thickness of the buried insulating layer 12 is 200 nm, the thickness of the MOS transistor 13 and the interlayer insulating layer 16 covering it is 600 nm, the thickness of the wiring layer 14 above it is 600 nm, and the thickness of the protective insulating layer 16 covering the wiring layer 14 is 400 nm, the thickness of the signal processing circuit layer 10 excluding the support layer 11 is the sum of these, which is approximately 1800 nm.

(b) As shown in FIG. 3B, a temporary adhesive substrate 19 is bonded onto the insulating layer 16 of the first substrate including the completed signal processing circuit layer 10. This temporary adhesive substrate 19 is, for example, a silicon substrate, a silicon oxide substrate, a glass substrate, etc., and may be a substrate of any material as long as it is possible to hold the entire substrate.

(c) As shown in FIG. 3C, the support layer 11 is removed from the first substrate. The support layer 11 may be removed by mechanical processing or chemical etching. The support layer 11 can be removed by utilizing the selectivity between the support layer (e.g., silicon layer) and the buried insulating layer (silicon oxide film). By removing the support layer 11, the thickness of the signal processing circuit layer 10 is thinned to, for example, 1800 nm, as described above.

(d) Next, a signal processing circuit is formed on the second substrate to fabricate the second signal processing circuit layer 20. The second substrate is an SOI substrate including a support layer 21, a buried insulating layer 22, and a semiconductor layer on the buried insulating layer 22. It is preferable to fabricate the signal processing circuit of the second (and each subsequent) signal processing circuit layer 20 on a fully depleted SOI substrate. Figure 3D shows the completed state of the second signal processing circuit layer 20. In the signal processing circuit layer 20, semiconductor elements 23 such as MOS transistors are connected by electrodes and wiring 24 to form a signal processing circuit having input/output pads 25. The manufacturing process of the signal processing circuit layer 20 is the same as the manufacturing process of the signal processing circuit layer 10, so details will be omitted.

In addition, since both signal processing circuit layer 10 and signal processing circuit layer 20 are signal processing circuits that process pixel signals, the circuits in both layers can be made identical. This allows the circuit design of each layer to be standardized, thereby reducing costs.

(e) Next, the signal processing circuit layer 10 of the first layer and the signal processing circuit layer 20 of the second substrate are bonded face-to-back. As shown in FIG. 3E, the region (corresponding to the pixel region) where the input/output pads 25 of the second substrate are provided is aligned and bonded so that it is shifted by one block from the region (corresponding to the pixel region) where the input/output pads 15 of the first substrate are provided. In this embodiment, the region corresponding to one pixel of the solid-state imaging element is one block, and is indicated by a dotted line. Here, it is possible to use the same substrate for the first substrate and the second substrate, and bond them by shifting them by one block, or to create a substrate with a layout shifted by one block in advance and bond them. The former is more desirable in the sense that it can reduce the cost of the photomask for forming the signal processing circuit.

(f) As shown in FIG. 3F, the support layer 21 is removed from the second substrate. This removal may be performed by mechanical processing or chemical etching. By removing the support layer 21, the signal processing circuit layer 20 is also thinned in the same manner as the signal processing circuit layer 10.

(g) Next, a signal processing circuit is formed on the third substrate to fabricate the third signal processing circuit layer 30. The third substrate is an SOI substrate including a support layer 31, a buried insulating layer 32, and a semiconductor layer on the buried insulating layer 32, and is preferably a fully depleted SOI substrate. FIG. 3G shows the completed state of the third signal processing circuit layer 30. In the signal processing circuit layer 30, semiconductor elements 33 such as MOS transistors are connected by electrodes and wiring 34, and a signal processing circuit having an input/output pad 35 is formed. The manufacturing process of the signal processing circuit layer 30 is the same as the manufacturing process of the signal processing circuit layers 10 and 20, so details are omitted. In this embodiment, the third substrate is the substrate that becomes the bottom layer, and the support layer 40 is the substrate that supports the entire stacked semiconductor device 100. The support layer 40 may be a silicon substrate that constitutes the third SOI substrate, and any material layer may be selected according to the characteristics.

(h) Next, the stack of signal processing circuit layers 10 and 20 is bonded face-to-back to the signal processing circuit layer 30 of the third substrate. As shown in FIG. 3H, the pixel region of the third substrate is aligned and bonded so that it is shifted by one block from the pixel region of the second substrate. By doing so, the input/output pads 15, 25, and 35 of each signal processing circuit layer are shifted by one block (one pixel). It is possible to increase the number of stacked signal processing circuits to three or four layers by repeating steps (f) to (h).

(i) After lamination of the signal processing circuit layers 10, 20, and 30 is completed, the temporary adhesive substrate 19 is peeled off as shown in FIG. 3I.

(j) The surface (signal processing circuit layer 10) of the semiconductor device stacked up to this point is patterned by normal means such as resist formation and exposure, and as shown in FIG. 3J, the SiO ₂ interlayer insulating layers 16, 26, 36 and the buried insulating layers (BOX) 12, 22, 32 are etched by dry or wet etching to simultaneously form holes (through holes) for connection electrodes toward the input/output pads (for example, metal layers such as Al) 15, 25, 35 of the signal processing circuits of each layer. Note that dry etching is preferably used to form holes with a high aspect ratio. At this time, an insulating film such as SiO ₂ may be stacked on the oxide film of the top layer by CVD (Chemical Vapor Deposition) or the like, and the surface may be flattened by CMP (Chemical Mechanical Polishing) before the hole formation.

In the process of forming this hole (through hole penetrating a plurality of signal processing circuit layers), the depth of the hole differs depending on the pixel, so it is necessary to prevent the wiring of the previously opened portion from disappearing by etching before the deepest hole is opened. In the present invention, the thickness of the SiO ₂ layer required for etching can be made very small by removing the support layers 11 and 21 of the fully depleted SOI, so that holes can be formed in a batch across multiple layers. If the etching selectivity ratio of SiO ₂ to the wiring material is 30:1, then for a thickness of 600 nm of the input/output pad (electrode/wiring), SiO ₂ can be etched up to 600×30=18000 nm as the range in which the input/output pad is not lost. In the above-mentioned configuration, since the thickness of one layer excluding the support layer is 1800 nm, even if up to 10 layers are stacked, the holes can be formed in a batch. The number of layers that can be stacked can be further increased by adjusting the material and process conditions to increase the etching selectivity, or by changing the device structure to make the device thickness other than the support layer thinner.

In addition, when forming a fine hole, the aspect ratio of the hole that can be formed is generally limited by the performance of the manufacturing equipment. In the present invention, in this respect, the thickness of the SiO ₂ layer required for etching can be made very small by removing the support layer of the fully depleted SOI, so that the hole can be formed across multiple layers. For example, when the aspect ratio is 20 and the diameter of the hole is 1 μm, a hole with a depth of 20 μm can be formed, but since the thickness of one layer excluding the support layer is 1800 nm, the hole can be formed even if up to 20÷1.8=11 layers are stacked. The number of layers that can be stacked can be further increased by adjusting the material and process conditions to increase the aspect ratio, or by changing the device structure to make the device thickness other than the support layer thinner.

In addition to Al, Ti, Mo, W, Nb, Ta, Cu, Cr and compounds thereof can be used as wiring materials for input/output pads. Here, it is desirable to select an etchant (gas or solution used for etching) and wiring material so that the etching selectivity between the wiring material and SiO ₂ is high. The etching selectivity of 30:1 can be sufficiently achieved by appropriately selecting the input/output pad material and etchant. The holes for the connection electrodes do not need to be connected to the metal wiring of each layer, and the diffusion layer or gate electrode of the transistor may be formed in the shape of a pad, and the holes may be opened toward the diffusion layer or gate electrode. For example, when opening a hole toward the diffusion layer, an etchant is selected so that the etching selectivity between silicon, which is the diffusion layer material, and SiO ₂ is high.

(k) After the holes are formed, as shown in FIG. 3K, a conductive material (e.g., Au) 50 that will become a connection electrode is formed by plating or the like to fill the holes.

(l) The conductive material 50 is planarized by CMP to form embedded connection electrodes 51, 52, and 53, as shown in FIG. 3L. At this point, the laminated structure on the signal processing circuit side (sometimes called a laminated signal processing circuit board) is completed.

(m) Next, in order to form a photoelectric conversion element layer 60, a photoelectric conversion element (light receiving section) or a circuit including a photoelectric conversion element is formed on the SOI substrate. Although a fully depleted SOI substrate may be used for this SOI substrate, in order to receive visible light, it is desirable for the SOI substrate to have a semiconductor layer (Si device layer) 63 having a thickness of 3 μm or more on a support layer 61 via a buried insulating layer ( _{SiO 2} ) 62. As shown in FIG. 3M, for example, impurities are introduced into the semiconductor layer 63 to form a pn junction, and a photodiode (photoelectric conversion element) 64 and an FD (floating diffusion layer) 66 are formed. In addition, a gate electrode is provided between the two to form a transfer gate 65. Then, after forming an interlayer insulating layer 68, an electrode/wiring 67 connected to the FD 66 is formed, and a part of it is used as an electrode pad for guiding a signal. Here, an amplifier circuit may be inserted between the FD 66 and the electrode/wiring 67 to amplify the signal voltage before transmitting it to the signal processing circuit of each layer. After the surface is further covered with an insulating layer 68, a resist or the like is formed and patterned, and the insulating layer 68 (SiO ₂ ) is etched by dry or wet etching to form a hole that reaches the electrode pad (for example, a metal layer such as Al) 67. Thereafter, similar to steps (k) and (l), the hole is filled with an electrode material (for example, Au) by plating or the like, and the electrode material on the insulating layer 68 is removed by CMP to form a pixel electrode 69 with a planarized surface.

(n) The stacked signal processing circuit board shown in FIG. 3L and the substrate having the photoelectric conversion element shown in FIG. 3M are bonded face-to-face as shown in FIG. 3N. At this time, they are aligned pixel by pixel and bonded so that the connection electrodes 51, 52, and 53 of the stacked signal processing circuit board are connected to the pixel electrodes 69. Finally, the support layer 61 on the light receiving side is removed to complete the stacked semiconductor device 100.

The completed stacked semiconductor device 100 has the structure shown in the cross-sectional view in FIG. 1. An example of a perspective view of the completed stacked semiconductor device (stacked solid-state imaging element) 100 is shown in FIG. 4. The signals of the pixels 60A, 60B, and 60C are processed in the signal processing circuit layers 10, 20, and 30, respectively. The squares on the surface of the stacked semiconductor device 100 are conceptual drawings of the photodiodes 64.

According to the above process, the thickness of the _SiO2 layer required for etching can be made very small by removing the support layers 11 and 21 of the fully depleted SOI substrate, so the process of forming holes for the multi-layered signal processing circuit can be performed in one go, reducing the number of processes and improving the yield. Since the fully depleted SOI substrate does not have a well structure and the parts where no transistors are formed are _SiO2 , the process of insulating holes from each other like TSV is not required.

Regarding alignment, in face-to-face bonding with the light receiving substrate, alignment is performed once for each pixel. However, since the size of the pixel electrode 69 in face-to-face bonding can be increased without exceeding the pixel pitch, the alignment precision requirements can be relaxed compared to the conventional technology of forming fine electrodes on the back surface and bonding them face-to-back. Also, when each substrate of the signal processing circuit is shifted by one block for face-to-back bonding, alignment does not need to be performed with the precision of the hole diameter, but can be performed with the precision of the wiring layer, diffusion layer, and pad size of the gate electrode of the transistor used as an input/output pad.

(Modification of the first embodiment)
5 is a cross-sectional view of a stacked semiconductor device 110 according to a first modification of the first embodiment, and FIG. 6 is a plan view of the stacked semiconductor device 110 according to the first modification. As shown in FIG. 5, the signal processing circuits of each substrate can be formed not only in one direction but also symmetrically. As seen in the plan view of FIG. 6, the pixels are folded back in the y direction (up and down), so the number of pixels can be doubled with the same number of layers. The signal output of the pixels on the upper side (y direction + side) of FIG. 6 can be output from the external input/output pad 80 provided on the upper side, and the signal output of the pixels on the lower side (y direction - side) can be output from the external input/output pad 80 provided on the lower side.

Figures 7A, 7B, and 7C show yet another modified example of the stacked semiconductor device of the first embodiment. In the first embodiment, a pixel signal processing circuit in parallel with the pixels is used, but a signal processing circuit (a pixel signal processing circuit that processes the signal of one pixel) does not have to be provided for each pixel, and a configuration in which signals from multiple pixels are sequentially switched and read out from one signal processing circuit is also possible.

Figure 7A is a plan view of a stacked semiconductor device 120 of a second modified example of the first embodiment. In the stacked semiconductor device 120 of Figure 7A, signals of the pixels in the top two rows are processed in the first signal processing circuit layer 10, signals of the pixels in the center two rows are processed in the second signal processing circuit layer 20, and signals of the pixels in the bottom two rows are processed in the third signal processing circuit layer 30. In Figure 7A, two pixels (e.g., 60A) adjacent in the column direction (y direction) share a signal processing circuit (a pixel signal processing circuit that processes a signal of one pixel). In the stacked semiconductor device 120 of Figure 7A, one block to be shifted is two pixels, and the signal processing circuit layer 10, the signal processing circuit layer 20, and the signal processing circuit layer 30 are stacked with a shift of two pixels (in the y direction). Regarding the connection between each pixel and the signal processing circuit, there is a method of providing each pixel with a connection electrode that reaches the signal processing circuit layer and switching between the two pixels in the signal processing circuit, or a method of providing one connection electrode that connects to the signal processing circuit layer corresponding to the two pixels and controlling the transfer gate or switching circuit of each pixel to switch the connection to the connection electrode. Note that the output signals of the two pixels may be output from a common external input/output pad 80, for example, in a time-division manner, or may be output from multiple external input/output pads.

Also, FIG. 7B is a plan view of a stacked semiconductor device 130 of a third modified example of the first embodiment. FIG. 7B is an example of sharing circuits in the row direction (x direction). A pixel-parallel signal processing circuit for each layer is formed for every two columns in the figure, and a signal processing circuit (a pixel signal processing circuit that processes a signal of one pixel) is shared by two pixels (for example, 60A) adjacent in the row direction (x direction). In the stacked semiconductor device 130 of FIG. 7B, the signal processing circuit layer 10, the signal processing circuit layer 20, and the signal processing circuit layer 30 are stacked with a shift of one pixel (in the y direction) as in FIG. 1, but the area in which the signal processing circuit is formed is twice as wide in the x direction. Therefore, the length in the y direction of the area in which the signal processing circuit is formed can be shortened, and the area of the semiconductor device can be reduced. As for the connection between each pixel and the signal processing circuit, as in FIG. 7A, there is a method of providing each pixel with a connection electrode that reaches the signal processing circuit layer and switching between the two pixels in the signal processing circuit, or a method of providing one connection electrode that connects to the signal processing circuit layer corresponding to the two pixels and controlling the transfer gate or switching circuit of each pixel to switch the connection to the connection electrode. The output signals of the two pixels may be output from a common external input/output pad 80, for example, in a time-division manner, or may be output from multiple external input/output pads.

Furthermore, FIG. 7C is a plan view of a stacked semiconductor device 140 of a fourth modified example of the first embodiment. FIG. 7C is an example in which a pixel-parallel signal processing circuit is shared in an area including a plurality of pixels. The signal processing circuit of each layer is formed every two columns in the figure, and a signal processing circuit (a pixel signal processing circuit that processes a signal of one pixel) is shared by four pixels (for example, 60A) adjacent in the row direction (x direction) and column direction (y direction). The signals of the four pixels are sequentially switched and read out from one signal processing circuit. In the stacked semiconductor device 140 of FIG. 7C, one block to be shifted is two pixels, and the signal processing circuit layer 10, the signal processing circuit layer 20, and the signal processing circuit layer 30 are stacked with a shift of two pixels (in the y direction). Furthermore, the area in which the signal processing circuit is formed is twice as wide in the x direction. Therefore, the length in the y direction of the area in which the signal processing circuit is formed can be shortened, and the area of the semiconductor device can be reduced. Regarding the connection between each pixel and the signal processing circuit, there is a method of providing each pixel with a connection electrode that reaches the signal processing circuit layer and switching between the four pixels in the signal processing circuit, or a method of providing one connection electrode that connects to the signal processing circuit layer corresponding to the four pixels and controlling the transfer gate or switching circuit of each pixel to switch the connection to the connection electrode. The output signals of the four pixels may be output from a common external input/output pad 80, for example, in a time-division manner, or may be output from multiple external input/output pads.

In the case of pixel parallel configuration shown in Figures 1 and 2, the number of pixels may be limited by the number of circuit layers, but as shown in Figures 7A to 7C, by also sharing signal processing circuits between multiple pixels, it is possible to implement a multi-pixel sensor and a large-scale signal processing circuit even with a stack of, for example, 10 layers. Furthermore, by increasing the number of pixels in one area in Figure 7C, a solid-state image sensor with even more pixels can be realized.

Second Embodiment
An example of a stacked semiconductor device according to a second embodiment of the present invention is shown in Fig. 8 and Fig. 9. Fig. 8 is an example of a cross-sectional view of the stacked semiconductor device 200 according to the second embodiment. Fig. 9 is an example of a plan view of the stacked semiconductor device 200 according to the second embodiment. The stacked semiconductor device 200 according to the second embodiment constitutes a solid-state imaging element, and includes a photoelectric conversion film as its light receiving portion.

The stacked semiconductor device 200 comprises a photoelectric conversion film layer 70, a first signal processing circuit layer 10 from the front side, a second signal processing circuit layer 20, a third signal processing circuit layer 30, and a support layer 40. Note that in this embodiment, the signal processing layer is composed of three layers, but this is just one example, and any number of signal processing circuit layers may be stacked as long as they are multiple layers. Here, the configuration of the signal processing circuit layers 10, 20, 30 and the support layer 40 is the same as that of the stacked semiconductor device 100 of the first embodiment in FIG. 1, so the explanation will be simplified.

The support layer 40 is a layer that supports the stacked semiconductor device 100, and may be, for example, a semiconductor substrate such as silicon or a glass substrate.

Each signal processing circuit layer 10, 20, 30 includes, for example, buried insulating layers (BOX) 12, 22, 32, semiconductor elements 13, 23, 33 such as MOS transistors, electrodes/wirings 14, 24, 34, input/output pads 15, 25, 35, insulating layers 16, 26, 36, etc. In this embodiment, the input/output pads 15, 25, 35 are input terminals of the signal processing circuit of each layer, and are arranged at the ends of the signal processing circuit in each layer. Each signal processing circuit layer 10, 20, 30 is stacked with the upper signal processing circuit shifted in the planar direction (leftward in FIG. 1) by one block (in this embodiment, an area corresponding to one pixel) relative to the lower signal processing circuit so that the positions of the input/output pads 15, 25, 35 of each layer do not overlap.

The stacked semiconductor device 200 also includes connection electrodes 51, 52, and 53 that penetrate and connect from the surface of the uppermost signal processing circuit layer 10 to the input/output pads 15, 25, and 35 of each layer. These connection electrodes 51, 52, and 53 have the function of transmitting pixel signals from the photoelectric conversion film layer 70 to the corresponding signal processing circuit layers.

The photoelectric conversion film layer 70 includes, from the side in contact with the signal processing circuit layer 10, for example, a gallium oxide (Ga2O3) film 71, a crystalline selenium (c-Se) film 72, and a transparent conductive film (ITO: indium tin oxide) 73. The photoelectric conversion film layer 70 is formed as an integral layer on the substrate, and each region connected to the connection electrodes 51, 52, and 53 constitutes a pixel (pixel region) 70A, 70B, and 70C. The signal charge generated in each region in the photoelectric conversion film layer 70 is transmitted to the signal processing circuit of each layer via the connection electrodes 51, 52, and 53.

The stacked semiconductor device 200 is a solid-state imaging element, and signal processing for each pixel can be performed in a different layer. That is, the pixel signal generated in pixel 70A is transmitted from the surface to the first-layer signal processing circuit layer 10 via the connection electrode 51, where signal processing is performed within the signal processing circuit layer 10 and output. Similarly, the pixel signal generated in pixel 70B is transmitted to the second-layer signal processing circuit layer 20 via the connection electrode 52, where signal processing is performed within the signal processing circuit layer 20 and output. Also, the pixel signal generated in pixel 70C is transmitted to the third-layer signal processing circuit layer 30 via the connection electrode 53, where signal processing is performed within the signal processing circuit layer 30 and output.

Figure 9 shows an example of a pixel array of the stacked semiconductor device 200 of the second embodiment. Pixels 70A, 70B, and 70C in the plan view correspond to pixels 70A, 70B, and 70C in the cross-sectional view of Figure 8. In Figure 9, solid lines indicate the ends of the photoelectric conversion film layer 70, and dashed lines indicate the boundaries of each pixel. In each pixel, the position of the connection electrode is conceptually drawn as a circle.

In the stacked semiconductor device 200, the signal charges of multiple pixels 70A, 70B, and 70C arranged in the x direction (row direction) in the plan view of FIG. 9 are processed by signal processing circuit layers 10, 20, and 30, respectively. Note that although four pixels are drawn in the x direction in FIG. 9, any number of pixels can be formed in the x direction.

In this embodiment, each column of the stacked semiconductor device in FIG. 9 has the same structure and circuit. That is, each pixel is provided with an independent pixel signal processing circuit, enabling pixel-parallel signal processing. Each signal processing circuit layer processes each pixel signal in a signal processing circuit arranged in the y direction, and outputs the signal to the outside from an external input/output pad 80 provided at an arbitrary position (for example, the upper direction in the plan view). The external input/output pad 80 may be provided for each signal processing circuit layer, or may be shared by multiple signal processing circuit layers.

According to the stacked semiconductor device 200 of this embodiment, since fine connection electrodes 51, 52, and 53 are used, interlayer connection can be performed within the pixel region for each pixel. In addition, the connection electrodes 51, 52, and 53 are formed after stacking the signal processing circuit layers 10, 20, and 30, and it is not necessary to perform strict alignment between the electrodes when stacking the signal processing circuit layers, and a large number of layers can be easily stacked. Furthermore, each pixel can be configured with a flat photoelectric conversion film layer 70, and a light receiving section with good characteristics can be formed by a simple manufacturing method. In this embodiment, various problems caused by the light receiving surface not being flat, that is, problems such as the occurrence of insensitive areas, uneven sensitivity between pixels, and asymmetric incidence angle dependency, can be solved. In addition, the lens focus can be matched for each pixel, and it is possible to handle incident light at a wide angle.

Next, an example of a method for manufacturing the stacked semiconductor device 200 of the second embodiment will be described. However, since steps (a) to (l) from stacking the signal processing circuit layers 10, 20, and 30 to forming the connection electrodes 51, 52, and 53 are the same as those in Figures 3A to 3L, their description will be omitted. The method for manufacturing the stacked semiconductor device 200 from this point onwards (step (m)) will be described with reference to Figure 8.

(m) To form the photoelectric conversion film layer 70, a gallium oxide (Ga2O3) film 71 is formed on the stacked signal processing circuit board (a substrate of stacked signal processing circuit layers) shown in FIG. 3L. Then, an amorphous selenium (a-Se) film is formed, heated, and crystallized to form a crystalline selenium (c-Se) film 72, and finally, ITO is formed as a transparent conductive film 73 to complete the process. A heterojunction pn photodiode is formed by combining gallium oxide, an n-type semiconductor, and crystalline selenium, a p-type semiconductor. In this way, the stacked semiconductor device 200 is completed.

The photoelectric conversion film layer 70 may be configured such that the semiconductor is a single layer of crystalline selenium (c-Se) film 72, and a Schottky junction diode is formed between the pixel electrode or the transparent electrode. A high voltage may be applied to the crystalline selenium (c-Se) film 72 to form a highly sensitive light receiving element that avalanche-multiplies the charge. In addition to crystalline selenium, materials such as amorphous selenium (a-Se), CIGS (CuInGaSe), crystalline silicon (c-Si), amorphous silicon (a-Si), cadmium telluride (CdTe), gallium arsenide (GaAs), indium phosphide (InP), and copper sulfide (Cu ₂ S), which are semiconductors that absorb light in the visible light region, may also be used.

Figure 10 shows an example of a perspective view of a completed stacked semiconductor device (stacked solid-state imaging element) 200. Note that the circles on the surface of each pixel of the stacked semiconductor device 200 are conceptual illustrations of the connection electrodes 51, 52, and 53 of each pixel.

The stacked semiconductor device 200 of the second embodiment is also formed through the same manufacturing steps (a) to (l) as those of the first embodiment, and therefore has the same effects and advantages as those of the first embodiment. That is, by removing the support layer of the fully depleted SOI substrate, the thickness of the SiO ₂ layer to be etched to form the holes (through holes) can be made very thin, so that the process of forming holes in the multi-layered signal processing circuit can be performed in one go, thereby reducing the number of processes and improving the yield. In the fully depleted SOI substrate, since it does not have a well structure and the parts where the transistors are not formed are SiO ₂ , the process of insulating holes from each other as in the case of TSV is not required.

In addition, since the process of bonding surfaces with electrodes together (hybrid bonding) is not required, the number of processes can be reduced and yields can be improved. When shifting each substrate of the signal processing circuit by one block to bond face-to-back, alignment does not need to be done with the precision of the hole diameter, but can be done with the precision of the wiring layer, diffusion layer, and pad size of the gate electrode of the transistor used as the input/output pad.

Furthermore, in the stacked semiconductor device 200 of the second embodiment, the light receiving section is formed from the photoelectric conversion film layer 70, and there is no need for a process of bonding the stacked signal processing circuit board (Figure 3L) and the substrate having the light receiving section (Figure 3M). This further reduces the number of alignment steps, further simplifying the manufacturing process.

(Modification of the second embodiment)
FIG. 11 is a cross-sectional view of a stacked semiconductor device 210 of a first modified example of the second embodiment, and FIG. 12 is a plan view of the stacked semiconductor device 210 of the first modified example. As shown in FIG. 11, the signal processing circuits of each substrate can be formed not only in one direction but also symmetrically. As seen in the plan view of FIG. 12, the pixels are folded back in the y direction (up and down), so the number of pixels can be doubled with the same number of layers. The signal output of the pixels on the upper side (y direction + side) of FIG. 12 can be output from the external input/output pad 80 provided on the upper side, and the signal output of the pixels on the lower side (y direction - side) can be output from the external input/output pad 80 provided on the lower side.

13A is a plan view of a stacked semiconductor device 220 of a second modified example of the second embodiment. In the stacked semiconductor device 220 of FIG. 13A, signals of the pixels in the top two rows are processed in the signal processing circuit layer 10 of the first layer, signals of the pixels in the center two rows are processed in the signal processing circuit layer 20 of the second layer, and signals of the pixels in the bottom two rows are processed in the signal processing circuit layer 30 of the third layer. In FIG. 13A, two pixels (e.g., 70A) adjacent in the column direction (y direction) share a signal processing circuit (a pixel signal processing circuit that processes a signal of one pixel). In the stacked semiconductor device 220 of FIG. 13A, one block to be shifted is two pixels, and the signal processing circuit layer 10, the signal processing circuit layer 20, and the signal processing circuit layer 30 are stacked with a shift of two pixels (in the y direction). For the connection between each pixel and the signal processing circuit, a method is used in which a connection electrode that reaches the signal processing circuit layer is provided in each pixel, and two pixels are switched in the signal processing circuit. The signals from the two pixels may be output, for example, in a time-division manner from a common external input/output pad 80, or may be output from multiple external input/output pads.

Also, FIG. 13B is a plan view of a stacked semiconductor device 230 of a third modified example of the second embodiment. FIG. 13B is an example in which a circuit is shared in the row direction (x direction). A signal processing circuit of each layer is formed every two columns in the figure, and a signal processing circuit (a pixel signal processing circuit that processes a signal of one pixel) is shared by two pixels (for example, 70A) adjacent in the row direction (x direction). In the stacked semiconductor device 230 of FIG. 13B, the signal processing circuit layer 10, the signal processing circuit layer 20, and the signal processing circuit layer 30 are stacked with a shift of one pixel (in the y direction) as in FIG. 1, but the area in which the signal processing circuit is formed is twice as wide in the x direction. Therefore, the length in the y direction of the area in which the signal processing circuit is formed can be shortened, and the area of the semiconductor device can be reduced. As for the connection between each pixel and the signal processing circuit, a method is used in which a connection electrode that reaches the signal processing circuit layer is provided in each pixel and two pixels are switched in the signal processing circuit as in FIG. 13A. The output signals of the two pixels may be output, for example, in a time-division manner from a common external input/output pad 80, or may be output from multiple external input/output pads.

Furthermore, FIG. 13C is a plan view of a stacked semiconductor device 240 of a fourth modified example of the second embodiment. FIG. 13C is an example in which a pixel-parallel signal processing circuit is shared in an area including a plurality of pixels. The signal processing circuit of each layer is formed every two columns in the figure, and a signal processing circuit (a pixel signal processing circuit that processes a signal of one pixel) is shared by four pixels (e.g., 70A) adjacent in the row direction (x direction) and column direction (y direction). The signals of the four pixels are sequentially switched and read out from one signal processing circuit. In the stacked semiconductor device 240 of FIG. 13C, one block to be shifted is two pixels, and the signal processing circuit layer 10, the signal processing circuit layer 20, and the signal processing circuit layer 30 are stacked with a shift of two pixels (in the y direction). Furthermore, the area in which the signal processing circuit is formed is twice as wide in the x direction. Therefore, the length in the y direction of the area in which the signal processing circuit is formed can be shortened, and the area of the semiconductor device can be reduced. For the connection between each pixel and the signal processing circuit, a connection electrode that reaches the signal processing circuit layer is provided for each pixel, and the four pixels are switched within the signal processing circuit. The output signals of the four pixels may be output, for example, in a time-division manner from a common external input/output pad 80, or may be output from multiple external input/output pads.

In the case of pixel parallel configuration shown in Figures 8 and 9, the number of pixels may be limited by the number of circuit layers, but as shown in Figures 13A to 13C, by also sharing signal processing circuits between multiple pixels, it is possible to implement a multi-pixel sensor and a large-scale signal processing circuit even with a stack of, for example, 10 layers. Furthermore, by increasing the number of pixels in one area in Figure 13C, a solid-state imaging element with even more pixels can be realized.

Other Embodiments
In the first and second embodiments, a photoelectric conversion element layer 60 or a photoelectric conversion film layer 70 is formed on the surface of the stacked signal processing circuit layers to fabricate a stacked solid-state imaging element (image sensor), but it is also possible to fabricate a semiconductor device having other functions.

In the present invention, the basic structure is a laminated signal processing circuit board as shown in FIG. 3L, in which multiple signal processing circuit layers 10, 20, 30 are laminated and connection electrodes 51, 52, 53 are formed on the surfaces of the layers to connect to the input/output pads 15, 25, 35 of the layers. The number of signal processing circuit layers can be any number, and other functional layers can also be formed on the surface of this board.

For example, an organic EL (Electroluminescence) layer is formed on the surface of the laminated signal processing circuit board shown in FIG. 3L, and the signal processing circuits of each layer are made into organic EL light-emitting circuits. With this configuration, the organic EL regions connected to the connection electrodes can be made into light-emitting pixels, and each pixel can be made to emit light, thereby making it possible to fabricate a display device.

In addition, a pressure sensor is formed for each block (corresponding to a pixel) on the surface of the laminated signal processing circuit board shown in Figure 3L, and the signal processing circuit of each layer is made into a signal processing circuit of the pressure sensor. With this configuration, a pressure-sensing device can be fabricated that can detect pressure for each minute block.

In addition, an actuator is formed for each block (corresponding to a pixel) on the surface of the laminated signal processing circuit board shown in Figure 3L, and the signal processing circuit of each layer is used as the actuator operation circuit. With this configuration, it is possible to operate the actuator for each fine block, and a fine operating device can be produced.

In this way, it can be applied to various integrated devices, such as functional devices that require circuits for each unit (block), and devices can be formed with high yield.

In addition, the connection electrodes 51, 52, 53 connected to the input/output pads 15, 25, 35 of each layer can be used as output electrodes, and electrode pads can be formed on the surfaces of the connection electrodes 51, 52, 53 to serve as the external input/output pads 80 shown in Figures 2 and 6. For example, circuits such as logic and memory can be formed on each signal processing circuit layer 10, 20, 30, and signals can be input/output directly to/from each layer using the external input/output pads 80 on the surface.

The lamination technology of the present invention allows the process of forming holes in multi-layered signal processing circuits to be performed in one go, and the alignment precision of the bonding process can be minimized, which reduces the number of processes and improves yield. It also allows the fabrication of highly integrated devices with excellent characteristics.

The above-mentioned embodiments have been described as representative examples, but it will be apparent to those skilled in the art that many modifications and substitutions can be made within the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited by the above-mentioned embodiments, and various modifications or changes are possible without departing from the scope of the claims. For example, the functions included in each configuration, each process, etc. described in the embodiments can be rearranged so as not to cause logical inconsistencies, and multiple configurations, processes, etc. can be combined into one or divided.

Reference Signs List 10, 20, 30 Signal processing circuit layer 11, 21, 40 Support layer 12, 22, 32 Buried insulating layer 13, 23, 33 Semiconductor element 14, 24, 34 Electrode/wiring 15, 25, 35 Input/output pad 16, 26, 36 Insulating layer 51, 52, 53 Connection electrode 60 Photoelectric conversion element layer 61 Support layer 62 Insulating layer 63 Semiconductor layer 64 Photodiode 65 Transfer gate 66 FD (floating diffusion layer)
67 Electrode/wiring 68 Insulating layer 69 Pixel electrode 70 Photoelectric conversion layer 71 Gallium oxide film 72 Crystalline selenium film 73 Transparent conductive film 100, 110, 120, 130, 140 Stacked semiconductor device 200, 210, 220, 230, 240 Stacked semiconductor device

Claims (9)

A stacked semiconductor device formed by stacking a plurality of signal processing circuit layers,
the signal processing circuit layer includes an input/output pad at an end of the signal processing circuit;
the signal processing circuit layers are stacked such that the signal processing circuits on the upper side are shifted by one block in a planar direction relative to the signal processing circuits on the lower side so that the positions of the input/output pads do not overlap;
1. A stacked semiconductor device comprising: connection electrodes embedded in through holes extending from a surface of an uppermost signal processing circuit layer to the input/output pads of each signal processing circuit layer. 2. The stacked semiconductor device according to claim 1,
a photoelectric conversion element layer including a plurality of photoelectric conversion elements on a surface of the uppermost signal processing circuit layer;
4. A stacked semiconductor device, comprising: a pixel electrode of each of said photoelectric conversion elements connected to said connection electrodes, said pixel electrode being electrically connected to said connection electrodes; 2. The stacked semiconductor device according to claim 1,
A photoelectric conversion film layer is further provided on a surface of the uppermost signal processing circuit layer,
A stacked semiconductor device, wherein each of the regions of the photoelectric conversion film layer connected to the connection electrode is used as a pixel region. 4. The stacked semiconductor device according to claim 2,
4. A stacked semiconductor device, wherein the one block corresponds to one or a plurality of pixels. 5. The stacked semiconductor device according to claim 2,
The signal processing circuit is a pixel signal processing circuit arranged in parallel with respect to each pixel, and a pixel signal processing circuit for processing a signal of one pixel is shared by a plurality of pixels. 6. The stacked semiconductor device according to claim 1,
4. The stacked semiconductor device according to claim 3, wherein a part of said connection electrode is used as an output electrode of said signal processing circuit. A method for manufacturing a stacked semiconductor device formed by stacking a plurality of signal processing circuit layers, comprising the steps of:
forming the signal processing circuitry layer with input/output pads at edges of the signal processing circuitry;
laminating the signal processing circuit layers by shifting the upper signal processing circuit by one block at a time in a planar direction relative to the lower signal processing circuit so that the positions of the input/output pads do not overlap;
simultaneously forming a plurality of through holes extending from a surface of the uppermost signal processing circuit layer to the input/output pads of each signal processing circuit layer;
and filling the plurality of through holes with a conductive material to form connection electrodes. 8. The method for manufacturing a stacked semiconductor device according to claim 7,
A method for manufacturing a stacked semiconductor device, comprising the steps of stacking a photoelectric conversion element layer having a plurality of photoelectric conversion elements on a surface of the uppermost signal processing circuit layer, and connecting pixel electrodes of the photoelectric conversion elements to the connection electrodes, respectively. 8. The method for manufacturing a stacked semiconductor device according to claim 7,
A method for manufacturing a stacked semiconductor device, comprising the steps of further forming a photoelectric conversion film layer on a surface of the uppermost signal processing circuit layer, and forming regions of the photoelectric conversion film layer connected to the connection electrodes into pixel regions.

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