JP7570168B2 - Silicon carbide semiconductor device - Google Patents

Description

This invention relates to a silicon carbide semiconductor device.

In silicon carbide (SiC), thermal diffusion of p-type impurities such as aluminum (Al) is difficult to occur. For this reason, it is known that the p-type impurity is ion-implanted in multiple stages (multiple times) at different acceleration voltages in order to form a p-type region in a semiconductor substrate made of SiC (hereinafter referred to as a SiC substrate) by ion-implanting p-type impurities, which has a so-called BOX (rectangular) dopant concentration distribution in which the dopant (acceptor) concentration is kept constant from the ion-implanted surface of the SiC substrate to a specified depth.

By varying the acceleration voltage for each of the multiple stages of ion implantation, it is possible to vary the depth position (average distance from the ion implantation surface: range) at which the doping concentration shows its maximum value (peak concentration) in the doping concentration distribution formed by each ion implantation. The range of ion implantation can be roughly predicted based on the acceleration voltage, and the acceleration voltage for ion implantation can be precisely controlled, so it is possible to control the dopant concentration distribution in the p-type region as designed.

As a method for forming a p-type region that constitutes a voltage-resistant structure, a method has been proposed in which the impurity is aluminum, and the p-type region is formed by one-stage ion implantation with an acceleration voltage of 350 keV, thereby increasing the margin of the etching amount for removing the damaged layer caused by the activation annealing for activating the ion-implanted impurity, and maintaining the p-type impurity in the p-type region at a predetermined dose (see, for example, Patent Document 1 below).

In the following Patent Document 1, in order to increase the margin of the amount of etching required to remove the damaged layer, a p-type region is formed by one-stage ion implantation under the above conditions such that the depth position (hereinafter referred to as peak depth) at which the impurity concentration in the depth direction reaches its peak (hereinafter referred to as peak concentration (maximum value)) is located deeper than 0.35 μm from the ion implantation surface of the SiC substrate, and is 1/10 or less of the peak impurity concentration in the surface region of the ion implantation surface of the SiC substrate.

As another method for forming the p-type regions that constitute the breakdown voltage structure, a method has been proposed in which multiple sets of p-type regions, each set consisting of a high-concentration region and a low-concentration region adjacent in the depth direction, are formed by multiple stages of ion implantation with different acceleration voltages (see, for example, Patent Document 2 below). Each of these high-concentration and low-concentration regions has a peak concentration and a tail in which the impurity concentration decreases as the concentration increases from the peak depth of the peak concentration.

JP 2012-129492 A International Publication No. 2012/056705

In the actual manufacturing process of silicon carbide semiconductor devices, the impurities are not activated simply by implanting ions into SiC, so after the ion implantation of the impurities, high-temperature activation annealing (heat treatment) is performed to activate the impurities as dopants (donors or acceptors). It has traditionally been said that impurities in SiC barely move, but the inventors' intensive research has revealed that under certain conditions (impurity type, crystal plane orientation, doping amount), the amount of movement of impurities in SiC during activation annealing is greater than previously known.

It has been confirmed that this problem becomes more pronounced as the total dose of impurities implanted into SiC becomes smaller, as the dopant concentration of the epitaxial layer into which the impurities are implanted becomes lower, and when the impurities implanted are aluminum or when the ion-implanted surface is the (0001) surface of SiC, or the so-called Si surface. Specifically, examples of structures formed under conditions that increase the amount of movement of impurities in SiC include junction termination extension (JTE) structures disposed in edge termination regions of silicon carbide semiconductor devices.

It was also found that as the amount of impurity migration in SiC increases, the dose of impurities remaining in SiC after activation annealing becomes smaller than the dose of the ion-implanted impurities. If this phenomenon occurs in a JTE structure, the designed breakdown voltage cannot be obtained. Furthermore, if the area occupied by the edge termination region relative to the area of the SiC substrate (semiconductor chip) is increased so that the designed breakdown voltage is equal to or greater than the desired breakdown voltage, in anticipation of the reduction in breakdown voltage due to the reduction in the dose of impurities in the p-type region that constitutes the JTE, the number of chips obtained from one semiconductor wafer decreases, and the production (manufacturing) cost per chip increases.

The present invention aims to provide a silicon carbide semiconductor device that can suppress the decrease in the dose of impurities before and after activation annealing in order to solve the problems associated with the conventional technology described above.

In order to solve the above-mentioned problems and achieve the object of the present invention, the silicon carbide semiconductor device according to the present invention comprises a first conductivity type silicon carbide layer made of silicon carbide and a second conductivity type region, and has the following characteristics. The second conductivity type region reaches a predetermined depth from the surface of the first conductivity type silicon carbide layer. The second conductivity type region contains a second conductivity type dopant at a predetermined dose. The second conductivity type dopant is aluminum.

The second conductivity type dopant concentration distribution in the second conductivity type region is a Gaussian distribution exhibiting peaks of dopant concentration at different heights at a plurality of different depth positions within a range of 0.18 μm or more and less than 0.35 μm from the surface of the first conductivity type silicon carbide layer, and the peaks do not exhibit less than 0.18 μm from the surface of the first conductivity type silicon carbide layer. A dose of the second conductivity type dopant present in a portion of the second conductivity type region that is 0.1 μm or less from the surface of the first conductivity type silicon carbide layer is less than 10% of a total dose of the second conductivity type dopant in the second conductivity type region. The surface of the first conductivity type silicon carbide layer is a (0001) plane.

In the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, a maximum concentration of the second conductivity type dopant in the second conductivity type region is not less than 1×10 ¹⁷ /cm ³ .

The silicon carbide semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the first conductivity type silicon carbide layer has a first conductivity type dopant concentration of 1×10 ¹⁶ /cm ³ or less. The silicon carbide semiconductor device according to the present invention is characterized in that the first conductivity type silicon carbide layer has a first conductivity type dopant concentration of 4×10 ¹⁴ /cm ³ or less.

The silicon carbide semiconductor device according to the present invention is the above-mentioned invention, in which the semiconductor substrate is provided with an active region through which the main current of the element flows, and a termination region surrounding the periphery of the active region. The first conductivity type silicon carbide layer constitutes the semiconductor substrate, and the surface forms the front surface of the semiconductor substrate in the termination region. In the termination region, the first conductivity type silicon carbide layer is provided with a breakdown voltage structure in which a plurality of the second conductivity type regions, the concentration of which is lower the further outward the region is located, are arranged adjacent to each other.

The silicon carbide semiconductor device according to the present invention can suppress the diffusion of the second conductivity type dopant in the second conductivity type region from the semiconductor substrate to the outside during activation annealing performed after ion implantation, thereby suppressing the decrease in the dose of the impurity in the second conductivity type region before and after activation annealing.

1 is a plan view showing a layout of a silicon carbide semiconductor device according to an embodiment as viewed from the front surface side of a semiconductor substrate. 2 is a cross-sectional view showing the cross-sectional structure along the line A-A' in FIG. 1. 2 is a characteristic diagram showing an example of a doping concentration distribution of a p-type impurity ion-implanted to form a p-type region that constitutes the JTE structure of FIG. 1. 4 is a table showing an example of ion implantation conditions for forming the total doping concentration distribution of FIG. 3; FIG. 13 is a characteristic diagram showing the relationship between the dose amount of p-type impurities in the p-type region and the breakdown voltage in the embodiment. FIG. 13 is a characteristic diagram showing a dopant concentration distribution in a p-type region in a conventional example. 1 is a table showing an example of general ion implantation conditions for forming a p-type region having a BOX-type dopant concentration distribution.

The preferred embodiments of the silicon carbide semiconductor device and the method of manufacturing the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the attached drawings. In this specification and the attached drawings, in layers and regions marked with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - marked with n or p respectively indicate a higher impurity concentration and a lower impurity concentration than layers and regions not marked with that sign. In the following description of the embodiments and the attached drawings, similar configurations are marked with the same reference numerals, and duplicated explanations will be omitted. In addition, in the notation of Miller indices, "-" means a bar attached to the index immediately following it, and placing "-" before an index indicates a negative index.

(overview)
The present inventors have found that even if the p-type region does not have a BOX (rectangular) type dopant concentration distribution in which the dopant (acceptor) concentration from the ion implantation surface of the SiC substrate to a predetermined depth is kept constant, it is possible to suppress a decrease in the dose of the p-type impurity in the p-type region during activation annealing and to maintain the dose of the p-type impurity in the p-type region within a design range, thereby suppressing characteristic variations (e.g., a decrease in breakdown voltage) from the design conditions of the silicon carbide semiconductor device. The present invention has been made based on findings from Experiments 1 and 2 described below and theoretical considerations.

(Embodiment)
An example of the structure of a silicon carbide semiconductor device produced (manufactured) by the method for producing a silicon carbide semiconductor device according to an embodiment will be described. Fig. 1 is a plan view showing a layout of the silicon carbide semiconductor device according to the embodiment as viewed from the front surface side of a semiconductor substrate. Fig. 2 is a cross-sectional view showing a cross-sectional structure taken along line A-A' in Fig. 1. Fig. 2 shows a portion from the outermost unit cell (on the chip end side) of a plurality of unit cells (element constituent units) arranged in an active region 10 to the chip end.

Figure 3 is a characteristic diagram showing an example of the doping concentration distribution of p-type impurities ion-implanted to form the p-type region constituting the JTE structure of Figure 1. Figure 4 is a chart showing an example of ion implantation conditions for forming the total doping concentration distribution 60 of Figure 3. Figure 3 shows the results of simulating the doping concentration distributions 61 and 62 of the p-type impurities before activation annealing for each ion implantation and the total doping concentration distribution 60. The horizontal axis of Figure 3 is the depth from the front surface (ion implantation surface) of the SiC substrate 40, and the vertical axis is the doping concentration.

The silicon carbide semiconductor device 50 according to the embodiment shown in Figures 1 and 2 comprises a semiconductor substrate (SiC substrate (semiconductor chip)) 40 made of silicon carbide (SiC), an active region 10 in which a semiconductor element having a predetermined element structure is arranged, and an edge termination region 20 in which a predetermined breakdown voltage structure is arranged. The active region 10 is a region through which a main current flows when the vertical MOSFET is in an on-state. The active region 10 has, for example, a substantially rectangular planar shape. The periphery of the active region 10 is surrounded by the edge termination region 20.

The edge termination region 20 is a region between the active region 10 and the side surface (chip end) of the SiC substrate 40, and maintains a breakdown voltage by mitigating the electric field on the front surface side of the SiC substrate 40. The breakdown voltage is the limit voltage at which the semiconductor device does not malfunction or break down. In the edge termination region 20, a breakdown voltage structure such as a junction termination extension (JTE) structure 30 or a field limiting ring (FLR) is disposed. Here, an example is described in which a JTE structure 30 is disposed in the edge termination region 20.

In the active region 10, for example, a vertical MOSFET having a trench gate structure is disposed as a semiconductor element having a predetermined element structure. The trench gate structure has a structure in which a gate electrode 9 is embedded through a gate insulating film 8 inside a trench 7 that reaches a predetermined depth from the front surface of the SiC substrate 40. A p-type base region 4, an n ⁺ -type source region 5, and a p ⁺⁺ -type contact region 6 of the vertical MOSFET are selectively provided between adjacent trenches 7 (mesa regions).

The SiC substrate 40 is formed by epitaxially growing the silicon carbide layers 42, 43 which become the n ^- type drift region 2, the n-type current diffusion region 3, and the p-type base region 4 on an n ⁺ type starting substrate 41 made of silicon carbide. The dopant (donor) concentration of the ^n- type silicon carbide layer (first conductive type silicon carbide layer) 42 is, for example, about 1× ¹⁰¹⁶ /cm3 or ^less , and is preferably about 1× ¹⁰¹⁴ /cm3 or ^more and 4× ¹⁰¹⁴ /cm3 ^or less in order to achieve a breakdown voltage of 20 kV or more. The crystal plane orientation of the front surface (the surface on the n ^- type silicon carbide layer 42 side) of the SiC substrate 40 is preferably, for example, the (0001) plane, so-called Si plane. The reason is that the above-mentioned problems are prominent, and the effects of the present invention are greatly obtained.

The trench 7 penetrates the p-type silicon carbide layer 43 from the front surface of the SiC substrate 40 in the depth direction to reach the n ^- type silicon carbide layer 42. The depth direction is the direction from the front surface of the SiC substrate 40 to the back surface (the surface on the n ⁺ type starting substrate 41 side). The n ⁺ type starting substrate 41 functions as an n ⁺ type drain region 1. The p-type base region 4 is provided on the front surface side of the SiC substrate 40 in the active region 10. The p-type base region 4 extends outward from the active region 10 to a step 21 described later.

The n ⁺ type source region 5 and the p ⁺⁺ type contact region 6 are provided between the front surface of the SiC substrate 40 and the p type base region 4 in contact with the p type base region 4. The n ⁺ type source region 5 and the p ⁺⁺ type contact region 6 are exposed in a portion 40a (hereinafter referred to as a first surface) of the front surface of the SiC substrate 40 that is closer to the active region 10 than a step 21 described later. The n ⁺ type source region 5 is disposed closer to the trench 7 than the p ⁺⁺ type contact region 6, and faces the gate electrode 9 via a gate insulating film 8 on a sidewall of the trench 7.

The n ^- type drift region 2 is provided on the back surface side of the SiC substrate 40 relative to the p-type base region 4. An n-type current diffusion region 3 is provided between the n ^- type drift region 2 and the p-type base region 4, in contact with the n ^- type drift region 2 and the p-type base region 4. The n-type current diffusion region 3 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. The n-type current diffusion region 3 is disposed in the mesa region, and is adjacent to the trench 7, for example.

Inside the n-type current diffusion region 3, first to third p ⁺ -type regions 11 to 13 are selectively provided. The first p ⁺ -type region 11 faces the bottom surface of the trench 7 in the depth direction. The first p ⁺ -type region 11 is disposed at a position deeper than the interface between the p-type base region 4 and the n-type current diffusion region 3 and separated from the p-type base region 4. The outermost first p ⁺ -type region 11 (hereinafter referred to as the outermost first p ⁺ -type region 11a) extends outside a step 21 described later and is exposed to a second surface 40b described later on the front surface of the SiC substrate 40.

The second p ⁺ type region 12 is provided in the mesa region, away from the first p ⁺ type region 11 and the trench 7. The second p ⁺ type region 12 contacts the p-type base region 4. The third p ⁺ type region 13 is disposed between the outermost first p ⁺ type region 11a and the p-type base region 4, and contacts the outermost first p ⁺ type region 11a and the p-type base region 4. The third p ⁺ type region 13 extends from the outermost trench 7a to a step 21 described later. The first and 2 p ⁺ type regions 11 and 12 have the function of reducing electric field concentration on the gate insulating film 8 at the bottom surface of the trench 7.

The interlayer insulating film 14 is provided on the entire front surface of the SiC substrate 40 in the active region 10 so as to cover the gate electrode 9. The source electrode 15 contacts the n ⁺ type source region 5 and the p ⁺⁺ type contact region 6 through a contact hole opened in the interlayer insulating film 14, and is electrically connected to these regions. The source electrode 15 may extend onto a field oxide film 22 described later. A drain electrode 16 is provided on the rear surface of the SiC substrate 40 (the rear surface of the n ⁺ type starting substrate 41).

In edge termination region 20, for example, p-type silicon carbide layer 43 may be removed from the entire area of edge termination region 20 to form a step 21 in which the front surface of SiC substrate 40 is made lower (recessed toward the drain side) at portion 40b of edge termination region 20 (hereinafter referred to as second surface) than first surface 40a (portion of active region 10). By forming step 21, n ^- type silicon carbide layer 42 is exposed at second surface 40b on the front surface of SiC substrate 40, which is located outside step 21.

The outermost first p ⁺ -type region 11a is exposed on the active region 10 side of the second surface 40b of the front surface of the SiC substrate 40. The p-type base region 4 and the third p + -type region 13 are exposed in a portion 40c (mesa edge of the step 21: hereinafter referred to as the third surface) between the first surface 40a and the second surface 40b of the front surface of the SiC substrate 40. Exposing to the second and third surfaces 40b and 40c of the front surface of the SiC substrate 40 means that they are disposed in the surface regions of the second ^and third surfaces 40b and 40c of the front surface of the SiC substrate 40 and are in contact with the field oxide film 22.

In addition, in the surface region of the second surface 40b of the front surface of the SiC substrate 40, a JTE structure 30 is provided adjacent to the first p ⁺ type region 11a, outside the outermost first p ⁺ type region 11a. The JTE structure 30 is a breakdown voltage structure in which a plurality of p-type regions (two in this case; hereinafter, the first and second JTE regions (second conductivity type regions) 31, 32 from the active region 10 side) are adjacently arranged, with the dopant (acceptor) concentration being lowered as they are arranged on the outer side. The p-type dopant concentration of the first and second JTE regions 31, 32 is higher than the n ^-type dopant concentration of the n ^-type silicon carbide layer 42 (n ^-type drift region). The p-type dopant concentration of the first and second JTE regions 31, 32 is lower than the p ⁺ type dopant concentration of the outermost first p ⁺ type region 11a.

The first JTE region 31 is adjacent to the outer side of the outermost first p ⁺ -type region 11a. The second JTE region 32 is adjacent to the outer side of the first JTE region 31. A predetermined breakdown voltage is ensured in the edge termination region 20 by the pn junction between the first and second JTE regions 31 and 32 and the n ^- -type drift region 2. The multiple p-type regions (the first and second JTE regions 31 and 32) constituting the JTE structure 30 are each formed by ion implantation of p-type impurities from the second surface 40b of the front surface of the SiC substrate 40 into the n ^- -type silicon carbide layer 42.

The p-type region constituting the JTE structure 30 is formed by ion-implanting p-type impurities into the n ^- type silicon carbide layer 42 from a second surface 40b (described later) on the front surface of the SiC substrate 40 in one step or in multiple steps (multiple times) at different acceleration voltages, and then performing activation annealing to activate the ion-implanted p-type impurities as dopants (acceptors). The p-type impurity used in the ion implantation to form the p-type region constituting the JTE structure 30 is, for example, aluminum (Al). FIG. 3 shows doping concentration distributions 61 and 62 of the p-type impurities before activation annealing and a total doping concentration distribution 60 thereof.

The total doping concentration distribution 60 of the p-type impurity ion-implanted to form the p-type region constituting the JTE structure 30 before activation annealing shows a maximum value (peak concentration) of the doping concentration in a portion 60b that is more than 0.1 μm from the second surface 40b of the front surface of the SiC substrate 40. When a p-type region is formed by multiple stages of ion implantation, there may be multiple points (two in FIG. 3) where the peak concentration is present in the total doping concentration distribution 60 of the p-type impurity before activation annealing. When a p-type region is formed by multiple stages of ion implantation, the points where the peak concentration is present in the total doping concentration distribution 60 are the depth positions of the ranges of one or more of the multiple stages of ion implantation.

In addition, the total doping concentration distribution 60 of the p-type impurity ion-implanted to form the p-type region constituting the JTE structure 30 before activation annealing has a gradient in which the doping concentration decreases from the shallowest peak depth of the doping concentration toward the second surface 40b in the portion 60a at a depth of 0.1 μm or less from the second surface 40b of the front surface of the SiC substrate 40. The total doping concentration distribution 60 of the p-type impurity before activation annealing may be a Gaussian distribution (FIG. 3) or a BOX type (not shown) in the portion 60b more than 0.1 μm from the second surface 40b of the front surface of the SiC substrate 40.

When forming the p-type region that constitutes the JTE structure 30, the p-type impurity is ion-implanted in one stage or in multiple stages at different acceleration voltages at a depth position that is equal to or greater than the amount of movement of the p-type impurity in the SiC substrate 40 that occurs during activation annealing (approximately 0.18 μm) and less than 0.35 μm from the second surface 40b of the front surface of the SiC substrate 40, thereby forming one p-type region having the total doping concentration distribution 60 of the p-type impurity before activation annealing described above.

When forming a p-type region by ion implantation of aluminum as a p-type impurity, if the range of ion implantation is 0.35 μm or more from the ion implantation surface, the peak depth of the doping concentration distribution 61, 62 of the p-type impurity before activation annealing becomes too deep, and the distribution width in the depth direction becomes wider. On the other hand, as in this embodiment, by setting the acceleration voltage to about 250 keV or less so that the range of ion implantation is at a depth position less than 0.35 μm from the ion implantation surface, the doping concentration distribution 61, 62 of the p-type impurity before activation annealing can be kept at a high peak concentration while suppressing the expansion of the distribution width in the depth direction.

Specifically, in forming the p-type region constituting the JTE structure 30, multiple stages of ion implantation with different acceleration voltages are performed with a range of 0.18 μm or more and less than 0.35 μm from the second surface 40b of the front surface of the SiC substrate 40. In addition, ion implantation to form the p-type region constituting the JTE structure 30 is not performed with a range of less than 0.18 μm from the second surface 40b of the front surface of the SiC substrate 40. For example, when the dopant is aluminum, the acceleration voltage of ion implantation is limited to 150 keV or more, and ion implantation is not performed at an acceleration voltage less than 150 keV, thereby realizing ion implantation with a range of 0.18 μm or more from the second surface 40b of the front surface of the SiC substrate 40.

That is, for example, among the ion implantation conditions (see FIGS. 6 and 7) in the conventional method for forming the p-type region 100 (hereinafter referred to as the conventional method) described later, the fourth and fifth stages (80 keV, 30 keV) of ion implantation with a range of less than 0.18 μm from the front surface of the SiC substrate are omitted, and the first stage (350 keV) of ion implantation with a range of 0.35 μm or more is omitted, and only the second and third stages of ion implantation are performed. FIG. 3 shows the results of simulating the doping concentration distributions 61 and 62 of the p-type impurity before activation annealing for the first and second stages of ion implantation in FIG. 4, and the total doping concentration distribution 60.

Here, the dose of each stage of ion implantation is adjusted so that the peak concentration of the doping concentration distributions 61, 62 of p-type impurities before activation annealing for each stage of ion implantation to form one p-type region is 1×10 ¹⁷ /cm ³ or more, and the dose of the total doping concentration distribution 60 obtained by integrating these doping concentration distributions 61, 62 is approximately the same as the dose of the total doping concentration distribution 110 of p-type impurities before activation annealing in the conventional method. As a result, in this embodiment, even if the number of ion implantation stages is smaller than the ion implantation conditions of the conventional method, the breakdown voltage of the edge termination region 20 can be made to be approximately the same as the designed breakdown voltage determined based on the design value of the total dose of p-type impurities in the p-type region 100 of the conventional example, and can be made higher than the actual breakdown voltage of the conventional example. The reason is as follows.

In the conventional example, the total dose of p-type impurities in the p-type region 100 is reduced by activation annealing as described below. Therefore, the breakdown voltage of the edge termination region in the conventional example is lower than the design breakdown voltage determined based on the design value of the total dose of p-type impurities ion-implanted to form the p-type region 100. On the other hand, in the embodiment, by not performing 4- or 5-stage ion implantation with a range of less than 0.18 μm from the second surface 40b of the front surface of the SiC substrate 40, the p-type impurities moving in the SiC substrate 40 during activation annealing are stopped within the SiC substrate 40 and hardly move outside the SiC substrate 40. This is because it is possible to suppress the reduction in the total dose of p-type impurities in the p-type region that occurs during activation annealing compared to the conventional method.

Specifically, the dose of p-type dopants (activated p-type impurities) present in the portion 60a of the p-type region at a depth of 0.1 μm or less from the second surface 40b of the front surface of the SiC substrate 40 after the activation annealing is less than 10% of the total dose of p-type impurities (non-activated p-type impurities) ion-implanted into the n ^- type silicon carbide layer 42 to form the p-type region. Therefore, the total dose of p-type dopants present in the portion 60b of the p-type region after the activation annealing that is more than 0.1 μm from the second surface 40b of the front surface of the SiC substrate 40 can be maintained at 90% or more of the total dose of p-type impurities in the p-type region before the activation annealing. This makes it possible to realize a design breakdown voltage determined based on a design value of the total dose of ion-implanted p-type impurities.

More specifically, the total dose of the p-type impurities in the p-type region after the activation annealing is preferably, for example, about 5×10 ¹² /cm ² or more and 7×10 ¹² /cm ² or less (the range indicated by the arrow B in FIG. 5). For this reason, the p-type impurities are ion-implanted in a plurality of stages so that the total dose of the p-type impurities is within the above range or slightly greater than the above range. In this embodiment, as described above, the p-type impurities do not substantially move outside the SiC substrate 40 during the activation annealing, so that the total dose of the p-type impurities in the p-type region after the activation annealing is substantially the same as the total dose of the p-type impurities ion-implanted. Therefore, it is possible to realize a breakdown voltage close to the maximum value of the breakdown voltage obtained based on the total dose of the p-type impurities ion-implanted and the n-type dopant concentration of the n ^-type silicon carbide layer 42 into which the p-type impurities are ion-implanted.

Although not shown, the dopant concentration distribution of the p-type region constituting the JTE structure 30 becomes a dopant concentration distribution different from the total doping concentration distribution 60 of the p-type impurity before the activation annealing between the second surface 40b of the front surface of the SiC substrate 40 and a predetermined depth due to the subsequent activation annealing. The dopant concentration distribution of the p-type region constituting the JTE structure 30 has a lower doping concentration in a portion at a depth of 0.1 μm or less from the second surface 40b of the front surface of the SiC substrate 40 than the same portion 101a of the conventional example. In addition, the dopant concentration distribution of the p-type region constituting the JTE structure 30 has a peak depth at a depth position of 0.18 μm or more and less than 0.35 μm from the second surface 40b of the front surface of the SiC substrate 40, and has a peak concentration higher than the total doping concentration distribution 60 of the p-type impurity before the activation annealing.

The reason why the dopant concentration distribution in the p-type region constituting the JTE structure 30 differs before and after activation annealing is presumably because activation annealing causes the p-type impurities present at a shallow depth from the second surface 40b of the front surface of the SiC substrate 40 to move in a deeper direction and reach a predetermined depth, and the p-type impurities present at a deep position from the second surface 40b of the front surface of the SiC substrate 40 to move in a shallower direction and similarly reach the predetermined depth, increasing the amount of p-type impurities at the predetermined depth and reaching a peak concentration at the predetermined depth.

The conditions for determining the above-mentioned predetermined depth to which the p-type impurities in the SiC substrate 40 move and reach by the activation annealing are the total dose of the ion-implanted p-type impurities, and the peak concentration and peak depth of the total doping concentration distribution 60 of the p-type impurities before the activation annealing. Specifically, for example, when forming a p-type region of a predetermined p-type dopant concentration that constitutes the JTE structure 30, the conditions for determining the above-mentioned predetermined depth to which the p-type impurities in the SiC substrate 40 move and reach by the activation annealing are the superposition of the concentration distributions diffused with a spread of about ±0.18 μm from the peak depth generated by each stage of ion implantation performed before the activation annealing.

2 , an n ^{+ -type} stopper region 33 is selectively provided away from the JTE structure 30 in a surface region of the second face 40b of the front surface of the SiC substrate 40 so as to be exposed on a side surface (i.e., a chip end) of the SiC substrate 40. The n ⁻ -type drift region 2 is exposed in a portion of the second face 40b of the front surface of the SiC substrate 40 other than the portion where the JTE structure 30 and the n ⁺ -type stopper region 33 are exposed. The second and third faces 40b, 40c of the front surface of the SiC substrate 40 are covered with a field oxide film 22.

As described above, according to the embodiment, when forming one p-type region inside the SiC substrate, p-type impurities are ion-implanted with a depth range of 0.18 μm or more and less than 0.35 μm from the ion-implanted surface of the SiC substrate, thereby preventing the p-type impurities in the p-type region from diffusing outward from the SiC substrate during subsequent activation annealing. The ion implantation of p-type impurities into the SiC substrate can be performed in one stage or in multiple stages with different acceleration voltages, as long as the range is within the above-mentioned depth range from the ion-implanted surface of the SiC substrate. Therefore, by adjusting the acceleration voltage and dose amount of each ion implantation for each design condition, the total dose amount of p-type impurities in the p-type region can be easily controlled and maintained within the design range.

Since the total dose of p-type impurities in the p-type region can be easily controlled in this way, there is no need to ensure a process margin or design margin more than necessary. Therefore, for example, each p-type region of a JTE structure consisting of one or more p-type regions can be formed with the designed dimensions to give the edge termination region a minimum length (width), and each p-type region of the JTE structure can be formed with a total dose within the design range to set the breakdown voltage of the edge termination region as designed. This makes it possible to suppress breakdown voltage fluctuations and breakdown voltage reductions from the design value, thereby improving reliability. In addition, since there is no need to increase the length of the edge termination region in anticipation of a breakdown voltage reduction, the manufacturing cost per chip can be reduced.

(Experiment 1)
Next, the relationship between the dose of p-type impurities in the p-type region constituting JTE structure 30 and the breakdown voltage of edge termination region 20 was examined. Figure 5 is a characteristic diagram showing the relationship between the dose of p-type impurities in the p-type region of the example and the breakdown voltage. The horizontal axis of Figure 5 is the design value of the dose of p-type impurities in the p-type region constituting JTE structure 30 of the silicon carbide semiconductor device according to the above-mentioned embodiment (hereinafter referred to as the example), and the vertical axis is the breakdown voltage of edge termination region 20 of the example.

5 shows the results of simulating the breakdown voltage of edge termination region 20 by variously changing the dose of p-type impurity in the p-type region constituting JTE structure 30 of the embodiment (hereinafter simply referred to as the "dose of p-type impurity in the p-type region") and the n-type dopant concentration of n ^-type silicon carbide layer 42. FIG 5 shows the relationship between the dose of p-type impurity in the p-type region and the breakdown voltage of edge termination region 20 for each n-type dopant concentration of n ^-type silicon carbide layer 42.

From the results shown in Figure 5, it was confirmed that the breakdown voltage of edge termination region 20 reaches a maximum value (maximum breakdown voltage value) at a predetermined dose of p-type impurity in the p-type region (near 6 x ¹⁰¹² /cm2 in Figure ⁵ ). It was also confirmed that the breakdown voltage of edge termination region 20 decreases as the dose of p-type impurity in the p-type region increases from the predetermined dose, or decreases from the predetermined dose. It was also confirmed that the breakdown voltage of edge termination region 20 increases as the dopant concentration of n ^- type silicon carbide layer 42 decreases.

From these results, it can be seen that the breakdown voltage of edge termination region 20 can be controlled by controlling the dose of p-type impurities in the p-type region and the dopant concentration of n ⁻ type silicon carbide layer 42. As described above, in the embodiment, the decrease in the dose of p-type impurities in the p-type region before and after activation annealing can be suppressed, so that the dose of p-type impurities in the p-type region can be easily controlled as designed and maintained within the design range, and therefore the breakdown voltage of edge termination region 20 can be set as designed.

In this experiment 1, the relationship between the dose of p-type impurities in the p-type region and the breakdown voltage of edge termination region 20 is verified using a sample in which the n-type dopant concentration in n ^-type silicon carbide layer 42 is 4× ¹⁰ /cm ³ or less. If the n-type dopant concentration in n ^-type silicon carbide layer 42 is different from that of the sample in experiment 1, the maximum breakdown voltage value of edge termination region 20 will change, but the dose dependence of the p-type impurity in the p-type region ( FIG. 5 ) of the breakdown voltage of edge termination region 20 verified in experiment 1 above can also be obtained in the case in which the n-type dopant concentration in n ^-type silicon carbide layer 42 is 1× ¹⁰ /cm ³ or less. The reason is as follows.

For each n-type dopant concentration of n ^- type silicon carbide layer 42, there is an optimal dose of p-type impurities in the p-type region (hereinafter referred to as optimal dose) as in the sample of Experiment 1 above. This optimal dose is the dose of p-type impurities in the p-type region when edge termination region 20 exhibits the maximum breakdown voltage value. If the dose of p-type impurities in the p-type region is less than the optimal dose, a depletion region spreads over the entire p-type region constituting JTE structure 30 at a low applied voltage, and the breakdown voltage of edge termination region 20 decreases. That is, the lower the dose of p-type impurities in the p-type region is compared to the optimal dose, the lower the breakdown voltage of edge termination region 20 becomes.

On the other hand, when the dose of the p-type impurity in the p-type region exceeds the optimum dose, the depletion region does not easily spread in the p-type region constituting the JTE structure 30, and the narrowing of the spread causes the electric field strength in the direction parallel to the front surface of the semiconductor substrate (lateral direction) to become too high, lowering the breakdown voltage of the edge termination region 20. That is, the higher the dose of the p-type impurity in the p-type region is compared to the optimum dose, the lower the breakdown voltage of the edge termination region 20. In this way, the same result as the relationship between the breakdown voltage of the edge termination region 20 and the dose of the p-type impurity in the p-type region verified in the above experiment 1 is obtained, based on the optimum dose of the p-type impurity in the p-type region.

(Experiment 2)
Next, the amount of movement of p-type impurities in SiC due to activation annealing was verified. FIG. 6 is a characteristic diagram showing the dopant concentration distribution of the p-type region of the conventional example. A conventional silicon carbide semiconductor device (hereinafter, referred to as the conventional example) having a general JTE structure composed of a p-type region 100 was manufactured. The p-type region 100 of the conventional example was formed to have a BOX-type dopant concentration distribution by multiple stages of ion implantation and activation annealing. The configuration of the conventional example, other than the dopant concentration distribution 101 of the p-type region 100 after activation annealing, is the same as that of the above-mentioned embodiment.

Figure 6 shows the results of measuring the dopant concentration distribution 101 in the p-type region 100 after activation annealing in this conventional example using secondary ion mass spectrometry (SIMS). In the ion implantation to form the p-type region 100 in the conventional example, the p-type impurity (dopant) was aluminum, the ion implantation surface was the Si surface of the SiC substrate, and the number of ion implantation stages was five. An example of the conditions (acceleration voltage and dose) for multiple stages of p-type impurity ion implantation to form the p-type region 100 in the conventional example is shown in Figure 7.

Figure 7 is a chart showing an example of typical ion implantation conditions for forming a p-type region with a BOX-type dopant concentration distribution. The results of simulating the doping concentration distributions 111-115 of p-type impurities before activation annealing for each of the first to fifth ion implantation stages in Figure 7 and their total doping concentration distribution 110 are shown in Figure 6, superimposed on the dopant concentration distribution 101 of the p-type region 100 after activation annealing. The horizontal axis of Figure 6 is the depth from the ion implantation surface of the SiC substrate, and the vertical axis is the concentration.

As shown in FIG. 6, one to five stages of ion implantation with different acceleration voltages formed p-type impurity doping concentration distributions 111 to 115, each having a peak concentration at a different depth position from the ion implantation surface (depth = 0 μm) of the SiC substrate. It was confirmed that the total doping concentration distribution 110 obtained by integrating these p-type impurity doping concentration distributions 111 to 115 before activation annealing was a BOX type with a nearly uniform dopant concentration between the deepest doping concentration distribution 111 and the shallowest doping concentration distribution 115 (from the ion implantation surface to a depth position of about 0.5 μm).

Although not shown, it has been confirmed that the total doping concentration distribution of the p-type impurity before activation annealing, even when measured by SIMS, is a BOX type that is approximately the same as the total doping concentration distribution 110 by the simulation in FIG. 6. Even if the p-type impurity is ion-implanted in multiple stages so that the total doping concentration distribution 110 before activation annealing of the p-type impurity becomes a BOX type, it has been confirmed that the dopant concentration distribution 101 of the p-type region 100 after activation annealing in the conventional example does not maintain the BOX type due to the subsequent activation annealing.

Specifically, it was confirmed that the dopant concentration distribution 101 of the p-type region 100 after activation annealing in the conventional example is a flat concentration distribution in which the minimum value of the dopant concentration is kept almost constant in the portion 101a from near the ion implantation surface of the SiC substrate to a depth of 0.1 μm or less. Due to the characteristics of SIMS, the outermost surface of the SiC substrate is a portion that is affected by contamination and is ignored because it does not reflect the actual dopant concentration. It was also confirmed that the dopant concentration of the p-type region 100 in the conventional example is significantly lower than the total doping concentration distribution 110 of the p-type impurity before activation annealing in the portion 101a from near the ion implantation surface of the SiC substrate to a depth of 0.1 μm or less.

In addition, it was confirmed that the dopant concentration distribution 101 of the p-type region 100 after activation annealing in the conventional example shows a peak concentration in a portion 101b that is more than 0.1 μm from the ion implantation surface of the SiC substrate, and has a Gaussian distribution with the depth position (peak depth) 101d of the peak concentration as the apex. In other words, the dopant concentration distribution 101 of the p-type region 100 after activation annealing in the conventional example does not become a BOX type. Note that the peak depth 101d of the dopant concentration distribution 101 of the p-type region 100 after activation annealing in the conventional example was about 0.27 μm. It was also confirmed that the peak concentration at the peak depth 101d of the dopant concentration distribution 101 of the p-type region 100 after activation annealing in the conventional example is higher than the total doping concentration distribution 110 of the p-type impurity before activation annealing.

The reason for this is presumably that even if p-type impurities are ion-implanted in multiple stages so that the total doping concentration distribution 110 of the p-type impurities before activation annealing is a BOX type, the subsequent activation annealing causes the p-type impurities present at shallow depths from the ion-implanted surface of the SiC substrate to move in the deeper direction and reach the predetermined depth range 101c, and the p-type impurities present at deep depths from the ion-implanted surface of the SiC substrate to move in the shallower direction and similarly reach the predetermined depth range 101c, so that the p-type impurities in the predetermined depth range 101c increase in amount, and reach a peak concentration at the peak depth 101d within the predetermined depth range 101c.

It was also confirmed that the dose of p-type impurities in the p-type region 100 of the conventional example was significantly reduced after activation annealing. This is presumably because activation annealing causes the p-type impurities present at a shallow depth from the ion-implanted surface of the SiC substrate to move outward from the ion-implanted surface of the SiC substrate and diffuse into an insulating film such as a field oxide film on the ion-implanted surface of the SiC substrate. It was confirmed that the reduction in the dose of p-type impurities in the p-type region 100 of the conventional example caused the breakdown voltage of the edge termination region of the conventional example to be lower than the design value.

In FIG. 6, it appears that there are two peak concentration points in the dopant concentration distribution 101 of the p-type region 100 after activation annealing in the conventional example, but this is due to fluctuations in the detection results by SIMS. In reality, the dopant concentration distribution 101 of the p-type region 100 after activation annealing in the conventional example shows a peak concentration at one peak depth 101d. In FIG. 6, the actual peak depth 101d of the dopant concentration distribution 101 of the p-type region 100 after activation annealing in the conventional example is the point showing the highest peak concentration of the two peak concentrations (the peak concentration deeper from the ion implantation surface of the SiC substrate than the other peak concentration).

The present invention is not limited to the above-mentioned embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, when forming a p-type region inside a SiC substrate, it is sufficient that the range of all ion implantation performed in multiple stages is located at a depth of 0.18 μm or more and less than 0.35 μm from the ion implantation surface of the SiC substrate, and the number of ion implantation stages can be modified in various ways according to design conditions.

As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines, etc.

REFERENCE SIGNS LIST 1 n ⁺ type drain region 2 n ^- type drift region 3 n type current diffusion region 4 p type base region 5 n ⁺ type source region 6 p ⁺⁺ type contact region 7, 7a trench 8 gate insulating film 9 gate electrode 10 active region 11, 11a, 12, 13 p ⁺ type region 14 interlayer insulating film 15 source electrode 16 drain electrode 20 edge termination region 21 step on front surface of SiC substrate 22 field oxide film 30 JTE structure 31, 32 p type regions constituting the JTE structure (first and second JTE regions)
33 n ⁺ type stopper region 40 SiC substrate 40a to 40c First to third surfaces of the front surface of the SiC substrate 41 n ⁺ type starting substrate 42 n ^- type silicon carbide layer 43 p type silicon carbide layer 50 Silicon carbide semiconductor device 60 Total doping concentration distribution of p type impurities before activation annealing 60a, 60b Part of total doping concentration distribution of p type impurities before activation annealing 61, 62 Doping concentration distribution of p type impurities before activation annealing for each ion implantation 100 p type region of conventional example 101 Dopant concentration distribution of p type region after activation annealing of conventional example measured by SIMS analysis 101a Portion of dopant concentration distribution of p type region after activation annealing of conventional example from near ion implantation surface of SiC substrate to a depth of 0.1 μm or less 101b Portion of dopant concentration distribution in p-type region after activation annealing in conventional example, exceeding 0.1 μm from ion implantation surface of SiC substrate 101c Range of depth position of peak concentration in dopant concentration distribution in p-type region after activation annealing in conventional example 101d Peak depth of dopant concentration distribution in p-type region after activation annealing in conventional example 110 Total doping concentration distribution of p-type impurity before activation annealing in conventional example 111 to 115 Doping concentration distribution of p-type impurity before activation annealing for each ion implantation in conventional example

Claims (5)

a first conductivity type silicon carbide layer made of silicon carbide;
a second conductivity type region extending to a predetermined depth from a surface of the first conductivity type silicon carbide layer and containing a second conductivity type dopant at a predetermined dose;
the second conductivity type dopant is aluminum;
the second conductivity type dopant concentration distribution of the second conductivity type region is a Gaussian distribution exhibiting peaks of dopant concentration at different heights at a plurality of different depth positions within a range of 0.18 μm or more and less than 0.35 μm from the surface of the first conductivity type silicon carbide layer, and the peak is not exhibited less than 0.18 μm from the surface of the first conductivity type silicon carbide layer;
a dose of the second conductivity type dopant present in a portion of the second conductivity type region that is 0.1 μm or less from the surface of the first conductivity type silicon carbide layer is less than 10% of a total dose of the second conductivity type dopant in the second conductivity type region;
a first conductivity type silicon carbide layer having a first surface that is a (0001) surface; 2 . The silicon carbide semiconductor device according to claim 1 , wherein a maximum value of a concentration of the second conductivity type dopant in said second conductivity type region is equal to or greater than 1×10 ¹⁷ /cm ^{3 .} 3. The silicon carbide semiconductor device according to claim 1, wherein a concentration of the first conductivity type dopant in said first conductivity type silicon carbide layer is 1×10 ¹⁶ /cm ³ or less. 4. The silicon carbide semiconductor device according to claim 3, wherein the first conductivity type silicon carbide layer has a first conductivity type dopant concentration of 4×10 ¹⁴ /cm ³ or less. an active region provided on a semiconductor substrate through which a main current of the element flows;
a termination region provided in the semiconductor substrate and surrounding the active region;
the first conductivity type silicon carbide layer constituting the semiconductor substrate and forming, at its surface, a front surface of the semiconductor substrate in the termination region;
a breakdown voltage structure in which a plurality of second conductivity type regions are adjacently arranged in the first conductivity type silicon carbide layer in the termination region, the second conductivity type regions having a lower second conductivity type dopant concentration toward the outside;
5. The silicon carbide semiconductor device according to claim 1, further comprising:

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