JP7572984B2 - Switching Power Supply Unit - Google Patents

Description

The present invention relates to a switching power supply device that controls a current limiting mode so that the peak value of the switching current flowing through the main switching element does not exceed a reference value.

<Conventional switching power supply device 10>
Conventionally, there has been a switching power supply 10 configured as shown in Fig. 6. The switching power supply 10 includes a power conversion circuit 16 that converts an input voltage Vi to an output voltage Vo by the switching operation of a main switching element 12 and supplies the output voltage Vo to a load 14. The main switching element 12 is composed of an N-channel MOS type FET that is turned on when a gate voltage Vg is at a high level and turned off when it is at a low level, and the on/off of the main switching element 12 is controlled by a main control circuit 18.

The main control circuit 18 is a circuit that outputs a drive pulse Vk that is a pulse voltage that controls the on/off of the main switching element 12 and repeats high and low levels at a predetermined time ratio. This main control circuit 18 performs two types of control. One is a control that determines the high and low level times of the drive pulse Vk so that the output voltage Vo is maintained at the target value Vr when the peak value of the switching current Isw flowing through the main switching element 12 does not reach the reference value Ith [output voltage stabilization mode control]. The other is a control that determines that an overcurrent state exists when the peak value of the switching current Isw reaches the reference value Ith, and forcibly inverts the drive pulse Vk from high to low to reduce the output voltage Vo regardless of the target value Vr of the output voltage Vo [current limit mode control (overcurrent protection control)]. The contents of each control mode will be described in detail in the explanation of the operation of the switching power supply device 10.

A drive pulse transmission path 20 is provided between the main control circuit 18 and the main switching element 12, and the drive pulse Vk output by the main control circuit 18 is transmitted between the gate and source of the main switching element 12 via the drive pulse transmission path 20.

The drive pulse transmission path 20 is composed of a diode 22 whose cathode is connected to the output terminal of the main control circuit 18, a gate resistor 24 connected in parallel to both ends of the diode 22, a gate resistor 26 connected between the anode of the diode 22 and the gate of the main switching element 12, and a wiring pattern connecting these. In the case of this drive pulse transmission path 20, the path (charge path 28) through which the charging current flows to raise the gate voltage Vg of the main switching element 12 from a low level to a high level is a path that passes from the output terminal of the main control circuit 18 through the gate resistor 24 and resistor 26 in order to reach the gate of the main switching element 12. In addition, the path (discharge path 30) through which the discharge current flows to lower the gate voltage Vg from a high level to a low level is a path that passes from the gate of the main switching element 12 through the gate resistor 26 and diode 22 in order to reach the output terminal of the main control circuit 18. The gate resistors 24 and 26 are resistive elements for adjusting the rate of change of the gate voltage Vg, and their resistance values are set to very small values.

Next, the operation of the switching power supply device 10 will be described. When the power conversion circuit 16 is a flyback converter (hereinafter, FB converter), the switching power supply device 10 performs the operation shown in FIG. 7(a) and FIG. 8(a) to (c).

Operating point A is the operating point when the load 14 is normal (when the impedance is high), and since the output current Io is smaller than the specified value and the peak value of the switching current Isw does not reach the reference value Ith, the main control circuit 18 performs control in the output voltage stabilization mode so that the output voltage Vo is maintained at the target value Vr. In other words, in order for the output voltage Vo to be maintained at the target value Vr, the high level time t (Vgh) of the gate voltage Vg needs to be Ta, so the high level time t (Vkh) of the drive pulse Vk is controlled to Ta.

When some abnormality occurs in the load 14 and the impedance drops slightly, the output current Io increases slightly, and the peak value of the switching current Isw becomes almost equal to the reference value Ith at operating point B. At this operating point B, the output voltage Vo is almost at the target value Vr, so times t(Vkh) and t(Vgh) are controlled to Tb ≒ Ta, just like at operating point A.

When the impedance of the load 14 further decreases from the operating point B, the output current Io increases and the peak value of the switching current Isw attempts to exceed the reference value Ith, so the main control circuit 18 starts control in the current limit mode to prevent the peak value of the switching current Isw from exceeding the reference value Ith, and the times t(Vkh) and t(Vgh) gradually become shorter. Then, at the operating point C (Vo=Vc<Vr), the times t(Vkh) and t(Vgh) are controlled to Tc<Tb, and at the operating point D (Vo=Vd<Vc), the times t(Vkh) and t(Vgh) are controlled to Td<Tc. The output current Io is limited so that the Vo-Io characteristic is roughly a constant power curve (Vo·Io ≒ constant) between the operating points B and D.

At operating point D, times t(Vkh) and t(Vgh) are Td = Tmin. Tmin is the minimum pulse width (minimum value of high level time) of the drive pulse Vk output by the main control circuit 18. Here, we will briefly explain the minimum pulse width Tmin.

The main control circuit 18 can be configured using, for example, a commercially available current mode PWM control IC, but many current mode PWM control ICs are equipped with a leading edge blanking function. The leading edge blanking function is a function that prevents the control system from malfunctioning due to whisker-like switching noise entering the current detection comparator when the switching current Isw begins to flow, and performs an operation of holding the drive pulse Vk at a high level regardless of the output of the comparator for a period of tens to hundreds of nsec (blanking period) immediately after the drive pulse Vk changes from low level to high level. Therefore, if the main control circuit 18 has a leading edge blanking function, the blanking period is the main factor of the minimum pulse width Tmin. Also, even if the control IC used does not have a leading edge blanking function, the delay time from when it is detected that the crest value of the switching current Isw has reached the reference value Ith until the drive pulse Vk is inverted from high level to low level is the minimum pulse width Tmin.

When the impedance of the load 14 decreases further from the operating point D, the output current Io tries to increase, but the main control circuit 18 cannot make the times t(Vkh) and t(Vgh) shorter than Te=Tmin, and the current limit mode control becomes impossible. In other words, in order for the current limit mode control to be established at the operating point E (Vo=Ve<Vd), the condition is that the time t(Vgh) is Te<Td=Tmin, but the main control circuit 18 cannot make the times t(Vkh) and t(Vgh) shorter than the minimum pulse width Tmin, so the peak value of the switching current Isw increases significantly beyond the reference value Ith, and the output current Io deviates from the constant power curve and increases sharply.

When the output current Io increases so rapidly, the elements that make up the power conversion circuit 16 generate more heat than expected, and excessive surge voltages are generated in the power semiconductors in each part that performs switching operations. For this reason, special measures must be taken to ensure the safety of the switching power supply 10, such as improving the heat dissipation of each component and significantly strengthening the snubber circuit that absorbs the surge voltage. Of course, the safety of the load 14 is also a concern, as an excessive output current Io will be supplied to the load 14.

So far, we have explained the operation when the power conversion circuit 16 of the switching power supply 10 is an FB converter, but the operation is similar when the power conversion circuit 16 is a single-ended forward converter (hereinafter, SF converter). In the case of an SF converter, the Vo-Io characteristics of the switching power supply 10 are shown in Figure 7(b), and the operating waveforms at operating points A to E are almost the same as those in Figures 8(a) to (c).

In the case of an SF converter, unlike the case of an FB converter, the output current Io is limited so that the Vo-Io characteristic is an almost constant current curve (Io ≒ constant) between operating points B and D. However, if the impedance of the load 14 drops further from operating point D, the current limit mode control becomes impossible due to the minimum pulse width Tmin of the main control circuit 18. At operating point E (Vo = Ve < Vd), the peak value of the switching current Isw increases significantly beyond the reference value Ith, and the output current Io deviates from the constant current curve and increases sharply. Therefore, even when the power conversion circuit 16 is an SF converter, special safety measures are required for the switching power supply device 10, and the safety of the load 14 is also a concern.

As described above, in the conventional switching power supply 10, when the output voltage Vo drops significantly, the main control circuit 18 cannot make the high-level time t (Vkh) of the drive pulse Vk equal to or less than the minimum pulse width Tmin, and the high-level time t (Vgh) of the gate voltage also does not fall below the minimum pulse width Tmin, resulting in the problem that control of the current limit mode (control of overcurrent protection) becomes impossible.

<Conventional switching power supply device 32>
Another conventional switching power supply device 32 has been configured as shown in Fig. 9. The switching power supply device 32 includes a power conversion circuit 16 and a main control circuit 18 similar to those of the switching power supply device 10 described above, but differs from the switching power supply device 10 in that a drive pulse transmission path 34 having a different configuration from the drive pulse transmission path 20 described above is provided.

The drive pulse transmission path 34 is a totem-pole type buffer circuit combining an NPN transistor 38 and a PNP transistor 40. The collector of the NPN transistor 38 is connected to the DC voltage Vcc via a resistor 36, the base is connected to the output terminal of the main control circuit 18, and the emitter is connected to the gate of the main switching element 12. The base of the PNP transistor 40 is connected to the output terminal of the main control circuit 18, the emitter is connected to the gate of the main switching element 12, and the collector is connected to the ground line. In the case of the drive pulse transmission path 34, the drive pulse Vk output by the main control circuit 18 is transmitted between the gate and source of the main switching element 12 via the PN junction between the base emitters of the transistors 38 and 40. Even if it is difficult to change the gate voltage Vg at high speed using the current capacity of the output stage of the main control circuit 18 (for example, even when the parasitic capacitance between the gate and source of the main switching element 12 is very large), the gate voltage Vg can be changed at high speed by having the transistors 38 and 40 pass a large collector current instead of the main control circuit 18, making it possible to make the gate voltage Vg and drive pulse Vk into roughly similar rectangular waves.

In addition, the drive pulse transmission path 34 is provided with a switch element 42 connected to both ends of the resistor 36, and a switch element control circuit 44 that controls the on/off state of the switch element 42. The switch element control circuit 44 detects the output voltage Vo, and controls the switch element 42 to be in the on state when the output voltage Vo is higher than a predetermined value Vx (Vd<Vx<Vc), and to be in the off state when the output voltage Vo is lower.

In the case of this drive pulse transmission path 34, the path (charging path 46) through which the charging current flows to raise the gate voltage Vg of the main switching element 12 from a low level to a high level is essentially a path that runs from the power supply voltage Vcc through the parallel circuit of the resistor 36 and the switch element 42 and the NPN transistor 38 in this order to the gate of the main switching element 12. Also, the path (discharging path 48) through which the discharging current flows to lower the gate voltage Vg from a high level to a low level is essentially a path that runs from the gate of the main switching element 12 through the PNP transistor 40 to the ground line.

The resistor 36 is an element that acts to significantly limit the collector current passed by the NPN transistor 38, and its resistance value is set to a value greater than that of a typical gate resistor (e.g., the gate resistors 24 and 26 of the switching power supply 10). More details will be given in the explanation of the operation of the switching power supply 32.

Next, the operation of the switching power supply 32 will be described. When the power conversion circuit 16 is an FB converter, the switching power supply 32 operates as shown in FIG. 10(a) and FIG. 11(a)-(c). At operating points A-C, the output voltage Vo is higher than a predetermined value Vx, the switch element 42 is on, and the resistor 36 does not contribute to the circuit operation. Therefore, the operation of the switching power supply 32 is almost the same as that of the switching power supply 10 described above. However, at operating point D where the output voltage Vo falls below the predetermined value Vx, the switch element 42 is turned off and the operating waveform changes as shown in FIG. 11(b).

Here, we precisely define the time t(Vkh) when the drive pulse Vk is at a high level and the time t(Vgh) when the gate voltage Vg is at a high level shown in FIG. 11(b). The former time t(Vkh) is the time when the main control circuit 18 is trying to make the drive pulse Vk at a high level, and is the time from when the drive pulse Vk starts to rise until it turns to a low level. On the other hand, the latter time t(Vgh) is the time when the main switching element 12 is on, and is equivalent to the time when the switching current Isw flows. This definition also applies to FIG. 8(b) explained earlier.

At the operating point D, the collector current (the charging current between the gate and source of the main switching element 12) flowing through the NPN transistor 38 is greatly limited by the resistor 36. Then, after the drive pulse Vk changes from low level to high level, the gate voltage Vg rises gradually, and when the delay time Tx has elapsed, it reaches the gate threshold voltage Vth of the main switching element 12, the main switching element 12 turns on, and the switching current Isw flows. Therefore, at the operating point D, the time t (Vgh) when the gate voltage Vg is at a high level is Td = Tmin, and the time t (Vkh) when the drive pulse Vk is at a high level is Tx + Td, which is longer than the minimum pulse width Tmin. In other words, in order for the control of the current limiting mode to be established at the operating point D (Vo = Vd), the condition is that the time T (Vgh) is Td = Tmin, but the main control circuit 18 only needs to control the time t (Vkh) to a time Tx + Td longer than the minimum pulse width Tmin, so that the control of the current limiting mode can be appropriately executed.

Furthermore, at operating point E (Vo = Ve < Vd), the time t (Vgh) when the gate voltage Vg is at a high level is Te < Td = Tmin, and the time t (Vkh) when the drive pulse Vk is at a high level is Tx + Te, which is longer than the minimum pulse width Tmin. In other words, in order for the current limit mode control to be established at operating point E (Vo = Ve < Vd), the condition is that the time t (Vgh) is Te < Td = Tmin, but the main control circuit 18 can appropriately execute the current limit mode control by simply setting the time t (Vkh) to a time Tx + Te, which is longer than the minimum pulse width Tmin. Therefore, the output current Io is limited so that the Vo-Io characteristic is approximately a constant power curve (Vo · Io ≒ constant) between operating points B and E.

In this way, when the output voltage Vo falls below a predetermined value Vx (Vd<Vx<Vc), the switching power supply 32 turns off the switch element 42 and generates a delay time Tx. This makes it possible to control the current limit mode (control for overcurrent protection) even at operating points D to E where the output voltage Vo is very low, and prevents the output current Io from deviating from the constant power curve and increasing rapidly.

So far, we have explained the operation when the power conversion circuit 16 of the switching power supply 32 is an FB converter, but the operation is similar when the power conversion circuit 16 is an SF converter. In the case of an SF converter, the Vo-Io characteristics of the switching power supply 32 are shown in Figure 10(b), and the operating waveforms at operating points A to E are almost the same as those in Figures 11(a) to (c). And, in the case of an SF converter, as in the case of an FB converter, current limit mode control (overcurrent protection control) is possible even at operating points D to E where the output voltage Vo is very low, and it is possible to prevent the output current Io from deviating from the constant current curve and increasing sharply.

As described above, the conventional switching power supply 32 can avoid the problem of the switching power supply 10 described above (when the output voltage Vo drops significantly, the minimum pulse width Tmin of the main control circuit 18 makes it impossible to control the current limit mode (control for overcurrent protection)). The configuration of the switching power supply 32 is disclosed in Patent Document 1.

JP 2011-30379 A

The conventional switching power supply 10 has a problem in that when the output voltage Vo drops significantly, the minimum pulse width Tmin of the main control circuit 18 makes it impossible to control the current limit mode (control for overcurrent protection), and special measures are required to ensure safety. Furthermore, the conventional switching power supply 32 can solve the problems of the switching power supply 10 to some extent, but still has problems in terms of ensuring the safety of the power supply.

In the case of the switching power supply 32, as shown in Figures 11(b) and (c), in order to generate a sufficient delay time Tx between operating points D and E, the resistance value R36 is set to a large value to make the rise of the gate voltage Vg very gradual, so the turn-on speed of the main switching element 12 drops significantly and the cross loss becomes very large. Moreover, while the main switching element 12 is on, the gate voltage Vg remains at a voltage slightly exceeding the gate threshold voltage Vth, so the on-resistance Ron of the main switching element 12 cannot be made sufficiently small, and the conduction loss due to the on-resistance Ron also becomes very large.

Therefore, when the output voltage Vo drops and the switch element 42 turns off in the switching power supply 32, the loss in the main switching element 12 increases and heat generation becomes greater than expected, so special measures are required to ensure the safety of the switching power supply 32.

The present invention was made in consideration of the above background technology, and aims to provide a switching power supply device with a simple configuration that can easily avoid the problem of the current limit mode becoming uncontrollable due to the minimum pulse width of the main control circuit.

The present invention provides a switching power supply device comprising: a power conversion circuit which converts an input voltage into a predetermined output voltage by the switching operation of a main switching element and supplies the output voltage to a load; and a main control circuit which outputs a drive pulse which is a pulse voltage for controlling the on/off of the main switching element and which repeats high and low levels at a predetermined time ratio, the main switching element being an N-channel MOS type FET which is turned on when its gate voltage is at a high level and turned off when it is at a low level, the drive pulse output by the main control circuit being transmitted between the gate and source of the main switching element via a drive pulse transmission path, and the main control circuit controlling a current limit mode which reduces the output voltage by inverting the drive pulse from high to low when the peak value of a switching current flowing through the main switching element reaches a reference value,
The drive pulse transmission path is provided with a charge path through which a charge current flows to raise the gate voltage of the main switching element from a low level to a high level, a discharge path through which a discharge current flows to lower the gate voltage from a high level to a low level, an auxiliary switching element that is inserted in the charge path at a position that does not affect the interruption of the discharge path and interrupts the charge path, and an auxiliary control circuit that controls the on/off of the auxiliary switching element,
The auxiliary control circuit is a switching power supply device that turns on the auxiliary switching element when a specified time has elapsed after the drive pulse changes from a low level to a high level, and turns off the auxiliary switching element when the drive pulse changes from a high level to a low level.

The main control circuit may be configured to control an output voltage stabilization mode that determines the high and low level times of the drive pulse so that the output voltage is maintained at a target value when the peak value of the switching current does not reach the reference value, and to control the current limit mode regardless of the target value of the output voltage when the peak value of the switching current reaches the reference value.

It is preferable that a gate resistor for adjusting the rate of change of the gate voltage is inserted at a position midway along the charging path of the drive pulse transmission line, or at a position midway along the discharging path, or both.

The auxiliary switching element is a PNP bipolar transistor having an emitter connected to the output terminal of the main control circuit and a collector connected to one end of the charging path, and the auxiliary control circuit is composed of an auxiliary capacitor connected between the base and emitter of the auxiliary switching element and an auxiliary resistor connected between the base and collector.

Alternatively, the auxiliary switching element is composed of a P-channel MOS FET having a source connected to the output terminal of the main control circuit and a drain connected to one end of the charging path, and the auxiliary control circuit is composed of an auxiliary capacitor located between the gate and source of the auxiliary switching element and an auxiliary resistor connected between the gate and drain, and the auxiliary capacitor is composed of a parasitic capacitance between the gate and source of the auxiliary switching element, or is composed of the parasitic capacitance and a capacitor element connected in parallel to the parasitic capacitance.

The switching power supply of the present invention has a unique configuration in which an auxiliary switching element is inserted at a specified position in the charging path of the drive pulse transmission line and this auxiliary switching element is turned on at the appropriate timing, so that it is easy to avoid the problem of the current limit mode becoming uncontrollable due to the minimum pulse width of the main control circuit. In addition, by using a PNP type bipolar transistor or a P-channel MOS type FET as the auxiliary switching element, the auxiliary control circuit that controls the on/off of the auxiliary switching element can be constructed simply and inexpensively using capacitor elements and resistor elements.

In addition, the technology of the present invention is highly versatile and can be applied to various isolated converters (flyback converters, single-ended forward converters, bridge converters, push-pull converters, etc.) and non-isolated converters (step-down choppers, step-up choppers, step-up/step-down choppers, etc.).

1 is a block diagram showing an embodiment of a switching power supply device according to the present invention; 2 is a circuit diagram showing a specific configuration of an auxiliary switching element and an auxiliary control circuit shown in FIG. 1 . 1 is a graph showing the output voltage-output current characteristics (Vo-Io characteristics) of the switching power supply device of this embodiment, in which (a) is a graph of the Vo-Io characteristics when the power conversion circuit is a flyback converter, and (b) is a graph of the Vo-Io characteristics when the power conversion circuit is a single-ended forward converter. 1A is an operational waveform at operating point A to E of the switching power supply device of this embodiment, and FIG. 1C is an operational waveform at operating point D. FIG. 3A is a circuit diagram showing a modified example of the auxiliary switching element and the auxiliary control circuit shown in FIG. 2 , and FIG. 3B is a block diagram showing an example of an insertion position when a gate resistor is inserted in a drive pulse transmission line. FIG. 1 is a block diagram showing one embodiment of a conventional switching power supply device. 7 is a graph showing the output voltage-output current characteristics (Vo-Io characteristics) of the switching power supply device of FIG. 6, in which (a) is a graph of the Vo-Io characteristics when the power conversion circuit is a flyback converter, and (b) is a graph of the Vo-Io characteristics when the power conversion circuit is a single-ended forward converter. 7A is an operational waveform at operating point A to E of the switching power supply device of FIG. 6, FIG. 7B is an operational waveform at operating point D, and FIG. 7C is an operational waveform at operating point E. FIG. 11 is a block diagram showing another example of a conventional switching power supply device. 10 is a graph showing the output voltage-output current characteristics (Vo-Io characteristics) of the switching power supply device of FIG. 9, in which (a) is a graph of the Vo-Io characteristics when the power conversion circuit is a flyback converter, and (b) is a graph of the Vo-Io characteristics when the power conversion circuit is a single-ended forward converter. 10A is an operational waveform at operating point A to E of the switching power supply device of FIG. 9; FIG. 10C is an operational waveform at operating point D; and FIG.

One embodiment of the switching power supply of the present invention will be described below with reference to Figs. 1 to 5. Here, components similar to those of the conventional switching power supply 10 are given the same reference numerals and will not be described. The switching power supply 50 of this embodiment includes the power conversion circuit 16 and main control circuit 18 described above, and a drive pulse transmission path 52 having a different configuration from the drive pulse transmission path 20 described above.

The drive pulse transmission path 52 has a charge path 28, a discharge path 30, and gate resistors 24, 26 similar to those of the drive pulse transmission path 20, but is characterized in that an auxiliary switching element 54 is inserted in the charge path 28 at a position between the gate resistor 24 and the output end of the main control circuit 18, and an auxiliary control circuit 56 is further provided to control the on/off of the auxiliary switching element 54.

The auxiliary control circuit 56 is a circuit that controls the auxiliary switching element 54 to be turned on when a specified time Tn has elapsed after the drive pulse Vk has changed from a low level to a high level, and to be turned off when the drive pulse Vk has changed from a high level to a low level.

As shown in FIG. 2, the auxiliary switching element 54 is a PNP bipolar transistor whose emitter is connected to the output terminal of the main control circuit 18 and whose collector is connected to one end of the gate resistor 24, and the auxiliary control circuit 56 is composed of an auxiliary capacitor 58 connected between the base and emitter of the auxiliary switching element 54 and an auxiliary resistor 60 connected between the base and collector. The value of the auxiliary resistor 60 is sufficiently larger than the gate resistors 24 and 26.

To briefly explain the operation of the circuit shown in FIG. 2, when the drive pulse Vk is at a low level, the voltage V58 of the auxiliary capacitor 58 becomes almost zero volts, and the auxiliary switching element 54 is turned off. Then, when the drive pulse Vk changes from a low level to a high level, a current flows through the path of the auxiliary capacitor 58, the auxiliary resistor 60, the gate resistors 24 and 26, and the parasitic capacitance (not shown) between the gate and source of the main switching element 12, and the voltage V58 gradually increases. Then, when a specified time Tn has elapsed, the voltage V58 reaches the base-emitter saturation voltage of the auxiliary switching element 54, and the auxiliary switching element 54 is quickly turned on. After that, when the drive pulse Vk changes from a high level to a low level, the voltage V58 drops to almost zero volts, and the auxiliary switching element 54 is turned off.

The specified time Tn can be easily adjusted by changing the value of the auxiliary capacitor 58 and the value of the auxiliary resistor 60. However, it should be noted that the value of the auxiliary capacitor 58 should be set to a relatively small value in relation to the value of the parasitic capacitance between the gate and source of the main switching element 12. This is because if the value of the auxiliary capacitor 58 is set too large, the voltage V58 will not reach the base-emitter saturation voltage of the auxiliary switching element 54.

Next, the operation of the switching power supply device 50 will be described. When the power conversion circuit 50 is a flyback converter (hereinafter, FB converter), the switching power supply device 50 performs the operation shown in FIG. 3(a) and FIG. 4(a) to (c).

Operating point A is the operating point when the load 14 is normal (when the impedance is high), and since the output current Io is smaller than the specified value and the peak value of the switching current Isw does not reach the reference value Ith, the main control circuit 18 performs control in the output voltage stabilization mode so that the output voltage Vo is maintained at the target value Vr. In other words, in order for the output voltage Vo to be maintained at the target value Vr, the high level time t (Vgh) of the gate voltage Vg needs to be Ta, so the high level time t (Vkh) of the drive pulse Vk is controlled to Tn + Ta.

When some abnormality occurs in the load 14 and the impedance drops slightly, the output current Io increases slightly, and the peak value of the switching current Isw becomes almost equal to the reference value Ith at operating point B. At this operating point B, the output voltage Vo is almost at the target value Vr, so like operating point A, time t(Vkh) is controlled to Tn+Tb≒Tn+Ta so that time t(Vgh) is Tb≒Ta.

When the impedance of the load 14 further decreases from the operating point B, the output current Io increases and the peak value of the switching current Isw attempts to exceed the reference value Ith, so the main control circuit 18 starts control in the current limit mode to prevent the peak value of the switching current Isw from exceeding the reference value Ith, and the times t(Vkh) and t(Vgh) gradually become shorter. Then, at the operating point C (Vo=Vc<Vr), t(Vkh) is controlled to Tn+Tc so that t(Vgh) is Tc<Tb, and at the operating point D (Vo=Vd<Vc), the time t(Vkh) is controlled to Tn+Td so that the time t(Vgh) is Td<Tc.

At operating point D, time t(Vgh) is Td=Tmin, and time t(Vkh) is Tn+Td, which is longer than the minimum pulse width Tmin. In other words, in order for current limit mode control to be established at operating point D (Vo=Vd), time T(Vgh) must be Td=Tmin, but the main control circuit 18 only needs to control time t(Vkh) to Tn+Td, which is longer than the minimum pulse width Tmin, so current limit mode control can be executed appropriately.

Furthermore, at operating point E (Vo=Ve<Vd), time t(Vgh) is Te<Td=Tmin, and time t(Vkh) is Tn+Te, which is longer than the minimum pulse width Tmin. In other words, in order for current limit mode control to be established at operating point E (Vo=Ve<Vd), time t(Vgh) must be Te<Td=Tmin, but the main control circuit 18 only needs to control time t(Vkh) to Tn+Te, which is longer than the minimum pulse width Tmin, so current limit mode control can be properly executed. Therefore, the output current Io is limited so that the Vo-Io characteristic is approximately a constant power curve (Vo·Io ≒ constant) between operating points B and E.

In this way, the switching power supply 50 is configured so that the gate voltage Vg goes to high when the specified time Tn has elapsed after the drive pulse Vk goes to high level, so that even at operating points D to E where the output voltage Vo is very low, current limiting mode control (overcurrent protection control) is possible, and it is possible to prevent the output current Io from deviating from the constant power curve and increasing rapidly. In addition, even at operating points D to E, the gate voltage Vg of the switching power supply 50 rises very steeply and quickly passes through the gate threshold voltage Vth to reach a high voltage, so problems such as those of the conventional switching power supply 32 (problems such as a sudden increase in cross loss and conduction loss of the main switching element 12 at operating points D to E) do not occur.

The length of the specified time Tn is set individually in consideration of the length of the minimum pulse width Tmin and other circumstances, but it is preferable to set it in the range of 1/2·Tmin≦Tn≦2·Tmin, for example. As can be seen from the explanation of the operating points D and E above, if the specified time Tn is extended to Tn>Tmin, control of the current limit mode becomes possible until the output voltage Vo drops to almost zero volts. However, if the specified time Tn is set too long, the maximum on-time (maximum value of the time t(Vgh)) of the main switching element 12 is effectively shortened, and other adverse effects such as "control of the output voltage stabilization mode becomes impossible when the input voltage Vi is low" may occur, so it is preferable to set the specified time Tn in the range of Tn≦2·Tmin. In addition, if the specified time Tn is shortened to Tn<Tmin, it is assumed that the current limit mode will become impossible to control when the output voltage Vo drops to near zero volts, but if the specified time Tn is in the range of Tn≧1/2·Tmin, the increase in the output current Io will be significantly suppressed even if control of the current limit mode becomes impossible.

So far, we have explained the operation of the switching power supply device 50 when the power conversion circuit 16 is an FB converter, but the operation is similar when the power conversion circuit 16 is an SF converter. In the case of an SF converter, the Vo-Io characteristics of the switching power supply device 50 are shown in Figure 3 (b), and the operating waveforms at operating points A to E are almost the same as those in Figures 4 (a) to (c). In the case of an SF converter, as in the case of an FB converter, current limit mode control (overcurrent protection control) is possible even at operating points D to E where the output voltage Vo is very low, and it is possible to prevent the output current Io from deviating from the constant current curve and increasing rapidly. In addition, the problem of the conventional switching power supply device 32 (problem of a sudden increase in cross loss and conduction loss of the main switching element 12 at operating points D to E) does not occur.

As described above, the switching power supply device 50 has a unique configuration in which the auxiliary switching element 54 is inserted at a predetermined position in the drive pulse transmission path 52 and the auxiliary switching element 54 is turned on at the appropriate timing, so that it is easy to avoid the problem of the current limit mode becoming uncontrollable due to the minimum pulse width Tmin of the main control circuit 18. In addition, since the auxiliary switching element 54 is a PNP type bipolar transistor 54, the auxiliary control circuit 56 that controls the on/off of the auxiliary switching element 54 can be constructed simply and inexpensively using the auxiliary capacitor 58 and auxiliary resistor 60, and the setting of the specified time Tn can be easily changed.

The switching power supply of the present invention is not limited to the above embodiment. For example, the configuration of the auxiliary switching element and the auxiliary control circuit can be different from that of the auxiliary switching element 54 and the auxiliary control circuit 56 shown in FIG. 2. In FIG. 2, the auxiliary switching element 54 is a PNP bipolar transistor, and the auxiliary control circuit 56 is composed of an auxiliary capacitor 58 and an auxiliary resistor 60. However, as shown in FIG. 5(a), the auxiliary switching element 54 can be replaced with a P-channel MOS type FET, and the operation can be almost the same. In this case, the auxiliary capacitor 58 is composed of a parasitic capacitance 58a between the gate and source of the MOS type FET and a capacitor element 58b connected in parallel thereto. Also, if the conditions are met, the auxiliary capacitor 58 can be composed of only the parasitic capacitance 58a, and the capacitor element 58b can be eliminated to reduce the number of parts.

The auxiliary switching element is inserted at a position in the charging path that does not affect the on/off of the discharging path, and interrupts the charging path. Therefore, in the case of the switching power supply 50, as shown in Fig. 1, the auxiliary switching element 54 is inserted at point P1, which is one end of the gate resistor 24. If the auxiliary switching element 54 is inserted at point P3, which is one end of the gate resistor 26, or at point P4, which is the other end of the gate resistor 26, the on/off of the auxiliary switching element 54 will also affect the on/off of the discharging path 30, so it cannot be inserted at points P3 or P4.

It is preferable to provide a gate resistor in the drive pulse transmission path to adjust the rate of change of the gate voltage of the main switching element. The gate resistor is a resistor whose main purpose is to suppress the switching speed of the main switching element below a certain level and reduce switching noise, and its resistance value is not set to a large value like resistor 36 of the conventional switching power supply device 32.

The gate resistor can be inserted at a position in the middle of the charging path of the drive pulse transmission line, or at a position in the middle of the discharging path, or both. For example, in the case of a switching power supply device 50, as shown in FIG. 1, a gate resistor 24 is inserted in the path through which only the charging current flows, and a gate resistor 26 is inserted in the path through which both the charging current and the discharging current flow. This circuit configuration is essentially the same as the circuit configuration shown in FIG. 5(b), and is therefore naturally within the technical scope of the present invention. Note that the gate resistors may be completely removed if not necessary.

In the above explanation of the switching power supply 50, it has been explained that the switching power supply 50 is a constant voltage power supply, and that the current limit mode control is performed as an overcurrent protection control. As another example, it is also possible to configure a constant current power supply by utilizing the region of the constant current curve (the region between operating points B and E) in the Vo-Io characteristic shown in FIG. 3(b), and good constant current characteristics can be obtained even at very low output voltages Vo. Note that when configuring a constant current power supply, output voltage stabilization mode control is not essential.

In addition to the flyback converter and single-ended forward converter, the power conversion circuit may be an isolated converter such as a half-bridge converter, a full-bridge converter, or a push-pull converter, or a non-isolated converter such as a step-down chopper, a step-up chopper, or a step-up/step-down chopper. The present invention is a highly versatile technology that can be applied to various types of switching converters and can achieve the same effects.

10, 32, 50 Switching power supply device 12 Main switching element 16 Power conversion circuit 18 Main control circuits 24, 26 Gate resistor 28 Charging path 30 Discharging path 52 Drive pulse transmission path 54 Auxiliary switching element 56 Auxiliary control circuit 58 Auxiliary capacitor 60 Auxiliary resistors A to E Operating point
Ith reference value
Isw Switching current
Tmin Minimum pulse width
Tn: Specified time
t(Vgh) Gate voltage high level time
t(Vhk) High level time of the drive pulse
Vg Gate voltage
Vi input voltage
Vk drive pulse
Vo output voltage
Vr target value

Claims (4)

a power conversion circuit that converts an input voltage into a predetermined output voltage by the switching operation of a main switching element and supplies the output voltage to a load; and a main control circuit that outputs a drive pulse that is a pulse voltage for controlling the on/off of the main switching element and that repeats high and low levels at a predetermined time ratio;
The main switching element is an N-channel MOS FET that is turned on when its gate voltage is at a high level and turned off when its gate voltage is at a low level, and the drive pulse output by the main control circuit is transmitted between the gate and source of the main switching element via a drive pulse transmission line,
a main control circuit performing a current limiting mode control in which the drive pulse is inverted from a high level to a low level to reduce the output voltage when a peak value of a switching current flowing through the main switching element reaches a reference value,
The drive pulse transmission path is provided with a charge path through which a charge current flows to raise the gate voltage of the main switching element from a low level to a high level, a discharge path through which a discharge current flows to lower the gate voltage from a high level to a low level, an auxiliary switching element that is inserted in the charge path at a position that does not affect the interruption of the discharge path and interrupts the charge path, and an auxiliary control circuit that controls the on/off of the auxiliary switching element,
the auxiliary switching element is a PNP bipolar transistor having an emitter connected to an output terminal of the main control circuit and a collector connected to one end of the charging path,
the auxiliary control circuit is composed of an auxiliary capacitor connected between a base and an emitter of the auxiliary switching element and an auxiliary resistor connected between a base and a collector of the auxiliary switching element,
the auxiliary control circuit turns on the auxiliary switching element when a specified time has elapsed after the drive pulse changes from a low level to a high level, and turns off the auxiliary switching element when the drive pulse changes from a high level to a low level. a power conversion circuit that converts an input voltage into a predetermined output voltage by the switching operation of a main switching element and supplies the output voltage to a load; and a main control circuit that outputs a drive pulse that is a pulse voltage for controlling the on/off of the main switching element and that repeats high and low levels at a predetermined time ratio;
The main switching element is an N-channel MOS FET that is turned on when its gate voltage is at a high level and turned off when its gate voltage is at a low level, and the drive pulse output by the main control circuit is transmitted between the gate and source of the main switching element via a drive pulse transmission line,
a main control circuit performing control of a current limiting mode in which the drive pulse is inverted from a high level to a low level to reduce the output voltage when a peak value of a switching current flowing through the main switching element reaches a reference value,
The drive pulse transmission path is provided with a charge path through which a charge current flows to raise the gate voltage of the main switching element from a low level to a high level, a discharge path through which a discharge current flows to lower the gate voltage from a high level to a low level, an auxiliary switching element that is inserted in the charge path at a position that does not affect the interruption of the discharge path and interrupts the charge path, and an auxiliary control circuit that controls the on/off of the auxiliary switching element,
the auxiliary switching element is a P-channel MOS type FET having a source connected to an output terminal of the main control circuit and a drain connected to one end of the charging path,
the auxiliary control circuit is composed of an auxiliary capacitor located between a gate and a source of the auxiliary switching element, and an auxiliary resistor connected between the gate and the drain, the auxiliary capacitor being composed of a parasitic capacitance between the gate and the source of the auxiliary switching element, or being composed of the parasitic capacitance and a capacitor element connected in parallel to the parasitic capacitance;
the auxiliary control circuit turns on the auxiliary switching element when a specified time has elapsed after the drive pulse changes from a low level to a high level, and turns off the auxiliary switching element when the drive pulse changes from a high level to a low level. 3. The switching power supply device according to claim 1, wherein the main control circuit performs control in an output voltage stabilization mode that determines times of high level and low level of the drive pulse so that the output voltage is maintained at a target value when a peak value of the switching current does not reach the reference value, and performs control in the current limiting mode regardless of the target value of the output voltage when the peak value of the switching current reaches the reference value. The switching power supply device according to claim 1 or 2, wherein a gate resistor for adjusting the rate of change of the gate voltage is inserted at a position midway along the charging path of the drive pulse transmission line, or at a position midway along the discharging path, or both.

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