JP7579094B2 - Power Good Circuit - Google Patents

Description

The present invention relates to a semiconductor circuit device as an electronic component, and in particular to a power good circuit that is built into or connected to a semiconductor circuit device.

Semiconductor circuit devices as electronic components are configured as integrated circuits (ICs) on semiconductor chips and are available on the market as IC packages with multiple terminals (pins or leads). Electronic circuit systems are usually constructed by mounting multiple IC packages on a circuit board, such as a printed wiring board.

A typical example of a semiconductor circuit device that has a built-in power-good circuit and has a power-good terminal on its IC package is a power supply IC. In such a power supply IC, the output transistor of the power-good circuit is, for example, an NMOS transistor (or NPN transistor), and the power-good terminal is provided as an open-drain terminal (or open-collector terminal). This type of power-good circuit is configured to monitor the output voltage of the power supply IC or power supply device as a basic function, and when the output voltage is within the normal range, the output transistor is turned off and the power-good terminal is in a high-impedance state, and when the output voltage is outside the normal range, the output transistor is turned on and the power-good terminal is at a low level (hereinafter referred to as "L level").

When a power supply IC with a built-in power-good circuit as described above is installed in an electronic circuit system, corresponding terminals are connected between this power supply IC and an IC (hereinafter referred to as a "load IC") that receives power from this power supply IC. Of these, the voltage output terminal of the power supply IC is connected to the voltage input terminal of the load IC. In addition, the power good terminal of the power supply IC is connected to the enable terminal of the load IC and is also connected to the power supply voltage terminal via a pull-up resistor.

When the output transistor of the power-good circuit is on (when the output voltage of the power supply IC is outside the normal range), the pull-up resistor limits the current flowing from the power supply voltage terminal through the output transistor to the ground potential terminal, providing a stable L-level power-good output to the enable terminal of the load IC. Furthermore, when the output transistor is off (when the output voltage of the power supply IC is within the normal range), the pull-up resistor electrically connects the power-good terminal in a high-impedance state to the power supply voltage terminal, providing a stable High-level (hereinafter referred to as "H level") power-good output to the enable terminal of the load IC. Any power supply voltage within the electronic circuit system can be used as the power supply voltage for pull-up.

JP 2018-148676 A

Normal power supply ICs have a feedback control function to keep the output voltage close to the set value. For this reason, for example, when the load state fluctuates greatly immediately after power-on, the feedback control function works to counter this, causing the output voltage to exceed the reference value but immediately return to below the reference value, causing ringing for a while. In this case, if the power-good circuit responds to the ringing immediately after the output voltage rises and repeatedly turns the output driver on and off, repeatedly inverting the power-good output (H level/L level), the load IC may malfunction. Therefore, a power-good circuit that operates under the above-mentioned load environment is required to have a delay function that activates the power-good output (H level) after a certain delay time has passed, rather than immediately activating the power-good output (H level) when the output voltage of the monitored object enters the normal range.

As another example, in an electronic circuit system, the output voltages of multiple power supply ICs, for example three, may be sequentially raised with a fixed time difference. In this case, in order to have the three load ICs, which receive power from the three power supply ICs, start operating at approximately the same time, the above-mentioned time difference may be set for the timing at which the power-good circuit of each power supply IC activates the power-good output (H level). In other words, the system is designed so that, with regard to the timing at which the power-good output is activated (H level), the power-good circuit of the power supply IC whose output voltage rises first has a delay function that adds a relatively long delay time, the power-good circuit of the power supply IC whose output voltage rises next has a delay function that adds a relatively short delay time, and the power-good circuit of the power supply IC whose output voltage rises last does not have a delay function (i.e. has an immediate response function).

In this way, it has been customary to add a delay function to the power-good circuit of a power supply IC as necessary during the design or construction stage of an electronic circuit system. Conventionally, the technique for doing so has been to selectively connect a capacitor between the power-good terminal and the ground potential terminal on the circuit board of the electronic circuit system, and set the required delay time using the time constant of an RC series circuit consisting of this capacitor and a pull-up resistor. In this case, the delay time is determined by the product of the resistance value of the pull-up resistor and the capacitance of the capacitor, and the larger these resistance values and/or capacitances are, the longer the delay function with a longer delay time can be obtained.

However, with this conventional technique, when a long delay time (time constant) of, for example, several tens of milliseconds or more is set, the voltage waveform becomes significantly rounded when the power-good circuit activates the power-good output (H level), and a large through current flows in the input circuit (particularly the CMOS inverter circuit) of the load IC that inputs such a power-good output. Furthermore, if there is variation in the threshold of the input circuit of the load IC, the variation in the threshold is combined with the rounding of the power-good output waveform, resulting in very large variation in the delay time provided by the power-good output.

To solve the problems of the conventional techniques described above, a technique can be considered in which a delay circuit for providing a delay time to the power-good circuit is incorporated, and a certain default is given to the power-good circuit from outside the power supply IC when constructing the electronic circuit system, to set whether or not to use the delay circuit, i.e., whether or not to add a delay time. However, with this technique, it is necessary to add at least one additional terminal to the package of the power supply IC for setting whether or not to add a delay time from outside. In power supply ICs, particularly power supply ICs where miniaturization is desired, adding additional terminals to the package for the power-good function leads to an increase in package size and complication of specifications and setting work, which is not desirable.

The present invention solves the problems of the conventional technology described above, and provides a power-good circuit that can set whether or not to add a delay time without causing distortion in the voltage waveform of the power-good output, which becomes an active logic level when the output voltage of the monitored object is normal, and without increasing the number of terminals on the package or requiring the connection of new external components.

The power-good circuit according to the first aspect of the present invention is a power-good circuit that monitors an output voltage and outputs a power-good signal indicating whether the output voltage is normal or not with a binary logic level, and includes an output circuit that outputs the power-good signal from a power-good node, an output current detection circuit that detects a current flowing through the power-good node, a determination circuit that determines whether the output voltage is normal or not by referring to a predetermined reference voltage, and a control circuit that controls the output circuit to a first state or a second state according to the determination output of the determination circuit and the output of the output current detection circuit.

In the first aspect, when at least one of the first transistor constituting the output circuit and the second transistor constituting the output current detection circuit is on, the power-good terminal, which is the power-good node, is short-circuited to the ground potential terminal, and the voltage of the power-good terminal, i.e., the power-good output, is kept near the ground level (L level). When both the first and second transistors are off, the power-good terminal is in a high-impedance state, and the power-good output is pulled up to the power supply voltage level (H level) via a pull-up resistor.

The control circuit keeps the first transistor on when the judgment output of the judgment circuit indicates that the output voltage is not normal. This keeps the power good output at ground level (L level). Then, when the output voltage of the monitored object is within the normal range and the judgment circuit indicates this with its judgment output, the control circuit turns off the first transistor and turns on the second transistor in response to this. Then, a current flows from the power supply voltage terminal through the pull-up resistor and the second transistor in the on state. The amount of current (monitor current) that flows during this monitor time depends on the resistance value of the pull-up resistor. That is, when a pull-up resistor with a low resistance value is connected to the power good terminal, a large monitor current flows, and when a pull-up resistor with a high resistance value is connected, a small monitor current flows. The control circuit can determine whether the resistance value of the pull-up resistor is lower or higher than a predetermined resistance threshold by determining whether the monitor current is higher than the current threshold.

In one embodiment, when the monitor current is greater than the current threshold, the control circuit determines that a low-resistance pull-up resistor is connected to the power-good terminal and immediately turns off both the first and second transistors without adding a delay time, and when the monitor current is less than the current threshold, the control circuit determines that a high-resistance pull-up resistor is connected to the power-good terminal and turns off both the first and second transistors after a predetermined delay time has elapsed.

In another embodiment, when the monitor current is smaller than the current threshold, the control circuit determines that a pull-up resistor with a high resistance is connected to the power-good terminal and immediately turns off both the first and second transistors without adding a delay time, and when the monitor current is larger than the current threshold, the control circuit determines that a pull-up resistor with a low resistance is connected to the power-good terminal and turns off both the first and second transistors after a predetermined delay time has elapsed.

The power-good circuit of the present invention, having the above-mentioned configuration, can set whether or not to add a delay time without causing distortion in the voltage waveform of the power-good output, which becomes an active logic level when the output voltage of the monitored object is normal, and without increasing the number of terminals on the package or needing to connect new external components. This makes it possible to improve the efficiency and reliability of the power-good function or output monitoring function.

1 is a diagram showing a configuration of a semiconductor circuit device and an electronic circuit system incorporating a power-good circuit according to an embodiment of the present invention; FIG. 2 is a diagram showing a basic configuration of the power-good circuit shown in FIG. FIG. 11 is a diagram illustrating a configuration of a power-good circuit according to a second embodiment. 4 is a graph showing voltage-current characteristics and current characteristics of a constant current source for explaining the operation of the monitor current detection unit and the determination circuit of FIG. 3. FIG. 4 is a circuit diagram showing a configuration example of a determination circuit in FIG. 3 . FIG. 4 is a circuit diagram showing a configuration example of the logic circuit of FIG. 3 . 4 is a timing diagram showing waveforms of each part for explaining the operation of the power-good circuit of FIG. 3 (when the resistance value of the pull-up resistor is lower than the resistance threshold value). FIG. 4 is a timing diagram showing waveforms of each part to explain the operation of the power-good circuit of FIG. 3 (when the resistance value of the pull-up resistor is higher than the resistance threshold value). FIG. FIG. 13 is a diagram illustrating a configuration of a power-good circuit according to a third embodiment. FIG. 9 is a circuit diagram showing a configuration example of the logic circuit of FIG. 8 . FIG. 10 is a circuit diagram showing a configuration example of the timer circuit of FIG. 9 . FIG. 1 is a diagram showing an example of an electronic circuit system in which a power-good circuit according to an embodiment is independent of a semiconductor circuit device to be monitored. FIG. 13 is a diagram showing a configuration of a power-good circuit according to another embodiment. FIG. 13 is a circuit diagram showing a configuration example of the logic circuit of FIG. 12 . 13 is a timing diagram showing waveforms of each part to explain the operation of the power-good circuit of FIG. 12 (when the resistance value of the pull-up resistor is lower than the resistance threshold value). FIG. 13 is a timing diagram showing waveforms of each part to explain the operation of the power-good circuit of FIG. 12 (when the resistance value of the pull-up resistor is higher than the resistance threshold value). FIG.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
[Overall configuration of semiconductor circuit device and electronic circuit system]

Figure 1 shows an example of the configuration of a semiconductor circuit device incorporating a power-good circuit according to one embodiment of the present invention and an electronic circuit system including the same.

This electronic circuit system includes a power supply 10, a power supply IC 12, and a load IC 14. The power supply 10 is, for example, a battery, a DC-DC converter, or an AC-DC converter, and supplies DC power to the power supply IC 12.

The power supply IC 12 is, for example, a controller for a synchronous rectification type step-down switching power supply 16, which receives a DC voltage _VIN from the power supply 10 and supplies a DC output voltage _VOUT lower than the voltage _VIN to a load IC 14. The power supply IC 12 is a semiconductor circuit device incorporating a power-good circuit 50 according to an embodiment of the present invention.

The load IC 14 is any semiconductor circuit device that operates using power supplied from the power supply IC 12, and may be, for example, a microcontroller, a logic IC, an arithmetic IC, etc. The power supply IC 12 and the load IC 14 are each provided as individual IC packages and are combined on the circuit board of this electronic circuit system.

The power supply IC 12 package has a total of seven terminals: a GND terminal (control ground terminal), a VDD terminal (control power supply input terminal), a PVIN terminal (voltage conversion power supply input terminal), an LX terminal (switching output terminal), a PGND terminal (power ground terminal), a PG terminal (power good terminal), and an FB terminal (feedback terminal).

Here, the LX terminal (switching output terminal) is connected to the voltage input terminal IN of the load IC 14 via the choke coil 18. A smoothing circuit consisting of a capacitor 22 having an equivalent series resistance, and a voltage detection circuit 28 consisting of two resistors 24 and 26 are connected between the output terminal of the choke coil 18 and the ground potential terminal. When the switching power supply 16 is operating, a divided voltage proportional to the output voltage (the voltage at the output terminal of the choke coil 18) V _OUT is obtained at a node _NM between the resistors 24 and 26 of the voltage detection circuit 28. This divided voltage is input to the FB terminal (hereinafter referred to as the "feedback terminal FB") of the power supply IC 12 as a feedback signal S _FB .

The PG terminal (hereinafter referred to as the "power good terminal PG") is connected to the enable terminal EN of the load IC 14, and is also connected to the power supply voltage terminal VPU of the load IC 14 via a pull-up resistor 30. No capacitor is connected between the power good terminal PG and the ground potential terminal.

The power supply IC 12 includes a voltage regulator 32, an error amplifier 34, a reference voltage generating circuit 36, a PWM conversion circuit 38, a driver circuit 40, a P-type MOSFET 42, an N-type MOSFET 44, and a power good circuit 50.

The voltage regulator 32 is, for example, a linear regulator, receives the voltage _VIN supplied from the power supply 10 via the VDD terminal, generates a stable power supply voltage _VREG for control, and supplies this power supply voltage _VREG to each section in the power supply IC 12. The error amplifier 34 compares a feedback signal SFB input from the voltage detection circuit 28 via a feedback terminal _FB with a reference voltage _VREF1 from the reference voltage generation circuit 36, and outputs a comparison error as an analog signal. A resistor 46 and a capacitor 48 around the error amplifier 34 form a phase compensation circuit.

The PWM conversion circuit 38 converts the output of the error amplifier 34 into a PWM (pulse width modulation) signal. The driver circuit 40 drives the P-type MOSFET 42 and the N-type MOSFET 44 on and off in a complementary manner at a constant cycle according to the PWM signal from the PWM conversion circuit 38. As a result, during the period when the P-type MOSFET 42 is on and the N-type MOSFET 44 is off, a current flows from the power supply 10 to the choke coil 18 via the PVIN terminal, the P-type MOSFET 42, and the LX terminal, and electromagnetic energy is accumulated. Next, during the period when the P-type MOSFET 42 is off and the N-type MOSFET 44 is on, an induced electromotive force is generated in the choke coil 18 in a direction that maintains the current, and a current flows through the N-type MOSFET 44 and the choke coil 18, and electromagnetic energy is released to the load IC 14.

The basic function of the power-good circuit 50 is to input a feedback signal _SFB via a feedback terminal FB, monitor the output voltage _VOUT of the switching power supply 16 based on this feedback signal _SFB , and when the output voltage _VOUT is within a predetermined normal range, set the voltage of the power-good terminal PG or the power-good output _VPG to a high impedance state, i.e., H level, and when the output voltage _VOUT is out of the normal range, set the power-good output _VPG to an L level.

The load IC 14 inputs the output voltage _VOUT of the switching power supply 16 to an internal voltage regulator (not shown) via a voltage input terminal IN, and inputs the power-good output _VPG from the power-good circuit 50 to an internal enable signal input circuit (not shown) via an enable terminal EN. The voltage regulator converts the output voltage _VOUT of the switching power supply 16 to a DC power supply voltage _VPU and supplies it to each part in the load IC 14, and also supplies it to the pull-up resistor 30 from the power supply voltage terminal VPU. The enable signal input circuit has a CMOS inverter circuit and outputs a binary signal that inverts the logic level of the input power-good output _VPG . The load IC 14 identifies the logic level of the power-good output _VPG through the enable signal input circuit, and when it is an inactive L level, it remains in a disabled state, and when it is an active H level, it becomes in an enabled state.

In this electronic circuit system, the present invention is applied to the power-good circuit 50 in the power supply IC 12. With this power-good circuit 50, even if a delay function that adds a delay time is set, as well as when a real-time response function that does not add a delay time to the timing of making the power-good output _VPG active (H level) is set, the voltage waveform of the power-good output _VPG can be raised steeply without blunting, regardless of the length of the delay time. As a result, in the load IC 14, even if the through current is small in the enable signal input circuit and there is a variation in the threshold, no large error occurs in the delay time given by the power-good output _VPG .

Furthermore, in the power supply IC 12, of all the terminals of the package, only two terminals are directly related to the power-good circuit 50, namely the power-good terminal PG and the feedback terminal FB, as in the conventional case, and no special terminal is provided for setting whether or not to add a delay time to the power-good circuit 50.

[Embodiment 1 regarding power-good circuit]

Figure 2 shows the basic configuration of a power-good circuit 50 in the first embodiment of the present invention. This power-good circuit 50 includes, as its basic configuration, a determination circuit 52, an output transistor 58, a bypass transistor 60, and a control circuit 62.

The judgment circuit 52 has a comparator 54 and a reference voltage generating circuit 56. The comparator 54 has a non-inverting input terminal (+) connected to a feedback terminal FB and an inverting input terminal (-) connected to the output terminal of the reference voltage generating circuit 56. The comparator 54 compares a feedback signal _{S_FB} input from the feedback terminal FB with a reference voltage _{V_REF2} from the reference voltage generating circuit 56, and when the feedback signal _{S_FB} is lower than the reference voltage _{V_REF2} , the comparator 54 sets its output, i.e., a judgment output CMP-FB, to an L level, and when the feedback signal _{S_FB} is equal to or higher than the reference voltage _{V_REF2} , the comparator 54 sets the judgment output CMP-FB to an H level. The judgment output CMP-FB is provided to a control circuit 62.

The output transistor 58 and the bypass transistor 60 are each made of an NMOS transistor, connected in parallel with each other between the power good terminal PG and the ground potential terminal, and individually controlled by the control circuit 62.

More specifically, the output transistor 58 has a drain connected to the power-good terminal PG, a source connected to the ground potential terminal, and is turned on or off according to a control signal V _G1 given to its gate from a control circuit 62. The bypass transistor 60 has a drain connected to the power-good terminal PG, a source connected to the ground potential terminal, and is turned on or off according to a control signal V _G2 given to its gate from the control circuit 62.

With this configuration, when at least one of the output transistor 58 and the bypass transistor 60 is on, the power-good terminal PG is short-circuited to the ground potential terminal, and the voltage of the power-good terminal PG, i.e., the power-good output _VPG, is kept at the ground level. At this time, the current flowing from the power supply voltage terminal _VPU of the power supply voltage VPU to the ground potential terminal via the pull-up resistor 30, the power-good terminal PG, and the output transistor 58 or the bypass transistor 60 is limited by the pull-up resistor 30.

Furthermore, when both the output transistor 58 and the bypass transistor 60 are off, the power-good terminal PG is in a high impedance state, and the power-good output _VPG of the power-good terminal PG is pulled up to the level of the power supply voltage _VPU, i.e., the H level, via the pull-up resistor 30.

The control circuit 62 controls the output transistor 58 and the bypass transistor 60 in the following manner in response to the determination output CMP-FB of the determination circuit 52. That is, when the determination output CMP-FB of the determination circuit 52 indicates that the output voltage _VOUT to be monitored is not normal (when it is at L level), the control circuit 62 keeps the output transistor 58 in the ON state.

Then, when the output voltage _VOUT becomes normal and the determination output CMP-FB of the determination circuit 52 indicates that the output voltage _VOUT to be monitored is normal (when it changes from L level to H level), the control circuit 62 turns off the output transistor 58 and turns on the bypass transistor 60 for an extremely short time (monitoring time) T _M of, for example, about 10 μsec, to determine whether the current (monitoring current) I _M flowing through the pull-up resistor 30 and the bypass transistor 60 is larger than one or a plurality of current threshold values I _THn (n=1, 2, . . . ), and selects the timing for turning off both the output transistor 58 and the bypass transistor 60, that is, the timing for raising the power-good output _VPG from an inactive L level to an active H level, depending on the determination result.

For example, when there is one current threshold (I _TH1 ), whether the monitor current I _M is greater than the current threshold I _TH1 depends on whether the resistance value R ₃₀ of the pull-up resistor 30 is lower or higher than a certain resistance threshold R _TH1 . That is, there is a correlation in which when the resistance value R ₃₀ of the pull-up resistor 30 is lower than the resistance threshold R _TH1 , the monitor current I _M is greater than the current threshold I _TH1 , and when the resistance value R ₃₀ of the pull-up resistor 30 is higher than the resistance threshold R _TH1 , the monitor current I _M is lower than the current threshold I _TH1 .

In this power-good circuit 50, based on the functions of the bypass transistor 60 and the control circuit 62 as described above and the correlation between the monitor current I _M and the resistance value _R30 of the pull-up resistor ₃₀ as described above, when the output voltage V _OUT to be monitored is normal, it is possible to select either an immediate response function that does not add a delay time or a delay function that adds a certain delay time by selecting the resistance value _R30 of the pull-up resistor 30.

For example, when the resistance threshold value R _TH1 is set to 120 to 130 kΩ, when the designer of the electronic circuit system selects an immediate response function that does not add a delay time for the power-good circuit 50, the designer may select the resistance value R ₃₀ of the pull-up resistor 30 to be, for example, around 100 kΩ, and when the designer selects a delay function that adds a delay time, the designer may select the resistance value R ₃₀ of the pull-up resistor 30 to be, for example, around 150 kΩ.

In this manner, according to the power-good circuit 50 of this embodiment, by appropriately selecting the resistance value _R30 of the pull-up resistor 30 connected to the power-good terminal PG, it is possible to select or set either the immediate response function or the delayed function with regard to the timing for making the power-good _{output VPG} active (H level) when the output voltage VOUT to be monitored is normal.

In order to make such an alternative selection, it is not necessary to add a terminal for default setting to the package of the power supply IC 12. In addition, it is not necessary to newly connect an external component such as a capacitor to the power-good terminal PG in order to select the delay function. Furthermore, since a capacitor is not connected to the power-good terminal PG, when the power-good output _VPG changes from the L level to the H level, the voltage waveform rises sharply without dulling even if a considerably long delay time is added. Therefore, in the load IC 14, the through current is small in the enable signal input circuit, and even if there is a variation in the threshold, there is no large error in the delay time given by the power-good output _VPG . This makes it possible to improve the efficiency and reliability of the power-good function or the output monitoring function.

In the power-good circuit 50 of this embodiment, the output transistor 58 constitutes an output circuit, and the bypass transistor 60 constitutes an output current detection circuit. The pull-up resistor 30 is connected between the power supply voltage terminal VPU and the power-good terminal PG, but may be included in the output circuit. The monitor current I _M that flows when the bypass transistor 60 is turned on is a current that flows through the power-good node. The control circuit 62 controls the power-good output V _PG to an inactive L level (a first state indicating that the output voltage V _OUT is not normal) by turning on the output transistor 58 or to an active _H level (a second state indicating that the output voltage V _OUT is normal) by turning off the output transistor 58 according to the magnitude of the monitor current I M and the determination output CMP- _FB of the determination circuit 52.

[Embodiment 2 regarding power-good circuit]

Next, a second embodiment of the power-good circuit 50 will be described with reference to FIGS. 3 to 7B. This second embodiment provides a preferred specific configuration of the power-good circuit 50 (particularly the control circuit 62) in FIG. 2.

3, the control circuit 62 in this embodiment includes two NMOS transistors 64, 66, a constant current source 68, a determination circuit 70, and a logic circuit 72. Of these, the NMOS transistors 64, 66 and the constant current source 68 configure a monitor current detection unit 65 (output current detection circuit) for detecting the monitor current I _M flowing through the bypass transistor (NMOS transistor) 60.

<Monitor current detection section>

In the monitor current detection unit 65, the NMOS transistor 64 (fourth transistor) is a diode-connected NMOS transistor, the drain of which is connected to the source of the bypass transistor (NMOS transistor) 60 and is short-circuited to its own gate, and the source of which is connected to the ground potential terminal. On the other hand, the drain of the NMOS transistor 66 (fifth transistor) is connected to the output terminal of a constant current source 68 via an output node _NK , the source of which is connected to the ground potential terminal, and the gate of which is commonly connected to the gate of the NMOS transistor 64. The input terminal of the constant current source 68 is connected to the power supply voltage terminal of the power supply voltage _VREG . As a result, the NMOS transistors 64 and 66 form a current mirror circuit in a reference side and dependent side relationship, respectively. The current mirror ratio may be any, and is set to, for example, 1:1.

When the output transistor 58 is turned off and the bypass transistor 60 is turned on, a monitor current I M flows on a current path MP from the power supply voltage terminal VPU of the load IC 14 through the pull-up resistor 30, the power good terminal PG, the bypass transistor 60, and the reference-side NMOS transistor 64 to the ground potential terminal. At this time, the subordinate-side NMOS transistor 66 of the current mirror circuit attempts to pass a drain current I _K of the same amount as the monitor current I _M. However, _{the drain current I K of} the NMOS transistor 66 is limited by the output current (reference current) I _BIAS of the constant current source 68. In this case, the NMOS transistor 66 operates at a point (operating point) where its voltage-current characteristic intersects with the current characteristic of the constant current source 68.

4, when the drain current _IK is larger than the reference current _IBIAS , the intersection AC between the voltage-current characteristic A of the NMOS transistor 66 and the current characteristic C of the constant current source 68 at that time becomes the operating point, and the drain voltage of the NMOS transistor 66, that is, the monitor voltage DET-CUR on the output node _NK becomes lower toward the ground potential. However, when the drain current _IK is smaller than the reference current _IBIAS , the intersection BC between the voltage-current characteristic B of the NMOS transistor 66 and the current characteristic C of the constant current source 68 at that time becomes the operating point, and the monitor voltage DET-CUR becomes higher toward the power supply voltage _VREG . Note that when the monitor current _IM does not flow, both NMOS transistors 64 and 66 of the current mirror circuit are off, and the monitor voltage DET-CUR is close to the power supply voltage _VREG . In this embodiment, the reference current _IBIAS of the constant current source 68 corresponds to the current threshold _ITH1 for the monitor current _IM .

In this way, the monitor current detection unit 65 can accurately detect the monitor current I _M in accordance with the predetermined current threshold I _TH1 with a small-scale circuit configuration using a current mirror circuit.

<Discrimination circuit>

The determination circuit 70 inputs the monitor voltage DET-CUR obtained at the output node _NK of the monitor current detection unit 65, and converts it into a determination output TIME-EN having a binary logic level in accordance with a predetermined voltage threshold. The logic level of this determination output TIME-EN provides significant information when the monitor current I _M flows through the current path MP. In other words, the logic level (H level/L level) of the determination output TIME-EN when the monitor current I _M flows through the current path MP indicates the magnitude relationship between the monitor current I _M and the reference current I _BIAS, that is, the magnitude relationship between the monitor current I _M and the current threshold I _TH1 , and further indicates the magnitude relationship between the resistance value R ₃₀ of the pull-up resistor 30 and the resistance threshold R _TH1 .

As shown in FIG. 5, in one preferred configuration example, the discrimination circuit 70 has a cascade connection of a hysteresis inverter 74 and an inverter circuit 76. The monitor voltage DET-CUR from the monitor current detection unit 65 is input to the hysteresis inverter 74. The output of the inverter circuit 76 is provided to the logic circuit 72 as a discrimination output TIME-EN.

The hysteresis inverter 74 has a voltage threshold _VTHK corresponding to the vicinity of the intermediate value of the power supply voltage _VREG . When the monitor current I _M does not flow on the current path MP, the monitor voltage DET-CUR close to the power supply voltage _VREG is input from the monitor current detection unit 65 to the hysteresis inverter 74, and the hysteresis inverter 74 outputs an L level. As a result, the output (discrimination output) TIME-EN of the inverter circuit 76 becomes an H level.

When the monitor current I _M flows through the current path MP and is greater than the current threshold I _TH1 , the monitor current detector 65 outputs a monitor voltage DET-CUR, which corresponds to the operating point AC in Fig. 4, for example. Then, the hysteresis inverter 74 outputs an H level, and the output (discrimination output) TIME-EN of the inverter circuit 76 changes from the previous H level to an L level.

However, when the monitor current I _M is smaller than the current threshold I _TH1 , the monitor current detector 65 outputs a monitor voltage DET-CUR, which corresponds to, for example, the operating point BC in Fig. 4. In this case, the output of the hysteresis inverter 74 remains at the L level, and the output (discrimination output) TIME-EN of the inverter circuit 76 remains at the H level.

If the power supply voltage _VPU fluctuates unstably when the monitor current I _M flows, the amount of the monitor current I _M will fluctuate similarly, and the monitor voltage DET-CUR will also fluctuate similarly. However, due to the hysteresis characteristics of the hysteresis inverter 74, such fluctuations can be ignored, making it possible to avoid malfunction.

In this way, the determination circuit 70 has a simple configuration using the hysteresis inverter 74, yet is able to obtain a highly accurate determination output TIME-EN that accurately indicates the magnitude relationship between the monitor current I _M and the reference current I _BIAS, and further the magnitude relationship between the resistance value R ₃₀ of the pull-up resistor 30 and the resistance threshold value R _TH1 .

《Logic Circuit》

As shown in FIG. 6, the logic circuit 72 includes, as an example configuration, a delay circuit 80, an inverter circuit 82, an AND circuit 84, a D-type flip-flop (hereinafter referred to as "DFF") 86, a timer circuit 88, an OR circuit 90, and a NAND circuit 92.

As described above, the logic circuit 72 receives the determination output CMP-FB from the determination circuit 52 and the determination output TIME-EN from the discrimination circuit 70 , and applies the control signals V _G1 , V _G2 to the output transistor 58 and the bypass transistor 60 .

More specifically, the decision output CMP-FB from the decision circuit 52 is provided to one input terminal of an AND circuit 84, as well as to an input terminal of the delay circuit 80, a reset terminal (R) of a DFF 86, and one input terminal of a NAND circuit 92. On the other hand, the decision output TIME-EN from the determination circuit 70 is provided to a data terminal (D) of the DFF 86. The output of the AND circuit 84 is provided to the gate of the bypass transistor 60 as a control signal _VG2 . The output of the NAND circuit 92 is provided to the gate of the output transistor 58 as a control signal _VG1 .

The delay circuit 80 is, for example, configured by cascading a plurality of inverter circuits, and delays the determination output CMP-FB by a fixed time. This delay time specifies the time for which the monitor current I _M flows through the current path MP, i.e., the monitor time T _M , and is an extremely short time that can be ignored compared to the delay time (usually 1 msec or more) given by a timer circuit 88 described later, and is set to, for example, 10 μsec or less.

The output DE of the delay circuit 80 is provided to the other input terminal of the AND circuit 84 via the inverter circuit 82, and is also provided to the clock terminal (CK) of the DFF 86. As a result, when the output DE of the delay circuit 80 changes from the L level to the H level, that is, at the end of the monitor time _TM , the logical level of the discrimination output TIME-EN is latched by the DFF 86, and this becomes the logical level of the output (Q) of the DFF 86.

The output (Q) of DFF 86 is provided to an input terminal of a timer circuit 88, and the inverted output (Q-) is provided to one input terminal of an OR circuit 90. The output UR of the timer circuit 88 is provided to the other input terminal of the OR circuit 90, and the output QR of the OR circuit 90 is provided to the other input terminal of the NAND circuit 92.

The timer circuit 88 is adapted to measure a set time in response to the output (Q) of the DFF 86 changing from L level to H level. This timer circuit 88 includes a counter circuit and a clock circuit, and the counter circuit counts clock pulses of a constant frequency generated by the clock circuit, and when the count value reaches a set value, the output UR changes from L level to H level. The measurement time (timer count time) set in the timer circuit 88 specifies the delay time _Td when a delay time is added to the timing of making the power good output _VPG active (H level), and is usually set on the order of msec.

In this way, the logic circuit 72 accurately controls the output transistor 58 and the bypass transistor 60 through logical operations based on the determination output CMP-FB from the determination circuit 52 and the determination output TIME-EN from the discrimination circuit 70. In particular, the delay time _Td added when the power-good output _VPG is made active is generated by the timekeeping operation (counting operation) of the timer circuit 88 with a built-in counter, and therefore has a very small error.

<<Overall Function of the Power Good Circuit>>

Next, the operation of the power-good circuit 50 in this embodiment will be described with reference to the timing diagrams of Figures 7A and 7B.

7A and 7B, the output voltage V _OUT to be monitored is within the normal range (S _FB ≧V _REF2 ) at time t _0. Just before the output voltage V _OUT becomes normal, the states of the various parts are as follows.

That is, since S _FB <V _REF2 until just before the time t ₀ , the judgment output CMP-FB of the judgment circuit 52 is kept at the L level. As a result, the output (control signal) _VG2 of the AND circuit 84 is kept at the L level in the logic circuit 72. Therefore, the bypass transistor 60 is off, the monitor current I _M does not flow on the current path MP, and the judgment output TIME-EN of the judgment circuit 70 is at the H level. Also, in the logic circuit 72, the output DE of the delay circuit 80 is kept at the L level, and the output of the inverter circuit 82 is kept at the H level. The output (Q) and the inverted output (Q-) of the DFF 86 are kept at the L level and the H level, respectively, and the output QR of the OR circuit 90 is at the H level. However, since the judgment output CMP-FB is at the L level, the output (control signal) _VG1 of the NAND circuit 92 is at the H level, and the output transistor 58 is on. As a result, the power-good terminal PG is short-circuited to the ground potential terminal via the output transistor 58 in the ON state, and the power-good output _VPG is maintained at the ground level.

7A shows a case where the resistance value _R30 of the pull-up resistor 30 is selected to be low, around 100 kΩ (<resistance threshold _RTH1 ). When the decision output CMP-FB of the decision circuit 52 changes from L level to H level at time _t0 , the output _VG1 of the NAND circuit 92 changes from H level to L level, and the output transistor 58 switches from its previous on state to an off state. Meanwhile, as the decision output CMP-FB changes from L level to H level, the output _VG2 of the AND circuit 84 changes from L level to H level. This turns on the bypass transistor 60, and a monitor current I _M flows through the current path MP.

At this time, since the resistance value R ₃₀ (about 100 kΩ) of the pull-up resistor 30 is lower than the resistance threshold value R _TH1 (120 to 130 kΩ), the monitor current I _M flows at an amount greater than the reference current I _BIAS , and the discrimination circuit 70 outputs a discrimination output TIME-EN of L level.

When the monitor current I _M flows, the voltage of the power-good terminal PG, i.e., the power-good output V _PG , becomes slightly higher than the ground level by the voltage drop caused by the bypass transistor 60 and the NMOS transistor 64 on the current path MP, but is clearly at the L level.

When the monitor time T _M from time t ₀ ends and the output DE of the delay circuit 80 changes from L level to H level (time t ₁ ), the output _VG2 of the AND circuit 84 changes from H level to L level. This causes the bypass transistor 60 to return to the off state, and the monitor current I _M stops flowing. The discrimination output TIME-EN of the discrimination circuit 70 returns from L level to H level.

On the other hand, at time _t1 , in response to the change of the output DE of the delay circuit 80 from L level to H level, the DFF 86 takes in and latches the logical level of the discrimination output TIME-EN. In this case, since the discrimination output TIME-EN is at L level, the output (Q) and the inverted output (Q-) of the DFF 86 remain at L level and H level, respectively, and the output QR of the OR circuit 90 remains at H level. Therefore, the output _VG1 of the NAND circuit 92 remains at L level, and the output transistor 58 remains in the off state.

Thus, when the monitor time T _M ends (time t ₁ ), both the output transistor 58 and the bypass transistor 60 are turned off, whereby the power-good terminal PG is pulled up to the voltage of the power supply voltage V _PU via the pull-up resistor 30, and the power-good output V _PG rises from the previous L level to the H level. Since no capacitor is connected to the power-good terminal PG, the voltage waveform of the power-good output V _PG rises sharply without dulling.

7B shows a case where the resistance value _R30 of the pull-up resistor 30 is set to a relatively high level, around 150 kΩ. In this case as well, when the decision output CMP-FB of the decision circuit 52 changes from L level to H level at time _t0 , the output _VG1 of the NAND circuit 92 changes from H level to L level. This causes the output transistor 58 to switch from its previous ON state to an OFF state. On the other hand, when the decision output CMP-FB changes from L level to H level, the output _VG2 of the AND circuit 84 changes from L level to H level. This turns on the bypass transistor 60, and the monitor current I _M flows through the current path MP.

In this case, since the resistance value R ₃₀ (about 150 kΩ) of the pull-up resistor 30 is higher than the resistance threshold value R _TH1 (120 to 130 kΩ), the monitor current I _M flows at an amount smaller than the reference current I _BIAS , and the discrimination circuit 70 outputs the discrimination output TIME-EN at an H level.

Then, when the monitor time T _M has elapsed from time _t0 and the output DE of the delay circuit 80 changes from L level to H level (time t ₁ ), the output _VG2 of the AND circuit 84 changes from H level to L level. This causes the bypass transistor 60 to return to the OFF state, and the monitor current I _M stops flowing. The discrimination output TIME-EN of the discrimination circuit 70 is maintained at H level.

On the other hand, at time _t1 , in response to the change of the output DE of the delay circuit 80 from L level to H level, the DFF 86 takes in and latches the logical level of the discrimination output TIME-EN. In this case, since the discrimination output TIME-EN is H level, the output (Q) of the DFF 86 changes from the previous L level to H level, and the inverted output (Q-) changes from H level to L level. When the output (Q) of the DFF 86 becomes H level, in response, the timer circuit 88 starts counting the set delay time _Td .

However, the output UR of the timer circuit 88 remains at L level until the time count ends. Therefore, when the inverted output (Q-) of the DFF 86 becomes L level (time _t1 ), the output QR of the OR circuit 90 changes from H level to L level, the output _VG1 of the NAND circuit changes from L level to H level, and the output transistor 58 returns to the ON state. As a result, the power-good terminal PG is short-circuited to the ground potential terminal via the output transistor 58 in the ON state, and the power-good output _VPG is held at the ground level.

Then, when the timer circuit 88 finishes counting the set delay time _Td and its output UR changes from L level to H level (time _t2 ), the output QR of the OR circuit 90 changes from L level to H level, the output _VG1 of the NAND circuit changes from H level to L level, and the output transistor 58 turns off.

Thus, when the timer circuit 88 finishes counting the set delay time _Td (at time _t2 ), both the output transistor 58 and the bypass transistor 60 are turned off, whereby the power-good terminal PG is pulled up to the voltage of the power supply voltage _VPU via the pull-up resistor 30, and the power-good output _VPG rises from the previous L level (ground level) to an active H level ( _VPU ). Since no capacitor is connected to the power-good terminal PG, no matter how long the delay time _Td is, for example, even if it is several tens of milliseconds or more, the voltage waveform of the power-good output _VPG rises sharply without dulling.

In this manner, according to this embodiment, in addition to obtaining the same effects as those of the first embodiment, the respective parts of the control circuit 62 (the monitor current detection part 65, the discrimination circuit 70, and the logic circuit 72) can be configured on a small scale, resulting in an effect of high accuracy.

[Embodiment 3 regarding power-good circuit]

Next, a power-good circuit 50Φ in a third embodiment will be described with reference to Figures 8 to 10. In the power-good circuit 50Φ in this embodiment, by appropriately selecting the resistance value _R30 of the pull-up resistor 30 connected to the power-good terminal PG, it is possible to select or set whether or not to add a delay time to the timing at which the power-good output _VPG is made active (H level) when the output voltage _VOUT to be monitored is normal.

Furthermore, in the power-good circuit 50Φ of this embodiment, when selecting to add a delay time, it is possible to select one of a plurality of different delay times by setting the resistance value _R30 of the pull-up resistor 30 to a region higher than the minimum resistance monitor value _RTH1, and further setting one or more resistance monitor values _RTH2 , _RTH3 , ....

Figure 8 shows a preferred example of a power-good circuit 50Φ that allows selection of one of three different delay times. Figure 9 shows the configuration of the logic circuit 72Φ in Figure 8. Figure 10 shows a preferred example of a timer circuit 88Φ in Figure 9.

In the monitor current detection unit 65Φ of Fig. 8, three dependent side NMOS transistors 66A, 66B, 66C are provided in parallel with a reference side diode-connected NMOS transistor 64, each of whose gates is commonly connected. The drains of these three dependent side NMOS transistors 66A, 66B, 66C are connected to output terminals of constant current sources 68A, 68B, 68C via output nodes N _A , N _B , N _C , and the sources of these transistors are connected to a ground potential terminal. The input terminals of the constant current sources 68A, 68B, 68C are connected to the power supply voltage terminal of the power supply voltage _VREG . This forms three independent current mirror circuits that share the reference side diode-connected NMOS transistor 64.

The output currents (reference currents) _IBIAS1 , _IBIAS2 , and _IBIAS3 of constant current sources 68A, 68B, and 68C correspond to three resistance thresholds _RTH1 , _RTH2 , and _RTH3 (where _RTH1 < _RTH2 < _RTH3 ), respectively, and are set to a relationship of _IBIAS1 > _IBIAS2 > _IBIAS3 .

The monitor voltages DET-CURA, DET-CURB, and DET-CURC obtained at the three output nodes N _A , N _B , and N _C of the monitor current detection unit 65Φ are input to three discrimination circuits 70A, 70B, and 70C, respectively. These three discrimination circuits 70A, 70B, and 70C have a configuration similar to that of the discrimination circuit 70 in Fig. 3, and convert the monitor voltages DET-CURA, DET-CURB, and DET-CURC into discrimination outputs TIME-ENA, TIME-ENB, and TIME-ENC, respectively, having binary logical levels in accordance with predetermined voltage thresholds, and provide them to a logic circuit 72#.

In the logic circuit 72Φ in FIG. 9, the discrimination outputs TIME-ENA, TIME-ENB, and TIME-ENC from the discrimination circuits 70A, 70B, and 70C are input to the data terminal (D) of the DFF 86 via the OR circuit 94, and are also input to the timer circuit 88Φ.

As shown in Fig. 10, the timer circuit 88Φ has three timers 96A, 96B, and 96C connected in cascade. These three timers 96A, 96B, and 96C have the same configuration as the timer circuit 88 in Fig. 6, and can set independent time count times (timer count times) _Td1 , _Td2 , and _Td3 , respectively. The timer circuit 88Φ as a whole provides three delay times: [ _Td1 ], [ _Td1 + _Td2 ], and [ _Td1 + _Td2 + _Td3 ].

The first stage timer 96A starts a timekeeping operation (counting operation) in response to the output (Q) of the DFF 86 changing from L level to H level, and when the measurement of the set time _Td1 ends, changes its output from L level to H level. In response to this, the second stage timer 96B starts a timekeeping operation (counting operation), and when the measurement of the set time _Td2 ends, changes its output from L level to H level. In response to this, the third stage timer 96C starts a timekeeping operation (counting operation), and when the measurement of the set time _Td3 ends, changes its output from L level to H level.

The outputs of the timers 96A, 96B, and 96C are input to one input terminal of each of the AND circuits 98A, 98B, and 98C. The other input terminals of the AND circuits 98A, 98B, and 98C receive the discrimination outputs TIME-ENA, TIME-ENB, and TIME-ENC from the discrimination circuits 70A, 70B, and 70C, respectively. The AND circuit 98A also receives an inverted signal of the discrimination output TIME-ENB, and the AND circuit 98B also receives an inverted signal of the discrimination output TIME-ENC. The outputs of the AND circuits 98A, 98B, and 98C are provided to the other input terminal of the OR circuit 92 (Figure 9) via the OR circuit 100.

In this power-good circuit 50Φ, as described above, when the output voltage V _OUT to be monitored falls within the normal range (V _OUT ≧V _REF2 ), the judgment output CMP-FB of the judgment circuit 52 changes from L level to H level, and in response, the logic circuit 72 switches the output transistor 58 from ON to OFF and the bypass transistor 60 from OFF to ON. This causes the monitor current I _M to flow through the current path MP. The amount of this monitor current I _M depends on the resistance value _R30 of the pull-up resistor 30.

When the resistance value _R30 of the pull-up resistor 30 is selected to be lower than the minimum resistance threshold _RTH1 (when no delay time is added), I _M > I _BIAS1 , and in the monitor current detection unit 65Φ, the monitor voltages DET-CURA, DET-CURB, and DET-CURC all become lower toward the ground potential during the monitor time T _M in the monitor current detection unit 65Φ, and the discrimination outputs TIME-ENA, TIME-ENB, and TIME-ENC of the discrimination circuits 70A, 70B, and 70C all become L level. This results in the same operation as in the case of Fig. 7A, and when the monitor time T _M ends, both the output transistor 58 and the bypass transistor 60 are turned off, and the power-good output _VPG rises from L level to active H level.

When the resistance value _R30 of the pull-up resistor 30 is selected to be _RTH1 < _R30 < _RTH2 (when the shortest delay time [ _Td1 ] is selected), the monitor current I _M flowing through the current path MP during the monitor time T _M is I _BIAS2 < I _M < I _BIAS1 , and in the monitor current detection unit 65Φ, only the monitor voltage DET-CURA is high and closer to the power supply voltage _VREG , while the other monitor times DET-CURB, DET-CURC are low and closer to ground potential, so that the discrimination output TIME-ENA of the discrimination circuit 70A is at an H level, and the discrimination outputs TIME-ENB, TIME-ENC of the discrimination circuits 70B, 70C are at an L level. This results in the same operation as in FIG. 7B, and when a further delay time [T _d1 ] has elapsed since the end of the monitor time T _M , both the output transistor 58 and the bypass transistor 60 are turned off, and the power-good output V _PG rises from the L level to the active H level.

In this case, in the timer circuit 88Φ, when the first stage timer 96A finishes timing the set time _Td1 and outputs an H level, the output of the AND circuit 98A goes to H level and the output of the OR circuit 100 also goes to H level. Even if the second stage timer 96B and the third stage timer 96C finish timing the set times _Td2 and _Td3 , respectively, and output an H level, the outputs of the AND circuits 98B and 98C remain at L level because the discrimination outputs TIME-ENB and TIME-ENC are at L level.

Next, if the resistance value _R30 of the pull-up resistor 30 is selected to be _RTH2 < _R30 < _RTH3 (if the intermediate delay time [ _Td1 + _Td2 ] is selected), then _IBIAS3 < _IM < _IBIAS2 , and in the monitor current detection unit 65Φ, during the monitor time _TM, the monitor voltages DET-CURA, DET-CURB become higher toward the power supply voltage _VREG and the monitor voltage DET-CURC becomes lower toward the ground potential, the discrimination outputs TIME-ENA, TIME-ENB of discrimination circuits 70A and 70B become H level, and the discrimination output TIME-ENC of discrimination circuit 70C becomes L level. This basically results in the same operation as in the case of FIG. 7B, and when a further delay time [T _d1 +T _d2 ] has elapsed since the end of the monitor time T _M , both the output transistor 58 and the bypass transistor 60 are turned off, and the power-good output V _PG rises from the L level (ground level) to the active H level (V _PU ).

In this case, in the timer circuit 88Φ, even if the first stage timer 96A finishes timing the set time _Td1 and outputs an H level, the output of the AND circuit 98A remains at an L level because the inverted output of the discrimination output TIME-ENB by the inverter circuit 99A is at an L level. Then, when the second stage timer 96B finishes timing the set time _Td2 and outputs an H level, the output of the AND circuit 98B becomes an H level, and the output of the OR circuit 100 also becomes an H level.

Finally, when the resistance value _R30 of the pull-up resistor 30 is selected to be _RTH3 < _R30 (when the longest delay time [ _Td1 + _Td2 + _Td1 ] is selected), I _M < _IBIAS3 , and in the monitor current detection unit 65Φ, the monitor voltages DET-CURA, DET-CURB, and DET-CURC all become higher toward the power supply voltage _VREG during the monitor time T _M in the monitor current detection unit 65Φ, and the discrimination outputs TIME-ENA, TIME-ENB, and TIME-ENC of the discrimination circuit 70A all become H level. This basically results in the same operation as in the case of Fig. 7B, and when a further delay time [ _Td1 + _Td2 + _Td1 ] has elapsed since the end of the monitor time T _M , both the output transistor 58 and the bypass transistor 60 are turned off, and the power-good output V _PG rises from L level to active H level.

In this case, in the timer circuit 88Φ, even if the first stage timer 96A finishes timing the set time _Td1 and outputs an H level, the output of the AND circuit 98A remains at the L level because the inverted output of the discrimination output TIME-ENB by the inverter circuit 99A is at the L level. And even if the second stage timer 96B finishes timing the set time _Td2 and outputs an H level, the output of the AND circuit 98B remains at the L level because the inverted output of the discrimination output TIME-ENC by the inverter circuit 99B is at the L level. And when the third stage timer 96C finishes timing the set time _Td3 and outputs an H level, the output of the AND circuit 98C becomes the H level, and the output of the OR circuit 100 also becomes the H level.

In this manner, according to this embodiment, in addition to obtaining the same effects as those of the second embodiment, the delay time added when the power-good output _VPG is made active can be arbitrarily selected from a plurality of delay times set in the built-in timer circuit by selecting the resistance value _R30 of the pull-up resistor 30. As a result, when the output voltages of a plurality of power supply ICs are sequentially raised with a certain time difference, for example, the power-good circuit of each power supply IC can be suitably adapted to an electronic circuit system in which the above-mentioned time difference is set in the timing of making the power-good output active (H level) so that the operation start of a plurality of load ICs receiving power from the plurality of power supply ICs is approximately simultaneous.

[Other embodiments or modifications]

Although several preferred embodiments of the present invention have been described above, the present invention is not limited to the above-mentioned embodiments. Those skilled in the art can make various modifications and changes to specific embodiments without departing from the technical concept and scope of the present invention.

For example, the above-described embodiment relates to the power-good circuits 50, 50Φ built into the power supply IC 12. However, the present invention is also applicable to a power-good circuit that is independent of the power supply IC 12.

For example, the electronic circuit system shown in FIG. 11 includes a DC/DC converter 102, LDOs (low drop linear regulators) 104 and 106, load ICs 108 and 110, and a power good circuit 50#, each of which is provided as an independent semiconductor circuit device or IC.

The DC/DC converter 102 converts a DC input voltage V _IN to a DC voltage V _OUT-Main , and supplies the converted DC voltage V _OUT-Main to a first and a second LDO (low drop linear regulator) 104, 106. Both LDOs 104, 106 convert the input DC voltage V _OUT-Main to DC voltages V _OUT1 and V _OUT2 , respectively. The output voltage V _OUT1 of the first LDO 104 is supplied to a first load IC 108, and the output voltage V _OUT2 of the second LDO 106 is supplied to a second load IC 110.

The output terminal of the DC/DC converter 102 is also connected to the enable terminal (EN) of the second LDO 106 via resistor 30#. Resistor 30# functions as a pull-up resistor, and therefore the output terminal of the DC/DC converter 102 functions as a power supply voltage terminal for pull-up.

A voltage detection circuit 118 including a smoothing capacitor 112 and resistors 114 and 116 is connected in parallel between the output terminal of the first LDO 104 and the ground potential terminal. An output node _NM of the voltage detection circuit 118 is connected to a feedback terminal FB of the LDO 104 and a feedback terminal FB of the power-good circuit 50#.

The power-good circuit 50# is connected to the output terminal of the first LDO 104 via a voltage detection circuit 118, monitors the output voltage _VOUT1 of the first LDO 104, and provides a power-good output _VPG indicating whether the output voltage _VOUT1 is normal or not at a binary logical level from a power-good terminal PG to the second LDO (second semiconductor circuit device) 106. As described above, the power-good terminal PG is connected to the enable terminal EN of the second LDO 106, and is also connected to the output terminal (power supply voltage terminal) of the DC/DC converter 102 via a pull-up resistor 30#.

The power-good circuit 50# may have the same circuit configuration and function as the power-good circuit 50 in the first embodiment. Therefore, when the output voltage _VOUT1 of the first LDO 104 enters the normal range, the power-good output _VPG immediately changes from the L level to the active H level, or changes to the active H level after the set delay time _TD has elapsed, depending on the resistance value R30# of the pull-up resistor _30# . When the power-good output _VPG becomes the active H level, the second LDO 106 is enabled in response to this and operates, supplying its output voltage _VOUT2 to the load IC 110. The power-good circuit 50# and the electronic circuit system of this embodiment also provide the same effects as those of the first embodiment. Furthermore, the effect of the present invention, which does not require the addition of package terminals to add a function for setting whether or not to apply a delay time, is even more advantageous because it can be obtained with the IC package of the power-good circuit 50#, which has an extremely small number of terminals.

As in this embodiment, the semiconductor circuit device (load IC 108) to which the output voltage _VOUT1 to be monitored by the power-good circuit 50# is supplied and the semiconductor circuit device (second LDO 106) to which the power-good output _VPG is given from the power-good circuit 50# may be different.

Although not shown in the figure, the power-good circuit 50Φ according to the second embodiment can also be applied to the electronic circuit system of this embodiment. In addition, as the power supply voltage to be connected to the power-good terminal PG, a voltage other than the output voltage of the DC/DC converter 102, for example, the output voltage _VOUT1 or an internal voltage of the first LDO 104, can also be used.

In the power-good circuit 50 (50Φ) of the above embodiment, a bypass transistor 60 constituting an output current detection circuit is provided in parallel with an output transistor 58 constituting an output circuit between the power-good terminal PG and the ground potential terminal. The control circuit 62 (62Φ) keeps the output transistor 58 on when the determination output CMP-FB of the determination circuit 52 is at L level (indicating that the output voltage _VOUT to be monitored is not normal), and turns off the output transistor 58 and turns on the bypass transistor 60 for a predetermined monitor time T _M when the determination output CMP-FB of the determination circuit 52 is at H level (indicating that the output voltage is normal), causing the discrimination circuit 70 (70A, 70B, 70C) to determine whether the monitor current I _M flowing through the pull-up resistor 30 and the bypass transistor 60 is larger than one or more current threshold values I _THn , and causes the logic circuit 72 (72Φ) to select the timing for turning off both the output transistor 58 and the bypass transistor 60 based on the discrimination output TIME-EN (TIME-ENA, TIME-ENB, TIME-ENC).

As a power-good circuit in another embodiment of the present invention, when the determination output CMP-FB of the determination circuit 52 is at an L level, the output transistor 58 is kept in an OFF state, and when the determination output CMP-FB of the determination circuit is at an H level, the bypass transistor 60 is turned on while maintaining the output transistor 58 in an OFF state for a predetermined monitor time T _M , so that the determination circuit 70 (70A, 70B, 70C) determines whether the monitor current I _M flowing through the pull-up resistor 30 and the bypass transistor 60 is greater than one or more current threshold values I _THn , and based on the determination output TIME-EN (TIME-ENA, TIME-ENB, TIME-ENC), the logic circuit 72 (72Φ) can select the timing for turning on the output transistor 58 and turning off the bypass transistor 60.

As yet another embodiment, it is possible to configure a single output transistor 59 to function as both the output transistor 58 and the bypass transistor 60, as in the power-good circuit 50θ shown in FIG. 12.

In this power-good circuit 50θ, the output transistor 59 (third transistor) is an NMOS transistor, the drain of which is connected to the power-good terminal PG, the source of which is connected to the drain of the NMOS transistor 64 of the monitor current detection section 65, and which serves as both an output circuit and an output current detection circuit that is turned on or off according to a control signal _VG given to the gate from a logic circuit 72θ. The monitor current detection section 65, the determination circuit 70, and the decision circuit 52 may be the same as those in the second embodiment (FIG. 3).

The logic circuit 72θ keeps the output transistor 59 on when the judgment output CMP-FB of the judgment circuit 52 is at L level, and when the judgment output CMP-FB is at H level, it selects the timing to switch the output transistor 59 from the on state to the off state based on the judgment output TIME-EN from the discrimination circuit 70.

As in the second embodiment, the logic circuit 72θ can capture (read) the discrimination output TIME-EN after a predetermined monitor time T _M has elapsed immediately after the decision output CMP-FB goes to the H level. Alternatively, the logic circuit 72θ can capture (read) the discrimination output TIME-EN when or before the decision output CMP-FB goes to the H level, in which case there is no need to provide a monitor time T _M.

13 shows an example of the configuration of a logic circuit 72θ in which a monitor time T _M is not provided. The discrimination output TIME-EN from the discrimination circuit 70 is given to the clock terminal (CK) and reset terminal R of the DFF 86 and one input terminal of a NAND circuit 92, and is also given to one input terminal of an OR circuit 95 via an inverter circuit 93. The output of the OR circuit 90 is given to the other input terminal of the NAND circuit 92. The output of the NAND circuit 92 is given to the other input terminal of the OR circuit 95. The output of the OR circuit 95 is given to the gate of the output transistor 59 as a control signal _VG .

14A and 14B show the operation of the power-good circuit 50θ (FIGS. 12 and 13). Fig. 14A shows the case where the resistance value _R30 of the pull-up resistor 30 is selected to be lower than the resistance threshold value _RTH1 . Fig. 14B shows the case where the resistance value _R30 of the pull-up resistor 30 is selected to be higher than the resistance threshold value _RTH1 .

In this example, the output voltage V _OUT to be monitored is in the normal range (S _FB ≧V _REF2 ) at time t ₀ . Before the output voltage V _OUT enters the normal range, S _FB <V _REF2 , so the judgment output CMP-FB of the judgment circuit 52 is kept at the L level. As a result, in the logic circuit 72θ, the output XR of the inverter circuit 93 is at the H level, and the output (control signal) _VG of the OR circuit 95 is kept at the H level. For this reason, the output transistor 59 is on, the current I _M flows through the current path MP, and the judgment output TIME-EN of the judgment circuit 70 is at a significant logical level. That is, when R ₃₀ <R _TH1 ( FIG. 14A ), the judgment output TIME-EN is at the L level, and when R ₃₀ >R _TH1 ( FIG. 14B ), the judgment output TIME-EN is at the H level. The DFF 86 was reset when the judgment output CMP-FB changed from H level to L level last time, and the output (Q) and the inverted output (Q-) are at L level and H level, respectively. As a result, the output QR of the OR circuit 90 is at H level, and the output WR of the NAND circuit 92 is at H level.

When the decision output CMP-FB of the decision circuit 52 changes from L level to H level at time _t0 , the output XR of the inverter circuit 93 changes from H level to L level. At the same time, the DFF 86 takes in the logic level of the decision output TIME-EN. In the case of _R30 < _RTH1 (FIG. 14A), the decision output TIME-EN is at L level, so the output (Q) and the inverted output (Q-) of the DFF 86 remain at L level and H level, respectively, and the output QR of the OR circuit 90 maintains H level. As a result, the output WR of the NAND circuit 92 changes from H level to L level, the output (control signal) _VG of the OR circuit 95 changes from H level to L level, and the output transistor 59 changes from ON state to OFF state. Then, the power-good terminal PG is pulled up to the voltage of the power supply voltage _VPU via the pull-up resistor 30, and the power-good output _VPG rises from L level to H level. Since no capacitor is connected to the power-good terminal PG, the power-good output _VPG rises sharply without its voltage waveform becoming dull.

In the case of _R30 > _RTH1 (FIG. 14B), when the DFF86 takes in the logic level (H level) of the discrimination output TIME-EN (time _t0 ), the output (Q) and inverted output (Q-) of the DFF86 change to H level and L level, respectively. When the output (Q) of the DFF86 becomes H level, the timer circuit 88 starts counting the set delay time _Td in response. Then, when the timer circuit 88 finishes counting the set delay time _Td and its output UR changes from L level to H level (time _t2 ), the output QR of the OR circuit 90 changes from L level to H level, and the output WR of the NAND circuit 92 changes from H level to L level. At this timing, the output (control signal) _VG of the OR circuit 95 changes from H level to L level, and the output transistor 59 changes from ON state to OFF state. Then, the power-good terminal PG is pulled up to the voltage of the power supply voltage _VPU via the pull-up resistor 30, and the power-good output _VPG rises from the previous L level (ground level) to an active H level ( _VPU ). Since no capacitor is connected to the power-good terminal PG, the voltage waveform of the power-good output _VPG rises sharply without dulling, no matter how long the delay time _Td is, for example, even if it is more than several tens of msec.

The power-good circuit 50θ (FIG. 12) of this embodiment is a modification of the power-good circuit 50 (FIG. 3) of the second embodiment. The power-good circuit 50Φ (FIG. 8) of the third embodiment can also be modified in the same way to obtain a circuit equivalent to the power-good circuit 50θ.

According to the present invention, when the output voltage _VOUT of the monitor target is normal, the timing for raising the power-good output _VPG to an active H level can be set to either an immediate response function that does not add a delay time or a delay function that adds a certain delay time by selecting the resistance value _R30 of the pull-up resistor 30. In the above second embodiment, when the immediate response function that does not add a delay time is selected, the resistance value _R30 of the pull-up resistor 30 is selected to be lower than the resistance threshold value _RTH1 , and when the delay function that adds a delay time is selected, the resistance value _R30 of the pull-up resistor 30 is selected to be higher than the resistance threshold value _RTH1 . This rule is just an example. A rule of reverse logic is also possible.

That is, when the immediate response function is selected, the resistance value _R30 of the pull-up resistor 30 is selected to be higher than the resistance threshold value _RTH1 , and when the delay function for adding a delay time is selected, the resistance value _R30 of the pull-up resistor 30 is selected to be lower than the resistance threshold value _RTH1 . In this case, when the monitor current _I3M is smaller than the current threshold value _I3M (when _R30 > _RTH1 ), the control circuit 50 turns off both the output transistor 58 and the bypass transistor 60 immediately after the end of the monitor time _T3M , and when the monitor current _I3M is larger than the current threshold value _I3M (when _R30 < _RTH1 ), the control circuit 50 turns off both the output transistor 58 and the bypass transistor 60 after a predetermined delay time _Td has elapsed after the end of the monitor time _T3M . Not only in the second embodiment, but also in the other embodiments, the logic of the rule regarding the selection of the resistance value _R30 of the pull-up resistor 30 can be reversed.

In general, a power good circuit is provided as a type of output voltage monitoring circuit that monitors an arbitrary output voltage of a given semiconductor circuit device and indicates the state of the output voltage with a binary logic level. The present invention is not limited to power good circuits, but is also applicable to other output voltage monitoring circuits that provide a voltage monitoring output that indicates the state of the output voltage to be monitored with a binary logic level to a given semiconductor circuit device. Furthermore, the present invention is not limited to power good circuits or output voltage monitoring circuits built into or connected to a power supply IC, but is also applicable to power good circuits or output voltage monitoring circuits built into or connected to a semiconductor circuit device other than a power supply IC.

The determination circuit in the power good circuit or output voltage monitoring circuit of the present invention may use multiple reference voltages (e.g., lower and upper limits) to determine whether the output voltage being monitored is normal or not.

12 Power supply IC
14 Load IC
16 Switching power supply 28 Voltage detection circuit 30, 30# Pull-up resistor 50, 50Φ, 50#, 50θ Power good circuit 52 Determination circuit 58, 59 Output transistor 60 Bypass transistor 62, 62Φ, 62θ Control circuit 64, 66 NMOS transistor 65 Monitor current detection unit 68, 68A, 68B, 68C Constant current source 70, 70A, 70B, 70C Discrimination circuit 72, 72Φ, 72θ Logic circuit 74 Hysteresis inverter 80 Delay circuit 86 D-type flip-flop (DFF)
88, 88Φ Timer circuit 102 DC/DC converter 104, 106 LDO (low drop linear regulator)
PG Power Good terminal 108, 110 Load IC

Claims (9)

A power-good circuit that monitors an output voltage and outputs a power-good signal that indicates whether the output voltage is normal or not with a binary logic level,
an output circuit that outputs the power-good signal from a power-good node;
an output current detection circuit for detecting a current flowing through the power good node;
a determination circuit that determines whether the output voltage is normal by referring to a predetermined reference voltage;
a control circuit for controlling the output circuit to a first state or a second state in response to a determination output of the determination circuit and an output of the output current detection circuit;
having
The control circuit includes:
maintain the output circuit in a first state when the determination output of the determination circuit indicates that the output voltage is not normal;
a power-good circuit which, when the judgment output of the judgment circuit indicates that the output voltage is normal, turns on the output current detection circuit for a predetermined monitor time, judges whether or not a monitor current flowing through the output current detection circuit is greater than one or more current threshold values, and selects the timing to put the output circuit into a second state based on the judgment result. The control circuit includes:
when the output voltage is abnormal, a first transistor constituting the output circuit is maintained in an ON state;
When the determination output of the determination circuit indicates that the output voltage is normal, the first transistor is turned off for a predetermined monitor time and a second transistor constituting the output current detection circuit is turned on to determine whether or not a monitor current flowing through a pull-up resistor and the second transistor constituting the output circuit is greater than one or more current threshold values, and a timing for turning off both the first transistor and the second transistor is selected based on the determination result; or
when the determination output of the determination circuit indicates that the output voltage is not normal, the first transistor is kept in an off state;
when the determination output of the determination circuit indicates that the output voltage is normal, turning on the second transistor while maintaining the first transistor in an off state for a predetermined monitor time, determining whether or not a monitor current flowing through the pull-up resistor and the second transistor is greater than one or more current threshold values, and selecting a timing for turning on the first transistor and turning off the second transistor based on the determination result;
2. The power good circuit of claim 1. The control circuit includes:
a third transistor serving as both the output circuit and the output current detection circuit;
when the determination output of the determination circuit indicates that the output voltage is not normal, the third transistor is maintained in an on state;
when the determination output of the determination circuit indicates that the output voltage is normal, the output current detection circuit is turned on for a predetermined monitor time, and a timing for switching the third transistor from an on state to an off state is selected based on a determination result obtained from a determination circuit which determines whether or not a monitor current flowing through the output current detection circuit is greater than one or more current threshold values.
2. The power good circuit of claim 1. The control circuit includes:
when the monitor current flowing through the output current detection circuit is greater than a predetermined current threshold, immediately after a predetermined monitor time has elapsed, turning off both a first transistor constituting the output circuit and a second transistor constituting the output current detection circuit;
when the monitor current is smaller than the current threshold, turning off both the first transistor and the second transistor after a predetermined delay time has elapsed after the end of the predetermined monitor time;
4. The power-good circuit according to claim 2 or 3. The control circuit includes:
when the monitor current flowing through the output current detection circuit is smaller than a predetermined current threshold, immediately after a predetermined monitor time has elapsed, turning off both a first transistor constituting the output circuit and a second transistor constituting the output current detection circuit;
when the monitor current is greater than the current threshold, turning off both the first transistor and the second transistor after a predetermined delay time has elapsed after the end of the predetermined monitor time;
4. The power-good circuit according to claim 2 or 3. The control circuit includes:
a diode-connected fourth transistor that constitutes the output current detection circuit and is connected to the second transistor that constitutes the output current detection circuit;
a fifth transistor forming a current mirror circuit together with the fourth transistor;
a discrimination circuit that converts a voltage of a node of the output of the current mirror circuit into a discrimination output having a binary logic level in accordance with a predetermined voltage threshold;
4. The power-good circuit of claim 2, further comprising: The control circuit includes:
when the monitor current is greater than a first current threshold, immediately after the end of the monitor time, turning off both a first transistor constituting the output circuit and a second transistor constituting the output current detection circuit;
when the monitor current is greater than a second current threshold and less than the first current threshold, turning off both the first transistor and the second transistor after a first delay time has elapsed since the end of the monitor time;
when the monitor current is smaller than the second current threshold, after a second delay time longer than the first delay time has elapsed after the end of the monitor time, both the first transistor and the second transistor are turned off;
2. The power good circuit of claim 1. The control circuit includes:
when the monitor current is smaller than a first current threshold, immediately after the end of the monitor time, turning off both a first transistor constituting the output circuit and a second transistor constituting the output current detection circuit;
when the monitor current is greater than the first current threshold and less than a second current threshold, turning off both the first transistor and the second transistor after a first delay time has elapsed since the end of the monitor time;
when the monitor current is greater than the second current threshold, after a second delay time longer than the first delay time has elapsed after the end of the monitor time, both the first transistor and the second transistor are turned off;
2. The power good circuit of claim 1. The output current detection circuit includes a plurality of output current detection circuits that convert the current flowing through the power-good node detected by the output current detection circuit into respective discrimination outputs having binary logic levels in accordance with different current thresholds.
The power-good circuit according to any one of claims 1 to 8.

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