JP7581942B2 - Driving circuit for droplet ejection head and droplet ejection device - Google Patents

Description

This invention relates to a drive circuit for a droplet ejection head and a droplet ejection device.

There are droplet ejection devices that apply pressure fluctuations to liquids such as ink, causing them to be ejected from nozzles. A known method of applying pressure fluctuations is to apply a pulsed drive signal to an actuator, causing it to deform. One method of generating a drive signal is to generate a square wave by switching the output between multiple supply voltages.

The waveform of the drive signal affects the frequency distribution and amplitude of the pressure fluctuation applied to the liquid, so the drive signal needs to be generated and output with high precision. Patent Document 1 discloses a technology for improving the waveform precision by controlling the output voltage and the ground voltage output in a drive circuit having a transistor that selectively outputs a supply voltage and a ground voltage by feeding back the output voltage and comparing it with the input voltage, and finely controlling the output and non-output of the supply voltage and the ground voltage, respectively, so that the trapezoidal drive signal waveform does not deviate significantly from the input signal waveform. In addition, when switching between the output and non-output, if the supply voltage supply path and the ground voltage supply path are turned on simultaneously, the supply voltage flows directly to the ground surface, consuming power. Therefore, in Patent Document 1, the threshold for outputting the supply voltage and the threshold for outputting the ground voltage are made different by a buffer circuit, so that the output of one voltage is stopped before the output of the other voltage begins, and both voltages are not output at the same time.

However, with an input signal that has abrupt voltage changes, such as a square wave, it is difficult to determine two different timings using the input signal itself. Therefore, there is a technique for determining different timings based on a delayed signal that adds a certain delay to the change in the input signal.

JP 2019-147247 A

However, it is difficult to determine an accurate voltage threshold with a simple configuration, and if a single threshold is off-center or multiple thresholds are not symmetrical, it is easy for asymmetry to occur in the switching timing between the rising edge and the falling edge of the input signal. As a result, there is an issue that the pulse width and pulse interval are not accurate values, and the waveform and timing of the drive signal are not accurate.

The object of this invention is to provide a drive circuit and a droplet ejection device that can output a more accurate drive signal.

In order to achieve the above object, the present invention provides:
a first delay circuit for causing a predetermined delay in an input signal representing a drive pulse waveform to be output;
a first switching control unit that outputs a first switching signal based on the input signal and an output signal of the first delay circuit;
a first level conversion circuit including a first switching element that switches between outputting and not outputting a first voltage in response to the first switching signal, and a second switching element that is connected to an output of the first switching element and switches between outputting and not outputting a second voltage, and that outputs a drive signal having the drive pulse waveform to a droplet ejection element by a combination of the first voltage and the second voltage;
A first signal generating unit having
The first delay circuit is a drive circuit characterized in having a first adjustment circuit that makes the magnitude of the delay different between the rising edge and the falling edge of the input signal.

The present invention provides a driving circuit according to claim 2,
the first signal generating section has a second switching control section that outputs a second switching signal based on the input signal and the output signal of the first delay circuit;
the second switching element switches between output and non-output of the second voltage in response to the second switching signal;
The first switching signal and the second switching signal are switched so as to include a period during which neither the first voltage nor the second voltage is output between a period during which the first voltage is output by the first switching element and a period during which the second voltage is output by the second switching element.

The present invention provides a driving circuit according to claim 3, comprising:
The first adjustment circuit is characterized in that the difference between the time from the start of the rising edge until the voltage of the output signal of the first delay circuit reaches a predetermined reference voltage related to the first switching control unit and the time from the start of the falling edge until the voltage of the output signal reaches the predetermined reference voltage is within 150 nsec.

The invention described in claim 4 is a drive circuit according to any one of claims 1 to 3,
the first delay circuit includes a first resistive element, a capacitor electrically connecting one end of the first resistive element to a ground plane, and a diode and a second resistive element that are connected in series and are positioned in parallel with the first resistive element;
The diode and the second resistor element are included in the first adjustment circuit.

The invention described in claim 5 is the drive circuit described in claim 4,
the reference voltage for the first switching control unit is smaller than the intermediate value of the voltage range of the input signal;
The diode has an anode located on the output side of the first delay circuit and a cathode connected to the input side of the first delay circuit.

The present invention as set forth in claim 6 provides a drive circuit as set forth in any one of claims 1 to 5,
a second delay circuit that generates a predetermined delay in an input signal representing a drive pulse waveform to be output;
a third switching control unit that outputs a third switching signal based on an output signal of the second delay circuit;
a second level conversion circuit including a third switching element that switches between outputting and not outputting a third voltage in response to the third switching signal, and a fourth switching element that is connected to an output of the third switching element and switches between outputting and not outputting a fourth voltage, and that outputs a drive signal having the drive pulse waveform to a droplet ejection element by a combination of the third voltage and the fourth voltage;
A second signal generating unit having
the second delay circuit has a second adjustment circuit that makes the magnitude of the delay different between the rising edge and the falling edge of the input signal;
the first signal generating section outputs a first drive signal to a first end of the droplet ejecting element in response to a first input signal;
the second signal generating section outputs a second drive signal corresponding to a second input signal to a second end of the droplet ejecting element opposite to the first end;
At least one of the first adjustment circuit and the second adjustment circuit is characterized in that it equalizes the magnitude of the delay at the falling edge of the first input signal and the magnitude of the delay at the rising edge of the second input signal, or equalizes the magnitude of the delay at the falling edge of the second input signal and the magnitude of the delay at the rising edge of the first input signal.

The invention described in claim 7 is a driving circuit according to any one of claims 1 to 6,
a third delay circuit that generates a predetermined delay in an input signal representing a drive pulse waveform to be output;
a fourth switching control unit that outputs a fourth switching signal based on an output signal of the third delay circuit;
a third level conversion circuit including a fifth switching element that switches between outputting and not outputting a fifth voltage in response to the fourth switching signal, and a sixth switching element that is connected to the output of the fifth switching element and switches between outputting and not outputting a sixth voltage, and that outputs a drive signal having the drive pulse waveform to a droplet ejection element by a combination of the fifth voltage and the sixth voltage;
a third signal generating unit having
the third delay circuit has a third adjustment circuit that makes the magnitude of the delay different between a rising edge and a falling edge of the input signal;
the first signal generating section outputs a first drive signal to a first end of the droplet ejecting element in response to a first input signal;
the third signal generating unit outputs a third drive signal in response to a third input signal to a second end of the droplet ejecting element opposite to the first end;
the third input signal includes a drive pulse waveform equal to that of the first input signal;
The third adjustment circuit is characterized in that it aligns the magnitude of the delay associated with the rising edge of the first drive signal with the magnitude of the delay associated with the rising edge of the third drive signal, or aligns the magnitude of the delay associated with the falling edge of the first drive signal with the magnitude of the delay associated with the falling edge of the third drive signal.

The invention according to claim 8 is as follows:
A drive circuit according to any one of claims 1 to 7;
a droplet ejection element that is driven in response to the drive signal input from the drive circuit;
a nozzle for ejecting droplets in response to the operation of the droplet ejection element;
The droplet ejection device is characterized by comprising:

The present invention has the advantage of making it possible to output more accurate drive signals to droplet ejection elements.

FIG. 2 is a block diagram showing a functional configuration of the droplet ejection device. FIG. 2 is a diagram showing a circuit configuration from a drive circuit to an actuator of the droplet ejection device of the present embodiment. 4A to 4C are diagrams illustrating an input signal to a signal generating unit, an output drive signal, and voltage changes within the signal generating unit. FIG. 13 is a diagram illustrating a drive circuit according to a first modified example. 13 is a diagram showing a voltage change in a drive circuit of the first modified example and a change in the voltage applied to an actuator. FIG. FIG. 13 is a diagram showing a drive circuit according to a second modified example. FIG. 13 is a diagram showing a drive circuit of a modified example 3. 13 is a diagram showing an example of a correspondence relationship between an input signal in a drive circuit of Modification 3, a drive signal to be output, and a voltage applied to an actuator. FIG.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing the functional configuration of a droplet ejection device 1. As shown in FIG.

The droplet ejection device 1 of this embodiment is, for example, an inkjet recording device that ejects ink. The droplet ejection device 1 includes a transport unit 51, a head drive control unit 52, a droplet ejection head 53, a control unit 61, a memory unit 62, a communication unit 7, a display unit 8, an operation reception unit 9, and the like.

The transport unit 51 moves the medium, on which an image or the like is to be recorded by the droplet ejection device 1, relative to the ink ejection surface of the droplet ejection head 53 while facing the ink ejection surface. The transport unit 51 has a transport drive unit 511. The transport drive unit 511 has, for example, a roller around which an endless belt on which the medium is placed is stretched, and rotates the roller at a predetermined speed to move the endless belt and the medium on the belt in a circular motion at the predetermined speed.

The head drive control unit 52 outputs a drive voltage signal to obtain a drive signal that drives the actuator 200 of the droplet ejection head 53 at an appropriate timing according to each pixel data of the image to be recorded. The head drive control unit 52 may be formed collectively on a substrate or the like, or may be distributed and arranged in each part of the droplet ejection device 1. In addition, some or all of the components of the head drive control unit 52 may be possessed by the droplet ejection head 53. The head drive control unit 52 includes a head control unit 521 and a signal control unit 522.

The head control unit 521 includes a CPU and a memory unit, and controls the operation of the head drive control unit 52 depending on the presence or absence of image data to be recorded and the contents of the image data. The memory unit stores in advance data on the waveform patterns of drive signals for ejecting ink from the nozzles N and vibrating the ink surface (meniscus) in the nozzles N. The signal control unit 522 outputs waveform signals (input signals) obtained from the head control unit 521 to the head drive unit 531 at appropriate timing according to a clock signal (synchronization signal) not shown. Multiple types of waveform patterns of the drive signals may be stored and switched in a predetermined order and timing.

The droplet ejection head 53 ejects ink onto a medium to record or form an image. The droplet ejection head 53 includes a head drive unit 531 and a nozzle N.

The head driving unit 531 performs an operation of ejecting ink in accordance with the ink ejection timing from each nozzle N. The head driving unit 531 has a driving circuit 100, an actuator 200 (droplet ejection element), etc. The actuator 200 deforms in response to an applied voltage. The driving circuit 100 has a signal generating unit 101 (first signal generating unit).
The drive circuit 100 generates a drive signal by combining input signals input from the signal control unit 522 at appropriate timing based on image data to be recorded, and switches between output and non-output of the drive signal to each actuator 200. When a drive signal is output to the actuator 200, the actuator 200 deforms, and a pressure fluctuation is applied to the ink in the nozzle N, causing the ink to be ejected from the nozzle N or vibrations to occur in the nozzle N.

Each nozzle N ejects ink in accordance with pressure fluctuations applied in response to the deformation of the actuator 200. The openings of the nozzles N are arranged in a predetermined pattern on one surface (nozzle surface) facing the medium (medium transport surface). The arrangement pattern is not particularly limited, but for example, an arrangement of multiple nozzle openings arranged at intervals according to the image resolution in a direction perpendicular to the direction in which the medium is transported by the transport unit 51 is provided at one or several locations in the transport direction. Alternatively, it may be a two-dimensional head in which the nozzle openings are distributed at multiple positions in the transport direction as well.

The droplet ejection device 1 is, for example, a one-pass type using a line head in which ink is ejected from a fixed droplet ejection head 53 onto a medium being transported and moved to record an image, but is not particularly limited as long as the droplet ejection head 53 and the medium move relatively at a constant speed during the ink ejection operation. When the openings of the nozzles N are arranged two-dimensionally, the ink ejection timing from nozzles N at different positions in the relative movement direction is controlled so that they are each shifted according to the relative movement speed.

The control unit 61 includes a CPU 611 that performs calculations, a RAM 612 that provides working memory space for the CPU 611 and stores temporary data, and generally controls the operation of the droplet ejection device 1.

The storage unit 62 stores programs and setting data related to operation control. The storage unit 62 has a non-volatile memory and/or a hard disk drive (HDD). The storage unit 62 may also be capable of storing image data 621 to be recorded and its processing data acquired from the outside via the communication unit 7. To store this data, the storage unit 62 may have a volatile memory such as a DRAM.

The communication unit 7 controls communication with external devices to send and receive data. The communication unit 7 includes, for example, a network card, and controls data communication based on communication standards such as TCP/IP using a LAN. The connected external devices include various computer terminals that output image recording commands and data to be recorded. In addition, as described below, the detection results from a detector that detects the ink flight speed may be obtained directly or via a computer terminal, etc.

The display unit 8 causes various displays to be made on the display screen based on the control of the control unit 61. An example of the display screen is a liquid crystal display. The display screen includes, for example, a display of the status related to the image recording operation and a display of a setting selection screen. The display unit 8 may also include an LED lamp or the like, and may be capable of notifying, for example, the presence or absence of power supply from the main power source and/or the presence or absence of an abnormal status.

The operation reception unit 9 receives an external input operation by a user or the like, and outputs the input operation to the control unit 61 as an input signal. An example of the operation reception unit 9 is a touch panel superimposed on the display screen. The operation reception unit 9 may also include a push button switch and/or a rotary switch.

Next, a drive circuit for the droplet ejection device 1 of this embodiment will be described.
FIG. 2 is a diagram showing a circuit configuration from the drive circuit 100 to the actuator 200 of the droplet ejection device 1 of this embodiment.

The signal generating unit 101 generates and outputs a drive signal Sm according to an input signal Sin. The drive circuit 100 has a delay circuit 10 (first delay circuit), logic circuits 21 and 22 (first and second switching control units, respectively), a level conversion circuit 30 (first level conversion circuit), and an ejection selection unit 40. The ejection selection unit 40 switches between output and non-output of the drive signal Sm, and when output, the drive signal Sm is output to one end (first end) of the actuator 200. The second end of the actuator 200 opposite the first end is grounded (grounded to the housing).

Note that, although one signal generating unit 101 is shown for one actuator 200 here, the signal generating unit 101 may output the drive signal Sm to multiple (e.g., two) actuators 200 via individual ejection selection units 40. Also, there may be multiple signal generating units 101 corresponding to groups of multiple actuators 200, each group having a different ink ejection timing, and the input signal Sin may be distributed and input to each of the multiple signal generating units 101. The amplitude of the input signal Sin may be a voltage that is expressed by a normal digital signal, for example, about 3 V, which is smaller than the supply voltage Vc described below.

The delay circuit 10 outputs, in parallel, an input signal Sin and a delayed signal Sd that is a predetermined delay from the input signal Sin. The delay circuit 10 includes, for example, an RC circuit having a resistive element R1 (first resistive element) and a capacitor C1 that electrically connects one end of the resistive element R1 to the ground surface. As is well known, an RC circuit is a low-pass filter that removes high-frequency components from the input signal Sin, resulting in a waveform with gentler rising and falling edges than a square wave. The time constant τ is expressed as τ = RC, where R is the resistance value of the resistive element R1 and C is the capacitance of the capacitor C1.

The delay circuit 10 further includes an adjustment circuit 11 (first adjustment circuit). The adjustment circuit 11 includes a resistance element R2 (second resistance element) that is parallel to the resistance element R1, and a diode D1 that is connected to the resistance element R2 (connected in series to the resistance element R2). Here, the anode of the diode D1 is located on the output side of the delay circuit 10, and the cathode is located on the input side. As a result, the resistance element R2 functions only in the direction in which current flows through the diode D1 (from the anode to the cathode), and the resistance value related to the time constant decreases to the combined resistance of the resistance value of the resistance element R1 and the resistance value of the resistance element R2. In other words, when the current flows to the input side of the input signal Sin, the time constant τ decreases and the magnitude of the delay of the delay signal Sd decreases. In other words, the magnitude of the delay of the delay signal Sd differs depending on the direction of signal change, that is, the rising edge and the falling edge when the input signal Sin is a pulse signal.

The input signal Sin and the delayed signal Sd output from the delay circuit 10 are each divided into two and input to logic circuits 21 and 22, respectively. Here, the logic circuit 21 is a NAND element, and outputs a switching signal Sc1 (first switching signal) obtained by inverting the logical product of the input signal Sin and the delayed signal Sd to the level conversion circuit 30. The logic circuit 22 is a NOR element, and outputs a switching signal Sc2 (second switching signal) obtained by inverting the logical sum of the input signal Sin and the delayed signal Sd to the level conversion circuit 30.

The level conversion circuit 30 has a pnp transistor Tr1 (first switching element) and an npn transistor Tr2 (second switching element). The above-mentioned switching signal Sc1 is input to the base of the pnp transistor Tr1, and the emitter is connected to the supply voltage Vc. The collector (output) is connected to the collector of the npn transistor Tr2. The above-mentioned switching signal Sc2 is input to the base of the npn transistor Tr2, and the emitter is grounded. A drive signal Sm is output from between the collectors of the pnp transistor Tr1 and the npn transistor Tr2. The switching signal Sc1 switches between the output and non-output of the supply voltage Vc (first voltage), and the switching signal Sc2 switches between the output and non-output of the ground voltage (second voltage). The level conversion circuit 30 has a push-pull configuration in which the switching signals Sc1 and Sc2 exclusively turn on the pnp transistor Tr1 and the npn transistor Tr2, so that the drive signal Sm switches between the supply voltage Vc and the ground voltage. A drive signal Sm having a drive pulse waveform is output to the actuator 200 via the ejection selection unit 40 by combining the supply voltage Vc and the ground voltage. The supply voltage Vc is a voltage required to drive the actuator 200, and is, for example, 15 V. That is, the input signal Sin is converted into the drive signal Sm by amplifying the voltage amplitude. In addition, the current supplied from the supply voltage Vc is also amplified, so that the drive signal Sm becomes the input signal Sin that has been power-amplified.

The ejection selection unit 40 switches whether or not to operate the actuator 200. The ejection selection unit 40 is switched on and off based on the image data to be output, etc.

The actuator 200 deforms in response to a voltage applied to both ends. As described above, one end of the actuator 200 is grounded, so that the actuator 200 deforms while the supply voltage Vc is being output, and the deformation of the actuator 200 is eliminated when the ground voltage is being output and the output of the drive signal Sm is turned off by the ejection selection unit 40. The actuator 200 is located along an ink flow path that communicates with a nozzle, and applies a pressure fluctuation corresponding to the deformation to the ink in the ink flow path, thereby ejecting the ink from the nozzle.
The pnp transistor Tr1 and npn transistor Tr2 of the level conversion circuit 30 which performs the switching operation, and the ejection selection section 40 may be formed together on a substrate as a drive IC.

Next, the output of the drive signal by the drive circuit of this embodiment will be described.
A signal generating unit 101 of the drive circuit 100 outputs a drive signal Sm obtained by power amplifying a predetermined waveform, here a rectangular input signal Sin (rectangular wave). The voltage amplitude of the drive signal Sm is determined by the difference between a supply voltage Vc and a ground voltage, i.e., the supply voltage Vc.

FIG. 3 is a diagram showing an input signal Sin to the signal generating unit 101, an output drive signal Sm, and voltage changes within the signal generating unit 101. As shown in FIG.
Here, the input signal Sin is a square wave, and changes (voltage width) between the lower end voltage (low level) and the upper end voltage (high level). The part where the voltage changes suddenly from the reference voltage (ground voltage) is called the rising edge, and the part where the voltage after the change is maintained and then suddenly returns to the reference voltage is called the falling edge. In other words, it does not matter whether the reference voltage is larger or smaller than the voltage after the change.

The change in voltage V(Sd) of the delayed signal Sd, which is the input signal Sin from which high-frequency components have been removed by the delay circuit 10, according to the elapsed time t can be expressed using an exponential function as V(Sd) = (α/RC)(1-exp(-t/τ)) (α is the amplitude), so the rising edge is upwardly convex and the falling edge is downwardly convex. Also, the larger the time constant τ, the slower the rising and falling edges become.

Here, the reference voltage Vth related to the output change of the logic circuits 21 and 22 is smaller than the intermediate value within the voltage range of the input signal Sin (lower end voltage < reference voltage Vth < (upper end voltage + lower end voltage) / 2). When the supply voltage Vc is positive, as described above, when the voltage falls, a current flows through the adjustment circuit 11, and the resistance value R included in the time constant τ becomes the combined resistance of the resistance elements R1 and R2 and becomes smaller than when the voltage rises. Therefore, the fall of the delay signal Sd becomes faster than the rise, and the time from the fall start timing te to the reference voltage Vth of the logic circuits 21 and 22 becomes shorter than in the case where the adjustment circuit 11 is not present. The resistance value of the resistance element R2 of the adjustment circuit 11 is set so that the time from the rise start timing tb to the timing tb1 at which the voltage rises to the reference voltage Vth and the time from the fall start timing te to the timing te2 at which the voltage falls to the reference voltage Vth are approximately the same time dt1. The "approximately the same" range here is, for example, a time difference of 150 nsec, but this may be determined according to the pulse width of the drive signal Sm (input signal Sin). In other words, the resistance value of the resistive element R2 may be determined so that the ratio of the deviation amount to the pulse width falls within the standard range of approximately the same. Also, adjustments may be made within a meaningful range depending on the response speed of the pnp transistor Tr1 and the npn transistor Tr2, the transition characteristics of the operation with respect to the base voltage, and the like.

As shown by the dashed line, in the absence of the adjustment circuit 11, the voltage change at the falling edge of the delayed signal Sd is a nonlinear change represented by the same time constant as the voltage change at the rising edge, and here, the time dt2 from the timing te at which the falling edge starts to the timing te1 at which the voltage drops to the reference voltage Vth is longer than the time dt1.

Since the logic circuit 21 is a NAND element, the switching signal Sc1 output from the logic circuit 21 is at low level when both the input signal Sin and the delayed signal Sd are equal to or higher than the reference voltage Vth, and is at high level (a voltage higher than low level) when either is lower than the reference voltage Vth. Therefore, the switching signal Sc1 changes from high level to low level at timing tb1 when the delayed signal Sd also becomes equal to or higher than the reference voltage Vth after a time dt1 has elapsed from timing tb when the input signal Sin starts to rise. Also, at the time of falling, the switching signal Sc1 immediately changes from low level to high level at timing te when the input signal Sin starts to fall. The pnp transistor Tr1 outputs the supply voltage Vc from the collector while the switching signal Sc1 is at low level (first voltage output period).

Since the logic circuit 22 is a NOR element, the switching signal Sc2 output by the logic circuit 22 is at high level when both the input signal Sin and the delayed signal Sd are less than the reference voltage Vth, and is at low level when at least one of them is equal to or greater than the reference voltage Vth. Therefore, the signal changes from high level to low level at the timing tb when the input signal Sin starts to rise, and changes from low level to high level when the delayed signal Sd falls below the reference voltage Vth at timing te2, which is delayed by a time dt from the timing te when the input signal Sin starts to fall. The npn transistor Tr2 outputs the ground voltage from the collector while the switching signal Sc2 is at high level (the output period of the second voltage).

The period when the switching signal Sc1 is at a low level (timing tb1 to timing te when the fall begins) does not overlap with the period when the switching signal Sc2 is at a high level (before timing tb when the rise begins and after timing te2), and the above-mentioned time dt1 is sandwiched before and after. Therefore, the pnp transistor Tr1 and the npn transistor Tr2 are not turned on at the same time (exclusive switching), and no through current flows from the supply voltage Vc to the ground surface. During time dt1, neither the supply voltage Vc nor the ground voltage is output, and the previous voltage is maintained for a short period of time, so the change in voltage in the drive signal Sm is the drop to the ground voltage at timing tb1, and the rise to the supply voltage Vc at timing te2. In other words, the drive signal Sm is always output with a delay of time dt1 from the switching of the input signal Sin, with the same pulse width as the input signal Sin. Therefore, the ejection volume and ejection speed of the droplets are accurately maintained. The ejection timing is delayed by time dt1, so the position of the medium on which the droplets land can be adjusted if necessary.

[Modification 1]
In the above embodiment, the adjustment of the drive signal Sm applied to the same side of the actuator 200 has been described as an example, but the contents of the present disclosure may also be used to adjust the timing of the drive signals Smp, Smn applied to different sides of the actuator 200.

FIG. 4 is a diagram illustrating a drive circuit 100a according to the first modification.
The driving circuit 100a has a signal generating unit 101 (in each of the following modified examples, referred to as the "first signal generating unit (signal generating unit 101)") connected to one end (first end) of the actuator 200 via an ejection selection unit 40, and a second signal generating unit 1012 connected to the end (second end) of the actuator 200 opposite the first end via an ejection selection unit 40a.

The first signal generating unit (signal generating unit 101) outputs a drive signal Smn (first drive signal) in response to an input signal Sin1 (first input signal representing a drive pulse waveform) and its delay signal Sd1, and the second signal generating unit 1012 outputs a drive signal Smp (second drive signal) in response to an input signal Sin2 (second input signal) and its delay signal Sd2. The supply voltages Vc1 and Vc2 (third voltages) related to the amplitudes of the drive signals Smn and Smp may be different from each other.

The circuit configuration of the first signal generating unit (signal generating unit 101) is the same as that of the signal generating unit 101 in the above embodiment, and the same reference symbols are used to denote each component, and detailed explanations are omitted. The second signal generating unit 1012 has an adjustment circuit 11a (second adjustment circuit) having the same configuration as the adjustment circuit 11, a delay circuit 10a (second delay circuit) having the same configuration as the delay circuit 10, a logic circuit 21a (third switching control unit) and a logic circuit 22a having the same configuration as the logic circuits 21 and 22, respectively, a pnp transistor Tr1a (third switching element) that switches the output of the supply voltage Vc2 and an npn transistor Tr2a (fourth switching element) that switches the output of the ground voltage (fourth voltage), and a level conversion circuit 30a (second level conversion circuit) having the same configuration as the level conversion circuit 30 that outputs a drive signal Smp to the actuator 200 according to the switching signal Sc3 output by the logic circuit 21a and the switching signal Sc4 output by the logic circuit 22a. That is, the circuit configuration of the second signal generating unit 1012 is the same as that of the first signal generating unit (signal generating unit 101).

For example, when the actuator 200 is deformed in shear mode, a drive signal may be output to both ends of the actuator 200 in this manner. In this case, for example, among the multiple actuators 200 belonging to each ejection selection unit 40, a common drive signal may be output to a first end of one of two adjacent actuators 200 and a second end of the other actuator 200 by one circuit (such as a first signal generation unit (signal generation unit 101)). The actuators 200 may be divided into three groups in the order in which they are lined up, and each group may be set to eject ink at a different ejection cycle.

In the drive circuit 100a of this modified example 1, the delay magnitudes associated with the rising and falling edges of the input signal Sin2 are adjusted by the adjustment circuit 11a to be different from each other, so that the rising timing of the drive signal Smn and the falling timing of the drive signal Smp, and/or the falling timing of the drive signal Smn and the rising timing of the drive signal Smp (i.e., the delay magnitudes) are aligned. The range of alignment here can be, for example, 200 nsec or less. Alternatively, as above, depending on the pulse width of the drive signal, a predetermined ratio or the like may be determined so that the shorter the pulse width, the smaller the deviation range is aligned. Also, adjustments may be made within a meaningful range depending on the response speed of the pnp transistors Tr1, Tr1a and the npn transistors Tr2, Tr2a, etc., the transition characteristics of the operation relative to the base voltage, etc.

Figure 5 shows the voltage change in the drive circuit 100a of variant 1 and the change in the voltage applied to the actuator 200.

The drive pulse (not the reference voltage portion) of the input signal Sin1 to the first signal generating unit (signal generating unit 101) and the drive pulse of the input signal Sin2 to the second signal generating unit 1012 are in a timing that is not interchangeable, and the input signal Sin1 rises at the same time as the input signal Sin2 falls. When aligning the fall timing of the drive signal Smp corresponding to the input signal Sin2 and the rise timing of the drive signal Smn corresponding to the input signal Sin1, it is effective to make the time constant τ of the delay signal at the fall different from the time constant τ at the rise, as in the above embodiment.

The rising delay of the delayed signal Sd1, which is obtained by delaying the input signal Sin1 by the delay circuit 10, and the rising delay of the delayed signal Sd2, which is obtained by delaying the input signal Sin2 by the delay circuit 10, are both time dt1. As a result, the drive signals Smp and Smn become pulse signals of the same width, which are the input signals Sin1 and Sin2 delayed by time dt1, respectively. Therefore, by also setting the falling delay of the delayed signal Sd2 to time dt1, the rising of the drive signal Smn corresponding to the input signal Sin1 is determined to be simultaneous with the falling of the drive signal Smp corresponding to the input signal Sin2.

Since the drive signals Smn and Smp are input to opposite sides of the actuator 200, the drive signals Smn and Smp are applied voltages of opposite polarity to the actuator 200. In other words, voltages of opposite polarity are continuously applied to the actuator 200 by the drive signals Smn and Smp. In the first and subsequent variants, a positive applied voltage is indicated when the voltage at the second end is higher than the voltage at the first end.

[Modification 2]
When the first signal generating unit (signal generating unit 101) connected to the first end suppresses the through current using such a delay circuit 10, even if there is no need to suppress the through current on the second end side, the timing of the rise and fall of the drive signal can be aligned by generating a drive signal using a circuit that similarly has a delay circuit.

Figure 6 is a diagram showing a drive circuit 100b of modified example 2. The second signal generating unit 1012b differs from the second signal generating unit 1012 in modified example 1 in that only the delay signal Sd2 output by the delay circuit 10a is input to the logic circuit 23. The switching signal Sc3a (third switching signal) output by the logic circuit 23 is split into two and input to the pnp transistor Tr1a and the npn transistor Tr2a, respectively. Since the other configurations are the same, the same reference numerals are used and detailed explanations are omitted.

The logic circuit 23 is a NOT element and inverts the delay signal Sd2. By simply dividing the switching signal Sc3a output by the logic circuit 23 into two, the output inversion of the pnp transistor Tr1a, i.e., the timing at which the output of the supply voltage Vc2 is switched, and the output inversion of the npn transistor Tr2a, i.e., the timing at which the output of the ground voltage is switched, become the same. Therefore, there is no time dt between the two. In this circuit, in the transition state in which the output of the level conversion circuit 30a is switched, a small amount of through current flows from the supply voltage Vc2 to the ground surface. For example, when the magnitude (absolute value) of the supply voltage Vc2 is smaller than the magnitude of the supply voltage Vc1, or when the output frequency of the supply voltage Vc2 is smaller than the output frequency of the supply voltage Vc1, the drive circuit 100b may have such a circuit configuration.

In such a case, if the input signal Sin2 is simply input to the logic circuit 23 as is, the timing will be shifted between the drive signals Smn and Smp by the delay of the drive signal Smn relative to the input signal Sin1 in the first signal generating unit (signal generating unit 101). Therefore, even in this case, the second signal generating unit 1012b may have a delay circuit 10a including an adjustment circuit 11a.

[Modification 3]
In the above, the voltage of the drive signal is constant at a fixed supply voltage Vc, but it may be selectively output from a plurality of supply voltages. In addition, when the drive signal is not output, it is not necessary to simply not output the drive signal, but it is also possible to apply the same voltage to both ends. In such a case, it is sufficient to have a plurality of signal generating units that output a plurality of mutually different supply voltages to the same end of the actuator 200, and selectively switch between these outputs.

FIG. 7 is a diagram showing a drive circuit 100c according to the third modification.
This drive circuit 100c includes a first signal generating unit (signal generating unit 101c), a second signal generating unit 1012c, and a third signal generating unit 1013. The second signal generating unit 1012c and the third signal generating unit 1013 are each connected to the same side (second end) of the actuator 200, and the first signal generating unit (signal generating unit 101c) is connected to the opposite side (first end) of the actuator 200.

The first signal generating unit (signal generating unit 101c) outputs a drive signal Smn corresponding to the input signal Sin1, the second signal generating unit 1012c outputs a drive signal Smp1 corresponding to the input signal Sin2, and the third signal generating unit 1013 outputs a drive signal Smp2 (third drive signal) based on the delay signal Sd3 in response to the input signal Sin3 (third input signal). Here, the supply voltage (fifth voltage) related to the amplitude of the drive signal Smp2 of the third signal generating unit 1013 is the same as the supply voltage Vc1 of the first signal generating unit (signal generating unit 101c). The first signal generating unit (signal generating unit 101c) is the first signal generating unit (signal generating unit 101c) of the above embodiment with the ejection selection unit 40 removed. The second signal generating unit 1012c differs from the second signal generating unit 1012b shown in the above modified example 2 in that the ejection selection unit 40b is located at a different position from the ejection selection unit 40a. Since the other configurations are the same, the same components are given the same reference numerals and detailed explanations are omitted.
The third signal generating unit 1013 has an adjustment circuit 11c (third adjustment circuit) that is the same as the adjustment circuit 11, and includes a delay circuit 10c (third delay circuit) that has the same configuration as the delay circuit 10 and outputs a delay signal Sd3 in response to an input signal Sin3, a logic circuit 23c (fourth switching control unit) that is the same as the logic circuit 23 and outputs a switching signal Sc5 (fourth switching signal) in response to an input of the delay signal Sd3 (output signal of the third delay circuit), and a level conversion circuit 30c (third level conversion circuit) that has the same configuration as the level conversion circuit 30 and receives the switching signal Sc5 as an input to a pnp transistor Tr1c (fifth switching element) that switches whether or not to output a supply voltage Vc1 and an npn transistor Tr2c (sixth switching element) that switches whether or not to output a ground voltage (sixth voltage), and outputs a drive signal Smp2. That is, the third signal generating unit 1013 differs from the second signal generating unit 1012b of the modified example 2 in that the ejection selection unit 40c is located at a position different from that of the ejection selection unit 40a. Since the other configurations are the same, detailed description will be omitted.

Here, the input signal Sin3 is the same as the input signal Sin1. The input signal Sin1 may be divided and one of them may be input as the input signal Sin3. The delay circuit 10c of the third signal generating unit 1013 is set to the same delay as the delay circuit 10a of the first signal generating unit (signal generating unit 101c), and the supply voltage Vc1 is also the same. The drive signal Smp2 output from the third signal generating unit 1013 is equal to the drive signal Smn, and is a rectangular pulse whose amplitude delayed by time dt1 with respect to the input signal Sin3 (input signal Sin1) is the supply voltage Vc1. That is, the rising edge of the drive signal Smp2 is at the same timing as the rising edge of the drive signal Smn. The same range here can be, for example, 200 nsec or less, as described in the above modified example 1. Alternatively, it may be determined by a predetermined ratio or the like according to the pulse width of the drive signal so that the shorter the pulse width, the smaller the deviation range. Furthermore, adjustments may be made within a meaningful range depending on the response speed of pnp transistors Tr1, Tr1a, Tr1c and npn transistors Tr2, Tr2a, Tr2c, etc., and the transition characteristics of operation with respect to the base voltage.

Either of the ejection selection units 40b, 40c may be selectively turned on to output the drive signal Smp1 or drive signal Smp2, or both may be turned off. The drive signal output from either the second signal generation unit 1012c or the third signal generation unit 1013, which includes the ejection selection unit 40b, 40c that is turned on, is input to the second end of the actuator 200.

Figure 8 shows an example of the correspondence between the input signals Sin1 to Sin3 in the drive circuit 100c of variant 3 and the output drive signals Smn, Smp1, and Smp2, and the voltage applied to the actuator 200.

As described above, the first signal generating unit (signal generating unit 101c) does not have an ejection selection unit, so a drive signal Smn with an amplitude according to the supply voltage Vc1 is output each time with a delay of time dt1 from the input signal Sin.

When droplets are to be ejected, the ejection selection unit 40b of the second signal generation unit 1012c is turned on, and the ejection selection unit 40c of the third signal generation unit 1013 is turned off. A drive signal Smp1 having an amplitude corresponding to the supply voltage Vc2 is output with a delay of time dt1 from the rising edge of the input signal Sin2 input to the second signal generation unit 1012c at timing tp, and continues until timing tb1. At timing tb1, the drive signal Smn, which is delayed by time dt from the input signal Sin1, rises in its place, so that the positive and negative of the applied voltage are reversed. At this time, the drive signal Smp2 corresponding to the input signal Sin3 is not output in response to the ejection selection unit 40c.

When droplets are not to be ejected, the ejection selection unit 40b of the second signal generation unit 1012c is turned off and the ejection selection unit 40c of the third signal generation unit 1013 is turned on. The input signal Sin2 is input to the second signal generation unit 1012c at timing tp3, but the drive signal Smp1 is not output at timing tp4 delayed by time dt1. In response to the input signals Sin1 and Sin3 input to the first signal generation unit (signal generation unit 101c) and the third signal generation unit 1013, respectively, between timing tb3 and timing tb4, the drive signals Smn and Smp2 are output between timing tb4 and timing te4 delayed by time dt1. The drive signals Smn and Smp2 are applied to both ends of the actuator 200 with the same voltage and the same waveform, so that no voltage difference occurs between both ends of the actuator 200 and the applied voltage remains zero. In response to this, the actuator 200 does not deform. Note that the voltage supplied to the third signal generating unit 1013 may be different from the voltage Vc1 supplied to the first signal generating unit (signal generating unit 101c). In this case, a voltage corresponding to the difference in the supply voltages is applied to the actuator 200.

In this way, the rising edges of the drive signals Smn and Smp2 are properly aligned with respect to the falling edge of the drive signal Smp1. The rising and falling edges of the drive signals Smn and Smp2 are also properly aligned, and their pulse widths can also be matched.
As in the first modification, either or both of the second signal generating unit 1012c and the third signal generating unit 1013 may have a combination of a NAND element and a NOR element as the logic circuit 23 instead of a NOT element.

The resistance value of the resistor element R2 in the adjustment circuit 11 as described above is roughly determined by design, but may be adjustable during pre-shipment inspection of the drive circuit 100 (droplet ejection device 1).

As described above, the drive circuit 100 of the droplet ejection device 1 of this embodiment includes a delay circuit 10 that generates a predetermined delay in the input signal Sin that represents the drive pulse waveform (rectangular wave) to be output, a logic circuit 21 that outputs a switching signal Sc1 based on the input signal Sin and the output signal of the delay circuit 10, a pnp transistor Tr1 that switches between outputting and not outputting the supply voltage Vc in response to the switching signal Sc1, and an npn transistor Tr2 that is connected to the output of the pnp transistor Tr1 and switches between outputting and not outputting the ground voltage, and a signal generating unit 101 that outputs a drive signal Sm having the above drive pulse waveform to the actuator 200 by combining the supply voltage Vc and the ground voltage. The delay circuit 10 includes an adjustment circuit 11 that changes the magnitude of delay between the rising edge and the falling edge of the input signal Sin.
In this way, when the operation of the level conversion circuit 30 is controlled using the delay circuit 10 for timing control, the magnitude of the delay in the delay circuit may differ depending on the reference voltage Vth of the logic circuits 21, 22, etc. Therefore, the time it takes for the voltage before the change to reach the reference voltage Vth differs between the rising edge and the falling edge of the signal, which may cause deviations from the expected pulse width and timing of the output drive signal. Therefore, by configuring the delay circuit 10 to have an adjustment circuit 11 and to be able to make the magnitude of the delay different between the rising edge and the falling edge, it is possible to adjust the above-mentioned arrival times to be equal. This makes it possible to output a drive signal more accurate than before and eject droplets with more appropriate liquid volume, timing, and flight speed.

The signal generating unit 101 also has a logic circuit 22 that outputs a switching signal Sc2 based on the input signal Sin and a delay signal Sd output by the delay circuit 10. The npn transistor Tr2 switches between outputting and not outputting a ground voltage in response to the switching signal Sc2. The switching signals Sc1 and Sc2 are switched so as to include a period (time dt1) during which neither the supply voltage Vc nor the ground voltage is output between the period during which the pnp transistor Tr1 outputs the supply voltage Vc and the period during which the npn transistor Tr2 outputs the ground voltage.
In this way, the delay signal Sd may be used to generate a period (dead time) during which neither the first voltage (supply voltage Vc) nor the second voltage (ground voltage) is output. By providing this dead time, in a transition state in which the drive voltage is switched between the supply voltage Vc and the ground voltage, the power source of the supply voltage Vc and the ground plane of the ground voltage are directly connected, and it is possible to prevent a through current from flowing and increasing power consumption. In such a case, by making it possible to adjust the magnitude of the delay between the rising edge and the falling edge to be different from each other as described above, it is possible to output a more accurate drive signal.

In addition, the adjustment circuit 11 sets the difference between the time from the start of the rising edge of the input signal Sin until the voltage of the delayed signal Sd output by the delay circuit 10 reaches a predetermined reference voltage Vth related to the logic circuit 21, and the time from the start of the falling edge of the input signal Sin until the voltage of the delayed signal Sd reaches the reference voltage Vth, to within 150 nsec.
This improves the droplet ejection performance of the droplet ejection device 1 currently in use, making it possible to cause droplets to land on a medium with greater accuracy.

The delay circuit 10 also includes a resistor R1, a capacitor C1 that electrically connects one end of the resistor R1 to the ground plane, and a diode D1 and a resistor R2 that are connected in series and are positioned in parallel with the resistor R1. Of these, the diode D1 and the resistor R2 are included in the adjustment circuit 11.
In this way, when a delay is generated in the RC circuit, the time constant of the RC circuit can be easily made different for the rising and falling edges by adding a resistor element R2 through which a current flows only at the rising and falling edges by means of a diode D1. With such a simple configuration, it is possible to more accurately output the drive signal and eject droplets with greater precision without substantially increasing the cost, effort, or size of the drive circuit 100.

The reference voltage Vth related to the logic circuit 21 is smaller than the intermediate value of the voltage range of the input voltage Vin, and the anode of the diode D1 is located on the output side of the delay circuit 10, and the cathode is connected to the input side of the delay circuit 10. In this way, when the reference voltage Vth is closer to the voltage of the input signal Sin before it rises, the reference voltage Vth is reached faster when the voltage rises than when the voltage falls, for the same delay (time constant τ). Therefore, by further reducing the time constant τ when the voltage falls, that is, when a current flows to the input side of the input signal Sin, the delays when the voltage rises (here, when it rises) and when the voltage falls (here, when it falls) can be made closer. This makes it possible to easily output a more accurate drive signal Sm.

The droplet ejection device 1 of the first and second modified examples includes a delay circuit 10a that generates a predetermined delay in an input signal that represents a drive pulse waveform to be output, a logic circuit 21a that outputs a switching signal Sc3 or a logic circuit 23 that outputs a switching signal Sc3a based on the delay signal Sd2 output by the delay circuit 10a, a pnp transistor Tr1a that switches between outputting and not outputting a supply voltage Vc2 in response to the switching signals Sc3 and Sc3a, and an npn transistor Tr2a that is connected to the output of the pnp transistor Tr1a and switches between outputting and not outputting a ground voltage, and a second signal generating unit 1012, 1012b that has a level conversion circuit 30a that outputs a drive signal Smp of a drive pulse waveform (rectangular wave) to the actuator 200 by a combination of the supply voltage Vc2 and the ground voltage. The delay circuit 10a includes an adjustment circuit 11a that changes the magnitude of delay between the rising edge and the falling edge of the input signal Sin2. The first signal generating unit (signal generating unit 101) outputs a drive signal Smn corresponding to the input signal Sin1 to a first end of the actuator 200, and the second signal generating units 1012, 1012b output a drive signal Smp corresponding to the input signal Sin2 to a second end opposite to the first end of the actuator 200. At least one of the adjustment circuit 11 and the adjustment circuit 11a equalizes the magnitude of the delay at the falling edge of the input signal Sin1 to the magnitude of the delay at the rising edge of the input signal Sin2, or equalizes the magnitude of the delay at the falling edge of the input signal Sin2 to the magnitude of the delay at the rising edge of the input signal Sin1.
In this way, when a signal generating circuit is connected to each end of the actuator 200 and a drive signal is input to each, not only can the timing and pulse width of each drive signal be adjusted, but also the timing of the rise of one drive signal and the fall of the other drive signal can be adjusted. Therefore, the drive circuits 100a and 100b can output drive signals more accurately, which makes it possible to land droplets on the medium in more appropriate positions and amounts.

The drive circuit 100c of the third modification includes a third signal generating unit 1013 having a delay circuit 10c that generates a predetermined delay in an input signal Sin3 that represents a drive pulse waveform (rectangular wave) to be output, a logic circuit 23c that outputs a switching signal Sc5 based on a delay signal Sd3 output by the delay circuit 10c, a pnp transistor Tr1c that switches between outputting and not outputting a supply voltage Vc1 in response to the switching signal Sc5, and an npn transistor Tr2c that is connected to the output of the pnp transistor Tr1c and switches between outputting and not outputting a ground voltage, and outputs a drive signal Smp2 of the drive pulse waveform to the actuator 200 by a combination of the supply voltage Vc1 and the ground voltage. The delay circuit 10c includes an adjustment circuit 11c that changes the magnitude of delay between the rising edge and the falling edge of the input signal Sin3. The first signal generating unit (signal generating unit 101c) outputs a drive signal Smn corresponding to the input signal Sin1 to a first end of the actuator 200, and the third signal generating unit 1013 outputs a drive signal Smp2 corresponding to the input signal Sin3 to a second end opposite to the first end of the actuator 200. The input signal Sin3 includes a drive pulse waveform (the amplitude may be different) equal to that of the input signal Sin1. The adjustment circuit 11c aligns the magnitude of the delay associated with the rise of the drive signal Smn with the magnitude of the delay associated with the rise of the drive signal Smp2, or aligns the magnitude of the delay associated with the fall of the drive signal Smn with the magnitude of the delay associated with the fall of the drive signal Smp2.
In this way, when drive signals Smn, Smp2 are input to both ends of the actuator 200, and the drive signals Smn, Smp2 are identical and cancel each other out to prevent the actuator 200 from operating, the adjustment circuit 11c is determined not only to align the delays of the rising and falling edges of the drive signals Smn, Smp2, but also to align the rising edges and/or falling edges of the drive signals Smn, Smp2. This suppresses the deviation between the drive signals Smn, Smp2 at both ends, and reduces the disturbance and ejection of ink in the nozzle N caused by the application of unnecessary voltage.

The droplet ejection device 1 of this embodiment also includes any one of the drive circuits 100, 100a to 100c described above, an actuator 200 that is driven in response to a drive signal input from the drive circuit 100, 100a to 100c, and a nozzle N that ejects droplets in response to the operation of the actuator 200. With this droplet ejection device 1, droplets can be ejected more precisely and at the appropriate amount and speed with a more accurate drive signal.

The present invention is not limited to the above-described embodiment, but may be modified in various ways.
For example, in the above embodiment, the reference voltage Vth of the logic circuits 21 to 23 is closer to the low-level input voltage than the intermediate value between the upper end voltage and the lower end voltage of the input signal Sin or the delayed signal Sd (smaller than the intermediate value), but this is not limited to this. Since the relationship between the time required from the start of the rising edge of the delayed signal to the reference voltage and the time required from the start of the falling edge to the reference voltage changes depending on the magnitude of this reference voltage Vth, it is sufficient to have an adjustment circuit that shortens the longer one. In addition, the reference voltage Vth may be different between the logic circuits 21 and 22 in the same drive circuit 100. Even in this case, the adjustment circuit 11 may be adjusted so that the delay amount (time constant) and pulse width are appropriate.

In addition, the adjustment circuit 11 is not limited to a circuit that reduces the larger delay, but may also increase the smaller delay.

In the above embodiment, the diode D1 is connected in series to the parallel resistor element R2, but the adjustment circuit is not limited to this form. For example, the adjustment circuit may have a bypass line that shorts out some of the resistor elements arranged in series, and a diode is located in the middle of the bypass line, so that the combined resistance changes depending on whether or not there is a short circuit.

In the above embodiment, the resistor element R1, through which current flows at both rising and falling edges, and the resistor element R2, through which current flows only at falling edges due to the diode D1, are described as being located in parallel, but this is not limited to this. A diode in the opposite direction to the diode D1 may be located in series with the first resistor element so that current flows only at rising edges. Alternatively, the resistor elements R1 and R2 may each have a diode in the opposite direction connected in series, and each resistor element R1, R2 may be distinguished as being dedicated to rising edges and falling edges, respectively.

In the above embodiment, the delay circuit 10 has been described as an RC circuit, but this is not limited to this. It may be another circuit, such as an LC circuit or an RLC circuit that has an inductor instead of/in addition to a resistive element.

In the above embodiment, the level conversion circuit 30 has been described as a push-pull type having a combination of bipolar transistors, but this is not limited to this. For example, it may have a combination of FETs, i.e., a combination of an N-channel FET and a P-channel FET. Also, instead of a simple push-pull type, each transistor may have a bootstrap structure or the like, and power amplification may be performed by a level conversion circuit having the same structure combination, such as an npn transistor and an npn transistor, or an N-channel FET and an N-channel FET.

In the above embodiment, the reference voltage Vth is the same when the input voltage to the logic circuits 21 and 22 rises and falls, but the reference voltage Vth may be different. Even in this case, it is sufficient that the adjustment circuit 11 is configured to operate so that the time required for the voltage to change from the start timing of the rise to the reference voltage Vth at the rise is approximately the same as the time required for the voltage to change from the start timing of the fall to the reference voltage Vth at the fall.

The switching control unit does not have to be logic circuits 21 to 23. It may be other elements or circuits.

In addition, in the above-mentioned modified examples 1 and 2, the rising edge of the drive signal Smn output from the first signal generating unit (signal generating unit 101) and the falling edge of the drive signal Smp output from the second signal generating unit 1012 are simultaneous. However, this is not limited to this. Even if these timings are different from each other, the drive circuits 100a and 100b may have the above circuit configuration in order to accurately determine the interval between the two timings.

In addition, in the above-mentioned modified example 3, the drive signal is selectively output from either the second signal generating unit 1012c or the third signal generating unit 1013 to the second end of the actuator 200, but the second signal generating unit 1012c does not have to be present. Conversely, a signal generating unit other than the first signal generating unit (signal generating unit 101c) may be connected to the first end, and the drive signal may be selectively output from either one to the first end of the actuator 200.

In addition, input signal Sin3 does not have to be completely identical to input signal Sin1. It may contain a portion that is identical to input signal Sin1.

In addition, in the above embodiment, the drive pulse waveform is described as being a square wave, but this is not limited to this, as long as the waveform has clear rising and falling edges that allow the delay circuit to function effectively.

In the above embodiment, the actuator 200 that converts an electrical signal into mechanical motion has been described as an example of a droplet ejection element, but this is not limited to this. The droplet ejection element may be configured to eject droplets by converting an electrical signal into heat and heating the liquid, or may be an element that generates mechanical motion (deformation) in response to a magnetic field generated by electromagnetic induction in response to an electrical signal.

Furthermore, the droplets to be ejected are not limited to ink, but may be various other liquids.
In addition, the specific configurations, contents and procedures of the processing operations, etc. shown in the above embodiments can be modified as appropriate without departing from the spirit of the present invention. The scope of the present invention includes the scope of the invention described in the claims and its equivalents.

1 Droplet ejection device 7 Communication section 8 Display section 9 Operation reception section 10, 10a, 10c Delay circuit 11, 11a, 11c Adjustment circuits 21 to 23, 21a, 22a, 23c Logic circuit 30, 30a, 30c Level conversion circuit 40, 40a to 40c Ejection selection section 51 Transport section 511 Transport drive section 52 Head drive control section 521 Head control section 522 Signal control section 53 Droplet ejection head 531 Head drive section 61 Control section 611 CPU
612 RAM
62 Storage unit 621 Image data 100, 100a to 100c Drive circuit 101, 101c Signal generation unit 1012, 1012b, 1012c Second signal generation unit 1013 Third signal generation unit 200 Actuator C1 Capacitor D1 Diode N Nozzle R1, R2 Resistance elements Sc1 to Sc5, Sc3a Switching signals Sd, Sd1 to Sd3 Delay signals Sin, Sin1 to Sin3 Input signals Sm, Smn, Smp, Smp1, Smp2 Drive signals Tr1, Tr1a, Tr1c pnp transistors Tr2, Tr2a, Tr2c npn transistors Vc, Vc1, Vc2, Vc3 Supply voltage Vin Input voltage Vth Reference voltage

Claims (8)

a first delay circuit for causing a predetermined delay in an input signal representing a drive pulse waveform to be output;
a first switching control unit that outputs a first switching signal based on the input signal and an output signal of the first delay circuit;
a first level conversion circuit including a first switching element that switches between outputting and not outputting a first voltage in response to the first switching signal, and a second switching element that is connected to an output of the first switching element and switches between outputting and not outputting a second voltage, and that outputs a drive signal having the drive pulse waveform to a droplet ejection element by a combination of the first voltage and the second voltage;
A first signal generating unit having
a first delay circuit for adjusting a delay time of the input signal between the rising edge and the falling edge of the input signal; the first signal generating section has a second switching control section that outputs a second switching signal based on the input signal and the output signal of the first delay circuit;
the second switching element switches between output and non-output of the second voltage in response to the second switching signal;
2. The drive circuit according to claim 1, wherein the first switching signal and the second switching signal are switched so as to include a period in which neither the first voltage nor the second voltage is output between a period in which the first switching element outputs the first voltage and a period in which the second switching element outputs the second voltage. The drive circuit according to claim 1 or 2, characterized in that the first adjustment circuit sets the difference between the time from the start of the rising edge until the voltage of the output signal of the first delay circuit reaches a predetermined reference voltage related to the first switching control unit and the time from the start of the falling edge until the voltage of the output signal reaches the predetermined reference voltage to within 150 nsec. the first delay circuit includes a first resistive element, a capacitor electrically connecting one end of the first resistive element to a ground plane, and a diode and a second resistive element that are connected in series and are positioned in parallel with the first resistive element;
4. The drive circuit according to claim 1, wherein the diode and the second resistance element are included in the first adjustment circuit. the reference voltage for the first switching control unit is smaller than the intermediate value of the voltage range of the input signal;
5. The drive circuit according to claim 4, wherein the diode has an anode located on the output side of the first delay circuit and a cathode connected to the input side of the first delay circuit. a second delay circuit that generates a predetermined delay in an input signal representing a drive pulse waveform to be output;
a third switching control unit that outputs a third switching signal based on an output signal of the second delay circuit;
a second level conversion circuit including a third switching element that switches between outputting and not outputting a third voltage in response to the third switching signal, and a fourth switching element that is connected to an output of the third switching element and switches between outputting and not outputting a fourth voltage, and that outputs a drive signal having the drive pulse waveform to a droplet ejection element by a combination of the third voltage and the fourth voltage;
A second signal generating unit having
the second delay circuit has a second adjustment circuit that makes the magnitude of the delay different between the rising edge and the falling edge of the input signal;
the first signal generating section outputs a first drive signal to a first end of the droplet ejecting element in response to a first input signal;
the second signal generating section outputs a second drive signal corresponding to a second input signal to a second end of the droplet ejecting element opposite to the first end;
The drive circuit according to any one of claims 1 to 5, characterized in that at least one of the first adjustment circuit and the second adjustment circuit equalizes a delay in the falling edge of the first input signal to a delay in the rising edge of the second input signal, or a delay in the falling edge of the second input signal to a delay in the rising edge of the first input signal. a third delay circuit that generates a predetermined delay in an input signal representing a drive pulse waveform to be output;
a fourth switching control unit that outputs a fourth switching signal based on an output signal of the third delay circuit;
a third level conversion circuit including a fifth switching element that switches between outputting and not outputting a fifth voltage in response to the fourth switching signal, and a sixth switching element that is connected to the output of the fifth switching element and switches between outputting and not outputting a sixth voltage, and that outputs a drive signal having the drive pulse waveform to a droplet ejection element by a combination of the fifth voltage and the sixth voltage;
a third signal generating unit having
the third delay circuit has a third adjustment circuit that makes the magnitude of the delay different between a rising edge and a falling edge of the input signal;
the first signal generating section outputs a first drive signal to a first end of the droplet ejecting element in response to a first input signal;
the third signal generating unit outputs a third drive signal in response to a third input signal to a second end of the droplet ejecting element opposite to the first end;
the third input signal includes a drive pulse waveform equal to that of the first input signal;
The drive circuit according to any one of claims 1 to 6, characterized in that the third adjustment circuit aligns a magnitude of delay associated with a rising edge of the first drive signal and a magnitude of delay associated with a rising edge of the third drive signal, or aligns a magnitude of delay associated with a falling edge of the first drive signal and a magnitude of delay associated with a falling edge of the third drive signal. A drive circuit according to any one of claims 1 to 7;
a droplet ejection element that is driven in response to the drive signal input from the drive circuit;
a nozzle for ejecting droplets in response to the operation of the droplet ejection element;
A droplet ejection device comprising:

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