JP7582033B2 - Synchronization Acquisition Circuit - Google Patents

Description

This disclosure relates to a synchronization acquisition circuit that detects the position where the spreading code is synchronized in a spread spectrum receiver that receives radio waves that transmit a spread spectrum signal spread with a cascade-connected series of spreading codes.

When a conventional spread spectrum receiver captures radio waves that transmit spread spectrum signals spread with a spreading code of a cascade connection sequence (CAT sequence), the correlation characteristics deteriorate if there is a frequency deviation. If there is no frequency deviation and the spreading code is synchronized, the received signal after despreading by correlation processing becomes a signal that has a constant value for each symbol. If there is a frequency deviation ΔF, the vector of the received signal after despreading during a period (one symbol time) that would be a constant value without frequency deviation becomes a waveform that rotates on a unit circle in the complex plane at exp(j2π ΔF t). When correlation is performed in the presence of a frequency deviation, if the vector of the received signal rotates 360 degrees during the period of one symbol, the amplitude of the complex correlation value, which is the sum of the received signals during the period of one symbol, is almost zero. Even if the rotation angle in one symbol is not 360 degrees, if it rotates by a large angle, the amplitude of the complex correlation value becomes smaller than the unit amount. In other words, if there is a frequency deviation, the correlation characteristics deteriorate in conventional spread spectrum receivers.

The following methods are available for detecting frequency deviation. A received baseband signal for one period of the spreading code is divided into a front part and a rear part, and a first correlation calculation signal is calculated by performing a correlation calculation between the front part of the received signal and the first half of the spreading code, and a second correlation calculation signal is calculated by performing a correlation calculation between the rear part of the received signal and the second half of the spreading code. A phase error vector is calculated by multiplying the complex conjugate of the first correlation calculation signal by the second correlation calculation signal. An error signal for frequency deviation correction is calculated by circularly integrating the phase error vector (see Patent Document 1).

JP 2006-261985 A

In the method described in Patent Document 1, when the frequency deviation is large, the phase difference between the first correlation calculation result and the second correlation calculation result may exceed 360 degrees, and the phase error may not be accurately determined.

The synchronization acquisition circuit disclosed herein is a spread spectrum receiver that receives a signal spread with a spreading code which is a pseudo-random number taking on two values and has a sequence length which is the product of the number of units, which is an integer of 3 or more, and an integer of 2 or more, and which changes every chip time, and determines a synchronization sequence position which is the position in the sequence length of the spreading code to be multiplied by the received signal at discrete points in time spaced apart by the chip time.
The synchronization acquisition circuit includes a despreading received signal calculation unit that calculates despreading received signals, which are complex numbers obtained by multiplying the total number of time points obtained by multiplying the excess coefficient included in consecutive chips of the number of sequence lengths by the sequence length, or the number of received signals of the number of sequence lengths selected to have chip time intervals, by each of the spreading codes determined according to the position in the sequence length of the chip to which each of the received signals belongs, for a received signal expressed as a complex number by an in-phase component and an orthogonal component having a phase difference of 90 degrees from the in-phase component, and one chip containing the number of excess coefficients, the number of times being the total number of time points or the number of despreadings being the sequence length; and a unit correlation value that is the sum of consecutive despreading received signals of the number of units obtained by dividing the number of despreadings by the number of units, the number of units ordered by the despreading received signals used for the calculation. a unit correlation value calculation unit, a correlation value accumulation unit which calculates a correlation value which is the sum of despread received signals of a number equal to or greater than a difference number obtained by subtracting the number of units from the number of despread pieces and equal to or less than the number of despread pieces, a differential phase value calculation unit which calculates a differential phase value which is a complex number having a phase difference between the unit correlation value and the previous unit correlation value, an operation control unit which controls whether to operate the differential phase value calculation unit, a differential correlation value calculation unit which calculates a differential correlation value which is the sum of the differential phase values, a power calculation unit which calculates the power of the differential correlation value when the differential phase value calculation unit operates and calculates the power of the correlation value when the differential phase value calculation unit does not operate, a power storage unit which stores power for the total number of time points calculated by shifting the received signal by one time point at a time, and a peak detection determination unit which determines the synchronization sequence position based on the position at which the power stored in the power storage unit takes the maximum value.

The present invention also provides a synchronization acquisition circuit for determining a synchronization sequence position, which is a position in the sequence length of the cascaded concatenated spreading code to be multiplied by a received signal having a sequence length of the number of sequence lengths at discrete time points having a chip time interval, in a spread spectrum receiver that receives a signal spread with a cascaded concatenated spreading code which is a pseudo-random number taking a binary value that changes in a first chip time and has a first sequence length which is a product of a first division number which is an integer equal to or greater than 3 and a first unit number which is an integer equal to or greater than 2.
The synchronization acquisition circuit includes a second despreading received signal calculation unit for a second number of despreading points, which is a second number of time points or a second sequence length, for calculating a second despreading received signal that is a complex number obtained by multiplying a second number of time points obtained by multiplying a second sequence length by an excess coefficient for a received signal that is expressed as a complex number by an in-phase component and an orthogonal component having a phase difference of 90 degrees from the in-phase component and in which one chip contains the number of excess coefficients , or a second number of received signals of a second sequence length selected to have an interval of chip time, by each of second spreading codes determined according to the position of a chip in the second sequence length to which each of the received signals belongs; a second correlation value accumulator that calculates a second correlation value which is the sum of two despread number of second despread received signals; a second accumulated value storage that stores a stored number of second accumulated values which are second correlation values calculated by shifting the received signals by one time point for a number equal to or greater than the number obtained by multiplying the second number of time points by the minimum number of devices, which is an integer obtained by subtracting 1 from the first sequence length; and a second accumulated value storage that stores a stored number of second accumulated values which are second correlation values calculated by shifting the received signals by one time point for a number equal to or greater than the number obtained by multiplying the second accumulated values by the first spreading codes for the number of first sequence lengths, which are inputted a first correlation value accumulating unit that calculates a first correlation value which is a sum of a number of post-despreading second accumulated values which is equal to or greater than a first difference number, which is an integer obtained by subtracting a first unit number from a first sequence length, and is equal to or less than the first sequence length; a unit first correlation value calculating unit for a number of first division numbers ordered by the post-despreading second accumulated values used in the calculation, and a first differential phase value which is a complex number having a phase difference between the unit first correlation value and the previous unit first correlation value, the first differential phase value being the number of first difference numbers which is an integer obtained by subtracting 1 from the first division number a first differential correlation value calculation unit that calculates a first differential correlation value which is the sum of first differential phase values for the number of first differential numbers ; an operation control unit that controls whether to operate the first differential phase value calculation unit; a power calculation unit that calculates the power of the first differential correlation value when the first differential phase value calculation unit operates and calculates the power of the first correlation value when the differential phase value calculation unit does not operate; a power storage unit that stores power for the number of time points which is the product of the second number of time points and the first sequence length calculated by shifting the received signal by one time point at a time; and a peak detection determination unit that determines the synchronization sequence position based on the position where the power stored in the power storage unit takes the maximum value.

The present invention also provides a synchronization acquisition circuit for determining a synchronization sequence position, which is a position in the sequence length of the cascaded concatenated spreading code to be multiplied by a received signal having a sequence length equal to the product of a first and a second sequence length, the cascaded concatenated spreading code being obtained by multiplying a first spreading code, which is a pseudo-random number having a first sequence length and taking a binary value which changes every first chip time, with a second spreading code, which is a pseudo-random number having a second sequence length and taking a binary value which changes every chip time obtained by dividing the first chip time by the second sequence length.
The synchronization acquisition circuit includes a second despreading received signal calculation unit for a second despreading number, which is a second number of time points or a second sequence length, for calculating a second despreading received signal that is a complex number obtained by multiplying a second sequence length by an excess coefficient, the second number of time points obtained by multiplying the second sequence length by an excess coefficient, or each of the received signals of the number of second sequence lengths selected to have an interval of chip time, by each of second spreading codes determined according to the position of the chip in the second sequence length to which each of the received signals belongs , for a received signal expressed as a complex number by an in-phase component and an orthogonal component having a phase difference of 90 degrees from the in-phase component, and one chip containing the number of excess coefficients. a second correlation value accumulator that calculates a second correlation value, which is a sum of the scattered received signals; a second differential phase value calculator that calculates a second differential phase value, which is a complex number having a phase difference between the second correlation value and a second correlation value calculated using a received signal at a time point a first delay time earlier than the received signal used when calculating the second correlation value, which is a time obtained by multiplying a first chip time by a delay chip number that is an integer equal to or greater than 1; an operation controller that controls whether to operate the second differential phase value calculator; and a second differential phase value calculator that calculates a second differential phase value by shifting the received signal by one time point for a stored number of pieces, which is a number equal to or greater than a number obtained by multiplying a minimum number of pieces, which is an integer obtained by subtracting 1 from the first sequence length, by the second time point number. a second accumulated value storage unit for storing a second accumulated value which is either a second correlation value or a second differential phase value; and when each of the second accumulated values for the number of first sequence lengths calculated at each point in time of the first chip time is input, and when the second differential phase value calculation unit operates, each of the first differential codes which are spread codes having a first sequence length determined from the first spreading code and which take two values, a unchanged value which indicates that each of the first spreading codes is the same value as the first spreading code the number of delay chips before, and a changed value which indicates that each of the first spreading codes is a value different from the first spreading code the number of delay chips before, is input; and when the second differential phase value calculation unit does not operate, the first differential code or the first spreading code; a first summation value calculation unit that calculates a first summation value which is the sum of the second summation values after despreading for the number of first sequence lengths; a power calculation unit that calculates the power of the first summation value; a power storage unit that stores power for the number of time points which is the product of the second time point number and the first sequence length calculated by shifting the received signal by one time point; and a peak detection and determination unit that determines the synchronization sequence position based on the position at which the power stored in the power storage unit takes the maximum value.

The synchronization acquisition circuit disclosed here makes it possible to determine the synchronization sequence position of the spreading code with higher accuracy than conventional methods, even when the frequency deviation is large.

FIG. 2 is a diagram showing the configuration of a spreading code generator that generates a cascade connection spreading code PN in a spread spectrum transmitter. A diagram showing a sequence of a first spreading code CA generated by a CA generator. FIG. 13 is a diagram showing a sequence of a second spreading code CB. FIG. 2 is a diagram showing a sequence of cascade-connected spreading codes PN. FIG. 1 is a block diagram showing a configuration of a spread spectrum receiver. FIG. 2 is a diagram showing a configuration of an analog receiving section of a spread spectrum receiver. FIG. 2 is a diagram showing the configuration of a quadrature detector included in a spread spectrum receiver. FIG. 2 is a diagram showing the configuration of a timing corrector included in a spread spectrum receiver. FIG. 2 is a diagram showing the configuration of an AGC included in a spread spectrum receiver; FIG. 2 is a diagram showing the configuration of a despreader included in a spread spectrum receiver. FIG. 2 is a diagram showing the configuration of a spreading code generator included in a spread spectrum receiver. FIG. 2 is a diagram showing the configuration of a synchronous tracking circuit included in a spread spectrum receiver. 11 is a diagram showing the relationship between a timing error ΔTc and a power difference ^ΔR2 in a synchronous tracking circuit. 1 is a functional block diagram showing the configuration of a synchronization acquisition circuit according to a first embodiment of a cascade-connected series (CAT series) spread spectrum receiver; 11 is a diagram showing a configuration of a second differential phase value calculation unit included in the synchronization acquisition circuit according to the first embodiment; FIG. 4 is a diagram showing a configuration of a code selection unit included in the synchronization acquisition circuit according to the first embodiment; FIG. 4 is a diagram showing a configuration of a first differential phase value calculation unit included in the synchronization acquisition circuit according to the first embodiment; FIG. 11 is a diagram showing an operating state in which a second differential phase value calculation unit of the synchronization acquisition circuit according to the first embodiment operates; FIG. 13 is a diagram showing complex signals measured in each section when the second differential phase value calculation section operates during rough detection of the synchronization acquisition circuit according to the first embodiment and the cascade-connected spreading code PN is synchronized; FIG. FIG. 11 is a diagram showing complex signals measured in each section when the second differential phase value calculation section operates during rough detection of the synchronization acquisition circuit according to the first embodiment, the first spreading code CA is synchronized, and the second correlation value B is a small value. FIG. 11 is a diagram showing complex signals measured in each section when the second differential phase value calculation section operates during rough detection of the synchronization acquisition circuit according to the first embodiment, the first spreading code CA is synchronized, and the second correlation value B is close to zero. 13 is a diagram showing changes in the amplitudes of the second differential correlation value WB and the first correlation value A depending on the code position during rough detection by the synchronization acquisition circuit according to the first embodiment; FIG. 11 is a diagram showing an operating state in which the second differential phase value calculation unit of the synchronization acquisition circuit according to the first embodiment does not operate; FIG. 11A and 11B are diagrams illustrating complex signals measured in each section when a second differential phase value calculation section does not operate during rough detection in the synchronization acquisition circuit according to the first embodiment. 4 is a diagram showing an operating state in which a first differential phase value calculation unit of the synchronization acquisition circuit according to the first embodiment operates; FIG. 11A and 11B are diagrams illustrating complex signals measured in each unit when a first differential phase value calculation unit operates during rough detection in the synchronization acquisition circuit according to the first embodiment. 11A and 11B are diagrams illustrating complex signals measured in each unit when a first differential phase value calculation unit operates during fine detection in the synchronization acquisition circuit according to the first embodiment. 13 is a diagram showing changes in the amplitudes of the first differential correlation value WA and the first correlation value A depending on the code position during fine detection in the synchronization acquisition circuit according to the first embodiment; FIG. 1 is a functional block diagram showing a configuration of a first modified example of the synchronization acquisition circuit according to the first embodiment; FIG. 13 is a functional block diagram showing a configuration of a second modified example of the synchronization acquisition circuit according to the first embodiment. 11 is a block diagram showing a configuration of a spread spectrum receiver in which a second modified example of the synchronization acquisition circuit according to the first embodiment is used; FIG. 13 is a block diagram showing a configuration of a timing corrector included in a spread spectrum receiver in which a second modified example of the synchronization acquisition circuit according to the first embodiment is used. FIG. 13 is a block diagram showing the configuration of a despreader included in a spread spectrum receiver in which a second modified example of the synchronization acquisition circuit according to the first embodiment is used. FIG. FIG. 13 is a functional block diagram showing a configuration of a third modified example of the synchronization acquisition circuit according to the first embodiment. FIG. 13 is a functional block diagram showing a configuration of a fourth modified example of the synchronization acquisition circuit according to the first embodiment. FIG. 13 is a functional block diagram showing a configuration of a fifth modified example of the synchronization acquisition circuit according to the first embodiment. 13 is a diagram showing a configuration of a second differential phase value calculation unit included in a fifth modified example of the synchronization acquisition circuit according to the first embodiment; FIG. 13 is a diagram showing a configuration of a first differential phase value calculation unit included in a fifth modified example of the synchronization acquisition circuit according to the first embodiment; FIG. 13 is a diagram showing changes in amplitude of the second differential correlation value WB and the first correlation value A depending on the code position during rough detection in the fifth modified example of the synchronization acquisition circuit of the first embodiment. FIG. FIG. 13 is a diagram showing changes in the amplitudes of the first differential correlation value WA and the first correlation value A depending on the code position during fine detection in the fifth modified example of the synchronization acquisition circuit in accordance with the first embodiment. FIG. 13 is a functional block diagram showing a configuration of a sixth modified example of the synchronization acquisition circuit according to the first embodiment. FIG. 13 is a functional block diagram showing a configuration of a seventh modified example of the synchronization acquisition circuit according to the first embodiment. FIG. 13 is a functional block diagram showing a configuration of an eighth modified example of the synchronization acquisition circuit according to the first embodiment. FIG. 13 is a diagram showing a configuration of a first differential phase value calculation unit included in an eighth modification of the synchronization acquisition circuit according to the first embodiment. FIG. 13 is a functional block diagram showing a configuration of a ninth modified example of the synchronization acquisition circuit according to the first embodiment. 13 is a diagram showing an operating state in which the second differential phase value calculation unit and the first differential phase value calculation unit operate in the ninth modification of the synchronization acquisition circuit according to the first embodiment; FIG. FIG. 13 is a diagram showing complex signals measured in each section when the second differential phase value calculation section and the first differential phase value calculation section operate during rough detection in the ninth modification of the synchronization acquisition circuit according to the first embodiment, and the cascade-connected spreading code PN is synchronized. FIG. 13 is a diagram showing complex signals measured in each section when the second differential phase value calculation section operates during rough detection in the ninth modification of the synchronization acquisition circuit according to the first embodiment, the first differential phase value calculation section does not operate, and the cascade-connected spreading code PN is synchronized. FIG. 23 is a functional block diagram showing a configuration of a tenth modification of the synchronization acquisition circuit according to the first embodiment. FIG. 11 is a functional block diagram showing a configuration of a synchronization acquisition circuit according to a second embodiment. FIG. 13 is a functional block diagram showing a configuration of an eleventh modified example of the synchronization acquisition circuit according to the second embodiment. FIG. 15 is a functional block diagram showing a configuration of a twelfth modified example of the synchronization acquisition circuit according to the second embodiment. FIG. 11 is a functional block diagram showing a configuration of a synchronization acquisition circuit according to a third embodiment. 13 is a diagram showing a configuration of a cumulative addition unit included in a synchronization acquisition circuit according to a third embodiment; FIG. FIG. 13 is a functional block diagram showing a configuration of a synchronization acquisition circuit according to a fourth embodiment. 13 is a diagram showing a configuration of a second differential phase value calculation unit included in the synchronization acquisition circuit according to the fourth embodiment; FIG. FIG. 13 is a diagram showing a configuration of a code selection unit included in a synchronization acquisition circuit according to a fourth embodiment; FIG. 13 is a functional block diagram showing a configuration of a synchronization acquisition circuit according to a fifth embodiment. 13 is a diagram showing a configuration of a second differential phase value calculation unit included in the synchronization acquisition circuit according to the fifth embodiment. FIG. FIG. 13 is a diagram showing a configuration of a code selection unit included in a synchronization acquisition circuit according to a fifth embodiment. FIG. 13 is a functional block diagram showing a configuration of a synchronization acquisition circuit according to a sixth embodiment. 13 is a diagram showing a configuration of a second-stage first differential phase value calculation unit included in a synchronization acquisition circuit according to a sixth embodiment; FIG. 13 is a diagram showing an operating state in which a second differential phase value calculation unit included in the acquisition circuit according to the sixth embodiment operates; FIG. 13 is a diagram showing an operating state in which a first differential phase value calculation unit in the first stage of the synchronization acquisition circuit according to the sixth embodiment operates; FIG. 13 is a diagram showing an operating state in which a first differential phase value calculation unit in the second stage of the synchronization acquisition circuit according to the sixth embodiment operates; FIG. 13A to 13C are diagrams showing complex signals measured in each section when a first differential phase value calculation section in the second stage of the synchronization acquisition circuit according to the sixth embodiment is in operation; FIG. 13 is a functional block diagram showing a configuration of a synchronization acquisition circuit according to a seventh embodiment. FIG. 13 is a functional block diagram showing a configuration of a synchronization acquisition circuit according to an eighth embodiment. FIG. 13 is a functional block diagram showing a configuration of a synchronization acquisition circuit according to a ninth embodiment. FIG. 23 is a functional block diagram showing a configuration of a synchronization acquisition circuit according to a tenth embodiment. 23 is a diagram showing a configuration of a differential phase value calculation unit included in a synchronization acquisition circuit according to a tenth embodiment. FIG. FIG. 23 is a functional block diagram showing a configuration of a thirteenth modified example of the synchronization acquisition circuit according to the tenth embodiment. FIG. 23 is a diagram showing the configuration of a differential phase value calculation unit included in a thirteenth modified example of the synchronization acquisition circuit according to the tenth embodiment; FIG. 23 is a functional block diagram showing the configuration of a fourteenth modified example of the synchronization acquisition circuit according to the tenth embodiment. FIG. 23 is a functional block diagram showing a configuration of a synchronization acquisition circuit according to an eleventh embodiment. 13 is a diagram showing a configuration of a second-stage differential phase value calculation unit included in a synchronization acquisition circuit according to a sixth embodiment. FIG.

Hereinafter, embodiments will be described with reference to the drawings.
Embodiment 1.
A spread spectrum receiver having a synchronization acquisition circuit according to the present disclosure receives a spread spectrum wave, which is a radio wave carrying a spectrum-spread transmission signal transmitted by a spread spectrum transmitter (not shown). The synchronization acquisition circuit detects a position where a spreading code is synchronized in the spread spectrum received signal. The spread spectrum transmitter spreads a transmission signal by a cascade connection spreading code PN, and transmits the spectrum-spread transmission signal as a radio wave. Fig. 1 is a diagram showing a configuration of a spreading code generator 300 included in the spread spectrum transmitter. The spreading code generator 300 generates a cascade connection spreading code PN. The cascade connection spreading code PN is also called a CAT series spreading code.

The spreading code generator 300 includes a CA generator 1001, a CB generator 1002, and a multiplier 1003. The CA generator 1001 generates a first spreading code CA, which is a pseudo-random number that takes on two values. The CB generator 1002 generates a second spreading code CB, which is a pseudo-random number that takes on two values. The multiplier 1003 generates a cascade-connected spreading code PN, which is a pseudo-random number that takes on two values, by multiplying the first spreading code CA and the second spreading code CB together.

Figure 2 shows the sequence of the first spreading code CA generated by the CA generator 1001. The first spreading code CA is a pseudo-random number whose value is "+1" or "-1". The sequence length of the first spreading code CA is the first sequence length (NA chips). The time of one period of the first spreading code CA is TA. The first spreading code CA changes every time the first chip time SA (=TA/NA) elapses.

Figure 3 is a diagram showing the sequence of the second spreading code CB generated by the CB generator 1002. The second spreading code CB is a pseudo-random number whose value is "+1" or "-1". The sequence length of the second spreading code CB is the second sequence length (NB chips). The time of one period of the second spreading code CB is TB. The second spreading code CB changes every time the second chip time SB (=TB/NB) elapses. Here, TB=SA, SB=SA/NB. That is, the second chip time SB is the value obtained by dividing the first chip time SA by the second sequence length NB. Since NB>2, SA>SB. The time of one chip of the first spreading code CA corresponds to the time of NB chips of the second spreading code CB.

Figure 4 shows the sequence of cascaded spreading codes PN generated by the spreading code generator 300. The cascaded spreading code PN is a pseudo-random number whose value is "+1" or "-1". The sequence length of the cascaded spreading code PN is the third sequence length (NC chips). The third sequence length (NC chips) is the cascaded sequence length that is the product of the first sequence length (NA chips) and the second sequence length (NB chips). In other words, NC = NA * NB. The time of one period of the cascaded spreading code PN is TP (= TA). The cascaded spreading code PN changes every time the second chip time SB elapses. The sequence of cascaded spreading codes is also called a CAT (Concatenated) sequence.

The second chip time SB is the chip time during which the binary value of the cascaded spreading code PN changes. NA is expressed as the product of MA, which is an integer equal to or greater than 3, and DA, which is an integer equal to or greater than 2. MA is called the first division number, and DA is called the first unit number. MA is also called the number of units.

Figure 5 is a block diagram showing the configuration of the spread spectrum receiver 1. The spread spectrum receiver 1 includes an analog receiving unit 2, an ADC (Analog-to-Digital Converter) unit 3, a quadrature detector 4, a timing corrector 5, an AGC (Auto Gain Control) unit 6, a despreader 7, a synchronization tracking circuit 8, and a synchronization acquisition circuit 9. The analog receiving unit 2, the ADC unit 3, the quadrature detector 4, the timing corrector 5, the AGC unit 6, the despreader 7, and the synchronization tracking circuit 8 are connected in series in a cascade arrangement. The synchronization acquisition circuit 9 is connected in parallel with the despreader 7 and subsequent to the AGC unit 6.

The analog receiving unit 2 extracts the analog received signal. The ADC unit 3 converts the analog signal into a digital signal. The quadrature detection unit 4 converts the IF signal into a complex BB signal. The BB signal is a signal in a frequency band (base band) in which the communicated signal changes. The IF signal is an intermediate frequency signal that is higher than the frequency of the BB signal and lower than the frequency of the carrier wave. The timing corrector 5 corrects the chip timing. The AGC unit 6 amplifies the complex BB signal to a determined amplitude. The despreading unit 7 despreads the received signal to return it to the signal before it was spread by the cascade connection sequence (hereinafter referred to as the CAT sequence). The synchronization tracking circuit 8 estimates the amount of timing deviation to perform timing correction based on the signal from the despreading unit 7. The synchronization capture circuit 9 performs phase synchronization of the spreading code using the synchronization capture of the CAT sequence for the output of the timing corrector 5.

The analog receiver 2 receives an intermediate frequency signal IF0 spread by the cascade connection spreading code PN transmitted from the spectrum spreading transmitter, and outputs an intermediate frequency signal IF1.

The ADC unit 3 is connected in cascade to the rear of the analog receiving unit 2 and converts the analog intermediate frequency signal IF1 into a digital intermediate frequency signal IF2.

The quadrature detector 4 is connected in cascade to the rear of the ADC unit 3 and converts the intermediate frequency signal IF2 into a complex BB signal (BBI1+jBBQ1). The complex BB signal is a BB signal expressed as a complex number.

The timing corrector 5 is connected in cascade after the quadrature detector 4, and uses the chip rate error (-ΔRc) detected by the synchronization tracking circuit 8 to correct the chip timing shift of the complex BB signal (BBI1+jBBQ1) and output the complex BB signal (BBI2+jBBQ2). The complex BB signal (BBI2+jBBQ2) is a signal whose value changes every SB/2. The timing corrector 5 outputs the complex BB signal (BBI2+jBBQ2) that has been oversampled by a factor of 2.

The number of received signals contained in one chip is called the excess coefficient. Since the received signal is oversampled by 2, 2NC is the total number of time points obtained by multiplying the excess coefficient contained in consecutive chips of the sequence length by the sequence length. If oversampling is not performed, the sequence length and the total number of time points are the same. Even if oversampling is performed, the received signal may be despread by multiplying each spreading code by each of the received signals of the sequence length selected to have an interval of chip time. The number of received signals used for despreading, which is the total number of time points or sequence length, is called the despreading number. The value obtained by dividing the despreading number by the number of units is called the number of units. In the synchronization acquisition circuit 9, the value obtained by dividing the total number of time points 2NC by the number of units MA (2NC/MA = 2NB * DA) is the number of units.

The AGC unit 6 is connected in cascade to the rear of the timing corrector 5, and amplifies the power of the complex BB signal (BBI2+jBBQ2) so that it becomes a constant level indicated by a reference value. The AGC unit 6 outputs the amplified complex BB signal (BBI3+jBBQ3). The AGC unit 6 controls the amplification rate according to the level of the input signal so that the amplified signal level becomes the reference value.

The despreader 7 is connected in series after the AGC unit 6, and by despreading the complex BB signal (BBI3+jBBQ3), it restores the signal before spectrum spreading by the cascade-connected spreading code PN in the spectrum spreading transmitter. The despread complex BB signal (BBI4+jBBQ4) output by the despreader 7 is input to a demodulation unit (not shown). The demodulation unit demodulates the complex BB signal (BBI4+jBBQ4) according to the modulation method used in wireless communication. The despreader 7 also outputs the complex BB signal (BBI4P+jBBQ4P) and the complex BB signal (BBI4M+jBBQ4M) to the synchronization tracking circuit 8. The complex BB signal (BBI4P + jBBQ4P) is a signal obtained by despreading the complex BB signal (BBI3 + jBBQ3) with a spreading code delayed by SB/2 from the spreading code used to despread the complex BB signal (BBI4 + jBBQ4). The complex BB signal (BBI4M + jBBQ4M) is a signal obtained by despreading the complex BB signal (BBI3 + jBBQ3) with a spreading code that is earlier than the spreading code used to despread the complex BB signal (BBI4 + jBBQ4) by SB/2.

The synchronization tracking circuit 8 estimates the chip rate error (-ΔRc) based on the signal output from the despreader 7, and outputs it to the timing corrector 5. The chip rate error (-ΔRc) is a value obtained by averaging the timing error (ΔTc) between the complex BB signal (BBI4+jBBQ4) and the cascade-connected spreading code PN, and converting it into a chip rate (frequency) deviation (i.e., the amount of phase change per 2x oversampling).

The acquisition circuit 9 executes acquisition processing of the modulated wave that has been spectrum-spread by the cascade-connected spread code PN, using the output of the AGC unit 6. The acquisition circuit 9 determines a spread code phase correction value (-Δθ _PN ) for despreading when communication with the spread spectrum transmitter begins. It also outputs a frequency deviation (ΔF) that is the difference between the frequency used by the quadrature detector 4 and the carrier frequency (F) of the received signal.

Figure 6 is a diagram showing the configuration of the analog receiving unit 2. The analog receiving unit 2 includes a band pass filter (hereinafter, BPF) 21, an amplifier (hereinafter, AMP) 22, and a low pass filter (hereinafter, LPF) 23.

BPF21 reduces frequency components higher or lower than a determined frequency band from intermediate frequency signal IF0 to remove noise and spurious signals. AMP22 amplifies the level of the signal output from BPF21 to an appropriate value. LPF23 reduces frequency components higher than the determined frequency band to remove aliasing noise generated in ADC unit 3, and outputs intermediate frequency signal IF1.

Figure 7 is a diagram showing the configuration of the quadrature detector 4. The quadrature detector 4 detects the input intermediate frequency signal IF1 using two sine waves with a phase difference of 90 degrees. The two sine waves change based on the phase obtained by integrating (-F-ΔF). Here, (-ΔF) is the value obtained by inverting the sign of the frequency deviation estimated by the synchronization acquisition circuit 9. (-F) is the value obtained by inverting the sign of the carrier frequency of the predetermined intermediate frequency signal IF1.

The quadrature detector 4 includes an adder 49, a numerically controlled oscillator (NCO) 46, a cos/-sin generator 45, a first multiplier 41, a second multiplier 42, a low-pass filter (LPF) 43, and a low-pass filter (LPF) 44.

The adder 49 receives (-ΔF) and (-F) and outputs their sum. The adder 49 outputs (-F-ΔF) to the NCO 46 for each sampling period. The NCO 46 integrates (-F-ΔF) output from the adder 49 for each sampling period and outputs the phase (ξ) of the carrier wave of the IF signal.

The cos/-sin generator 45 generates a complex local signal (cosξ+jsinξ) having a phase (ξ) output by the NCO 46. The first multiplier 41 multiplies the intermediate frequency signal IF1 by cosξ. The second multiplier 42 multiplies the intermediate frequency signal IF1 by (-sinξ). The first LPF 43 removes harmonics from the output of the first multiplier 41 and outputs the BB signal BBI1. The second LPF 44 removes harmonics from the output of the second multiplier 42 and outputs the BB signal BBQ1.

Figure 8 is a diagram showing the configuration of the timing corrector 5. The timing corrector 5 converts the BB signals BBII and BBQ1 generated at the sampling frequency in the ADC unit 3 into the BB signal BBI2 generated at an interval of 1/2 the second chip time SB (= twice the frequency corresponding to one chip of the second spread code CB). In other words, the BB signals BBI2 and BBQ2 are signals that have been oversampled twice. Furthermore, the timing corrector 5 uses the value of the chip rate error (-ΔRc) detected by the synchronization tracking circuit 8 to remove the timing error of the BB signals BBI2 and BBBQ2.

The timing corrector 5 includes a first FIR filter type resampler 51, a second FIR filter type resampler 52, a filter coefficient update unit 53, an NCO 54, and an adder 55.

The adder 55, the NCO 54, and the filter coefficient update unit 53 determine the sampling timing of the sampling frequency determined by (2Rc-ΔRc). Rc is a frequency equivalent to one chip of the second spreading code CB. That is, Rc=1/SB. The adder 55 adds 2Rc and (-ΔRc) and outputs the result to the NCO 54. The NCO 54 outputs Δθ _NCO , which is a phase obtained by adding the numerical value output from the adder 55 at a determined period.

The first FIR filter type resampler 51 and the second FIR filter type resampler 52 interpolate and output the values of the complex BB signal at the sampling timing (every SB/2) between adjacent sampling times (sampling frequency in the ADC unit 3) by convoluting a series of finite input values and the filter coefficients. Typically, a sinc function, which is the time response of an ideal LPF, can be used as the filter coefficient of the first FIR filter type resampler 51 and the second FIR filter type resampler 52. Taking into account the conversion from a high oversampling number to a low oversampling number in the timing corrector 5, a filter coefficient other than the sinc function may be used.

The filter coefficient update unit 53 calculates filter coefficients of the first FIR filter type resampler 51 and the second FIR filter type resampler 52 for correcting the deviation based on the deviation between the output timing and the input timing at which Δθ _NCO becomes 2π, and sets the calculated filter coefficients to the first FIR filter type resampler 51 and the second FIR filter type resampler 52. The filter coefficient update unit 53 detects the output timing at which Δθ _NCO becomes 2π and the input timing closest to the output timing. The filter coefficient update unit 53 calculates the deviation between the detected output timing and the input timing. The filter coefficient update unit 53 calculates filter coefficients to be set to the first FIR filter type resampler 51 and the second FIR filter type resampler 52 according to the calculated deviation. The filter coefficient update unit 53 sets the calculated filter coefficients to the first FIR filter type resampler 51 and the second FIR filter type resampler 52. When the filter coefficients are set, the first FIR filter type resampler 51 and the second FIR filter type resampler 52 perform convolution integration using the filter coefficients and output BB signals BBI2 and BBQ2.

The first FIR filter type resampler 51 receives the BB signal BBI1 generated at the sampling frequency of the ADC unit 3, and outputs a BB signal BBI2 having a sampling frequency of (2Rc-ΔRc). The second FIR filter type resampler 52 receives the BB signal BBQ1 generated at the sampling frequency of the ADC unit 3, and outputs a BB signal BBQ2 having a sampling frequency of (2Rc-ΔRc).

Figure 9 is a diagram showing the configuration of the AGC unit 6. The AGC unit 6 amplifies the power level of the complex BB signal (BBI2 + jBBIQ) input to the despreader 7 and the synchronization acquisition circuit 9 so that it becomes a constant level indicated by a reference value. The amplification factor in the AGC unit 6 changes according to the power level of the input complex BB signal. By keeping the level of the complex BB signal input to the despreader 7 and the synchronization acquisition circuit 9 constant, it becomes easier to detect the phase (chip) at which the correlation value calculated in the synchronization acquisition circuit 9 reaches a peak.

The AGC unit 6 includes a first multiplier 61a, a second multiplier 61b, a first squaring circuit 63a, a second squaring circuit 63b, an adder 64, a first converter 65, a subtractor 66, a third multiplier 67a, a fourth multiplier 67b, an LF (Loop Filter) unit 68, and a second converter 69.

The first multiplier 61a multiplies the BB signal BBI2 by the output of the second converter 69 to output the BB signal BBI3. The second multiplier 61b multiplies the BB signal BBQ2 by the output of the second converter 69 to output the BB signal BBQ3. The first squaring circuit 63a calculates the square of the BB signal BBI3. The second squaring circuit 63b calculates the square of the BB signal BBQ3. The adder 64 calculates the power P of the complex BB signal (BBI3 + jBBQ3) by adding the square of the BB signal BBI3 and the square of the BB signal BBQ3.

The first converter 65 converts the power P into a dB value. The first converter 65 calculates 10*Log ₁₀ (P) as a dB value for the power P. The subtractor 66 subtracts a reference value REF from the dB value of the power P. The reference value REF is a target level of the output power P of the AGC unit 6. The AGC unit 6 performs feedback control so that the output power P coincides with the reference value REF. The third multiplier 67a multiplies the output of the subtractor 66 by a minus sign for feedback control. The fourth multiplier 67b multiplies the output of the third multiplier 67a by the GAIN value. The LF unit 68 averages the output of the fourth multiplier 67b to absorb variations due to noise.

The second converter 69 converts the result of averaging by the LF unit 68, X (dB value), back into a voltage value, which is a true value. The second converter 69 calculates 10X ^/20 as a voltage value for X (dB value). The output of the second converter 69 is sent to the first multiplier 61a and the second multiplier 61b, thereby performing feedback control on the input BB signals BBI2 and BBQ2.

In addition, in the AGC unit 6 in FIG. 9, the power P is controlled to be at a constant level indicated by the reference value REF. To reduce the bit length, the absolute value of the amplitude of the complex BB signal (BBI3+jBBQ3) may be controlled to be at a constant level.

10 is a diagram showing the configuration of the despreader 7. The despreader 7 multiplies the complex BB signal (BBI3+jBBQ3) by the cascade connection spreading code PN synchronized therewith, and outputs the complex BB signal (BBI4+jBBQ4) in the state before multiplication by the cascade connection spreading code PN in the spread spectrum transmitter. The cascade connection spreading code PN is a spreading code based on a pseudo-random number whose value is "+1" or "-1". Multiplying "+1" by "+1" results in "+1" and multiplying "-1" by "-1" results in "+1", so that the fact that the spread component disappears by multiplying the complex BB signal (BBI3+jBBQ3) by the cascade connection spreading code PN synchronized therewith is utilized. The phase of the cascade connection spreading code PN and the phase of the complex BB signal (BBI3+jBBQ3) are aligned using the phase correction value (-Δθ _PN ) of the cascade connection spreading code PN estimated by the synchronization acquisition circuit 9. The cascade connection spreading code PN changes in units of one chip (two samples).

The despreader 7 includes a spreading code generator 79, a first multiplier 71, a second multiplier 72, a third multiplier 73, a fourth multiplier 74, a fifth multiplier 75, a sixth multiplier 76, a first one-sample delay circuit 78, a second one-sample delay circuit 77, a first integration & thinning circuit 91, a second integration & thinning circuit 92, a third integration & thinning circuit 93, a fourth integration & thinning circuit 94, a fifth integration & thinning circuit 95, and a sixth integration & thinning circuit 96.

The spreading code generator 79 outputs the cascade connection spreading code PN. The spreading code generator 79 outputs the cascade connection spreading code PN at intervals (SB/2) that are 1/2 the second chip time SB. However, the value of the cascade connection spreading code PN output from the spreading code generator 79 changes in units of the second chip time SB. The spreading code generator 79 shifts the phase of the cascade connection spreading code PN by the spreading code phase correction value (-Δθ _PN ) output from the synchronization acquisition circuit 9. Thereafter, this shift amount is held. By shifting the phase of the cascaded spreading code PN by the spreading code phase correction value (-Δθ _PN ), the received signal (BBI3+jBBQ3) and the cascaded spreading code PN are synchronized, and the received signal (BBI3+jBBQ3) at discrete points in time can be despread to generate a complex BB signal (BBI4+jBBQ4).

The first one-sample delay circuit 78 delays the cascaded spreading code PN by one sample (SB/2). The second one-sample delay circuit 77 further delays the cascaded spreading code PN output from the first one-sample delay circuit 78 by one sample (SB/2).
The cascade-concatenated spreading code PN input to the third multiplier 73 and the fourth multiplier 74 is denoted as PN(t). PN(t-SB/2) is input to the first multiplier 71 and the second multiplier 72. PN(t+SB/2) is input to the fifth multiplier 75 and the sixth multiplier 76.

The first multiplier 71, the third multiplier 73, and the fifth multiplier 75 receive the BB signal BBI3 generated by oversampling at twice the same time. The first multiplier 71, the third multiplier 73, and the fifth multiplier 75 receive the cascade connection spreading codes PN with timings that differ by SB/2. The first multiplier 71, the third multiplier 73, and the fifth multiplier 75 output the despreading result of the in-phase component BBI3 of the complex BB signal using the cascade connection spreading codes PN with timings that differ by SB/2.

The second multiplier 72, the fourth multiplier 74, and the sixth multiplier 76 receive a BB signal BBQ3 that has been oversampled by 2 and has the same time as the BB signal BBI3. The second multiplier 72, the fourth multiplier 74, and the sixth multiplier 76 receive a cascade connection spreading code PN that differs in timing by SB/2. The second multiplier 72, the fourth multiplier 74, and the sixth multiplier 76 output the despreading result of the orthogonal component BBQ3 of the complex BB signal using the cascade connection spreading code PN that differs in timing by SB/2.

The despreader 7 outputs the despreading result integrated over one symbol for each symbol. To this end, the outputs of the first multiplier 71, the second multiplier 72, the third multiplier 73, the fourth multiplier 74, the fifth multiplier 75, and the sixth multiplier 76 are input to the first integration & thinning circuit 91, the second integration & thinning circuit 92, the third integration & thinning circuit 93, the fourth integration & thinning circuit 94, the fifth integration & thinning circuit 95, and the sixth integration & thinning circuit 96.

The integration and decimation circuits 91 to 96 integrate the despreading results output from the multipliers 71 to 76 over one symbol period in chip clock units, and output the integrated value of one symbol period to the subsequent stage for each symbol. The first integration and decimation circuit 91 outputs the BB signal BBI4M, which is the integrated value of one symbol period, to the synchronization tracking circuit 8. The second integration and decimation circuit 92 outputs the BB signal BBQ4M, which is the integrated value of one symbol period, to the synchronization tracking circuit 8. The third integration and decimation circuit 93 outputs the BB signal BBI4, which is the integrated value of one symbol period, to a demodulation unit not shown. The fourth integration and decimation circuit 94 outputs the BB signal BBQ4, which is the integrated value of one symbol period, to a demodulation unit not shown. The fifth integration and decimation circuit 95 outputs the BB signal BBI4P, which is the integrated value of one symbol period, to the synchronization tracking circuit 8. The sixth integration and thinning circuit 96 outputs the BB signal BBQ4P, which is the integrated value for one symbol period, to the synchronization tracking circuit 8.

The integration and thinning circuits 91 to 96 output the integration value to the next stage and at the same time reset the integration value to zero. The output timing and reset timing are controlled by the control signal CT output by the spreading code generator 79. The reset timing is determined based on the timing at which the series of cascaded spreading codes PN returns to the beginning.

FIG. 11 is a diagram showing the configuration of the spreading code generator 79.
The spreading code generator 79 includes a CA generator 2001 , a CB generator 2002 , a multiplier 2003 , and a phase correction section 2004 .

The CA generator 2001 generates a first spreading code CA which is a pseudo-random number having two values. The CB generator 2002 generates a second spreading code CB which is a pseudo-random number having two values. The multiplier 2003 multiplies the first spreading code CA by the second spreading code CB to generate a cascade-connected spreading code PN which is a pseudo-random number having two values. The phase correction unit 2004 shifts the phase of the cascade-connected spreading code PN by a phase correction value (-Δθ _PN ).

The first spreading code CA generated by the CA generator 2001 is the same as the first spreading code CA generated by the CA generator 1001 used in the spectrum spread transmitter. The second spreading code CB generated by the CB generator 2002 is the same as the second spreading code CB generated by the CB generator 1002. The cascade connection spreading code PN generated by the spreading code generator 79 is the same as the cascade connection spreading code PN generated by the spreading code generator 300. The cascade connection spreading code PN generated by the spreading code generator 79 is capable of changing the phase.

FIG. 12 is a diagram showing the configuration of the synchronous tracking circuit 8. As shown in FIG.
The synchronous tracking circuit 8 is generally called a DLL (Delay Locked Loop) and includes a first squaring circuit 81, a second squaring circuit 82, a first adder 85, a third squaring circuit 83, a fourth squaring circuit 84, a second adder 86, a subtractor 87, a first multiplier 88a, a second multiplier 88b, and an LF unit 89.

The first squaring circuit 81 calculates the square of the BB signal BBI4M. The second squaring circuit 82 calculates the square of the BB signal BBQ4M. The first adder 85 adds the square of the BB signal BBI4M and the square of the BB signal BBQ4M to calculate the power P1 of the complex BB signal (BBI4M+jBBQ4M) that is 1/2 the second chip time earlier (shifted by SB/2).

The third squaring circuit 83 calculates the square of the BB signal BBI4P. The fourth squaring circuit 84 calculates the square of the BB signal BBQ4P. The second adder 86 adds the square of the BB signal BBI4P and the square of the BB signal BBQ4P to calculate power P2 of the complex BB signal (BBI4P+jBBQ4P) that is delayed by 1/2 the second chip time (shifted by -SB/2). The subtractor 87 subtracts power P1 from power P2 to output a power difference ^ΔR2 .

13 is a diagram showing the relationship between the timing error ΔTc and the power difference ^ΔR2 . When the timing error ΔTc of the cascaded spreading code PN is in the range of -0.5 chips to 0.5 chips, the power difference ^ΔR2 has a property that the value increases as the timing error ΔTc of the cascaded spreading code PN increases. This property is generally called an S curve. When the timing error ΔTc=0, the power ^R2 after despreading is maximum. The powers P1 and P2 are the same amount of power that is reduced from the maximum value of the power ^R2 . Therefore, when ΔTc=0, the power difference ^ΔR2 =0. When ΔTc≠0, the power ^R2 after despreading decreases as the absolute value of the timing error ΔTc increases. When ΔTc=-0.5 chips, the power P2 of the complex BB signal (BBI4P+jBBQ4P) that is delayed by 1/2 the second chip time (shifted by -SB/2) is the maximum of power ^R2 when ΔTc=0. Power P1 is reduced to power ^R2 when ΔTc=1 chip. As a result, the power difference ^ΔR2 is positive and maximum. When ΔTc increases from ΔTc=-0.5 chips, power P2 decreases and power P1 increases. Therefore, when ΔTc increases from ΔTc=-0.5 chips, the power difference ^ΔR2 decreases. When ΔTc=0.5 chips, the power difference ^ΔR2 is negative and minimum.

The first multiplier 88a multiplies the power difference ^ΔR2 by a negative value for feedback control. The second multiplier 88b multiplies the output value of the first multiplier 88a by the GAIN value. The LF unit 89 averages the output of the second multiplier 88b to absorb variations due to noise, and outputs the chip rate error (-ΔRc). The chip rate error (-ΔRc) obtained by the averaging process is sent to the timing corrector 5, and feedback control is performed so that the power difference ^ΔR2 becomes zero.

Fig. 14 is a diagram showing the configuration of the synchronization acquisition circuit 9. The synchronization acquisition circuit 9 is a circuit that performs synchronization acquisition processing of a modulated wave that has been spectrum spread using a spreading code that is a CAT sequence. The synchronization acquisition circuit 9 includes a CB correlation processing unit 901, a CA correlation processing unit 910, a power calculation unit 920, an averaging processing unit 930, a peak detection and determination unit 940, a frequency deviation calculation unit 925, and an operation control unit 945. Fig. 14 also shows points P ₁ to P ₆ that indicate complex signals to explain the operation of the synchronization acquisition circuit 9. Points P ₁ to P ₆ will be explained later.

The CB correlation processing unit 901 receives the complex BB signal (BBI3+jBBQ3) oversampled twice and output by the AGC unit 6 every time SB/2 elapses. The CB correlation processing unit 901 holds one period (NB pieces) of the second spreading code CB output by the CB generator 2002 shown in FIG. 11.

The CB correlation processing unit 901 calculates the sum of the products of the complex BB signal (BBI3+jBBQ3) of NB chips (=2NB samples) and the second spreading code CB of NB chips (=NB samples) each time a new complex BB signal (BBI3+jBBQ3) is input after SB/2 has elapsed.

In equation (1), [X] for real number X is a Gaussian symbol, and returns an integer not exceeding X. In equation (1), the complex BB signals (BBI3[k] + BBQ3[k]) for k = 2m and k = 2m-1 are multiplied by the same second spreading code CB[m]. Note that the complex BB signal with a larger subscript [k] is the more recently received signal. The CB correlation processing unit 901 outputs the sum of products calculated using equation (1) to the CA correlation processing unit 910 as the second correlation value B every time SB/2 has elapsed. Note that the second correlation value B is a complex number.

In the CB correlation processing unit 901, the second correlation value B peaks when it is multiplied by the complex BB signal at a position that coincides with the position of the second spreading code CB when spreading by the spectrum spreading transmitter. The second correlation value B peaks for each NB chip.

The second correlation value B may be calculated as the sum of products of the complex BB signal and the second spreading code CB at the time of the SB interval within the NB chip, rather than the sum of products of all complex BB signals included in the NB chip and the second spreading code CB. The second correlation value B may be calculated using the following formula (1A).

When the received signal is oversampled, the second correlation value B is calculated as the sum of the products of the received signal and the second spreading code CB for all complex BB signals included in the NB chips, or one per chip, i.e., NB complex BB signals for the NB chips. When the received signal is not oversampled, the second correlation value B is calculated as the sum of the products of the received signal and the second spreading code CB for one per NB chip, i.e., NB complex BB signals.

Furthermore, the CA correlation processing unit 910 performs correlation processing on the second correlation value B using the first spreading code CA, and treats the sum of the results as the first correlation value A, thereby completing the correlation processing on the received signal of the CAT sequence. The first correlation value A is the correlation value of the received signal of the CAT sequence.

A new second correlation value B is input to the CA correlation processing unit 910 every time SB/2 elapses. The CA correlation processing unit 910 holds the first spreading code CA[1:NA] output by the CA generator 2001 shown in FIG. 11. Every time SB/2 elapses, the CA correlation processing unit 910 calculates the sum of products (first correlation value A) of the second correlation value B spaced every NA NB chips (=2NB samples) and the NA first spreading codes CA. The second correlation value B is the sum of products of 2NB complex BB signals (BBI3[i]+jBBQ3[i], i=1 to 2NB) and the second spreading code CB[m], m=[(k+1)/2], i=1 to 2NB). Therefore, the first correlation value A is the sum of the products of 2NB*NA complex BB signals (BBI3[i] + jBBQ3[i], i = 1 to 2NB*NA) and the cascade connection spreading code PN.

The first correlation value A has a small peak at the position where the second correlation value B peaks every 2NB samples, and one of the NA peaks has an amplitude approximately NA times that of the other peaks. The first correlation value A peaks every NB*NA chips.

The CA correlation processing unit 910 calculates a second differential phase value having a phase difference between the second correlation value B and the second correlation value B calculated using the complex BB signal the first chip time before, and an amplitude of a unit amount, so as to be able to handle cases where the frequency deviation is large, and can also calculate a correlation value calculated as the sum of the products of the second differential phase value and the differential code CD. The amplitude of the unit amount is a determined amplitude. The differential code CD is a spreading code determined in correspondence with the first spreading code CA. It is a code that takes an unchanged value when each code of the first spreading code CA has the same value as the previous code, and takes a changed value when each code is different. By making the amplitude of the second differential phase value a unit amount, the upper limit of the number of bits required to express the second differential phase value can be made smaller than when the amplitude is not a unit amount.

As yet another correlation value, the CA correlation processing unit 910 can also calculate a first differential correlation value, which is the sum of a unit first correlation value, which is the sum of the product of the second correlation value B of a determined first unit number DA and the first spreading code CA, and a first differential phase value having a phase difference from the previous unit first correlation value and an amplitude of a unit amount. By making the amplitude of the first differential phase value a unit amount, the upper limit of the number of bits required to express the first differential phase value can be made smaller than when the amplitude is not a unit amount.

The second correlation value B is a unit correlation value, which is a complex number representing the sum of consecutive despread received signals GR of the number of units (2NB). When the second correlation value B is a unit correlation value, the number of units is NA. The unit first correlation value is a unit correlation value, which is a complex number representing the sum of consecutive despread received signals GR of the number of units (2NB * DA). When the unit first correlation value is a unit correlation value, the number of units is MA. The synchronization acquisition circuit 9 can have two different numbers of units, NA and MA. The synchronization acquisition circuit may be configured to have three or more different numbers of units.

The second differential phase value VB is a differential phase value that is a complex number having the phase difference between the unit correlation value (second correlation value B) and the previous unit correlation value (second correlation value B). The second differential phase value calculation unit 960 is a differential phase value calculation unit that calculates the differential phase value.

For example, consider the case where a maximum of 8 bits are required to express the two input data used to calculate the second differential phase value VB or the first differential phase value, and the average amplitude is equivalent to 4 bits. In complex multiplication, 32 bits of data, which is four times the input data, are required as data before cumulative addition. However, if the amplitude is treated as a unit quantity, only 4 bits of average amplitude are required. Determining the upper limit of the number of bits required for calculations in this way makes it easier to design the H/W, and allows the use of small-scale H/W.

The complex correlation value calculated by the CA correlation processing unit 910 is called the first accumulated value XA. The first accumulated value XA is input to the power calculation unit 920. The power calculation unit 920 calculates the sum of the squares of the real and imaginary parts (i.e., power C). The averaging processing unit 930 stores the power C of the number of NA*NB chips (=NA*2NB samples=2NC samples) at SB/2 intervals calculated by the power calculation unit 920.

The averaging processing unit 930 calculates the average of the power C each time the power C of a sample at the same position among the 2NC samples is calculated. The averaging processing unit 930 stores the power C of 2NC first accumulated values XA calculated by multiplying and accumulating the first spreading code CA by shifting the received signal by one time point (one sample). The averaging processing unit 930 is a power memory unit that stores the power C of 2NC first accumulated values XA calculated by shifting the received signal by one time point.

The peak detection and determination unit 940 determines the time (sample) at which the 2NC powers C at SB/2 intervals stored in the averaging processing unit 930 reach their maximum peak. The peak detection and determination unit 940 determines the synchronization sequence position based on the time (sample) at which the power C reaches its maximum peak. Each of the 2NC powers C at SB/2 intervals is the power of a complex correlation value obtained by multiplying one received signal by spreading codes (2NC codes) at different positions. Each of the complex correlation values of the 2NC samples is the complex correlation value of a received signal that has been despread at a different code position. The synchronization sequence position is the code position at which the power of the complex correlation value is maximum.

The peak detection and determination unit 940 determines the spreading code phase correction value (-Δθ _PN ) based on the synchronization sequence position and notifies the despreader 7. For example, if the 0th sample is a peak, Δθ _PN =0. The synchronization sequence position is the position in the cascade concatenated code sequence length of the cascade concatenated spreading code PN that is multiplied by the received signal at discrete points in time. The synchronization acquisition circuit 9 determines the spreading code phase correction value (-θ _PN ), i.e., the synchronization sequence position.

After communication starts, the synchronization acquisition circuit 9 does not notify the despreader 7 of the spreading code phase correction value (-Δθ _PN ). After communication is interrupted, the synchronization acquisition circuit 9 operates again to determine the spreading code phase correction value (-Δθ _PN ) and notifies the despreader 7 of the determined spreading code phase correction value (-Δθ _PN ).

The process of calculating the average power C for each code position of the spreading code in the averaging processing unit 930 reduces the error at the point when the power C reaches its maximum peak due to the influence of noise.

The first accumulated value XA calculated by the CA correlation processing unit 910 is also input to the frequency deviation calculation unit 925. The frequency deviation calculation unit 925 calculates the frequency deviation ΔF based on the first accumulated value XA.

The operation control unit 945 controls the operation of the CA correlation processing unit 910 and the frequency offset calculation unit 925. The CA correlation processing unit 910 has a second differential phase value calculation unit 950, a first differential phase value calculation unit 960, and a code selection unit 970. The configuration of the CA correlation processing unit 910 will be described later. The operation control unit 945 outputs control signals G1, G2, G3, and G4. G1 controls the operation of the second differential phase value calculation unit 950. G2 controls the operation of the code selection unit 970. G3 controls the operation of the first differential phase value calculation unit 960. G4 controls the operation of the frequency offset calculation unit 925.

G4 indicates the operation mode of the synchronization acquisition circuit 9. The operation mode takes different values depending on whether the second differential phase value calculation unit 950, the first differential phase value calculation unit 960, and the code selection unit 970 are operating or not. The data of the first integrated value XA input to the frequency deviation calculation unit 925 changes depending on the operation mode. The frequency deviation calculation unit 925 processes the first integrated value XA and calculates the frequency deviation ΔF according to the operation mode notified by G4.

The CB correlation processing unit 901 includes a delay processing unit 121 and a second correlation value calculation unit 122. The delay processing unit 121 includes 2NB D-type flip-flops 902(1)-(2NB). The D-type flip-flops are hereinafter abbreviated as DFF, and in the figure are represented by a "D" written in a square. The second correlation value calculation unit 122 includes chip correlators 903(1)-(2NB) and an adder 904. The second correlation value calculation unit 122 calculates a second correlation value, which is the sum of the products of each complex BB signal included in NB consecutive chips and each second spreading code CB.

Every time SB/2 elapses, DFF 902(i) outputs the complex BB signal (BBI3+jBBQ3) that it holds to the subsequent DFF 902(i-1), and holds the complex BB signal (BBI3+jBBQ3) sent from the previous DFF 902(i+1).

The chip correlator 903(i) multiplies the complex BB signal (BBI3[i]+jBBQ3[i]) held in the DFF 902(i) by the second spreading code CB[m] according to the following equation (2), where m is calculated using the Gaussian notation as m=[(i+1)/2].
(BBI3[i]+jBBQ3[i])*CB[m]...(2)

The complex BB signal calculated by formula (2) is called the despread received signal GR. The chip correlator 903(i) is a despread received signal calculation unit that calculates the despread received signal obtained by multiplying each of the complex BB signals (BBI3[i]+jBBQ3[i]) generated from all the received signals included in the consecutive NB chips by the second spreading code CB[m] determined for each chip including the complex BB signal. The number of complex BB signals (2NB) generated from all the received signals included in the consecutive NB chips is called the second time point number. The number of chip correlators 903 in the CB correlation processing unit 901 is the second time point number. The number of chip correlators that the CB correlation processing unit has is called the second despread number. The total time point number 2NC is also the product of the second time point number 2NB and the first sequence length NA (2NC=2NB*NA).

Adder 904 adds the outputs of 2NB chip correlators 903(1)-(2NB) and outputs the second correlation value B, which is the addition result. The second correlation value B is a complex number representing the sum of the second number of despread received signals GR after despreading. Note that chip correlator 903(i) has a multiplier for BBI3 and a multiplier for BBQ3. Adder 904 also has an adder for BBI3 and an adder for BBQ3. Adder 904 is a second correlation value accumulator that calculates the second correlation value B.

The CA correlation processing unit 910 has a second differential phase value calculation unit 950, a code selection unit 970, MA unit first correlation value calculation units 221(1) to (MA), (MA-1) first differential phase value calculation units 960(1) to (MA-1), and an adder 914.

A new second correlation value B is input to the CA correlation processing unit 910 every time SB/2 has elapsed. The second differential phase value calculation unit 950 calculates the phase difference between the newly input second correlation value B and the second correlation value B input only NB chips ago. The second differential phase value calculation unit 950 then calculates the calculated phase difference and a second differential phase value VB having a unit amount of amplitude. The second differential phase value calculation unit 950 is controlled by the operation control unit 945 to calculate and output the second differential phase value VB, or to output the second correlation value B as is. Either the second differential phase value VB or the second correlation value B output by the second differential phase value calculation unit 950 is called the second accumulated value XB. The second differential phase value VB represents the phase difference between the second correlation value B at two points in time having a time difference equivalent to one chip of the spread code CA. The second differential phase value VB makes it easier to calculate the same complex number even when a frequency deviation exists. However, since the second correlation value B from two points in time is used, the influence of noise becomes greater.

The code selection unit 970 receives the first spreading code CA and generates and outputs a differential code CD, or outputs the first spreading code CA as is. The code selection unit 970 is controlled by the operation control unit 945 and outputs either the first spreading code CA or the differential code CD. The code selection unit 970 outputs the differential code CD during the period in which the second differential phase value calculation unit 950 outputs the second differential phase value VB. The code selection unit 970 outputs the first spreading code CA during the period in which the second differential phase value calculation unit 950 outputs the second correlation value B. The first spreading code CA or the differential code CD output by the code selection unit 970 is defined as the spreading code CX.

The unit first correlation value calculation unit 221(i) has DA delay circuits 911 (DA*i-DA+1) to (DA*i), DA chip correlators 912 (DA*i-DA+1) to (DA*i), and an adder 913(i). In the synchronization acquisition circuit 9, DA=4. m is an integer from 1 to NA. The output of the delay circuit 911(m) is connected to the input of the chip correlator 912(m). The delay circuit 911(m) is also connected to the input of the delay circuit 911(m-1).

The second accumulated value XB output by the second differential phase value calculation unit 950 is input to the delay circuit 911(NA) every time SB/2 has passed. The delay circuit 911(m) stores 2NB second accumulated values XB. The delay circuit 911(m) receives one second accumulated value XB every time SB/2 has passed, and outputs the second accumulated value XB input 2NB previously. The second accumulated values XB output by the delay circuits 911(m) for m=2 to NA are input to the chip correlator 912(m) and the delay circuit 911(m-1). The second accumulated value XB output by the delay circuit 911(1) is input to the chip correlator 912(1).

The delay circuit 911(m) may be realized by 2NB DFFs connected in series, or may be realized by a memory element such as a RAM (Random Access Memory) capable of storing 2NB or more complex numbers and a write reference circuit. When using a DPRAM (Dual Port Random Access Memory) capable of simultaneously writing and referencing as the delay circuit 911(m), a DPRAM capable of storing (2NB + 1) or more complex numbers is used.

The CA correlation processing unit 910 has DA*MA=NA chip correlators 912. Each chip correlator 912(m) multiplies the second accumulated value XB, which is an input complex number, by the spreading code CX[m]. The chip correlator 912(m) has a multiplier for the real part of the second accumulated value XB and a multiplier for the imaginary part of the second accumulated value XB. The output of the chip correlator 912(m) is the second accumulated value _GBm after despreading. When the second accumulated value XB is the second correlation value B, the second accumulated value _GBm after despreading is a value obtained by despreading the second correlation value B with the first spreading code CA. When the second accumulated value XB is the second differential correlation value WB, the second accumulated value _GBm after despreading is a value obtained by despreading the second differential correlation value WB with the differential code CD.

The 2NB chip correlators 903 are second despreading number of second despreading number calculation units, which calculate second despreading number of received signals, which are the second number of time points, and which calculate second despreading number of received signals, which are complex numbers obtained by multiplying each of the received signals in the second number of time points by each of the second spreading codes determined according to the position of the chip to which each of the received signals belongs in the second sequence length.

The NA chip correlators 912 are second accumulated value calculation units after despreading for the number of first sequence lengths, which receive the second accumulated values of the number of first sequence lengths calculated at each first chip time and the first spreading codes, and calculate the second accumulated values after despreading, which are complex numbers obtained by multiplying the second accumulated values by the first spreading codes.

The 2NB chip correlators 903 and the NA chip correlators 912 are despread received signal calculation units that calculate the despread received signals, which are complex numbers obtained by multiplying each of the received signals (the total number of time points) by each of the spreading codes determined according to the position in the sequence length of the chip to which each of the received signals belongs, the total number of time points.

The adder 913(i) adds the despread second accumulated values GB DA*i-DA ₊₁ to GB DA*i, which are the outputs of the DA chip correlators 912 (DA*i-DA+1) to ( _DA*i ), and outputs the unitary first correlation value UA _i, which is the addition result. The adder 913(i) has an adder for the real part of the unitary first correlation value UA _i and an adder for the imaginary part of the unitary first correlation value UA. The unitary first correlation value UA _i is the output of the unitary first correlation value calculation unit 221(i).

The unit first correlation value calculation unit 221(i) is DA unit first correlation value calculation units ordered by the despread second accumulated values GB _DA*i-DA+1 to GB _DA*i used in the calculation, which calculate a unit first correlation value UA _i , which is a complex number representing the sum of DA consecutive despread second accumulated values GB _DA*i-DA+1 to GB _DA*i . The unit first correlation value calculation units 221(1) to (MA) are also unit correlation value calculation units for the number of units that calculate unit correlation values. The unit first correlation value calculation units 221(i) are ordered by the despread second accumulated value GB _{DA*i-DA +1 using the received signal that was received the earliest among the despread second accumulated values GB DA*i-DA+1} to GB _DA*i used in the calculation.

The first differential phase value calculation unit 960(i) receives the unit first correlation values UA _i+1 and UA _i, which are complex numbers, and calculates a first differential phase value VA _i having a phase difference between UA _i+1 and UA _i and an amplitude of unit amount. The first differential phase value calculation unit 960(i) is controlled by the operation control unit 945 and outputs either the first differential phase value VA _i or the unit first correlation value UA _{i+1 .} The first differential phase value calculation unit 960(i) calculates the first differential phase value VA _i, which is a complex number having a phase difference between the unit first correlation value UA i+1 and the previous unit first correlation value UA _i . The first differential phase value calculation unit 960(i) is also a first selection output unit that uniformly switches and outputs either the unit first correlation value UA _i+1 or the first differential phase value VA _i . The output of the first differential phase value calculation section 960(i) is referred to as a unit first integrated value _UWAi .

The unit first correlation value UA _i is also a unit correlation value. The first differential phase value VA _i is also a differential phase value that is a complex number having a phase difference between the unit correlation value UA _i+1 and the previous unit correlation value UA _i . Each of the (MA-1) first differential phase value calculation units 960(1) to (MA-1) calculates each of the first differential phase values VA ₁ to VA _MA-1 . MA-1 is called a first differential number that is an integer obtained by subtracting 1 from the first division number MA. The first differential phase value calculation unit 960(i) is also a differential phase value calculation unit that calculates a differential phase value.

The first differential phase value calculation unit 960(i) may uniformly switch between either the unit first correlation value UA _i or the first differential phase value VA _i and output it. The first differential phase value calculation unit 960(i) is also a first selection output unit that uniformly switches between either the unit first correlation value UA _i+1 or UA _i, which is the earlier or newer of the two unit first correlation values UA _i+1 and UA _i inputted, and the first differential phase value VA _i and output it. The operation control unit 925 uniformly controls whether each first differential phase value calculation unit 960 outputs the unit first correlation value or the first differential phase value.

The adder 914 adds the unit first accumulated values UWA ₁ to UWA _MA-1 output by the (MA-1) first differential phase value calculation units 960(1) to (MA-1) and outputs the sum. The adder 914 has an adder for the real part of the complex number and an adder for the imaginary part. When the first differential phase value calculation unit 960(i) outputs the first differential phase value VA _i , the output of the adder 914 is the first differential correlation value WA which is the sum of the first differential phase values VA ₁ to VA _MA-1 . When the first differential phase value calculation unit 960(i) outputs the unit first correlation value UA _i+1 , the output of the adder 914 is called the first sum. The first sum is a complex number representing the sum of the NA despread second accumulated values GB ₁ to GB _NA . The adder 914 is a first sum calculation unit that calculates the first sum.

When the second differential phase value calculation unit 950 outputs the second correlation value B and the first differential phase value calculation unit 960(i) outputs the unit first correlation value UA _i+1 , the output of the adder 914 is the first correlation value A. When the second differential phase value calculation unit 950 outputs the second differential phase value VB and the first differential phase value calculation unit 960(i) outputs the unit first correlation value UA _i+1 , the output of the adder 914 is called the second differential correlation value WB. Note that when there is no frequency deviation, the second differential correlation value WB coincides with the first correlation value A.

The unit first correlation value _UA1 is not added to the first correlation value A output by the adder 914. A switch whose on/off is controlled by the operation control unit 945 may be provided between the unit first correlation value _UA1 and the adder 914. The operation control unit 945 controls the switch to be on when the first differential phase value calculation unit 960(i) outputs the unit first correlation value UAi ₊₁ . When the switch is provided, the adder 914 outputs the first correlation value A to which the unit first correlation value _UA1 has also been added.

When the first differential phase value calculation unit 960(i) outputs the first differential phase value VA _i , the adder 914 operates as a first differential correlation value calculation unit that calculates a first differential correlation value WA which is the sum of the (MA-1) first differential phase values VA _i . When the second differential phase value calculation unit 950 outputs the second correlation value B and the first differential phase value calculation unit 960(i) outputs the unit first correlation value UA _i+1 , the adder 914 operates as a first correlation value accumulating unit that calculates a first correlation value A. Any of the first differential correlation value WA, the first correlation value A, and the second differential correlation value WB output by the adder 914 is the first accumulated value XA.

Adder 914 is a correlation value accumulator that calculates correlation value A, which is a complex number representing the sum of 2NB*DA*(MA-1) despread received signals GR. Note that 2NB*DA*(MA-1)=2NC-2NB*DA*MA is the difference number obtained by subtracting the number of units 2NB*DA*MA from the number of despreads 2NC. Adder 914 may be any device that calculates the sum of despread received signals GR that is equal to or greater than the difference number and equal to or less than the number of despreads.

The first differential phase value VA is also a differential phase value. Therefore, the first differential correlation value WA is also a differential correlation value that is the sum of differential phase values VA that are equal to or greater than the difference number and equal to or less than the back-calculation diffusion number. When the first differential phase value calculation unit 960 is operating, the adder 914 is also a differential correlation value calculation unit that calculates a differential correlation value. When the first differential phase value calculation unit 960 is not operating, the adder 914 is a first sum calculation unit that calculates a first sum.

The second differential phase value VB is also a differential phase value. Therefore, the second differential correlation value WB is also a differential correlation value that is the sum of differential phase values VB that are equal to or greater than the number of differences and equal to or less than the number of back-calculated diffusions. When the second differential phase value calculation unit 950 is operating, the adder 914 is also a differential correlation value calculation unit that calculates the differential correlation value.

Each of the NA delay circuits 911 stores 2NB second accumulated values XB. The NA delay circuits 911 are second accumulated value storage units that store the second accumulated value XB of the total number of time points. Details will be described in the modified example below, but the second accumulated value storage unit only needs to store the second accumulated value XB of the saved number, which is a number equal to or greater than the integer obtained by multiplying the minimum number of units (NA-1), which is an integer obtained by subtracting 1 from the first sequence length (NA), by the second number of time points (2NB or NB).

The power calculation unit 920 calculates the power of the first accumulated value XA. In the synchronization acquisition circuit 9, the first accumulated value XA is the first differential correlation value WA when the first differential phase value calculation unit 960 operates. When the second differential phase value calculation unit 950 operates, the first accumulated value XA is the second differential correlation value WB. When the first differential phase value calculation unit 960 and the second differential phase value calculation unit 950 do not operate, the first accumulated value XA is the first correlation value A. When the first differential phase value calculation unit 960 does not operate, the second differential correlation value WB or the first correlation value A is the first total value. The first accumulated value XA is the first total value or the first difference is the correlation value WA.

The configuration of the second differential phase value calculation unit will be described with reference to FIG. 15. FIG. 15 is a diagram showing the configuration of the second differential phase value calculation unit included in the synchronization acquisition circuit according to the first embodiment. The second differential phase value calculation unit 950 includes an amplitude phase conversion unit 951, a delay circuit 952, a subtractor 953, an amplitude phase inverse conversion unit 954, and a SEL unit 955. The second differential phase value calculation unit 950 receives the second correlation value B every time SB/2 elapses. The amplitude phase conversion unit 951 converts the second correlation value B expressed in rectangular coordinates into values in polar coordinates of amplitude and phase. The input second correlation value B is expressed as B=BI+jBQ. The amplitude phase conversion unit 951 calculates the amplitude |B| and phase θ _B of the second correlation value B by the following formula.
|B|=√(BI ² + BQ ² )
θ _B = sin ⁻¹ (BQ/|B|)

The phase _θB output by the amplitude phase converter 951 is input to a delay circuit 952 and a subtractor 953. The delay circuit 952 delays by a time equivalent to NB chips (2NB samples). The time equivalent to NB chips (2NB samples) is equal to the first chip time SA. The phase θB _DELAY output by the delay circuit 952 is input to a subtractor 953. The subtractor 953 outputs a phase difference _ΔθB calculated by the following formula.
Δθ _B =θ _B -θ _BDELAY

The amplitude/phase inverse converter 954 receives the phase difference Δθ _B and outputs a second differential phase value VB=VBI+jVBQ, which is a complex number having a unit amplitude.
VB=exp(jΔθ _B )
VBI=cos(Δθ _B )
VBQ=sin(Δθ _B )
The second differential phase value VB is a complex number existing on a unit circle in a complex plane. When the frequency deviation ΔF is constant, the phase difference Δθ _B is constant at Δθ _B =2π*ΔF*SA.

The SEL unit 955 receives the second correlation value B and the second differential phase value VB. The SEL unit 955 receives the control signal G1 from the operation control unit 945. When the control signal G1 is ON, the SEL unit 955 outputs the second differential phase value VB. When the control signal G1 is OFF, the SEL unit 955 outputs the second correlation value B. The output of the SEL unit 955 is the output of the second differential phase value calculation unit 950. When the control signal G1 is ON, the second differential phase value calculation unit 950 operates to output the second differential phase value VB. When the control signal G1 is OFF, the second differential phase value calculation unit 950 does not operate and the second correlation value B is output.

The configuration of the code selection unit 970 will be described with reference to FIG. 16. FIG. 16 is a diagram showing the configuration of the code selection unit of the synchronization acquisition circuit according to the first embodiment. The first spreading code CA[k] is input to the code selection unit 970. The code selection unit 970 outputs the first spreading code CA[k] or the differential code CD[k]. The code selection unit 970 has a delay circuit 972 and a SEL unit 973. The operation control unit 945 controls the operation of the code selection unit 970 by the control signal G2. The delay circuit 972 delays CA[k] by one chip. In other words, the delay circuit 972 outputs CA[k-1]. The multiplier 971 multiplies CA[k] and CA[k-1]. The output of the multiplier 971 is the differential code CD[k].

It is shown that when the first spreading code CA[k] and the differential code CD[k] take the value "1" or "-1", the differential code CD[k] can be generated by a multiplier 971 and a delay circuit 972.
The difference code CD[k] takes two values: an unchanged value "1" and a changed value "-1" as shown below.
If CA[k]=CA[k-1], then CD[k]=“1”
If CA[k] ≠ CA[k-1], then CD[k] = "-1"

A multiplier 971 that multiplies CA[k] and CA[k-1] outputs the following value.
If CA[k] = CA[k-1] = "1", then CD[k] = "1"
If CA[k] = CA[k-1] = "-1", then CD[k] = "1"
If CA[k] = "1" and CA[k-1] = "-1", then CD[k] = "-1"
If CA[k] = "-1" and CA[k-1] = "1", then CD[k] = "-1"

The first spreading code CA[k] input to the code selection unit 970 and the differential code CD[k] output by the multiplier 971 are input to the SEL unit 973. The SEL unit 973 outputs either CA[k] or CD[k] according to the control signal G2 supplied from the operation control unit 945. When the control signal G2 is ON, it outputs CD[k]. When the control signal G2 is OFF, it outputs the input CA[k] as is. The output of the SEL unit 973 is the output of the code selection unit 970. The code output by the code selection unit 970 is CX[k]. When the control signal G2 is ON, the code selection unit 970 operates to output the differential code CD[k]. In other words, CX[k] = CD[k]. When the control signal G2 is OFF, the code selection unit 970 does not operate and outputs the first spreading code CA[k]. In other words, CX[k] = CA[k].

The difference code CD[1:NA] may be calculated in advance from the first spreading code CA[1:NA] and stored. The code selection unit 970 may output the stored difference code CD[k] for the input first spreading code CA[k]. The code selection unit 970 may be any type that can output the difference code CD[k] for the input first spreading code CA[k].

The control signals G1 and G2 have synchronized values. When the control signal G1 has an ON value, the control signal G2 also has an ON value. When the control signal G1 has an OFF value, the control signal G2 also has an OFF value. If there is no frequency deviation, the CA correlation processing unit 910 can calculate the same value of the first correlation value A in either case where the control signals G1 = G2 = ON or G1 = G2 = OFF.

The configuration of the first differential phase value calculation unit will be described with reference to FIG. 17. FIG. 17 is a diagram showing the configuration of the first differential phase value calculation unit of the synchronization acquisition circuit according to the first embodiment. The first differential phase value calculation unit 960(i) has an amplitude phase conversion unit 961, an amplitude phase conversion unit 962, a subtractor 963, an amplitude phase inverse conversion unit 964, and a SEL unit 965. The first differential phase value calculation unit 960 differs from the second differential phase value calculation unit 950 in that it does not have a delay circuit 952 and has an amplitude phase conversion unit 962.

The unit first correlation values UA _i+1 and UA _i are input to the first differential phase value calculation unit 960(i) every time SB/2 elapses. The amplitude and phase conversion unit 961 converts the unit first correlation value UA _i+1 expressed in rectangular coordinates into amplitude and phase polar coordinate values. The input unit first correlation value UA i ₊₁ is expressed as UA _i+1 = UAI _i+1 + jUAQ _i+1 . The amplitude and phase conversion unit 961 calculates the amplitude |UA _i+1 | and phase θ _UA(i+1) of the unit first correlation value UA _i+1 using the following formulas.
|UA _i+1 |=√(UAI _i+1 ² +UAQ _i+1 ² )
θ _UA(i+1) = sin ^-1 (UAQ _i+1 /|UA _i+1 |)

The amplitude-phase converter 962 converts the unit first correlation value UA _i expressed in Cartesian coordinates into amplitude and phase polar coordinate values. The amplitude-phase converter 962 calculates the amplitude |UA _i | and phase θ _UA(i) of the unit first correlation value UA _i by the following equations.
|UA _i |=√(UAI _i ² + UAQ _i ² )
θ _UA(i) = sin ⁻¹ (UAQ _i /|UA _i |)

The phase θ _UA(i+1) output by the amplitude phase converter 961 and the phase θ _UA(i) output by the amplitude phase converter 962 are input to a subtractor 963. The subtractor 963 outputs a phase difference Δθ _UA(i) calculated by the following equation.
Δθ _UA(i) =θ _UA(i+1) -θ _UA(i)

The amplitude/phase inverse converter 964 receives the phase difference Δθ _UA(i) and outputs a first differential phase value VA _i =VAI _i +jVAQ _i which is a complex number having a unit amplitude.
VA _i =exp(jΔθ _UA(i) )
VAI _i = cos(Δθ _UA(i) )
VAQ _i = sin(Δθ _UA(i) )
The first differential phase value VA _i is a complex number that exists on a unit circle in the complex plane.

The SEL unit 965 receives the unit first correlation value UA _i+1 and the first differential phase value VA _i . The SEL unit 965 receives a control signal G3 from the operation control unit 945. When the control signal G3 is ON, the SEL unit 965 outputs the first differential phase value VA _i . When the control signal G3 is OFF, the SEL unit 965 outputs the unit first correlation value UA _i+1 . The output of the SEL unit 965 is the output of the first differential phase value calculation unit 960(i). When the control signal G3 is ON, the first differential phase value calculation unit 960(i) operates to output the first differential phase value VA _i . When the control signal G3 is OFF, the first differential phase value calculation unit 960(i) does not operate and outputs the unit first correlation value UA _i+1 .

The frequency deviation calculation unit 925 calculates a frequency deviation ΔF based on the first integrated value XA output by the CA correlation processing unit 910. A control signal G4 is input to the frequency deviation calculation unit 925 from the operation control unit 945. The control signal G4 indicates whether the second differential phase value calculation unit 950 or the first differential phase value calculation unit 960 operates, or whether neither operates. The control signal G4 takes any of the following values, for example.
(Meaning of the value of control signal G4)
0: The second differential phase value calculation unit 950 and the first differential phase value calculation unit 960 are inactive.
1: The first differential phase value calculation unit 960 operates.
2: The second differential phase value calculation unit 950 operates.

When the second differential phase value calculation unit 950 and the first differential phase value calculation unit 960 do not operate (G4=0), the first integrated value XA is the first correlation value A. The frequency deviation calculation unit 925 receives the first correlation value A every time SB/2 elapses. The frequency deviation calculation unit 925 obtains a linear function that minimizes the square error that approximates the time change in the phase of the first correlation value A in the latest determined period TX. Based on the slope A _incl of the linear function, the frequency deviation ΔF=A _incl /(2π) is calculated. The slope A _incl is a value proportional to the frequency deviation, which is the time change rate of the phase. The frequency deviation calculation unit 925 calculates the frequency deviation ΔF based on the time change rate of the phase of the first correlation value A.

When the first differential phase value calculation unit 960 operates (G4=1), the first integrated value XA is the first differential correlation value WA. When the first differential phase value calculation unit 960 operates (G4=1), the phase of WA is a phase change caused by the frequency deviation ΔF in the time DA*SA. The average of the first differential correlation values WA input during the period TX is represented as WA _AV . When G4=1, the frequency deviation calculation unit 925 calculates ΔF by ΔF=WA _AV /(2π*DA*SA).

When the second differential phase value calculation unit 950 operates (G4=2), the first accumulated value XA is the second differential correlation value WB. The phase of the second differential correlation value WB, which is a complex number, is a phase change caused by the frequency deviation ΔF in the first chip time SA. When G4=2, the frequency deviation calculation unit 925 calculates ΔF by ΔF=WA _AV /(2π*SA). The frequency deviation calculation unit 925 calculates the frequency deviation ΔF based on the phase of the first differential correlation value WA or the second differential correlation value WB.

Referring to FIG. 14, points P ₁ to P ₆ indicating the signal of acquisition circuit 9 will be described.
Point _P1 is the input of the second differential phase value calculation unit 950. The signal measured at point _P1 is the second correlation value B. Point _P2 is the output of the second differential phase value calculation unit 950. The signal measured at point _P2 is the second accumulated value XB. The second accumulated value XB is the second differential phase value VB when the second differential phase value calculation unit 950 operates, and is the second correlation value B when the second differential phase value calculation unit 950 does not operate.

Points _P3,1 to _P3,NA are the outputs of chip correlators 912(1) to (NA). The signals measured at points _P3,1 to P3 _,NA are the second accumulated values _GB1 to _GBNA after despreading. Points _P4,1 to P4 _,MA are the outputs of adders 913(1) to (MA). Points _P4,1 to P4 _,MA are also the outputs of unit first correlation value calculation units 221(1) to (MA). The signals measured at points _P4,1 to P4 _,MA are the unit first correlation values _UA1 to _UAMA . Points _P5,1 to _P5,MA-1 are the outputs of first differential phase value calculation units 960(1) to (MA-1). The signals measured at _P5,1 to _P5,MA-1 are the unitary first accumulated values _UWA1 to _UWAMA-1 . When the first differential phase value calculation unit 960(i) operates, the unitary first accumulated value _UWAi is the first differential phase value _VAi . When the first differential phase value calculation unit 960(i) does not operate, the unitary first accumulated value _UWAi is the unitary first correlation value UAi ₊₁ .

Point _P6 is the output of the adder 914. Point _P6 is also the output of the CA correlation processing unit 910. The signal measured at point _P6 is the first accumulated value XA. When the second differential phase value calculation unit 950 and the first differential phase value calculation unit 960 do not operate (G4=0), the first accumulated value XA is the first correlation value A. When the first differential phase value calculation unit 960 operates (G4=1), the first accumulated value XA is the first differential correlation value WA. When the second differential phase value calculation unit 950 operates (G4=2), the first accumulated value XA is the second differential correlation value WB.

The operation will be described. At the start of communication, the operation control unit 945 outputs control signals G1=G2=ON, G3=OFF, and G4=2. The period during which the synchronization acquisition circuit 9 operates with the control signals G1=G2=ON, and G3=OFF is called the rough detection period. When the frequency deviation ΔF becomes smaller than the first threshold value _TH1 (ΔF< _TH1 ) during the rough detection period, the rough detection period ends and the fine detection period begins. During the fine detection period, the operation control unit 945 outputs control signals G1=G2=OFF, G3=ON, and G4=1. When the frequency deviation ΔF becomes small enough to be determined as zero during the fine detection period, the operation control unit 945 outputs control signals G1=G2=G3=OFF, and G4=0. Whether the frequency deviation ΔF is small enough to be determined as zero is determined by comparing it with a second threshold _TH2 (< _TH1 ) that is set smaller than the first threshold _TH1 . During the precise detection period, when the frequency deviation ΔF becomes smaller than the second threshold _TH2 (ΔF< _TH2 ), the precise detection is terminated.

The operation control section 945 outputs a control signal in the following cases.
(A) If ΔF≧ _TH1 (rough detection), G4=2, G1=G2=ON, and G3=OFF are output so that the second differential phase value calculation unit 950 operates.
(a) If TH ₁ >ΔF≧TH ₂ (precise detection), G4=1, G1=G2=OFF, and G3=ON are output so that the first differential phase value calculation unit 960 operates.
(c) If TH ₂ > ΔF, output G4=0, G1=G2=G3=OFF so that none of them operates.

The operating state of the acquisition circuit 9 during rough detection is as shown in Fig. 18. The second differential phase value calculation section 950 outputs the second differential phase value VB. The code selection section 970 outputs the differential code CD[m]. Fig. 19 shows a diagram on a complex plane of complex signals detected at points _P1 to _P6 of the acquisition circuit 9 in the operating state of Fig. 18. Fig. 19 shows complex signals when the cascade connection spreading code PN is synchronized. Here, NA=32, DA=4, and MA=8.

Point _P1 is the input of second differential phase value calculation unit 950. The signal measured at point _P1 is the second correlation value B. Point _P2 is the output of second differential phase value calculation unit 950. The signal measured at point _P2 is the second accumulated value XB. The second accumulated value XB is the second differential phase value VB when second differential phase value calculation unit 950 operates. Points _P3,1 to P3 _,NA are the outputs of chip correlators 912(1) to (NA). The signals measured at points _P3,1 to P3 _,NA are the second accumulated values _GB1 to _GBNA after despreading. Points _P4,1 to P4 _,MA are the outputs of adders 913(1) to (MA). The signals measured at points _P4,1 to P4 _,MA are the unit first correlation values _UA1 to _UAMA . Points _P5,1 to _P5,MA-1 are the outputs of the first differential phase value calculation units 960(1) to (MA-1). The signals measured at _P5,1 to _P5,MA-1 are the unit first accumulated values _UWA1 to _UWAMA-1 . The unit first accumulated value _UWAi is the unit first correlation value UAi ₊₁ when the first differential phase value calculation unit 960(i) does not operate. Point _P6 is the output of the adder 914. The signal measured at point _P6 is the first accumulated value XA. When the second differential phase value calculation unit 950 operates (G4=2), the first accumulated value XA is the second differential correlation value WB.

FIG. 19(A) shows the second correlation value B measured at point _P1 . FIG. 19(B) shows the second differential phase value VB measured at point _P2 . FIG. 19(C) shows the second accumulated values _GB1 to _GBNA after despreading measured at points _P3,1 to P3 _,NA . FIG. 19(D) shows the unit first correlation values _UA1 to _UAMA measured at points _P4,1 to P4 _{,MA .} FIG. 19(E) shows the unit first accumulated values _UWA1 to UWAMA _-1 measured at points P5,1 to _P5,MA-1 . FIG. 19(F) shows the second differential correlation value WB measured at point _P6 . In FIG. 19, the subscript t in _Bt , _VBt , and _WBt indicates time. The subscript t+1 indicates a time point when the first chip time SA has elapsed from the time point corresponding to the subscript t. _{GB_m} indicates the output of chip correlator 912(m). _{UA_m} indicates the output of adder 913(m). _{VA_m} indicates the output of first differential phase value calculation unit 960(m). _{GB_m} and _{UA_m} indicate values at the time point when _{VB_1} corresponds to _{GB_1} and _{VB_NA} corresponds to _{GB_NA} . That is, t=NA.

The second correlation value _Bt shown in FIG. 19A takes a value that can be calculated by the following formula.
B _t =CA[t]*NB*exp(j2πΔF*SA*t) t=1~NA
CA[t] is the first spreading code, and takes the value of "+1" or "-" randomly for each SA. _Bt is a complex signal that rotates at 2πΔF*SA and occasionally undergoes a phase change of 180 degrees (π radians). In Figure 19(A), this is the case where 2πΔF*SA≒0.49π radians, or about 88 degrees, of phase change occurs during SA.

The second differential phase value VB _t shown in FIG. 19B takes a value that can be calculated by the following formula.
VB _t = CD[t]*exp(j2πΔF*SA) t=1~NA
CD[t] is a differential code, and randomly takes the value of "+1" or "-" for each SA. VB _t is a complex number of amplitude 1 with a phase of 2πΔF*SA ≒ approximately 88 degrees or (π+2πΔF*SA) ≒ approximately 268 degrees. Note that the magnitude of the amplitude of |VB _t |=1 is equal to the amplitude of |B _t |=NB. The second differential phase value VB _t is a complex vector pointing in the same direction, although the randomness due to the value of the differential code remains.

The second accumulated value _GBm after despreading shown in Fig. 19C has a value that can be calculated by the following formula: where CD[m] ² = 1.
GB _m = CD[m]*VB _m = exp(j2πΔF*SA) m=1~NA
_GBm is a complex number with an amplitude of 1 having a phase of 2πΔF*SA≈approximately 88 degrees. The second despread accumulated value _GBm is a complex vector in the same direction. By operating the second differential phase value calculation unit 950 in this manner, the phases of the second despread accumulated values _GBm can be made the same, and the amplitude of the first correlation value A, which is the sum of the second despread accumulated values _GBm, can be increased.

The unit first correlation value UA _m shown in Fig. 19(D) is a complex number having a phase of 2πΔF*SA ≈ approximately 88 degrees and an amplitude of |UA _m | = DA = 4. Because the first differential phase value calculation units 960(1) to (NA-1) do not operate, the unit first correlation value UA _i+1 shown in Fig. 19(E) is also a complex number having a phase of 2πΔF*SA ≈ approximately 88 degrees and an amplitude of |UA _m+1 | = DA = 4. The second differential correlation value WB _NA shown in Fig. 19(F) is a complex number having a phase of 2πΔF*SA ≈ approximately 88 degrees and an amplitude of |WB _NA | = (NA-DA) = 28. When the first spreading code CA[m] is not synchronized, the second differential correlation value WB _m (m=1 to NA-1) becomes a complex number with a small amplitude |WB _m | having a phase of 2πΔF*SA≈about 88 degrees.

Fig. 20 shows a case where the second spreading code CB is not synchronized and the amplitude of the second correlation value B is 4. The second correlation value _Bt shown in Fig. 20(A) is a complex number whose amplitude is 4 instead of NB, as shown in the following formula.
B _t =CA[t]*4*exp(j2πΔF*SA*t) t=1~NA
Although the amplitudes are different, _Bm shown in FIG. 20(A) is a complex signal similar to _Bm shown in FIG. 19(A) in that the phase increases by 2πΔF*SA ≈ approximately 88 degrees every time m increases by 1, with occasional phase changes of 180 degrees (π radians) occurring.
The second differential phase value _VBt shown in Fig. 20(B) is the same as Fig. 19(B) since the amplitude is a unit quantity. The same is true for Fig. 20(C) and so on.

Fig. 21 shows a case where the second spreading code CB is not synchronized, the amplitude of the second correlation value B is less than 1, and the noise component is greater than the signal component. The second correlation value _Bm shown in Fig. 21(A) is a complex signal with an amplitude | _Bm | close to zero and a random phase. The second differential phase value _VBm and the second accumulated value after despreading _GBm are complex signals with a random phase and an amplitude of 1. The second differential correlation value _WBNA obtained by accumulating _GBm is also about 8.5 when the amplitude | _ANA | is as shown in Fig. 21, which is a small value of about 30% of the value when the second correlation value B is large.

When the second differential phase value calculation unit 950 is operating, the amplitude of the second differential correlation value WB output every time SB/2 passes is as shown in FIG. 22. Here, the case of NA=32, NB=8, and NC=256 is shown. In FIG. 22, the first correlation value A when the second differential phase value calculation unit 950 and the first differential phase value calculation unit 960 are not operating is shown by a dotted line, and the first correlation value A (shown by the symbol A0) when the frequency deviation ΔF=0 is shown by a dashed line. In the figure, the second differential phase value WB indicates a value divided by the maximum value at all code positions. The first correlation values A and A0 indicate values divided by the maximum value of A0 at all code positions.

In the period when the first spreading code CA is synchronized, the amplitude |WB| = amplitude |A0| = 1. The amplitude |A| of the first correlation value A is amplitude |A| < 0.1 at all code positions. By using the second differential correlation value WB, it is possible to detect the period when the first spreading code CA is synchronized even when the frequency deviation ΔF ≠ 0. Note that during the period when the first spreading code CA is synchronized, the amplitude |WB| of the second differential correlation value WB is amplitude |WB| = 1 even at code positions where synchronization is not achieved because the amplitude of VB is a unit quantity.

As a comparative example, a case will be described where the second differential phase value calculation unit 950 and the first differential phase value calculation unit 960 are not operated. FIG. 23 is a diagram showing an operating state where the second differential phase value calculation unit does not operate during rough detection of the synchronization acquisition circuit according to embodiment 1. FIG. 24 is a diagram showing complex signals measured in each unit when the second differential phase value calculation unit does not operate during rough detection of the synchronization acquisition circuit according to embodiment 1. This shows a case where the cascade connection spreading code PN is synchronized.

The second correlation value _Bt shown in Fig. 24(A) is the same as that shown in Fig. 19(A). Since the second differential phase value calculation unit 950 does not operate, the second correlation value _Bt is also measured at point _P2 . The second accumulated value _GBm after despreading shown in Fig. 24(C) takes a value that can be calculated by the following formula. Note that CA[m] ² = 1.
GB _m = CA[m]*VB _m = exp(j2πΔF*SA*m) m=1~NA
GB _m is a complex number with amplitude |GB _m |=1, which has a phase that is larger than GB _m-1 by 2πΔF*SA≈88 degrees. In FIG. 24(A), since 2πΔF*SA*DA≈88 degrees, the phases of GB _4k-3 , k=1 to MA are in the range of about 88 to 32 degrees, the phases of GB _4k- 2, k=1 to MA are in the range of about 176 to 120 degrees, the phases of GB _4k-3 , k=1 to MA are in the range of about 264 to 208 degrees, and the phases of GB _4k , k=1 to MA are in the range of about 344 to 296 degrees. In summary, GB _k , k=1 to NA are in four 56-degree ranges that are spaced 34 degrees apart from each other.

The unit first correlation value UA _m shown in Fig. 24(D) and (E) is a complex number with an amplitude |UA _m |≈0.10. The phase of UA _m is uniformly present in the range of about 220 to 156 degrees. The first correlation value _ANA shown in Fig. 24(F) is a complex number with an amplitude | _ANA |≈0.76 even when the cascade-connected spreading code PN is synchronized. When the second differential phase value calculation unit 950 operates, the amplitude | _ANA |=28, which is about 1/37. The amplitude | _ANA | is small, the effect of noise is large, and the accuracy of the synchronization sequence position is degraded. In this way, when the frequency deviation ΔF is large and the second integrated value GB _m after despreading is close to 350 degrees or exists dispersedly beyond 360 degrees, the amplitude of the first correlation value _ANA becomes a value close to zero, and it is difficult to accurately determine the synchronization sequence position of the spreading code.

As another comparative example, a case will be described where the second differential phase value calculation unit 950 is not operated, and the first differential phase value calculation unit 960 is operated. Figure 25 is a diagram showing an operating state where the first differential phase value calculation unit operates during rough detection of the synchronization acquisition circuit according to embodiment 1. Figure 26 is a diagram showing complex signals measured in each unit when the first differential phase value calculation unit operates during rough detection of the synchronization acquisition circuit according to embodiment 1. This shows a case where the cascade connection spreading code PN is synchronized.

In FIG. 25, since the second differential phase value calculation unit 950 does not operate, the signal measured at point _P2 is the second correlation value B. The code selection unit 970 outputs the first spreading code CA[m]. Since the first differential phase value calculation unit 960 operates, the signals measured at _P5,1 to P5 _,MA-1 are the first differential phase value _VAi . The signal measured at point _P6 is the first differential correlation value WA.

26(A)-(D) are the same as FIG. 24(A)-(D). The unit first correlation value UA _m shown in FIG. 26(D) is a complex number with an amplitude |UA _m |≈0.10. The first differential phase values VA ₁ to VA _MA-1 shown in FIG. 26(E) are complex numbers with an amplitude |VA _m |=1 and a phase of about -8 degrees. The first correlation value _ANA shown in FIG. 26(F) is a complex number with an amplitude | _ANA |=(MA-1) and a phase of about -8 degrees. Even when the second differential phase value calculation unit 950 is not operated and the first differential phase value calculation unit 960 is operated, the phases of the first differential phase values VA ₁ to VA _MA-1 are made almost the same, and the amplitude |WA _NA |=(MA-1) of the first differential correlation value WA _NA is set. The frequency deviation ΔF is calculated as a delay of 8 degrees over a time period four times SA, whereas in reality it is an advance of 88 degrees over the time SA. When the frequency deviation ΔF is large, it is not possible to calculate the frequency deviation ΔF based on the phase of the first correlation value _ANA calculated by operating the first differential phase value calculator 960 without operating the second differential phase value calculator 950.

Fig. 26 is a calculation ignoring noise components. When the noise components are large, the amplitude and phase of the unit first correlation value UA _m are considered to vary significantly from those shown in Fig. 26(E). When the noise components are large, the phases of the first differential phase values VA ₁ to VA _MA-1 are considered to be dispersed over a wide range, and the amplitude |A _NA | of the first correlation value _ANA is considered to be smaller than (MA-1).

In the first differential phase value calculation unit, when complex conjugates of one complex number are taken and complex multiplication is performed as in Patent Document 1, the first differential phase values VA ₁ to VA _MA-1 become complex numbers with amplitude |VA _m |≈0.010. This is about 1/160 compared to the amplitude |VA _m |=DA ² =16 when frequency deviation ΔF=0, and the accuracy of finding the synchronization sequence position of the spreading code decreases.

When the second differential phase value calculation unit 950 is operated and the frequency deviation ΔF becomes small, the operation control unit 945 controls the second differential phase value calculation unit 950 not to operate and controls the first differential phase value calculation unit 960 to operate. When the frequency deviation ΔF becomes small and the first differential phase value calculation unit 960 is operated, the complex signals measured in each unit of the synchronization acquisition circuit 9 become as shown in FIG. 27. The first differential phase value calculation unit 960 outputs the first differential correlation value WA. FIG. 27 is a diagram showing complex signals measured in each unit when the first differential phase value calculation unit operates during fine detection of the synchronization acquisition circuit according to the first embodiment. The frequency deviation ΔF in FIG. 27 is 1/8 of the frequency deviation ΔF in FIG. 26. That is, 2πΔF*SA≒0.061π radians≒11 degrees.

In the second correlation value _Bt shown in Fig. 27(A), _Bt and _Bt+1 are arranged with a phase difference of 2πΔF*SA≈11 degrees at the timing when CA[t] does not change. In the second accumulated value _GBm after despreading shown in Fig. 27(C), _GBm and _GBm+1 are arranged with a phase difference of 2πΔF*SA≈11 degrees. In the unit first correlation value _UAm shown in Fig. 27(D), _UAm and _UAm+1 are arranged with a phase difference of 2πΔF*SA*DA≈44 degrees. Therefore, the first differential phase value _VAm shown in Fig. 27(E) is a complex number with an amplitude of 1 and a phase of 2πΔF*SA*DA≈44 degrees. The first differential correlation value WA _NA shown in FIG. 27(F) is a complex number having a phase of 2πΔF*SA*DA≈44 degrees and an amplitude |WA _NA | of |WA _NA |=(MA-1).

When the frequency deviation ΔF is small, the frequency deviation ΔF can be detected by operating the first differential phase value calculation unit 960. When the first differential phase value calculation unit 960 operates, the amplitude of the first differential correlation value WA output every time SB/2 passes is as shown in FIG. 28. FIG. 28 also shows the first correlation value A and the first correlation value A0. FIG. 28 is a diagram showing the change in the amplitude of the first differential correlation value WA and the first correlation value A depending on the code position during fine detection of the synchronization acquisition circuit. The first differential phase value WA obtained by fine detection can detect the code position where the first spreading code CA and the second spreading code CB are synchronized. Since the amplitude of the first differential phase value VA is set to a unit quantity, during the period when the first spreading code CA is not synchronized, the amplitude |WA|>amplitude |A0|. 28 operates, the amplitude |WA _NA |=(MA-1), which is smaller than the amplitude |A|=NA. In the figure, the amplitude is shown as a value divided by the maximum value, so that in a period in which the first spreading code CA is not synchronized, the ratio of the amplitude |WA| to the amplitude |A0| is shown larger than it actually is.

Even if the frequency deviation ΔF is large, the synchronization acquisition circuit 9 can calculate the frequency deviation with higher accuracy than before and determine the synchronization sequence position of the spreading code.

Below, we will explain the variations of the first embodiment. Each variation can be freely combined with other variations. Each variation and any combination of multiple variations can also be applied to other embodiments.

First variant:
The configuration of a first modified example of the synchronization acquisition circuit according to the first embodiment will be described with reference to Fig. 29. Fig. 29 is a functional block diagram showing the configuration of a first modified example of the synchronization acquisition circuit according to the first embodiment. In the first modified example, a CB correlation processor calculates the sum of the products of the received signal at each SB and the second spreading code CB. The synchronization acquisition circuit 9A has a CB correlation processor 901A.

The CB correlation processing unit 901A comprises a delay processing unit 121A and a second correlation value calculation unit 122A. The delay processing unit 121A comprises (2NB-1) DFFs 902(1) to (2NB-1). The delay processing unit 121A has one less DFF than the delay processing unit 121. The second correlation value calculation unit 122A comprises NB chip correlators 903(2m-1), m=1 to NB. Each of the NB chip correlators 903(2m-1) receives the complex BB signal (BBI3[2m-1]+jBBQ3[2m-1]) output by the DFF 902(2m-1) and the second spreading code CB[m]. The adder 904A calculates the sum of NB complex numbers output by NB chip correlators 903 (2m-1), m=1 to NB. The second correlation value calculation unit 122A calculates the second correlation value B using the formula (1A) shown above. The second correlation value B calculated by the CB correlation processing unit 901A is a complex number representing the sum of NB despread received signals GR. The CB correlation processing unit 901A is a despread received signal accumulation unit that calculates the second correlation value B. In the CB correlation processing unit 901A, the second despread number is NB. The despread number is NC. The number of units is the value obtained by dividing NC by the number of units MA (NC/MA=NB*DA).

The NB chip correlators 903 of the synchronization acquisition circuit 9A are second despreading number of second sequence length post-despreading received signal calculation units that calculate the second despreading received signal, which is a complex number obtained by multiplying each of the received signals of the second sequence length number selected to have an interval of chip time by each of the second spreading codes determined according to the position of the chip to which each of the received signals belongs in the second sequence length.

NB chip correlators 903 and NA chip correlators 912 are despread received signal calculation units that calculate the despread received signals, which are complex numbers obtained by multiplying each of the received signals of the second sequence length by each of the spreading codes determined according to the position in the sequence length of the chip to which each of the received signals belongs, the number of despreads being the second sequence length.

The synchronization acquisition circuit 9A of the first modified example operates in the same manner as the synchronization acquisition circuit 9. The synchronization acquisition circuit 9A can calculate the frequency deviation with higher accuracy than before to determine the synchronization sequence position of the spreading code. The synchronization acquisition circuit 9A can calculate the second correlation value B using the same formula as in despreading. The change in the second correlation value B when the calculation time point increases or decreases by one near the peak is larger than when the second correlation value B is calculated using the received signal at all times with 2x oversampling. In addition, the synchronization acquisition circuit 9A can reduce the number of multipliers in the CB correlation processing unit 901A.

Second variant.
A second variant is when the spread spectrum receiver does not oversample the received signal, but instead generates a complex BB signal after every SB.
The configuration of a second modified example of the synchronization acquisition circuit according to embodiment 1 will be described with reference to Fig. 30. Fig. 30 is a functional block diagram showing the configuration of the second modified example of the synchronization acquisition circuit according to embodiment 1.

In the second modified example, the received signal is not oversampled, and a complex BB signal is input every time an SB passes. The synchronization acquisition circuit 9B has a CB correlation processing unit 901B, a CA correlation processing unit 910B, an averaging processing unit 930B, and a peak detection and determination unit 940B. A complex BB signal (BBI3+jBBQ3) is input to the synchronization acquisition circuit 9B every time an SB passes.

The CB correlation processing unit 901B includes a delay processing unit 121B and a second correlation value calculation unit 122B. The delay processing unit 121B includes NB DFFs 902(1) to (NB). The delay processing unit 121B has half the number of DFFs compared to the delay processing unit 121. The second correlation value calculation unit 122B includes NB chip correlators 903(1) to (NB). m is an integer ranging from 1 to NB. A second spreading code CB[m] is input to each of the NB chip correlators 903(m). The chip correlator 903(m) multiplies the complex BB signal (BBI3(m)+jBBQ3(m) output by the DFF 902(m) by CB[m].

The adder 904B calculates the sum of the NB complex numbers output by the NB chip correlators 903(1)-(NB). The second correlation value calculation unit 122B calculates the second correlation value B using the following formula.

ＣＢ相関処理部９０１Ｂでは、第２逆拡散個数および第２時点数はＮＢである。

In CB correlation processing section 901B, the second despreading number and the second time point number are NB.

The NB chip correlators 903 possessed by the synchronization acquisition circuit 9B are second despreading received signal calculation units for the second despreading number, which is the total number of time points, that calculate the second despreading received signal, which is a complex number obtained by multiplying each of the received signals, which is the total number of time points, by each of the second spreading codes determined according to the position of the chip to which each of the received signals belongs in the second sequence length.

NB chip correlators 903 and NA chip correlators 912 are despread received signal calculation units that calculate the despread received signals, which are complex numbers obtained by multiplying each of the received signals (the total number of time points) by each of the spreading codes determined according to the position in the sequence length of the chip to which each of the received signals belongs, the total number of time points.

The CA correlation processing unit 910B has unit first correlation value calculation units 221B(1) to (MA). In the unit first correlation value calculation unit 221B(i), DA delay circuits 911B (DA*i-DA+1) to (DA*i) are changed. The delay circuit 911B(m) stores NB second accumulated values XB. The delay circuit 911B(m) receives one second accumulated value XB every time SB elapses, and outputs the second accumulated value XB input NB times before.

Each of the NA delay circuits 911B stores NB second accumulated values XB. The NA delay circuits 911 are second accumulated value storage units that store the second accumulated values XB for the total number of time points.

The averaging processing unit 930B calculates the average of the power C each time the power C of a sample at the same position among the NC samples is calculated. The averaging processing unit 930B stores the power C of the NC first correlation values A calculated by shifting the received signal by one time point (one chip).

The peak detection and determination unit 940B determines the time when the N C powers C stored in the averaging processing unit 930B reach their maximum peak.

In the spread spectrum receiver without oversampling, components other than the synchronization acquisition circuit 9B are also modified. With reference to Figures 31 to 33, the configuration of a spread spectrum receiver using the second modified synchronization acquisition circuit according to embodiment 1 will be described. Figure 31 is a block diagram showing the configuration of a spread spectrum receiver using the second modified synchronization acquisition circuit according to embodiment 1. Figure 32 is a block diagram showing the configuration of a timing corrector provided in a spread spectrum receiver using the second modified synchronization acquisition circuit according to embodiment 1. Figure 33 is a block diagram showing the configuration of a despreader provided in a spread spectrum receiver using the second modified synchronization acquisition circuit according to embodiment 1.

As shown in FIG. 31, the spread spectrum receiver 1B of this modification differs from the spread spectrum receiver 1 of the first embodiment in the following points.
The spread spectrum receiver 1B includes a timing corrector 5B, a despreader 7B, and a synchronization acquisition circuit 9B instead of the timing corrector 5, the despreader 7, and the synchronization acquisition circuit 9 of the first embodiment. The spread spectrum receiver 1B does not include the synchronization tracking circuit 8 of the first embodiment.

As shown in FIG. 32, the timing corrector 5B differs from the timing corrector 5 of the first embodiment in that Rc is input to the NCO 54 instead of (2Rc-ΔRc). The timing corrector 5B does not oversample BBI1 and BBQ1 by a factor of two.

As shown in FIG. 33, the despreader 7B differs from the despreader 7 of embodiment 1 in that it does not include the first multiplier 71, the second multiplier 72, the fifth multiplier 75, the sixth multiplier 76, the first 1-sample delay circuit 78, the second 1-sample delay circuit 77, the first integration & thinning circuit 91, the second integration & thinning circuit 92, the fifth integration & thinning circuit 95, and the sixth integration & thinning circuit 96. This is because there is no oversampling, and therefore the despreader 7B only needs to output the complex BB signal (BBI4+jBBQ4).

The second modified synchronous acquisition circuit 9B operates in the same way as the synchronous acquisition circuit 9. Even if the frequency deviation ΔF is large, the synchronous acquisition circuit 9B can calculate the frequency deviation with higher accuracy than conventional circuits to determine the synchronous sequence position of the spreading code. Note that, since the received signal is not oversampled, the chip timing cannot be corrected by the synchronous tracking circuit.

Third variant.
The configuration of a third modified example of the synchronization acquisition circuit according to the first embodiment will be described with reference to Fig. 34. Fig. 34 is a functional block diagram showing the configuration of a third modified example of the synchronization acquisition circuit according to the first embodiment. In the third modified example, the second correlation value B calculated by the CB correlation processing unit 901 is input to a chip correlator 912 (NA) and a delay circuit 911 (NA-1). The synchronization acquisition circuit 9C has a CA correlation processing unit 910C.

In the CA correlation processing unit 910C, only the unit first correlation value calculation unit 221C (MA) has a different configuration from the unit first correlation value calculation units 221 (1) to (MA-1). The unit first correlation value calculation unit 221C (MA) does not have a delay circuit 911 (NA). The second accumulated value XB output by the second differential phase value calculation unit 950 every time SB/2 elapses and input to the unit first correlation value calculation unit 221C (MA) is input to the chip correlator 912 (NA) and delay circuit 911 (NA-1).

The CA correlation processing unit 910C has (NA-1) delay circuits 911 that store 2NB second correlation values B. (NA-1), i.e., the integer obtained by subtracting 1 from the first sequence length NA, is called the minimum number of units. The (NA-1) delay circuits 911 are second accumulated value storage units that store 2NB second correlation values B, i.e., the number obtained by multiplying the second time point number by the minimum number of units. The number of second correlation values B stored by the CA correlation processing unit may be equal to or greater than the integer obtained by multiplying the second time point number by the minimum number of units. The number of second correlation values B stored by the CA correlation processing unit is called the number of stored values. The number of stored values may be greater than the number obtained by multiplying the second time point number by the first sequence length. Specifically, there may be no delay circuit between the output of the second differential phase value calculation unit 950 and the inputs of the chip correlator 912 (NA) and the delay circuit 911 (NA-1), or there may be a delay circuit that stores any number of second correlation values B, one or more.

The third modified synchronization acquisition circuit 9C operates in the same manner as the synchronization acquisition circuit 9. Even when the frequency deviation ΔF is large, the synchronization acquisition circuit 9C can calculate the frequency deviation with higher accuracy than conventional circuits to determine the synchronization sequence position of the spread code. The synchronization acquisition circuit 9C has a simpler configuration by reducing the number of delay circuits or memories.

Fourth variant:
The configuration of a fourth modified example of the synchronization acquisition circuit according to the first embodiment will be described with reference to Fig. 35. Fig. 35 is a functional block diagram showing the configuration of the fourth modified example of the synchronization acquisition circuit according to the first embodiment. In the fourth modified example, a CA correlation processing unit 910D has a memory unit 224 instead of the delay circuit 911. The synchronization acquisition circuit 9D has a CA correlation processing unit 910D.

The CA correlation processing unit 910D has unit first correlation value calculation units 221D(1)-(MA), a write control unit 223, a memory unit 224, and a read control unit 225. The unit first correlation value calculation units 221D(1)-(MA) do not have delay circuits 911(1)-(NA). The second accumulated value XB output by the second differential phase value calculation unit 950 every time SB/2 has elapsed is written by the write control unit 223 to a specified address in the memory unit 224. The read control unit 225 reads out NA second accumulated values XB at intervals of 2NB samples.

The memory unit 224 has a single port and can store NN2 second correlation values B. However, NN2≧2NB*(NA-1)+1. The memory unit 224 can only be read or written at one time. Here, N _ALW =NN2-(2NB*(NA-1)+1). N _ALW indicates how much larger the number NN2 of second correlation values B that can be stored in the memory unit 224 is than the minimum number that must be stored. N _ALW ≧0. The second integrated value storage unit stores a stored number of second correlation values B that is equal to or larger than the second time point number multiplied by the minimum number of devices. The second integrated value storage unit may be any type of storage device that stores a stored number of second correlation values B.

The write control unit 223 writes the second correlation value B to the address specified by jw in the memory unit 224. jw=1 to NN2. jw increases by 1 in sequence. After jw=NN2, it returns to jw=1.

After writing the second correlation value B to the address specified by jw in the memory unit 224, the read control unit 225 reads out the NA second correlation values B output by the CB correlation processing unit 901 at intervals of 2NB samples from the memory unit 224. The read control unit 225 outputs the second correlation values B read out from the addresses jr[k], k=1 to NA in the memory unit 224 to the chip correlator 912(k) according to equation (3). Here, the difference between jw and jr[NA] is represented by the variable N _OST . _{N ALW} ≧N _OST ≧0.
jr[k]=mod(jw-N _OST +2NB*(k-NA), NN2)...(3)

The fourth modified example of the synchronization acquisition circuit 9D operates in the same manner as the synchronization acquisition circuit 9. Even if the frequency deviation ΔF is large, the synchronization acquisition circuit 9D can calculate the frequency deviation with higher accuracy than the conventional circuit and determine the synchronization sequence position of the spreading code.

Fifth variant:
The configuration of the fifth modified example of the synchronization acquisition circuit according to the first embodiment will be described with reference to FIG. 36. FIG. 36 is a functional block diagram showing the configuration of the fifth modified example of the synchronization acquisition circuit according to the first embodiment. In the fifth modified example, the second differential phase value calculation unit 950E and the first differential phase value calculation unit 960E calculate a differential phase value (first differential phase value or second differential phase value) as a complex number having a phase difference between two complex numbers by multiplying the complex conjugate of one complex number by the other complex number. The synchronization acquisition circuit 9E has a CA correlation processing unit 910E having the second differential phase value calculation unit 950E and the first differential phase value calculation unit 960E.

The configuration of the second differential phase value calculation unit 950E will be described with reference to FIG. 37. FIG. 37 is a diagram showing the configuration of the second differential phase value calculation unit of the fifth modified example of the synchronization acquisition circuit according to the first embodiment. The second differential phase value calculation unit 950E has a delay circuit 952, a complex conjugate unit 956, and a complex multiplier 957.

The second correlation value B is input to the second differential phase value calculation unit 950E every time SB/2 elapses. The delay circuit 952 delays by a time (=first chip time SA) equivalent to NB chips (2NB samples). The delay circuit 952 outputs the delayed second correlation value B _DELAY . The complex conjugate unit 956 calculates and outputs the complex conjugate B _DELAY ^* of the second correlation value B _DELAY . The complex multiplier 957 multiplies B and B _DELAY ^* as a complex number. The complex multiplier 957 calculates and outputs the second differential phase value VB by VB = B * B _DELAY ^* . The output of the second differential phase value calculation unit 950E is the second differential phase value VB.

The configuration of the first differential phase value calculation unit will be described with reference to FIG. 38. FIG. 38 is a diagram showing the configuration of the first differential phase value calculation unit of the fifth modified example of the synchronization acquisition circuit according to the first embodiment. The first differential phase value calculation unit 960E(i) has a complex conjugate unit 966 and a complex multiplier 967.

The first differential phase value calculation unit 960E(i) receives the unit first correlation values UA _i+1 and UA _i every time SB/2 elapses. The complex conjugate unit 966 calculates and outputs the complex conjugate UA _i ^* of the unit first correlation value UA _i . The complex multiplier 967 multiplies UA _i+1 and UA _i ^* as a complex number. The complex multiplier 967 calculates and outputs the first differential phase value VA _i = UA _{i + 1} * UA _i ^* . The output of the first differential phase value calculation unit 960E is the first differential phase value VA.

The synchronization acquisition circuit 9E of the fifth modified example operates in the same manner as the synchronization acquisition circuit 9. Even when the frequency deviation ΔF is large, the synchronization acquisition circuit 9E can calculate the frequency deviation with higher accuracy than conventional circuits to determine the synchronization sequence position of the spread code. Furthermore, the synchronization acquisition circuit 9E can detect the synchronization sequence position with higher accuracy than the synchronization acquisition circuit 9.

When the second differential phase value calculation unit 950E is operating, the amplitude of the second differential correlation value WB output every time SB/2 passes is as shown in FIG. 39. FIG. 39 is a diagram showing the change in amplitude of the second differential correlation value WB and the first correlation value A depending on the code position during rough detection by the synchronization acquisition circuit of the fifth modified example. As shown in FIG. 39, in the fifth modified example which uses the complex conjugate, the second differential correlation value WB reaches its maximum peak at the code position where the first spreading code CA and the second spreading code CB are synchronized. The second differential correlation value WB makes it possible to detect the code position where the first spreading code CA and the second spreading code CB are synchronized.

When the first differential phase value calculation unit 960E is operating, the amplitude of the first differential correlation value WA output every time SB/2 passes is as shown in Figure 40. Figure 40 shows the change in amplitude of the first differential correlation value WA and the first correlation value A depending on the code position during fine detection of the synchronization acquisition circuit of the fifth modified example.

The second differential phase value calculation unit 950E outputs a second differential phase value VB proportional to the amplitude of the input second correlation value B. The first differential phase value calculation unit 960E(i) outputs a first differential phase value VA _i proportional to the input unit first correlation values UA _i+1 and UA _i . Therefore, the second differential correlation value WB and the first differential correlation value WA calculate values that change depending on the amplitude of the second correlation value B used in the calculation. When the amplitude of the second correlation value B used in the calculation is large, the amplitudes of the second differential correlation value WB and the first differential correlation value WA become large. When the amplitude of the second correlation value B is small, the amplitudes of the second differential correlation value WB and the first differential correlation value WA become small. As a result, the synchronization acquisition circuit 9E can detect the synchronization sequence position taking into account the magnitude of the correlation result of the second correlation value B.

Sixth variant:
The configuration of a sixth modified example of the synchronization acquisition circuit according to the first embodiment will be described with reference to Fig. 41. Fig. 41 is a functional block diagram showing the configuration of a sixth modified example of the synchronization acquisition circuit according to the first embodiment. In the sixth modified example, the CA correlation processing unit 910F does not have a first differential phase value calculation unit 960. The synchronization acquisition circuit 9F has a CA correlation processing unit 910F.

The CA correlation processing section 910F does not have a first differential phase value calculation section 960. Since it does not have a first differential phase value calculation section 960, it does not have a unit first correlation value calculation unit 221 and an adder 913. The adder 914F adds the despread second accumulated values GB ₁ to GB _NA output by the chip correlators 912(1) to (NA). The operation control section 945F does not output a control signal G3.

Since the operation control unit 945F does not have the first differential phase value calculation unit 960, the operation control unit 945F does not output the control signal G3. The content of the control signal G4F is changed. The control signal G4F takes, for example, any of the following values. As the control signal G4F, G4F=0 or G4F=2 is output.
(Meaning of the value of control signal G4F)
0: The second differential phase value calculation unit 950 is inactive.
2: The second differential phase value calculation unit 950 operates.

When G4F = 0, the frequency deviation calculation unit 925F calculates the frequency deviation ΔF based on the time rate of change of the phase of the first correlation value A. When G4F = 2, the frequency deviation calculation unit 925F calculates the frequency deviation ΔF based on the phase of the second differential correlation value WB.

The operation control section 945F outputs a control signal in the following cases.
(A) If ΔF≧ _TH1 (rough detection), G4F=2 and G1=G2=ON are output so that the second differential phase value calculation unit 950 operates.
(a) If TH ₁ >ΔF, G4F=0 and G1=G2=OFF are output so that the second differential phase value calculation unit 950 is not operated.

In the synchronization acquisition circuit 9F, the first accumulated value XA is the second differential correlation value WB when the second differential phase value calculation unit 950 is operating. When the second differential phase value calculation unit 950 is not operating, the first accumulated value XA is the first correlation value A.

The acquisition circuit 9F of the sixth modification operates in the same manner as the acquisition circuit 9. Even when the frequency deviation ΔF is large, the acquisition circuit 9F can calculate the frequency deviation with higher accuracy than the conventional circuit to obtain the synchronization sequence position of the spread code. However, in the acquisition circuit 9F, the second differential phase value calculator 950 operates when ΔF is equal to or larger than the first threshold value _TH1 (ΔF≧ _TH1 ). When the frequency deviation ΔF is smaller than the first threshold value _TH1 (ΔF< _TH1 ), the second differential phase value calculator 950 does not operate.

Seventh variant:
The configuration of a seventh modified example of the synchronization acquisition circuit according to the first embodiment will be described with reference to Fig. 42. Fig. 42 is a functional block diagram showing the configuration of a seventh modified example of the synchronization acquisition circuit according to the first embodiment. In the seventh modified example, the first correlation value A can be calculated including the unit first correlation value _UA1 output by the unit first correlation value calculation unit 221(1). The synchronization acquisition circuit 9G has a CA correlation processing section 910G.

The CA correlation processing unit 910G has a switch 996. The switch 996 is provided between the output of the unit first correlation value calculation unit 221 (1) and the adder 914. The switch 996 is controlled to be turned on and off by a control signal G5 output by the operation control unit 945G. The control signal G5 is turned on when the control signal G3 that controls the operation of the first differential phase value calculation unit 960 is turned off. When the control signal G5 is turned on, the switch 996 is turned on. When the control signal G3 is turned on, the control signal G5 is turned off and the switch 996 is turned off. When the switch 996 is turned on, the switch 996 outputs the unit first correlation value UA _1. When the switch 996 is turned off, the switch 996 outputs zero. By controlling the on and off of the switch 996 in this way, the first correlation value A can be calculated, including the unit first correlation value UA ₁ output by the unit first correlation value calculation unit 221 (1).

The operation control section 945G outputs control signals G1, G2, G3, G4, and G5. The operation control section 945G outputs control signals in the following cases.
(A) If ΔF≧ _TH1 , the second differential phase value calculation unit 950 operates to output G1=G2=ON, G3=OFF, G4=2, and G5=ON so that the second differential correlation value WB can be calculated including _{the unit} first correlation value UA1.
(a) If TH ₁ >ΔF≧TH ₂ , G4=1, G1=G2=OFF, G3=ON, and G5=OFF are output so that the first differential phase value calculation unit 960 operates.
(c) If TH ₂ > ΔF, none of them operate, and G4=0, G1=G2=G3=OFF, and G5= _ON are output so that the first correlation value A can be calculated including the unit first correlation value UA 1.

When an OFF control signal G3 is input to the unitary first correlation value calculation unit 221(i), the unitary first correlation value calculation unit 221(i) may output the unitary first correlation value UA _i . In this case, the switch 996 is provided between the output of the unitary first correlation value calculation unit 221(MA) and the adder 914. In this case as well, the on/off of the switch 996 is controlled by the control signal G5 in the same manner as described above.

The switch 996 is a first switch provided between the output of the most recent unit first correlation value calculation unit 221(1) or the output of the most recent unit first correlation value calculation unit 221(MA) and the adder 914, and switches between an input complex number or zero and outputs the result. The adder 914 is a first adder that outputs the sum of the outputs of the first selection output units. When the first differential phase value calculation unit 960(i) outputs the previous unit first correlation value UA _i , the output of the most recent unit first correlation value calculation unit 221(MA) is input to the switch 996. When the first differential phase value calculation unit 960(i) outputs the newer unit first correlation value UA _i+1 , the output of the most recent unit first correlation value calculation unit 221(1) is input to the switch 996.

The acquisition circuit 9G of the seventh modification operates in the same manner as the acquisition circuit 9. Even when the frequency deviation ΔF is large, the acquisition circuit 9G can calculate the frequency deviation with higher accuracy than in the past to determine the synchronization sequence position of the spreading code. The acquisition circuit 9G has a first differential phase value calculation section 960, and can calculate the second differential correlation value WB and the first correlation value A, including the unitary first correlation value _UA1 output by the unitary first correlation value calculation unit 221(1).

Eighth variant:
The configuration of an eighth modified example of the synchronization acquisition circuit according to the first embodiment will be described with reference to Fig. 43. Fig. 43 is a functional block diagram showing the configuration of an eighth modified example of the synchronization acquisition circuit according to the first embodiment. In the eighth modified example, the first correlation value accumulator and the first difference correlation value calculator each have an adder. The synchronization acquisition circuit 9H has modified CA correlation processor 910H and operation controller 945H.

The CA correlation processing unit 910H has a first differential phase value calculation unit 960H(1)-(MA-1), an adder 915, and a switch 916. The configuration of the first differential phase value calculation unit 960H is shown in FIG. 44. The first differential phase value calculation unit 960H does not have a SEL unit 965. The first differential phase value calculation unit 960H(1)-(MA-1) always outputs the first differential phase values VA ₁ -VA _MA-1 when operating. The operation of the first differential phase value calculation unit 960H is controlled by a control signal G3. When the control signal G3 is ON, the first differential phase value calculation unit 960H operates. When G3 is OFF, the first differential phase value calculation unit 960H does not operate.

The adder 914 adds the first differential phase values VA ₁ to VA _MA-1 output from the (MA-1) first differential phase value calculation units 960H(1) to (MA-1) and outputs a first differential correlation value WA.

The unitary first correlation values UA ₁ to UA _MA output by the unitary first correlation value calculation units 221(1) to (MA) are input to the adder 915. The adder 915 outputs a first correlation value A which is the sum of UA ₁ to UA _MA .

The operation control unit 945H outputs control signals G1, G2, G3, G4, and G6. The control signal G6 is a control signal that switches the connection source of the switch 916.

The switch 916 switches between the output of the adder 914 or the output of the adder 915 and outputs it as the output of the CA correlation processing unit 910H. The switch 916 is controlled by a control signal G6. G6 and G3 have related values. When G3 is ON, G6 sets the adder 914 as the connection source. The switch 916 outputs the first differential correlation value WA. When G3 is OFF, G6 sets the adder 915 as the connection source. The switch 916 outputs the first correlation value A. By controlling the switch 916 in this way, when the first differential phase value calculation unit 960H operates, the CA correlation processing unit 910H outputs the first differential correlation value WA. When the first differential phase value calculation unit 960H does not operate, the CA correlation processing unit 910H outputs the first correlation value A or the second differential correlation value WB.

The operation control section 945H outputs a control signal in the following cases.
(A) If ΔF≧ _TH1 , the second differential phase value calculation unit 950 operates to output G4=2, G1=G2=ON, G3=OFF, and G6=adder 915 so as to output the second differential correlation value WB.
(a) If TH ₁ > ΔF≧TH ₂ , the first differential phase value calculation unit 960 operates to output G4=1, G1=G2=OFF, G3=ON, and G6=adder 914 so as to output the first differential correlation value WA.
(c) If TH ₂ >ΔF, none of the circuits operate, and G4=0, G1=G2=G3=OFF, and G6=adder 915 outputs so that the first correlation value A is output.

The eighth modified embodiment of the synchronization acquisition circuit 9H operates in the same manner as the synchronization acquisition circuit 9. Even if the frequency deviation ΔF is large, the synchronization acquisition circuit 9H can calculate the frequency deviation with higher accuracy than conventional circuits and determine the synchronization sequence position of the spreading code.

Ninth variant:
The configuration of a ninth modification of the synchronization acquisition circuit according to the first embodiment will be described with reference to Fig. 45. Fig. 45 is a functional block diagram showing the configuration of the ninth modification of the synchronization acquisition circuit according to the first embodiment. In the ninth modification, when the frequency change rate, which indicates the degree of time change of the frequency deviation, is large, the second differential phase value calculation unit and the first differential phase value calculation unit are operated simultaneously. In the synchronization acquisition circuit 9J, the operation control unit 945J and the frequency deviation calculation unit 925J are modified.

When the frequency change rate is zero or small, the second differential phase value VB calculated by the second differential phase value calculation unit 950 and the first differential phase value VA calculated by the first differential phase value calculation unit 960 are complex vectors having a phase determined by the frequency deviation ΔF. By accumulating VB or VA, which are complex vectors in the same direction, the second differential correlation value WB or the first differential correlation value WA can be made large. As a result, even when the frequency deviation ΔF is large, the synchronization sequence position can be calculated with higher accuracy than before.

When the frequency change rate is large enough to be unnegligible, the phase of the second differential phase value VB calculated by the second differential phase value calculation unit 950 changes according to the frequency change rate. When the first differential phase value calculation unit 960 is operated on the second differential phase value VB to calculate the first differential phase value VA, the phase of the first differential phase value VA becomes a value according to the frequency change rate. When the frequency change rate is a constant value other than zero, the phase of the first differential phase value VA obtained when the second differential phase value calculation unit 950 and the first differential phase value calculation unit 960 are operated becomes a constant value according to the frequency change rate. The first differential phase value VA becomes a complex vector in the same direction, and by adding VA, it is possible to determine whether the code of the spreading code has been obtained based on the amplitude |VA| of VA. Therefore, even if the frequency change rate is not zero, the synchronization sequence position can be obtained with higher accuracy than before.

The operation control section 945J controls, based on the frequency deviation ΔF and the frequency change rate _Fdiff , whether to operate the second differential phase value calculation section 950 and the first differential phase value calculation section 960. The operation control section 945J outputs control signals G1, G2, G3, and G4J.
The frequency change calculation unit 925J calculates the frequency deviation ΔF and the frequency change rate F _diff .

The phase of the first integrated value XA output by the CA correlation processor 910 is proportional to the frequency change rate _Fdiff when the second differential phase value calculator 950 and the first differential phase value calculator 960 operate simultaneously. The output of the CA correlation processor 910 when the second differential phase value calculator 950 and the first differential phase value calculator 960 operate simultaneously is called a differential phase value VC.
The control signal G4J output by the operation control unit 945J has the following values.
(Meaning of the value of control signal G4J)
0: The second differential phase value calculation unit 950 and the first differential phase value calculation unit 960 are inactive.
1: The first differential phase value calculation unit 960 operates.
2: The second differential phase value calculation unit 950 operates.
3: The second differential phase value calculation unit 950 and the first differential phase value calculation unit 960 operate.

The frequency change calculation unit 925J changes the calculation method in response to the control signal G4J to calculate the frequency deviation ΔF and the frequency change rate _Fdiff . ΔF and _Fdiff calculated by the frequency change calculation unit 925J are input to the operation control unit 945J.

The frequency change calculation unit 925J calculates the frequency deviation ΔF and the frequency change rate F _diff based on the first accumulated value XA input from the CA correlation processing unit 910. When the second differential phase value calculation unit 950 and the first differential phase value calculation unit 960 do not operate (G4J = 0), the first accumulated value XA is the first correlation value A. The frequency change calculation unit 925J obtains a quadratic function that minimizes the square error that approximates the time change of the phase of the first correlation value A input in the latest determined period TX. The frequency change calculation unit 925J calculates the frequency change rate F _diff = A _ACC / (2π) based on the coefficient A _ACC of the quadratic term of the quadratic function that approximates the time change of the obtained phase. The frequency change calculation unit 925J calculates the frequency deviation ΔF as ΔF = A _incl2 / (2π) based on the slope A _incl2 of the tangent at the latest point in time of the period TX of the quadratic function.

When only one of the second differential phase value calculator 950 or the first differential phase value calculator 960 operates (G4J=2 or G4J=1), the frequency change calculator 925J finds a linear function that minimizes the square error that approximates the time change in the phase of the first accumulated value XA input during the period TX. When G4J=2, the first accumulated value XA is the second differential correlation value WB. The frequency change calculator 925J calculates _Fdiff by _Fdiff = _{XAincl/(2π*SA) based on the slope XAincl of the found linear function. The frequency change calculator 925J calculates ΔF by ΔF=XAlatest / (} 2π*SA) based on the value _XAlatest of the linear function at the latest point in time during the period TX. When G4J=1, the first accumulated value XA is the first differential correlation value XA. The frequency change calculation unit 925J calculates _Fdiff as follows: _Fdiff = _XAincl /(2π*DA*SA), and calculates ΔF as follows: ΔF= _XAlatest /(2π*DA*SA).

When the second differential phase value calculator 950 and the first differential phase value calculator 960 operate (G4J=3), the first integrated value XA is the differential phase value VC. The differential phase value VC is the amount of change in the phase change amount DA*SA occurring in the first chip time SA over time. Based on XA _AV, which is the average of XA over the period TX, the frequency change calculator 925J calculates F _diff as F _diff =XA _AV /(2π*DA*SA ² ). The frequency change calculator 925J calculates ΔF by integrating XA. It is also possible to calculate F _diff over a period TY that is shorter than TX, and then integrate F _diff to calculate ΔF.

In the synchronization acquisition circuit 9J, the first accumulated value XA is the differential phase value VC when the second differential phase value calculation unit 950 and the first differential phase value calculation unit 960 operate. When the second differential phase value calculation unit 950 operates and the first differential phase value calculation unit 960 does not operate, the first accumulated value XA is the second differential correlation value WB. When the second differential phase value calculation unit 950 does not operate and the first differential phase value calculation unit 960 operates, the first accumulated value XA is the first differential correlation value WA. When the second differential phase value calculation unit 950 and the first differential phase value calculation unit 960 do not operate, the first accumulated value XA is the first correlation value A.

The operation will now be described. The operation control section 945J operates the second differential phase value calculation section 950 and the first differential phase value calculation section 960 when the frequency change rate _Fdiff is equal to or greater than the change rate _threshold THdiff ( _Fdiff ≧ _THdiff ).

When _Fdiff is smaller than _THdiff ( _Fdiff < _THdiff ), the operation control unit 945J operates in the same manner as the operation control unit 945. When _Fdiff < _THdiff and ΔF≧ _TH1 , the operation control unit 945J operates the second differential phase value calculation unit 950 and does not operate the first differential phase value calculation unit 960. When _Fdiff < _THdiff and _TH1 >ΔF≧ _TH2 , the operation control unit 945J does not operate the second differential phase value calculation unit 950 and operates the first differential phase value calculation unit 960. When _Fdiff < _THdiff and _TH2 >ΔF, the operation control unit 945J does not operate the second differential phase value calculation unit 950 and the first differential phase value calculation unit 960.

The operation control section 945J outputs a control signal in the following cases.
(A) If F _diff ≧TH _diff , then G4J=3, G1=G2=G3=ON are output so that the second differential phase value calculation unit 950 and the first differential phase value calculation unit 960 operate.
(a) If F _diff <TH _diff and ΔF≧ _TH1 , then G4J=2, G1=G2=ON, and G3=OFF are output so that the second differential phase value calculation unit 950 operates.
(c) If F _diff < TH _diff and TH ₁ > ΔF≧TH ₂ , G4J=1, G1=G2=OFF, and G3=ON are output so that the first differential phase value calculation unit 960 operates.
(d) If F _diff < TH _diff and TH ₂ > ΔF, output G4J=0 and G1=G2=G3=OFF so that none of them operates.

Fig. 46 shows an operating state in which the second differential phase value calculator 950 and the first differential phase value calculator 960 operate. The second differential phase value calculator 950 outputs the second differential phase value VB. The code selector 970 outputs the differential code CD[m]. The first differential phase value calculator 960 outputs the first differential correlation value VA. Fig. 47 shows a diagram in which complex signals detected at points _P1 to _P6 of the synchronization acquisition circuit 9J in the operating state of Fig. 46 are displayed on a complex plane. Fig. 47 shows complex signals when the cascade connection spreading code PN is synchronized.

The second correlation value _Bm shown in Fig. 47(A) is a complex signal that rotates with an increasing rotation speed (2πΔF) and occasionally generates a phase change of 180 degrees (π radians). In Fig. 47(A), the phase change amount (2πΔF*SA) in the first chip time SA increases from about 90 degrees to about 150 degrees while TP, which is the time of one period of the cascade-concatenated spreading code PN, has passed.

The second differential phase value VB _m shown in Figure 47 (B) is a complex number of amplitude 1 that randomly falls within either range 1 of approximately 90 degrees to approximately 150 degrees or range 2 of approximately 270 degrees to 330 degrees, and has a phase that increases over time within range 1 and range 2.

The second accumulated value _GBm after despreading shown in FIG. 47C is a complex number with an amplitude of 1 and a phase that increases over time in a range 1 from about 90 degrees to about 150 degrees.

The unit first correlation values UA _m , m=1 to MA shown in FIG. 47(D) are complex numbers having an angle of θ _UA(m) ≈84+8*m (degrees) and an amplitude of approximately DA.

47(E) is a complex _{number having a phase θ VA of about 8 degrees and an amplitude of 1. The phase θ VA of the} first differential phase value VA _m is a frequency change that occurs during the SA time.

The differential phase value VC ₃₂ shown in Figure 47(F) is a complex number of amplitude (MA-1) with a phase θ _VA of approximately 8 degrees. The frequency change rate F _diff can be calculated as F _diff = θ _VA /(2π*SA).

As a comparative example, Fig. 48 shows complex signals detected at points P ₁ to P ₆ of acquisition circuit 9J on a complex plane when only second differential phase value calculation unit 950 is operated with the same received signal as in Fig. 47. Fig. 48 shows complex signals when cascade-connected spreading code PN is synchronized. Figs. 48(A) to (D) are the same as Figs. 47(A) to (D). Since first differential phase value calculation unit 960 does not operate, unit first correlation values UA _m+1 , m=1 to MA-1 are output to points P _5,m , m=1 to MA-1, as shown in Fig. 48(E).

The first differential correlation value WA shown in Fig. 48(F) is a complex number having an amplitude of about 0.95*NA and a phase of about 124 degrees. Due to the influence of the frequency change rate _Fdiff , the amplitude |WA| of WA becomes 0.96 times the amplitude |WA| when _Fdiff =. The phase _θWA of WA becomes a value near the center of the range in which GB changes.

When the frequency change rate _Fdiff becomes larger, the amplitude |WA| becomes smaller when only the second differential phase value calculation unit 950 is operated, the effect of noise becomes larger, and the detection accuracy of the frequency deviation ΔF decreases. When the second differential phase value calculation unit 950 and the first differential phase value calculation unit 960 are operated, the amplitude |WA| does not change even if _Fdiff becomes larger, and _θWA proportional to _Fdiff is obtained.

When the frequency change rate _Fdiff is equal to or greater than the change rate threshold value _THdiff ( _Fdiff ≧ _THdiff ), by operating the second differential phase value calculation unit 950 and the first differential phase value calculation unit 960, it is possible to calculate the frequency deviation ΔF with higher accuracy than when only the second differential phase value calculation unit 950 is operated.

Tenth variant:
The configuration of a tenth modification of the synchronization acquisition circuit according to the first embodiment will be described with reference to Fig. 49. Fig. 49 is a functional block diagram showing the configuration of a tenth modification of the synchronization acquisition circuit according to the first embodiment. In the tenth modification, the synchronization acquisition circuit 9J of the ninth modification is further modified so that a frequency change calculation unit is provided outside the synchronization acquisition circuit. The synchronization acquisition circuit 9K does not have a frequency deviation calculation unit. The frequency deviation calculation unit 925K is provided outside the synchronization acquisition circuit. The frequency deviation calculation unit 925K calculates the frequency deviation and the frequency change rate using information from the synchronization acquisition circuit 9J and also information other than that from the synchronization acquisition circuit.

The frequency deviation calculation unit 925K receives the first integrated value XA output by the CA correlation processing unit 910. Other information is also input to the frequency deviation calculation unit 925K. Other information does not need to be input to the frequency deviation calculation unit 925K. The operation control unit 945K receives the frequency deviation ΔF and the frequency change rate _Fdiff calculated by the frequency deviation calculation unit 925K. The frequency deviation ΔF calculated by the frequency deviation calculation unit 925K is input to the quadrature detector 2.

The synchronization acquisition circuit 9K of the tenth modification operates in the same manner as the synchronization acquisition circuit 9J. Even if the frequency deviation ΔF is large, the synchronization acquisition circuit 9K can calculate the frequency deviation with higher accuracy than the conventional circuit and determine the synchronization sequence position of the spreading code. Furthermore, since the frequency deviation calculation unit 925K is located outside the synchronization acquisition circuit 9K, the frequency deviation calculation unit 925K can use information other than that which can be calculated by the synchronization acquisition circuit 9K to calculate the frequency deviation ΔF and the frequency change rate _Fdiff with higher accuracy.
The above also applies to the other embodiments and their modifications.

Embodiment 2.
The configuration of the synchronization acquisition circuit according to the second embodiment will be described with reference to Fig. 50. Fig. 50 is a functional block diagram showing the configuration of the synchronization acquisition circuit according to the second embodiment. In the second embodiment, the first embodiment is modified so that the differential phase value is also calculated inside the CB correlation processor so as to be able to handle the case where the frequency deviation ΔF is larger. Each of the modified examples of the first embodiment may be modified. The second sequence length NB is expressed as the product of the second division number MB, which is an integer of 3 or more, and the second unit number DB, which is an integer of 2 or more. That is, NB = MB * DB.

The synchronization acquisition circuit 9L has a modified CB correlation processing unit 901L and operation control unit 945L. The CB correlation processing unit 901L has a second correlation value calculation unit 122L. The second correlation value calculation unit 122L has MB adders 904L instead of the adder 904. The second correlation value calculation unit 122L has (MB-1) unit second differential phase value calculation units 905, a switch 906, and an adder 907.

The control signal G4 is changed to G4L. The operation control unit 945L outputs control signals G7 and G8 in addition to the control signals G1, G2, G3, and G4L. G7 controls the operation of the unit second differential phase value calculation unit 905. G8 controls the on/off of the switch 906. G4L also has a value that indicates the operation mode in which the unit second differential phase value calculation unit 905 operates.

The adder 904L(i) adds the despread received signals GR _2DB*i-2DB+1 to GB _{2DB*i which are the outputs of the 2DB chip correlators 902 (2DB*i-2DB+1) to (2DB*i} ), and outputs the unit second correlation value UB _i which is the addition result. The adder 904L(i) has an adder for the real part of the unit second correlation value UB _i and an adder for the imaginary part of the unit second correlation value UB.

The unitary second differential phase value calculation unit 905(i) receives the unitary second correlation values UB _i+1 and UB _i, which are complex numbers, and calculates the unitary second differential phase value VUB _i having the phase difference between UB _i+1 and the previous UB _i and the amplitude of a unit amount. The unitary second differential phase value calculation unit 905(i) is controlled by a control signal G7 output by the operation control unit 945L, and outputs either the unitary second differential phase value VUB _i or the unitary second correlation value UB _i+1 . When the control signal G6 is ON, the unitary second differential phase value calculation unit 905(i) outputs the unitary second differential phase value VUB _i . When the control signal G6 is OFF, the unitary second differential phase value calculation unit 905(i) outputs the unitary second correlation value UB _i+1 . The case where the unit second differential phase value calculation unit 905(i) operates is when G7 is input and the unit second differential phase value calculation unit 905(i) calculates and outputs the unit second differential phase value VUB _i . The operation control unit 925L uniformly controls whether each unit second differential phase value calculation unit 905 outputs a unit second correlation value or a unit second differential phase value.

The unit second differential phase value calculation unit 905 has a configuration similar to that of the first differential phase value calculation unit 960. The operation of the unit second differential phase value calculation unit 905 is controlled by the control signal G7, not the control signal G3.

The unitary second differential phase value calculation unit 905(i) calculates a unitary second differential phase value VUB _i , which is a complex number having a phase difference between the unitary second correlation value UB _i+1 and the previous unitary second correlation value UB _i . The unitary second differential phase value calculation unit 905(i) also functions as a second selection output unit that uniformly switches between and outputs either the unitary second correlation value UB _i+1 or the unitary second differential phase value VUB _i .

The switch 906 is provided between the output of the unit second differential phase value calculation unit 905(1) and the adder 907. The switch 906 is controlled to be turned on or off by a control signal G8 output by the operation control unit 945L. The control signal G8 is turned on when a control signal G7 that controls the operation of the unit second differential phase value calculation unit 905 is turned off. When the control signal G7 is turned off, the unit second differential phase value calculation unit 905 outputs the unit second correlation value. When G7 is turned on, G8 is turned off. When the control signal G7 is turned on, the unit second differential phase value calculation unit 905 outputs the unit second differential phase value. When G8=ON is input, the switch 906 is turned on. When G8=OFF is input, the switch 906 is turned off. When the switch 906 is turned on, the switch 906 outputs the unit second correlation value UB _i+1 . When the switch 906 is turned off, the switch 906 outputs zero. By controlling the on/off of switch 906, it is possible to calculate the second correlation value B including the unitary second correlation value UB _i+1 output by unitary second differential phase value calculation section 905(1).

When an OFF control signal G7 is input to the unitary second differential phase value calculation unit 905(i), the unitary second correlation value UB _i may be output. In this case, the switch 906 is provided between the output of the unitary second differential phase value calculation unit 905(MA) and the adder 907. The on/off of the switch 906 is controlled by the control signal G8 in the same manner as described above.

The switch 906 is a second switch that is provided between the output of the most recent unitary second differential phase value calculation unit 905(1) or the output of the most recent unitary second differential phase value calculation unit 905(MA) and the adder 907, and switches between an input complex number or zero and outputs the result. The adder 907 is a second adder that outputs the sum of the outputs of the second selection output units. When the unitary second differential phase value calculation unit 905(i) outputs the previous unitary second correlation value UB _i , the output of the most recent unitary second differential phase value calculation unit 905(MA) is input to the switch 906. When the unitary first correlation value calculation unit 221(i) outputs the newer unitary second correlation value UB _i+1 , the output of the most recent unitary second differential phase value calculation unit 905(1) is input to the switch 906.

The adder 907 adds the outputs of the (MA-1) unitary second differential phase value calculation units 905(1) to (MA-1) and the output of the switch 906, and outputs the addition result. The adder 907 has an adder for the real part of the complex number and an adder for the imaginary part. The output of the adder 907 is called the unitary second accumulated value XUB. When the unitary second differential phase value calculation unit 905(i) outputs the unitary second differential phase value VUB _i , the unitary second accumulated value XUB is the unitary second differential correlation value WUB, which is the sum of the unitary second differential phase values VUB ₁ to VUB _MA-1 . When the unitary second differential phase value calculation unit 905(i) outputs the unitary second correlation value UB _i+1 , the unitary second accumulated value XUB is the second correlation value B.

When the unit second differential phase value calculation unit 905(i) outputs the unit second differential phase value VUB _i , the adder 907 operates as a unit second differential correlation value calculation unit that calculates the unit second differential correlation value WUB which is the sum of the (MA-1) unit second differential phase values VUB _i . When the unit second differential phase value calculation unit 905(i) outputs the unit second correlation value UB _i+1 , the adder 907 operates as a second correlation value calculation unit that calculates the second correlation value B.

When the unit second differential phase value calculation unit 905 operates, the unit second differential correlation value WUB is stored in the second accumulated value storage unit. When the unit second differential phase value calculation unit 905 does not operate, the second accumulated value XB is stored in the second accumulated value storage unit.

In order to accommodate the operation of the unit second differential phase value calculation unit 905, the control signal G4 output by the operation control unit 945 takes the following value.
(Meaning of the value of control signal G4L)
0: The unit second differential phase value calculator 905, the second differential phase value calculator 950, and the first differential phase value calculator 960 are inactive.
1: The first differential phase value calculation unit 960 operates.
2: The second differential phase value calculation unit 950 operates.
4: The unit second differential phase value calculation unit 905 operates.

The phase of the first accumulated value XA output by the CA correlation processor 910 is proportional to the frequency deviation when the unit second differential phase value calculator 905 operates (G4L=4). The output of the CA correlation processor 910 when the unit second differential phase value calculator 905 operates (G4L=4) is also called the second accumulated value XB. The phase of the second accumulated value XB when the unit second differential phase value calculator 905 operates is equal to the phase change caused by the frequency deviation ΔF in DB*SB time. When G4L=4, the frequency deviation calculator 925L calculates ΔF by ΔF=XA _AV /(2π*DB*SB). When G4L=0, G4L=1, or G4L=2, the frequency deviation calculator 925L calculates ΔF in the same manner as the frequency deviation calculator 925.

In the synchronization acquisition circuit 9L, the first accumulated value XA is the second differential correlation value WB when the second differential phase value calculation unit 950 or the unit second differential phase value calculation unit 905 operates. When the first differential phase value calculation unit 960 operates, the first accumulated value XA is the first differential correlation value WA. When the second differential phase value calculation unit 950, the unit second differential phase value calculation unit 905, and the first differential phase value calculation unit 960 do not operate, the first accumulated value XA is the first correlation value A.

The operation will be described. The operation control section 945L determines which of the unit second differential phase value calculation section 905, the second differential phase value calculation section 950, and the first differential phase value calculation section 960 to operate, depending on the magnitude of the frequency deviation ΔF. Here, the third threshold value _TH3 is set to a threshold value that is greater than the first threshold value _TH1 ( _TH3 > _TH1 ).

The operation control section 945L outputs a control signal in the following cases.
(A) If ΔF≧ _TH3 , G4L=4, G1=G2=G3=OFF, G7=ON, and G8=OFF are output so that the unit second differential phase value calculation unit 905 operates.
(a) If TH ₃ > ΔF≧TH ₁ , G4L=2, G1=G2=ON, G3=OFF, G7=OFF, and G8=ON are output so that the second differential phase value calculation unit 950 operates.
(c) If TH ₁ > ΔF≧TH ₂ , G4L=1, G1=G2=OFF, G3=ON, G7=OFF, and G8=ON are output so that the first differential phase value calculation unit 960 operates.
(d) If TH ₂ > ΔF, output G4L=0, G1=G2=G3=OFF, G7=OFF, and G8=ON so that none of the controls operates.

The operation control unit 945L controls whether to operate one of the unit second differential phase value calculation unit 905, the second differential phase value calculation unit 950, and the first differential phase value calculation unit 960, or to operate neither of them. Note that the operation control unit 945L controls whether to operate one of the unit second differential phase value calculation unit 905 and the second differential phase value calculation unit 950, or to operate neither of them, and when neither of the unit second differential phase value calculation unit 905 nor the second differential phase value calculation unit 950 is operated, it can also be considered to control whether to operate the first differential phase value calculation unit 960.

At the start of communication, whether to operate the unitary second differential phase value calculation unit 905 or the second differential phase value calculation unit 950 is determined depending on the magnitude of ΔF. If ΔF≧TH ₃ , the unitary second differential phase value calculation unit 905 is operated. If ΔF<TH ₃ , the second differential phase value calculation unit 950 is operated. At the start of communication, the unitary second differential phase value calculation unit 905 may be operated regardless of the magnitude of ΔF. At the start of communication, the second differential phase value calculation unit 950 may be operated regardless of the magnitude of ΔF.

Even when the frequency deviation ΔF is large, the synchronization acquisition circuit 9L can calculate the frequency deviation with higher accuracy than before and determine the synchronization sequence position of the spread code. Even for a frequency deviation ΔF larger than the maximum frequency deviation ΔF that the synchronization acquisition circuit 9 can handle, the synchronization sequence position of the spread code can be determined with high accuracy.

The synchronization acquisition circuit 9L has a second differential phase value calculation unit 950 and a first differential phase value calculation unit 960. A synchronization acquisition circuit having a second differential phase value calculation unit 950 but not a first differential phase value calculation unit 960 may be modified to have a unit second differential phase value calculation unit 905.

11th variant:
The configuration of an eleventh modified example of the acquisition circuit according to the second embodiment will be described with reference to Fig. 51. Fig. 51 is a functional block diagram showing the configuration of an eleventh modified example of the acquisition circuit according to the second embodiment. In the eleventh modified example, when the frequency change rate is large, the second differential phase value calculation unit and the first differential phase value calculation unit are operated simultaneously. In the acquisition circuit 9M, the operation control unit 945M and the frequency deviation calculation unit 925M are modified.

The operation control unit 945M controls, based on the frequency deviation ΔF and the frequency change rate _Fdiff , whether to operate the second differential phase value calculation unit 950 and the first differential phase value calculation unit 960. The operation control unit 945M outputs control signals G1, G2, G3, G4M, G7, and G8.

When the second differential phase value calculation section 950 and the first differential phase value calculation section 960 operate simultaneously, the first integrated value XA output by the CA correlation processing section 910 becomes a value proportional to the frequency change rate _Fdiff .
The control signal G4M output by the operation control section 945M has the following values.
(Meaning of the value of control signal G4M)
0: The unit second differential phase value calculator 905, the second differential phase value calculator 950, and the first differential phase value calculator 960 are inoperative.
1: The first differential phase value calculation unit 960 operates.
2: The second differential phase value calculation unit 950 operates.
3: The second differential phase value calculation unit 950 and the first differential phase value calculation unit 960 operate.
4: The unit second differential phase value calculation unit 905 operates.

When G4M=0, G4M=1, G4M=2, or G4M=3, the frequency deviation calculation unit 925M calculates ΔF and _Fdiff in the same manner as the frequency deviation calculation unit 925J. When G4M=4, the frequency change calculation unit 925M calculates ΔF and _Fdiff as follows. The frequency change calculation unit 925M obtains a linear function that minimizes the square error that approximates the time change in the phase of the first integrated value XA input during the period TX. The frequency change calculation unit 925M calculates _Fdiff by _Fdiff = _XAincl /(2π*DB*SB) based on the slope _XAincl of the linear function. The frequency change calculation unit 925M calculates ΔF by ΔF= _XAlatest /(2π*DB*SB) based on the value _XAlatest of the linear function at the latest point in time during the period TX.

In the synchronization acquisition circuit 9M, the first accumulated value XA is the differential phase value VC when the second differential phase value calculation unit 950 and the first differential phase value calculation unit 960 operate. When the second differential phase value calculation unit 950 or the unit second differential phase value calculation unit 905 operates and the first differential phase value calculation unit 960 does not operate, the first accumulated value XA is the second differential correlation value WB. When the second differential phase value calculation unit 950 and the unit second differential phase value calculation unit 905 do not operate and the first differential phase value calculation unit 960 operates, the first accumulated value XA is the first differential correlation value WA. When the second differential phase value calculation unit 950, the unit second differential phase value calculation unit 905 and the first differential phase value calculation unit 960 do not operate, the first accumulated value XA is the first correlation value A.

The operation will be described. The operation control section 945M determines _which of the unit second differential phase value calculation section 905, the second differential phase value calculation section 950, and the first differential phase value calculation section 960 to operate, depending on the magnitude of the frequency deviation ΔF and the frequency change rate Fdiff. Note that there are also cases where none of the unit second differential phase value calculation section 905, the second differential phase value calculation section 950, and the first differential phase value calculation section 960 is operated.

The operation control section 945M outputs a control signal in the following cases.
(A) If ΔF≧ _TH3 , G4M=4, G1=G2=G3=OFF, G7=ON, and G8=OFF are output so that the unit second differential phase value calculation unit 905 operates.
(a) If TH ₃ > ΔF and F _diff ≧TH _diff , G4M=3, G1=G2=G3=ON, G7=OFF, and G8=ON are output so that the second differential phase value calculation unit 950 and the first differential phase value calculation unit 960 operate.
(c) If F _diff < TH _diff and TH ₃ > ΔF≧TH ₁ , G4M=2, G1=G2=ON, G3=OFF, G7=OFF, and G8=ON are output so that the second differential phase value calculation unit 950 operates.
(d) If F _diff < TH _diff and TH ₁ > ΔF≧TH ₂ , then G4M=1, G1=G2=OFF, G3=ON, G7=OFF, and G8=ON are output so that the first differential phase value calculation unit 960 operates.
(e) If F _diff < TH _diff and TH ₂ > ΔF, output G4M=0, G1=G2=G3=OFF, G7=OFF, and G8=ON so that none of the controls operates.

Even when the frequency deviation ΔF is large, the synchronization acquisition circuit 9M can calculate the frequency deviation with higher accuracy than in the past to determine the synchronization sequence position of the spreading code. The synchronization acquisition circuit 9M can determine the synchronization sequence position of the spreading code with high accuracy even for a frequency deviation ΔF larger than the maximum frequency deviation ΔF that the synchronization acquisition circuit 9 can handle. When there is a time change in the frequency deviation, i.e., when the frequency change rate _Fdiff is equal to or greater than the change rate threshold value _THdiff ( _Fdiff ≧ _THdiff ), the synchronization acquisition circuit 9M can calculate the frequency deviation ΔF with higher accuracy than when only the second differential phase value calculation unit 950 is operated by operating the second differential phase value calculation unit 950 and the first differential phase value calculation unit 960.

12th variant:
The configuration of a twelfth modified example of the synchronization acquisition circuit according to the second embodiment will be described with reference to Fig. 52. Fig. 52 is a functional block diagram showing the configuration of a twelfth modified example of the synchronization acquisition circuit according to the second embodiment. In the twelfth modified example, when the frequency change rate is large, the unit second differential phase value calculation unit or the second differential phase value calculation unit and the first differential phase value calculation unit are operated simultaneously. In the synchronization acquisition circuit 9N, the operation control unit 945N is modified.

The operation control unit 945N controls, based on the frequency deviation ΔF and the frequency change rate _Fdiff , whether to operate the second differential phase value calculation unit 950 and the first differential phase value calculation unit 960. The operation control unit 945N outputs control signals G1, G2, G3, G4N, G7, and G8.

The first accumulated value XA output by the CA correlation processing unit 910 has a large frequency change rate, and when the unit second differential phase value calculation unit or the second differential phase value calculation unit and the first differential phase value calculation unit operate simultaneously, the first accumulated value XA becomes a value proportional to the frequency change rate _Fdiff .
The control signal G4N output by the operation control section 945N has the following values.
(Meaning of the value of control signal G4N)
0: The unit second differential phase value calculator 905, the second differential phase value calculator 950, and the first differential phase value calculator 960 are inoperative.
1: The first differential phase value calculation unit 960 operates.
2: The second differential phase value calculation unit 950 operates.
3: The second differential phase value calculation unit 950 and the first differential phase value calculation unit 960 operate.
4: The unit second differential phase value calculation unit 905 operates.
5: The unit second differential phase value calculator 905 and the first differential phase value calculator 960 operate.

The frequency deviation calculation unit 925N calculates ΔF and _Fdiff in the same manner as the frequency deviation calculation unit 925M when G4N=0, G4N=1, G4N=2, G4N=3, or G4N=4. When the unit second differential phase value calculation unit 905 and the first differential phase value calculation unit 960 operate (when G4N=5), the first integrated value XA is the differential phase value VC. The differential phase value VC is the amount of change in the phase change amount DA*SA that occurs during the DB*SB time. Based on XA _AV , which is the average of XA during the period TX, the frequency change calculation unit 925N calculates _Fdiff by _Fdiff =XA _AV /(2π*DB*SB*DA*SA). The frequency change calculation unit 925N calculates ΔF by integrating XA. Alternatively, F _diff may be calculated at a period TY which is smaller than TX, and ΔF may be calculated by integrating F _diff .

In the synchronization acquisition circuit 9N, the first integrated value XA is the differential phase value VC when the second differential phase value calculation unit 950 or the unit second differential phase value calculation unit 905 and the first differential phase value calculation unit 960 are operating. In other cases, the first integrated value XA in the synchronization acquisition circuit 9N is the same as the first integrated value XA in the synchronization acquisition circuit 9L.

The operation control unit 945N determines which of the unit second differential phase value calculation unit 905, the second differential phase value calculation unit 950, and the first differential phase value calculation unit 960 to operate, depending on the magnitude of the frequency deviation ΔF and _the frequency change rate Fdiff.

The operation control section 945N outputs a control signal in the following cases.
(A) If F _diff ≧TH _diff and ΔF ≧ _TH3 , output G4N=5, G1=G2=OFF, G3=ON, G7=ON, and G8=OFF so that the unit second differential phase value calculation unit 905 and the first differential phase value calculation unit 960 operate.
(a) If F _diff ≧TH _diff and TH ₃ > ΔF, then G4N=3, G1=G2=G3=ON, G7=OFF, and G8=ON are output so that the second differential phase value calculation unit 950 and the first differential phase value calculation unit 960 operate.
(c) If F _diff < TH _diff and ΔF≧TH ₃ , G4N=4, G1=G2=G3=OFF, G7=ON, and G8=OFF are output so that the unit second differential phase value calculator 905 operates.
(d) If F _diff < TH _diff and TH ₃ > ΔF≧TH ₁ , G4N=2, G1=G2=ON, G3=OFF, G7=OFF, and G8=ON are output so that the second differential phase value calculation unit 950 operates.
(E) If F _diff < TH _diff and TH ₁ > ΔF≧TH ₂ , G4N=1, G1=G2=OFF, G3=ON, G7=OFF, and G8=ON are output so that the first differential phase value calculation unit 960 operates.
(f) If F _diff < TH _diff and TH ₂ > ΔF, then G4N=0, G1=G2=G3=OFF, G7=OFF, and G8=ON are output so that none of the controls operates.

Even when the frequency deviation ΔF is large, the synchronization acquisition circuit 9N can calculate the frequency deviation with higher accuracy than in the past to determine the synchronization sequence position of the spreading code. The synchronization acquisition circuit 9N can determine the synchronization sequence position of the spreading code with high accuracy even for a frequency deviation ΔF larger than the maximum frequency deviation ΔF that the synchronization acquisition circuit 9 can handle. When there is a time change in the frequency deviation, i.e., when the frequency change rate _Fdiff is equal to or larger than the change rate threshold value _THdiff ( _Fdiff ≧ _THdiff ), the synchronization acquisition circuit 9N can calculate the frequency deviation ΔF with higher accuracy than when only the unit second differential phase value calculation unit 905 or the second differential phase value calculation unit 950 is operated by simultaneously operating the unit second differential phase value calculation unit 905 or the second differential phase value calculation unit 950.

Embodiment 3.
The configuration of the synchronization acquisition circuit according to the third embodiment will be described with reference to FIG. 53. FIG. 53 is a functional block diagram showing the configuration of the synchronization acquisition circuit according to the third embodiment. The third embodiment is a modification of the first embodiment to include an accumulator 980 that adds the first integrated value XA for each phase of the spread code (described later) a determined number of times (L times). Each of the modifications of the first embodiment or other embodiments may be modified. The synchronization acquisition circuit 9P includes an accumulator 980. The synchronization acquisition circuit 9P has a modified operation control unit 945P. The operation control unit 945P outputs a control signal G9 that controls the operation of the accumulator 980.

The cumulative addition unit 980, like the averaging processing unit 930, holds the first accumulated value XA of NA*NB chips (=NA*2NB samples=2NC samples) for each time point (called phase) of SB/2 intervals in one period of the cascaded concatenated spreading code PN until L times of accumulation. After L times of accumulation, the cumulative addition unit 980 outputs the accumulated first accumulated value XA. Then, it resets the accumulated accumulated value of the first accumulated value XA for each phase stored inside to zero. L times is, for example, 4 times.

The operation control unit 945P controls whether or not to operate the cumulative addition unit 980 using the operation signal G9. When G9=ON, the cumulative addition unit 980 operates. When G9=OFF, the cumulative addition unit 980 does not operate.

The configuration of the cumulative addition unit 980 will be described with reference to FIG. 54. FIG. 54 is a diagram showing the configuration of the cumulative addition unit included in the synchronization acquisition circuit according to the third embodiment. The cumulative addition unit 980 includes a SEL unit 981, 2NC cumulative addition circuits 982, a SEL unit 983, and a control circuit 984. The SEL unit 981 switches between outputting the input first accumulated value XA _t as is, or outputting the accumulated first accumulated value XA ^R _i, depending on the control signal G9. The output of the cumulative addition unit 980 is represented by a variable XA ^Z _t . When G9=ON, the SEL unit 981 outputs the accumulated first accumulated value XA ^R _i (XA ^Z _t =XA ^R _i ). When G9=OFF, the SEL unit 981 outputs the non-accumulated first accumulated value XA _t (XA ^Z _t =XA _t ). An accumulative addition circuit 982 is provided for each received signal received in one period of the cascaded spreading code PN. The accumulative addition circuit 982 adds up received signals at the same position in one period L times. After adding up L times, the accumulated value is reset to zero. Each time a first integrated value XA _t is input, the SEL unit 983 selects one output from among the 2NC accumulative addition circuits 982 and inputs it to the SEL unit 981. The control circuit 984 controls the accumulative addition circuits 982 and the SEL unit 983.

All the cumulative addition circuits 982 _i (i=1 to 2NC) have the same configuration. FIG. 54 shows the configuration of the first cumulative addition circuit 982 _1. The cumulative addition circuit 982 _i has a data acquisition unit 98A, an adder 98B, a DFF 98C, and a hold unit 98D. The data acquisition unit 98A acquires a first accumulated value XA _t . The adder 98B adds the acquired first accumulated value XA _t and the output of the DFF 98C. The addition result by the adder 98B is input to the DFF 98C and the hold unit 98D. The DFF 98C holds and outputs the signal input one time before. The hold unit 98D holds a signal input at a specified timing and outputs the held signal. The signal held by the hold unit 98D is the cumulatively added first accumulated value XA ^R _i . The output of the hold unit 98D is the output of the cumulative addition circuit 982 _i .

The cumulative addition circuit _982i receives a clock signal _CLKi and a reset & hold signal _RHi from a control circuit 984. The clock signal _CLKi is generated by the control circuit 984 every time the first accumulated value _XAt is input to the cumulative addition unit 980. The clock signal _CLKi is input to a data acquisition unit 98A of the cumulative addition circuit _982i . Every time the clock signal _CLKi is generated, the control circuit 984 updates the counter i to i=mod(i, 2NC)+1. When the clock signal _CLKi is input to the cumulative addition circuit _982i , the data acquisition unit 98A takes in the first accumulated value _XAt and outputs it to the adder 98B. When the clock signal _CLKi is not input, the data acquisition unit 98A does not take in the first accumulated value _XAt .

The variables used to describe the operation of accumulating circuit _982i are defined as follows:
m: the number of times the first integrated value XA _t has been acquired since the DFF98C was reset.
XA _i,m : the first integrated value XA _t acquired by the accumulating circuit 982 _i .
Yi _,m : signals input to DFF98C.
Zi _,m : signal output by DFF98C.
XA ^R _i : A signal held by the holding unit 98D.
L: The number of times to accumulate.
The reset of DFF98C will be explained later.

The adder 98B adds the first integrated value XA _i,m acquired by the data acquisition unit 98A and the output of the DFF 98C. The result of the addition is input to the DFF 98C. That is, the following relational expression is established.
Y _i,m =Z _i,m +XA _i,m ...(4)
If the DFF 98C is not reset, it outputs the signal that was input the previous time. The following relational expression is established.
Z _i,m =Y _i,m-1 ...(5)

The control circuit 984 manages how many clock signals CLK _i have been output to the cumulative addition circuit 982 _i . When outputting the Lth clock signal CLK _i since the previous reset & hold signal RH _i was output, the control circuit 984 also outputs the reset & hold signal RH _i . The reset & hold signal RH _i is input to the hold section 98D of the DFF 98C of the cumulative addition circuit 982 _i . When the reset & hold signal RH _i is input, the DFF 98C resets the signal it holds to zero. Therefore, when the next clock signal CLK _i is input, the DFF 98C outputs zero. That is, the following is true.
Z _{i, 1} = 0 (6)
When the reset and hold signal RH _i is input, the hold unit 98D holds the input signal. That is, the following relational expression is established.
XA ^R _i =Y _{i, L} ... (7)

When the first clock signal CLK _i is input after the reset & hold signal RH _i is input to the cumulative addition circuit 982 _i , the output Y _i,1 of the adder 98B is as follows, based on equations (4) and (6).
Y _i,1 =Z _i,1 +XA _i,1 =0+XA _i,1 =XA _i,1 ...(8)
Y _i,2 and onwards are given as follows by equations (8), (4) and (5).
Y _i,2 =Z _i,2 +XA _i,2
=Y _i,1 +XA _i,2 =XA _i,1 +XA _i,2 ...(9)
Y _i,3 =Z _i,3 +XA _i,3 =Y _i,2 +XA _i,3
=XA _{i, 1} +XA _{i, 2} +XA _{i, 3} ...(10)
Y _i,m =Z _i,m +XA _i,m =Y _i,m-1 +XA _i,m
=XA _{i, 1} +XA _{i, 2} +...+XA _{i, m} ... (11)
Y _i,L =Z _i,L +XA _i,L =Y _i,L-1 +XA _i,L
=XA _{i, 1} +XA _{i, 2} +...+XA _{i, L} ... (12)

From equations (7) and (12), the following equation is obtained.
XA ^R _i =XA _{i, 1} +XA _{i, 2} +...+XA _{i, L} ... (13)
Equation (13) means that the cumulative addition circuit _982i holds XA ^R _i, which is a value obtained by cumulatively adding L first accumulated values XA _t . XA ^R _i is updated every time L first accumulated values XA _t are input.

XA ^R _i output from the cumulative addition circuit 982 _i (i=1 to 2NC) is input to the SEL unit 983. The SEL unit 983 receives counter i from the control circuit 984. The SEL unit 983 selects XA ^R _i output from the cumulative addition circuit 982 _i and outputs it to the SEL unit 981. Depending on the control signal G9, the SEL unit 981 switches between outputting the input first accumulated value XA _t as is, or outputting the cumulatively added first accumulated value XA ^R _i . When G9=ON, the SEL unit 981 outputs the cumulatively added first accumulated value XA ^R _i . When G9=OFF, the SEL unit 981 outputs the non-accumulated first accumulated value XA _t .

The first integrated value XA in the synchronization acquisition circuit 9P is the same as the first integrated value XA in the synchronization acquisition circuit 9 in each case.

The accumulator 980 accumulates the first integrated value XA a predetermined number of times (L times) for each first integrated value XA calculated by shifting the received signal by one time point at a time. The power calculator 920 calculates the power of the first integrated value XA ^Z output by the accumulator 980 when the accumulator 980 operates, and calculates the power of the first integrated value XA when the accumulator 980 does not operate.

When the other embodiment or its variant is modified to have a cumulative addition unit, the cumulative addition unit cumulatively adds the first integrated value input to the power calculation unit.

The operation will be described. The synchronization acquisition circuit 9P operates in the same manner as the synchronization acquisition circuit 9. When the cumulative addition unit 980 operates, each time the first integrated value XA is calculated L times in each phase, the cumulative addition unit 980 outputs the cumulatively added first integrated value XA in each phase.

The first integrated value XA is input to the power calculation unit 920. The power calculation unit 920 calculates the sum of the squares of the real and imaginary parts (i.e., power C). The averaging processing unit 930 stores the power C for the number of NA*NB chips (=NA*2NB samples=2NC samples) at SB/2 intervals calculated by the power calculation unit 920.

The cumulative addition unit 980 adds L first integrated values XA, so it can reduce the effects of noise. Because it adds the first integrated values XA instead of power, it is considered to be more effective at removing the effects of noise than the averaging processing unit 930.

Even when the frequency deviation ΔF is large, the synchronization acquisition circuit 9P can calculate the frequency deviation with higher accuracy than conventional circuits and determine the synchronization sequence position of the spreading code. Even when there is a lot of noise, the synchronization acquisition circuit 9P can determine the synchronization sequence position of the spreading code more accurately than the synchronization acquisition circuit 9.

Embodiment 4.
The configuration of the synchronization acquisition circuit according to the fourth embodiment will be described with reference to FIG. 55. FIG. 55 is a functional block diagram showing the configuration of the synchronization acquisition circuit according to the fourth embodiment. The fourth embodiment is a case where the first embodiment is modified so that the second differential phase value calculation unit can respond to a wider range in which the frequency deviation ΔF changes. Each modification of the first embodiment or other embodiments may be modified. The synchronization acquisition circuit 9Q has modified CA correlation processing unit 910Q, frequency deviation calculation unit 925Q, and operation control unit 945Q. The CA correlation processing unit 910Q has modified second differential phase value calculation unit 950Q and code selection unit 970Q.

The configuration of the second differential phase value calculation unit 950Q will be described with reference to Fig. 56. Fig. 56 is a diagram showing the configuration of the second differential phase value calculation unit included in the synchronization acquisition circuit according to the fourth embodiment. Regarding Fig. 56, differences from Fig. ₁₅ in the case of the first embodiment will be described. The second differential phase value calculation unit 950Q has a delay circuit 9522 in addition to the delay circuit 952, and further has a SEL unit 958. The SEL unit 955Q has been modified.

The second differential phase value calculation unit 950Q calculates a second differential value VB, which is a complex number having a phase difference between the second correlation value B calculated using a received signal at a point in time that is the number of delay chips (1 or 2) earlier than the received signal used to calculate the second correlation value B. The number of delay chips may be three or more. Furthermore, the number of delay chips does not have to be consecutive integers such as 1, 2, 4, etc. The number of delay chips may be any integer that is different from one or more.

The delay circuit 952 delays the input second correlation value B by a time equivalent to NB chips (2 NB samples). The time equivalent to NB chips (2 NB samples) is equal to the first chip time SA. The output of the delay circuit 952 is input to the delay circuit _952-2 . The delay circuit _952-2 delays the input second correlation value B by a time equivalent to NB chips (2 NB samples). The output of the delay circuit 952 is delayed by a time equivalent to NB chips (2 NB samples) with respect to the second correlation value B input to the second differential phase value calculation unit 950Q. The output of the delay circuit _952-2 is delayed by a time equivalent to 2 NB chips (4 NB samples).

The operation of the second differential phase value calculation unit 950Q is controlled by a control signal G1Q. G1Q is not ON/OFF, but takes any one of the values 0, 1, and 2. For example, the values that G1Q takes are as follows. When G1Q>0, the second differential phase value calculation unit 950Q operates.
(Meaning of the value of control signal G1Q)
0: The SEL unit 955Q selects and outputs the second correlation value B.
1: The SEL unit 958 selects the output of the delay circuit 952, and the SEL unit 955Q selects and outputs the second differential phase value VB.
2: The SEL unit 958 selects the output of the delay circuit ₉₅₂₂ , and the SEL unit 955Q selects and outputs the second differential phase value VB.

The output of the SEL unit 958 is the phase θ _BDELAY . The value of the phase θ _BDELAY changes depending on whether the SEL unit 958 selects the output of the delay circuit 952 or the delay circuit _952-2 . The phase θ _BDELAY is input to the subtractor 953. The subtractor 953 subtracts θ _BDELAY from the phase θ _B of the second correlation value B.

When G1Q=0, the SEL unit 955Q selects the second correlation value B. When G1Q>0, the SEL unit 955Q selects the second differential phase value VB output by the amplitude-phase inverse conversion unit 954.

The configuration of the code selection unit 970Q will be described with reference to Fig. 57. Fig. 57 is a diagram showing the configuration of the code selection unit included in the synchronization acquisition circuit according to the fourth embodiment. The code selection unit 970Q has a delay circuit ₉₇₂₂ in addition to the delay circuit 972, and has a multiplier ₉₇₁₂ in addition to the multiplier 971. The SEL unit 973Q has been modified.

The delay circuit 972 ₂ delays the first spreading code CA[k] by one chip. The output of the delay circuit 972 is input to the delay circuit 972 _2. When CA[k] is input to the delay circuit 972, the delay circuit 972 outputs CA[k-1], and the delay circuit 972 ₂ outputs CA[k-2].

The multiplier 971 multiplies CA[k] by CA[k-1] output from the delay circuit 972. The multiplier 971 outputs a difference code CD[k]. The multiplier _971-2 multiplies CA[k] by CA[k-2] output from the delay circuit _972-2 .

The multiplier 971 ₂ outputs a difference code CD ₂ [k] having the following value:
If CA[k] = CA[k-2] = "1", then CD ₂ [k] = "1"
If CA[k] = CA[k-2] = "-1", then CD ₂ [k] = "1"
If CA[k] = "1" and CA[k-2] = "-1", then CD ₂ [k] = "-1"
If CA[k] = "-1" and CA[k-2] = "1", then CD ₂ [k] = "-1"

The differential code _CD2 [k] is a spreading code having a sequence length of 2NA, in which a spreading code having a first sequence length NA when k is an even number and a spreading code having a first sequence length NA when k is an odd number are output alternately. The differential code _CD2 [k] is uniquely determined according to CA[k].

The operation of the code selection unit 970Q is controlled by a control signal G2Q. Like G11Q, G2Q can take any value from 0 to 3. For example, G2Q can take the following values:
(Meaning of the value of control signal G2Q)
0: The SEL unit 973Q selects and outputs CA[k]. CX[k]=CA[k].
1: The SEL unit 973Q selects and outputs CD[k]. CX[k]=CD[k].
2: The SEL unit 973Q selects and outputs CD ₂ [k]. CX[k]=CD ₂ [k].

G1Q and G2Q are generated so that G2Q always equals G1Q. If there is no frequency deviation, the CA correlation processing unit 910Q can calculate the same first correlation value A in any of the cases of G1Q = G2Q = 0, G1Q = G2Q = 1, and G1Q = G2Q = 2.

The operation control unit 945Q outputs control signals G1Q, G2Q, G3, and G4Q. G3, which controls the first differential phase value calculation unit 960, takes the value ON/OFF as in the first embodiment. G4Q, which controls the operation of the frequency deviation calculation unit 925Q, takes the following value, for example.
(Meaning of the value of control signal G4Q)
0: The second differential phase value calculation unit 950Q and the first differential phase value calculation unit 960 are inactive.
1: The first differential phase value calculation unit 960 operates.
2: The second differential phase value calculation unit 950Q operates. When G1Q=1.
3: The second differential phase value calculation unit 950Q operates. When G1Q=2.

When G4Q=0, G4Q=1, or G4Q=2, the frequency deviation calculation unit 925Q operates in the same manner as the frequency deviation calculation unit 925. When G4Q=3, the frequency deviation calculation unit 925Q calculates ΔF as follows: ΔF=WA _AV /(4π*SA).

The first integrated value XA in the synchronization acquisition circuit 9Q is the same as the first integrated value XA in the synchronization acquisition circuit 9 in each case.

The operation will be described. At the start of communication, the operation control section 945Q outputs control signals G1Q=G2Q=1, G3=OFF, and G4Q=2. When the synchronization acquisition circuit 9Q operates and the frequency deviation ΔF can be calculated, the operation control section 945Q changes the values of G1Q, G2Q, G3, and G4Q according to the magnitude of ΔF. The operation control section 945Q uses a fourth threshold _TH4 in addition to a first threshold _TH1 and a second threshold _TH2 . Each threshold is determined so that the relationship _TH2 < _TH1 < _TH4 is established. In the synchronization acquisition circuit 9Q, a period in which either G1Q=G2Q=1 or G1Q=G2Q=2 is satisfied is set as a period of rough detection.

The operation control section 945Q outputs a control signal in the following cases.
(A1) When ΔF≧TH ₄ (coarse detection 1), the second differential phase value calculation unit 950Q outputs G4Q=2, G1Q=G2Q=1, and G3=OFF so that the second differential phase value calculation unit 950Q operates with the number of delay chips=1. 1 is the first number of delay chips.
(A2) If _TH4 >ΔF≧ _TH1 (coarse detection 2), the second differential phase value calculation unit 950Q outputs G4Q=3, G1Q=G2Q=2, and G3=OFF so that the second delay chip number is operated with the delay chip number=2. The second delay chip number, which is larger than the first delay chip number, is 2.
(a) If TH ₄ > ΔF≧TH ₂ (precise detection), G4Q=1, G1Q=G2Q=0, and G3=ON are output so that the first differential phase value calculation unit 960 operates.
(c) If TH ₂ > ΔF, G4Q=0, G1Q=G2Q=0, and G3=OFF are output so that none of them operates.

Even when the frequency deviation ΔF is large, the synchronization acquisition circuit 9Q can calculate the frequency deviation with higher accuracy than before and determine the synchronization sequence position of the spread code. When the frequency deviation ΔF becomes smaller, the synchronization acquisition circuit 9Q can change the level at which the phase change is detected more finely than the synchronization acquisition circuit 9, and can determine the synchronization sequence position of the spread code with higher accuracy. The accuracy of determining the frequency deviation is also improved.

Embodiment 5.
The configuration of the synchronization acquisition circuit according to the fifth embodiment will be described with reference to Fig. 58. Fig. 58 is a functional block diagram showing the configuration of the synchronization acquisition circuit according to the fifth embodiment. The fifth embodiment is a case where the fourth embodiment does not have the first differential phase value calculation unit 960 and the number of delay chips taken by the second differential phase value calculation unit is changed. The fifth embodiment is also a case where the sixth modification of the first embodiment is modified so that the second differential phase value calculation unit 950F takes a plurality of delay chips.

Regarding FIG. 58, the points different from FIG. 41 of the sixth modified example of the first embodiment will be described. Compared to the synchronization acquisition circuit 9F, the synchronization acquisition circuit 9R has modified CA correlation processing unit 910R, frequency deviation calculation unit 925R, and operation control unit 945R. In the CA correlation processing unit 910R, the second differential phase value calculation unit 950R and the code selection unit 970R have been modified. The second differential phase value calculation unit 950R takes a value of delay chip number = 1 or 4. When the delay chip number = 4, the second differential phase value calculation unit 950R can detect the frequency deviation with the same accuracy as the first differential phase value calculation unit 960. Therefore, instead of operating the first differential phase value calculation unit 960, the synchronization acquisition circuit 9R operates the second differential phase value calculation unit 950R with the delay chip number = 4.

The configuration of the second differential phase value calculation unit 950R will be described with reference to Fig. 59. Fig. 59 is a diagram showing the configuration of the second differential phase value calculation unit included in the synchronization acquisition circuit according to the fifth embodiment. Regarding Fig. 59, differences from Fig. 14 in the case of the first embodiment will be described. The second differential phase value calculation unit 950R has a delay circuit ₉₅₂₄ in addition to the delay circuit 952, and further has a SEL unit 958R. The SEL unit 955R has been modified.

The second differential phase value calculation unit 950R calculates a second differential value VB, which is a complex number having a phase difference between the second correlation value B calculated using a received signal at a point in time that is the number of delay chips (1 or 4) earlier than the received signal used to calculate the second correlation value B.

The delay circuit 952 delays the input second correlation value B by a time equivalent to NB chips (2 NB samples). The time equivalent to NB chips (2 NB samples) is equal to the first chip time SA. The output of the delay circuit 952 is input to the delay circuit _952-4 . The delay circuit _952-4 delays the input second correlation value B by a time equivalent to 3 NB chips (6 NB samples). The output of the delay circuit 952 is delayed by a time equivalent to NB chips (2 NB samples) with respect to the second correlation value B input to the second differential phase value calculation unit 950R. The output of the delay circuit _952-4 is delayed by a time equivalent to 4 NB chips (8 NB samples).

The operation of the second differential phase value calculation unit 950R is controlled by a control signal G1R. G1R is not ON/OFF, but takes one of the values 0, 1, and 4. For example, the values that G1R takes are as follows. When G1R>0, the second differential phase value calculation unit 950R operates.
(Meaning of the value of control signal G1R)
0: The SEL unit 955R selects and outputs the second correlation value B.
1: The SEL unit 958R selects the output of the delay circuit 952, and the SEL unit 955R selects and outputs the second differential phase value VB.
4: The SEL unit 958R selects the output of the delay circuit ₉₅₂₄ , and the SEL unit 955R selects and outputs the second differential phase value VB.

The output of the SEL unit 958R is the phase θ _BDELAY . The value of the phase θ _BDELAY changes depending on whether the SEL unit 958R selects the output of the delay circuit 952 or the delay circuit _952-4 . The phase θ _BDELAY is input to the subtractor 953. The subtractor 953 subtracts θ _BDELAY from the phase θ _B of the second correlation value B.

When G1R=0, the SEL unit 955R selects the second correlation value B. When G1R>0, the SEL unit 955R selects the second differential phase value VB output by the amplitude-phase inverse conversion unit 954.

The configuration of the code selection unit 970R will be described with reference to Fig. 60. Fig. 60 is a diagram showing the configuration of the code selection unit included in the synchronization acquisition circuit according to embodiment 5. The code selection unit 970R has delay circuits 972 ₂ , 972 ₃ , and 972 ₄ in addition to the delay circuit 972, and has a multiplier 971 ₂ in addition to the multiplier 971. The SEL unit 973Z has been modified.

Each of delay circuit 972 ₂ , delay circuit 972 ₃ and delay circuit 972 ₄ delays the first spreading code CA[k] by one chip. The output of delay circuit 972 is input to delay circuit 972 _2. The output of delay circuit 972 ₂ is input to delay circuit 972 _3. The output of delay circuit 972 ₃ is input to delay circuit 972 _4. When CA[k] is input to delay circuit 972, delay circuit 972 outputs CA[k-1], delay circuit 972 ₂ outputs CA[k-2], delay circuit 972 ₃ outputs CA[k-3] and delay circuit 972 ₄ outputs CA[k-4].

A multiplier 971 multiplies CA[k] by CA[k-1] output from a delay circuit 972. A multiplier ₉₇₁₂ multiplies CA[k] by CA[k-4] output from a delay circuit ₉₇₂₄ .

The multiplier 971 ₂ outputs a difference code CD ₄ [k] having the following value:
If CA[k] = CA[k-4] = "1", then CD ₄ [k] = "1"
If CA[k] = CA[k-4] = "-1", then CD ₄ [k] = "1"
If CA[k] = "1" and CA[k-4] = "-1", then CD ₄ [k] = "-1"
If CA[k] = "-1" and CA[k-4] = "1", then CD ₄ [k] = "-1"

The differential code _CD4 [k] is a spreading code having a sequence length of 4NA, in which a spreading code of the first sequence length NA for k whose remainder when divided by 4 is 1, a spreading code of the first sequence length NA for k whose remainder when divided by 4 is 2, a spreading code of the first sequence length NA for k whose remainder when divided by 4 is 3, and a spreading code of the first sequence length NA for k whose remainder when divided by 4 is 0 are repeatedly output. The differential code _CD4 [k] is uniquely determined according to CA[k].

The operation of the code selection unit 970R is controlled by a control signal G2R. Like G11Z, G2R can take any value from 0 to 3. For example, the values that G2R can take are as follows:
(Meaning of the value of control signal G2R)
0: The SEL unit 973Z selects and outputs CA[k]. CX[k]=CA[k].
1: The SEL unit 973Z selects and outputs CD[k]. CX[k]=CD[k].
4: The SEL unit 973Z selects and outputs CD ₄ [k]. CX[k]=CD ₄ [k].

G1R and G2R are generated so that G2R = G1R at all times. If there is no frequency deviation, the CA correlation processing unit 910R can calculate the same first correlation value A in any of the cases of G1R = G2R = 0, G1R = G2R = 1, G1R = G2R = 2, and G1R = G2R = 4.

The operation control section 945R outputs control signals G1R, G2R, and G4R. G4R, which controls the operation of the frequency deviation calculation section 925R, takes the following value, for example.
(Meaning of the value of control signal G4R)
0: The second differential phase value calculation unit 950R is inactive.
1: The second differential phase value calculation unit 950R operates. When G1R=4.
2: The second differential phase value calculation unit 950R operates. When G1R=1.

When G4R=0 or G4R=2, the frequency deviation calculation unit 925R operates in the same manner as the frequency deviation calculation unit 925. When G4=1, the frequency deviation calculation unit 925R calculates ΔF as follows: ΔF=WA _AV /(8π*SA).

In the synchronization acquisition circuit 9R, the first accumulated value XA is the second differential correlation value WB when the second differential phase value calculation section 950 operates. When the second differential phase value calculation section 950 does not operate, the first accumulated value XA is the first correlation value A. The second differential correlation value WB or the first correlation value A is the first total value. The first total value is a complex number representing the sum of NA despread second accumulated values GB ₁ to GB _NA . The adder 914F is a first total value calculation section that calculates the first total value. The power calculation section 920 calculates the power of the first total value.

The operation will be described. At the start of communication, the operation control section 945R outputs control signals G1R=G2R=1 and G4R=2. When the synchronization acquisition circuit 9R operates and becomes capable of calculating the frequency deviation ΔF, the operation control section 945R changes the values of G1R, G2R, and G4R according to the magnitude of ΔF. The operation control section 945R uses a first threshold value TH ₁ and a second threshold value TH ₂ (TH ₂ <TH ₁ ). In the synchronization acquisition circuit 9R, the period when G4R=2 is the period of rough detection.

The operation control section 945R outputs a control signal in the following cases.
(A) If ΔF≧ _TH1 (rough detection), the second differential phase value calculation unit 950R outputs G1R=G2R=1 and G4R=2 so that the second differential phase value calculation unit 950R operates with the number of delay chips=1.
(a) If TH ₁ >ΔF≧TH ₂ (precise detection), the second differential phase value calculation unit 950R outputs G1R=G2R=4 and G4R=1 so that the second differential phase value calculation unit 950R operates with the number of delay chips=1.
(c) If TH ₂ > ΔF, G1R=G2R=G4R=0 are output so that the second differential phase value calculation unit 950R does not operate.

Even when the frequency deviation ΔF is large, the synchronization acquisition circuit 9R can calculate the frequency deviation with higher accuracy than conventional circuits to determine the synchronization sequence position of the spreading code. The synchronization acquisition circuit 9R can determine the synchronization sequence position of the spreading code with the same accuracy as the synchronization acquisition circuit 9. The synchronization acquisition circuit 9R does not have a first differential phase value calculation unit 960, and therefore has a simple configuration.

Embodiment 6.
The configuration of a synchronization acquisition circuit according to the sixth embodiment will be described with reference to Fig. 61. Fig. 61 is a functional block diagram showing the configuration of a synchronization acquisition circuit according to the sixth embodiment. The sixth embodiment is a modification of the first embodiment so as to have a two-stage first differential phase value calculation unit. Regarding Fig. 61, the differences from Fig. 14 for the first embodiment will be described.

In the sixth embodiment, two integers MC and DC are used such that MA=MC*DC. MC may be any positive integer smaller than the number of units MA. DC may be any integer equal to or greater than 2. In FIG. 61, DC=2. MC is called the second stage first division number or the second stage unit number. MC-1 is called the second stage first difference number or the second stage difference number. DC is called the second stage unit number. The despreading number 2NC=MA*2DA=MC*2DA*DC is divided by the second stage unit number MC to get 2NC/MC=2DA*DC, which is called the second stage unit number or the second stage first unit number. 2NC-2NC/MC=(MC-1)*2DA*DC is called the second stage difference number or the second stage first difference number.

The synchronization acquisition circuit 9S has modified CA correlation processing section 910S, frequency offset calculation section 925S, and operation control section 945S. CA correlation processing section 910S also has MC adders 917, (MC-1) first differential phase value calculation sections 96C, switches 996, and switches 997. One adder 917 sums the unit first integrated values UWA output by DC first differential phase value calculation sections 960. However, adder 917(1) sums (DC-1) UWAs. DC first differential phase value calculation sections 960 summed by one adder 917 have consecutive numbers. In other words, adder 917(1) calculates the sum of UWA ₁ to UWA _DC-1 output by first differential phase value calculation sections 960(1) to (DC-1). For i greater than 1, an adder 917(i) calculates the sum of UWA _DC*i-DC to UWA _{DC*i-1 output from first differential phase value calculation units 960 (DC*i-DC) to (DC*i-1} ). The output of the adder 917(i) is called a unit first correlation value EA _i .

The first differential phase value calculation unit 96C(i) receives the unit first correlation values EA _i+1 and EA _i, which are complex numbers, and calculates a first differential phase value FA _i having a phase difference between EA _i+1 and EA _i and an amplitude of unit amount. When the first differential phase value calculation unit 960 operates, the first differential phase value calculation unit 96C(i) does not calculate the first differential phase value FA _i . The first differential phase value calculation unit 96C(i) is controlled by the operation control unit 945S and outputs either the first differential phase value FA _i or the unit first correlation value EA _i+1 . The first differential phase value calculation unit 96C(i) calculates the first differential phase value FA _i, which is a complex number having a phase difference between the unit first correlation value EA _i+1 and the previous unit first correlation value EA _i . In addition, the first differential phase value calculation unit 96C(i) may uniformly switch between the unit first correlation value EA _i or the first differential phase value FA _i and output it. When the CA correlation processing unit has two stages of first differential phase value calculation units, the first differential phase value calculation unit 960 is called the first stage first differential phase value calculation unit, and the first differential phase value calculation unit 96C is called the second stage first differential phase value calculation unit.

The configuration of the second-stage first differential phase value calculation unit will be described with reference to FIG. 62. FIG. 62 is a diagram showing the configuration of the second-stage first differential phase value calculation unit of the synchronization acquisition circuit according to the sixth embodiment. The first differential phase value calculation unit 96C(i) has a configuration similar to that of the first differential phase value calculation unit 960(i). In the first differential phase value calculation unit 96C(i), the SEL unit 965 is controlled by a control signal G10. Also, the signals are represented by different variable names. The SEL unit 965 of the first differential phase value calculation unit 960(i) is controlled by a control signal G3. The first differential phase value calculation unit 960 and the first differential phase value calculation unit 96C are controlled so that neither operates or only one of them operates.

The signal processed by the first differential phase value calculation unit 96C(i) is expressed by a variable different from that of the first differential phase value calculation unit 960(i). The first differential phase value calculation unit 96C(i) receives the unit first correlation values EA _i and EA _i+1 . The first differential phase value calculation unit 96C(i) calculates the first differential phase value FA _i . The first differential phase value calculation unit 96C(i) outputs the unit first accumulated value HA _i, which is the first differential phase value FA _i or the unit first correlation value EA _i+1 .

The switch 996 is provided between the output of the unit first correlation value calculation unit 221(1) and the adder 917(1). The switch 996 is controlled to be turned on or off by the control signal G5 output by the operation control unit 945S. The control signal G5 is turned on when the control signal G3 that controls the operation of the first differential phase value calculation unit 960 is turned off. When the control signal G3 is turned off, the first differential phase value calculation unit 960 outputs the unit first integrated value. When the control signal G5 is turned on, the switch 996 is turned on. When the control signal G3 is turned on, the control signal G5 is turned off and the switch 996 is turned off. When the control signal G3 is turned on, the first differential phase value calculation unit 960 outputs the first differential phase value. When the switch 996 is turned on, the switch 996 outputs the unit first correlation value UA _1. When the switch 996 is turned off, the switch 996 outputs zero. By controlling the on/off of the switch 996 in this manner, it is possible to calculate the first correlation value A including the unitary first correlation value _UA1 output by the unitary first correlation value calculation unit 221(1).

The switch 996 is a first switch that is provided between the output of the most recent unit first correlation value calculation unit 221(1) and the adder 917(1), or between the output of the most recent unit first correlation value calculation unit 221(MA) and the adder 917(MC), and switches between an input complex number or zero and outputs it. When the first differential phase value calculation unit 960(i) outputs the previous unit first correlation value UA _i , the output of the most recent unit first correlation value calculation unit 221(MA) is input to the switch 996. When the first differential phase value calculation unit 960(i) outputs the newer unit first correlation value UA _i+1 , the output of the most recent unit first correlation value calculation unit 221(1) is input to the switch 996.

The switch 997 is provided between the adder 917(1) and the adder 914. The on/off of the switch 997 is controlled by a control signal G11 output by the operation control unit 945S. The control signal G11 is turned on when the control signal G10 that controls the operation of the first differential phase value calculation unit 96C is turned off. When the control signal G11 is input, the switch 997 is turned on. When the control signal G10 is on, the control signal G11 is turned off and the switch 997 is turned off. When the switch 997 is on, it outputs the unit first correlation value EA _i . When the switch 997 is off, it outputs zero. By controlling the on/off of the switch 997 in this way, the first correlation value A can be calculated including the unit first correlation value EA _{1 output by the adder 917(1} ).

The switch 997 is a second switch that is provided between the output of the most recent adder 917(1) and the adder 914, or between the output of the most recent adder 917(MC) and the adder 914, and switches between an input complex number or zero and outputs it. When the first differential phase value calculation unit 96C(i) outputs the earlier unit first correlation value EA _i , the output of the latest adder 917(MC) is input to the switch 997. When the first differential phase value calculation unit 96C(i) outputs the newer unit first correlation value EA _i+1 , the output of the most recent adder 917(1) is input to the switch 997.

The adder 914 adds the unit first accumulated values HA ₁ to HA _MC-1 output by the (MC-1) first differential phase value calculation units 96C(1) to (MC-1) and the output of the switch 997, and outputs an accumulated value XA which is the addition result. When the first differential phase value calculation unit 960 operates, the accumulated value XA is the first differential correlation value WA which is the sum of the first differential phase values VA ₁ to VA _MA-1 . When the first differential phase value calculation unit 96C operates, the accumulated value XA is the sum of the first differential phase values FA ₁ to FA _MC-1 . The sum of the first differential phase values FA ₁ to FA _MC-1 is called the first differential correlation value WH. When the second differential phase value calculation unit 950 operates, the accumulated value XA is the second differential correlation value WB which is the sum of the second differential phase values VB ₁ to VB _MA . When the second differential phase value 950, the first differential phase value calculator 960 and the first differential phase value calculator 96C do not operate, the integrated value XA is the first correlation value A which is the sum of the unit first correlation values UA ₁ to UA _MA .

The unitary first correlation value EA _i represents the sum of DC unitary first accumulated values UWA _i . The unitary first correlation value EA _i is a two-stage unit correlation value that is a complex number representing the sum of 2NC/MC consecutive despread received signals. The two-stage unit correlation value is also called a two-stage unitary first correlation value. The adders 917(1) to (MC) are two-stage unit correlation value calculation units for the number of two-stage units (MC) ordered by the despread received signal GR used in the calculation, which calculates the two-stage unit correlation value. The adders 917(1) to (MC) are also two-stage unitary first correlation value calculation units for the number of two-stage first division numbers MC ordered by the despread received signal GR used in the calculation, which calculates the two-stage unit first correlation value.

The second-stage differential phase value FA _i is a complex number having a phase difference between the second-stage unit correlation value EA _i+1 and the immediately previous second-stage unit correlation value EA _i . The first differential phase value calculation units 96C(1) to (MC-1) are two-stage differential phase value calculation units that calculate the two-stage differential phase value FA _i .

The first differential correlation value WH is a two-stage differential correlation value which is the sum of the two-stage differential phase values FA ₁ to FA _MC-1 . The sum of the two-stage differential phase values FA ₁ to FA _MC-1 is the sum of despread received signals that is equal to or greater than the two-stage difference number and equal to or less than the despread number. When the first differential phase value calculation unit 96C is operating, the adder 914 is a two-stage differential correlation value calculation unit that calculates the two-stage differential correlation value.

The operation control section 945S outputs control signals G1, G2, G3, G4S, G5, G10, and G11. G3, which controls the first differential phase value calculation section 960, has an ON/OFF value as in the first embodiment. G4S, which controls the operation of the frequency deviation calculation section 925S, has the following values, for example. The operation control section 945S controls whether to operate either the first differential phase value calculation section 960 or the first differential phase value calculation section 96C, or to operate neither of them.
(Meaning of the value of control signal G4S)
0: The second differential phase value calculation unit 950, the first differential phase value calculation unit 960, and the first differential phase value calculation unit 96C are inactive.
1: The first differential phase value calculation unit 960 operates.
2: The second differential phase value calculation unit 950 operates.
4: The first differential phase value calculation unit 96C operates.

When G4S=0, G4S=1, or G4S=2, the frequency deviation calculation unit 925S operates in the same manner as the frequency deviation calculation unit 925. When G4S=4, the frequency deviation calculation unit 925S calculates ΔF as follows: ΔF=WA _AV /(π*DA*DC*SA).

In the synchronization acquisition circuit 9S, the first accumulated value XA is the first differential correlation value WA when the first differential phase value calculation unit 960 operates. When the first differential phase value calculation unit 96C operates, it is the first differential correlation value WH. When the second differential phase value calculation unit 950 operates, the first accumulated value XA is the second differential correlation value WB. When the first differential phase value calculation unit 960, the first differential phase value calculation unit 96C, and the second differential phase value calculation unit 950 do not operate, the first accumulated value XA is the first correlation value A. When the first differential phase value calculation unit 960 and the first differential phase value calculation unit 96C do not operate, the first accumulated value XA is the first total value. The first accumulated value XA is the first total value, the first differential correlation value WA, or the first differential correlation value WH.

The operation will be described. At the start of communication, the operation control section 945S outputs control signals G4S=2, G1=G2=G5=G11=ON, and G3=G10=OFF. When the synchronization acquisition circuit 9S operates and the frequency deviation ΔF can be calculated, the operation control section 945S changes the values of G1, G2, G3, G4S, G5, G10, and G11 according to the magnitude of ΔF. The operation control section 945S uses a fifth threshold _TH5 in addition to the first threshold _TH1 and the second threshold _TH2 . Each threshold is determined so that the relationship _TH2 < _TH5 < _TH1 is established. In the synchronization acquisition circuit 9S, the period when G1=G2=ON is set as the period of rough detection. The period when G3=ON or G10=ON is set as the period of precise detection.

The operation control section 945S outputs a control signal in the following cases.
(A) If ΔF≧ _TH1 (rough detection), the second differential phase value calculation unit 950R outputs G4S=2, G1=G2=G5=G11=ON, and G3=G10=OFF so that the second differential phase value calculation unit 950R operates.
(a1) If TH ₁ > ΔF≧TH ₅ (precise detection 1), G4S=1, G1=G2=G5=G10=OFF, and G3=G11=ON are output so that the first differential phase value calculation unit 960 operates.
(a2) If _TH5 > _{.DELTA.F.gtoreq.TH2} (precise detection 2), G4S=4, G1=G2=G3=G11=OFF, and G5=G10=ON are output so that the first differential phase value calculation unit 96C operates.
(c) If TH ₂ > ΔF, output G4S=0, G1=G2=G3=G10=OFF, and G5=G11=ON so that none of the controls operates.

The synchronization acquisition circuit 9S operates in the same manner as the synchronization acquisition circuit 9 during the coarse detection and fine detection 1 periods. Figure 63 is a diagram showing the operating state in which the second differential phase value calculation unit 950 of the synchronization acquisition circuit operates. The complex signals measured at each unit when the second differential phase value calculation unit operates are similar to those in Figure 19 for the synchronization acquisition circuit 9. Figure 64 is a diagram showing the operating state in which the first stage first differential phase value calculation unit 960 of the synchronization acquisition circuit operates. The complex signals measured at each unit when the first stage first differential phase value calculation unit 960 operates during the fine detection 1 period are similar to those in Figure 27 for the synchronization acquisition circuit 9.

When the frequency deviation ΔF becomes smaller than the fifth threshold _TH5 , the second-stage first differential phase value calculation unit 96C operates. Fig. 65 is a diagram showing an operating state in which the second-stage first differential phase value calculation unit 96C of the synchronization acquisition circuit operates. Complex signals measured at each unit when the second-stage first differential phase value calculation unit 960 operates during fine detection 2 are as shown in Fig. 66. The frequency deviation ΔF in Fig. 66 is about 45% of the frequency deviation ΔF in the case shown in Fig. 27. Fig. 65 is a diagram showing complex signals measured at each unit when the second-stage first differential phase value calculation unit of the synchronization acquisition circuit according to embodiment 6 operates.

In Fig. 66(C), the frequency deviation ΔF is smaller than in Fig. 27, but the phase of the despread received signal GB _m gradually increases as in Fig. 27(C). Fig. 66(D) shows the unit first correlation value EA _m measured at point P _7.m. Although the frequency deviation ΔF is small, the number of GB _m to be summed is DC (=2) times larger, so EA _m becomes a vector with amplitude |EA _m |=7.8 having the same phase as UA _m shown in Fig. 27(D). Fig. 66(E) shows the first differential phase value FA _m measured at point P _8.m. FA _m becomes a unit vector having the same phase as UA _m shown in Fig. 27(E). WH ₃₂ shown in Fig. 66(F) also becomes a vector similar to WA shown in Fig. 27(E). It can be seen that the first differential phase value calculation section 96C in the second stage can detect the frequency deviation ΔF with the same accuracy as the first differential phase value calculation section 960 in the first stage when the frequency deviation ΔF is half.

Even when the frequency deviation ΔF is large, the synchronization acquisition circuit 9S can calculate the frequency deviation with higher accuracy than before and determine the synchronization sequence position of the spread code. When the frequency deviation ΔF becomes smaller, the synchronization acquisition circuit 9S can change the level at which the phase change is detected more finely compared to the synchronization acquisition circuit 9, and can determine the synchronization sequence position of the spread code with higher accuracy. The accuracy of determining the frequency deviation is also improved.

Embodiment 7.
The configuration of a synchronization acquisition circuit according to the seventh embodiment will be described with reference to Fig. 67. Fig. 67 is a functional block diagram showing the configuration of a synchronization acquisition circuit according to the seventh embodiment. The seventh embodiment is a modification of the sixth embodiment so as to include a second differential phase value calculation unit included in the synchronization acquisition circuit according to the fourth embodiment. Regarding Fig. 67, the differences from Fig. 61 for the sixth embodiment will be described.

The synchronization acquisition circuit 9T has modified CA correlation processing section 910T, frequency offset calculation section 925T, and operation control section 945T. CA correlation processing section 910T has a second differential phase value calculation section 950Q and a code selection section 970Q. The second differential phase value calculation section 950Q calculates a second differential value VB, which is a complex number having a phase difference between the second correlation value B calculated using a received signal at a time point that is the number of delay chips (1 or 2) before the received signal used when calculating the second correlation value B. The code selection section 970Q selects and outputs one of CA[k], CD[k], and CD ₂ [k].

The operation control section 945T outputs control signals G1Q, G2Q, G3, G4T, G5, G10, and G11. G1Q, which controls the second differential phase value calculation section 950Q, takes one of the values 0, 1, and 2, as in the fourth embodiment. The sign selection section 970Q takes one of the values 0, 1, and 2, as in the fourth embodiment. It is controlled so that G1Q=G2Q at all times. G3, which controls the first differential phase value calculation section 960, G5, which controls the switch 996, G10, which controls the first differential phase value calculation section 96C, and G11, which controls the switch 996, take ON/OFF values, as in the sixth embodiment. G4T, which controls the operation of the frequency deviation calculation section 925T, takes, for example, the following values.
(Meaning of the value of control signal G4T)
0: The second differential phase value calculation unit 950, the first differential phase value calculation unit 960, and the first differential phase value calculation unit 96C are inactive.
1: The first differential phase value calculation unit 960 operates.
2: The second differential phase value calculation unit 950Q operates. When G1Q=1.
3: The second differential phase value calculation unit 950Q operates. When G1Q=2.
4: The first differential phase value calculation unit 96C operates.

The frequency deviation calculation unit 925T operates in the same manner as the frequency deviation calculation unit 925 when G4T=0, G4T=1, or G4T=2. When G4T=3, the frequency deviation calculation unit 925T calculates ΔF as follows: ΔF=WA _AV /(4π*SA). When G4T=4, the frequency deviation calculation unit 925T calculates ΔF as follows: ΔF=WA _AV /(π*DA*DC*SA).

In each case, the first integrated value XA in the synchronization acquisition circuit 9T is the same as the first integrated value XA in the synchronization acquisition circuit 9S.

The operation will be described. At the start of communication, the operation control unit 945T outputs control signals G4T=2, G1Q=G2Q=1, G3=OFF, G3=G10=OFF, and G5=G11=ON. When the synchronization acquisition circuit 9T operates and the frequency deviation ΔF can be calculated, the operation control unit 945T changes the values of G1Q, G2Q, G3, G4S, G5, G10, and G11 according to the magnitude of ΔF. The operation control unit 945T uses a fourth threshold _TH4 and a fifth threshold _TH5 in addition to the first threshold _TH1 and the second threshold _TH2 . Each threshold is determined so that the relationship _TH2 < _TH5 < _TH1 < _TH4 is established. In the synchronization acquisition circuit 9T, the period when G1Q=G2Q=1 or G1Q=G2Q=2 is the period of rough detection. The period when G3=ON or G10=ON is set as the period of fine detection.

The operation control section 945T outputs a control signal in the following cases.
(A1) If ΔF≧ _TH4 (rough detection 1), the second differential phase value calculation unit 950T outputs G4T=2, G1Q=G2Q=1, G3=G10=OFF, and G5=G11=ON so that the second differential phase value calculation unit 950T operates with the number of delay chips=1.
(A2) If _TH4 > ΔF≧ _TH1 (rough detection 2), the second differential phase value calculation unit 950T outputs G4T=3, G1Q=G2Q=2, G3=G10=OFF, and G5=G11=ON so that the second differential phase value calculation unit 950T operates with the number of delay chips=2.
(a1) If TH ₁ > ΔF≧TH ₅ (precise detection 1), G4T=1, G1Q=G2Q=0, G3=G11=ON, and G5=G10=OFF are output so that the first differential phase value calculation unit 960 operates.
(a2) If _TH5 > _{.DELTA.F.gtoreq.TH2} (precise detection 2), G4T=4, G1Q=G2Q=0, G3=G11=OFF, and G5=G10=ON are output so that the first differential phase value calculation unit 96C operates.
(c) If TH ₂ > ΔF, then G4T=0, G1Q=G2Q=0, G3=G10=OFF, and G5=G11=ON are output so that none of the gates operates.

The synchronization acquisition circuit 9T operates in the same manner as the synchronization acquisition circuit 9Q during the periods of coarse detection 1 and coarse detection 2. The synchronization acquisition circuit 9T operates in the same manner as the synchronization acquisition circuit 9S during the periods of fine detection 1 and fine detection 2.

Even when the frequency deviation ΔF is large, the synchronization acquisition circuit 9T can calculate the frequency deviation with higher accuracy than before and determine the synchronization sequence position of the spread code. When the frequency deviation ΔF becomes smaller, the synchronization acquisition circuit 9T can change the level at which the phase change is detected more finely compared to the synchronization acquisition circuit 9, and can determine the synchronization sequence position of the spread code with higher accuracy. The accuracy of determining the frequency deviation also becomes higher.

Embodiment 8.
The configuration of a synchronization acquisition circuit according to the eighth embodiment will be described with reference to Fig. 68. Fig. 68 is a functional block diagram showing the configuration of a synchronization acquisition circuit according to the eighth embodiment. The eighth embodiment is a modification of the first embodiment so as not to have a second differential phase value calculation unit. Regarding Fig. 68, the differences from Fig. 14 for the first embodiment will be described.

The synchronization acquisition circuit 9U has modified CA correlation processing unit 910U, frequency deviation calculation unit 925U, and operation control unit 945U. The CA correlation processing unit 910U does not have a second differential phase value calculation unit 950 or a code selection unit 970.

The operation control unit 945U controls the operation of the first differential phase value calculation unit 960 and the frequency deviation calculation unit 925U. The operation control unit 945U outputs control signals G3 and G4U. The operation control unit 945U differs from the operation control unit 945 in that it does not output control signals G1 and G2.

G4U, which controls the operation of the frequency deviation calculation unit 925U, takes, for example, the following value: G4U is different from G4 output by the operation control unit 945 in that G4U does not take on the value G4U=2.
(Meaning of the value of control signal G4U)
0: The first differential phase value calculation unit 960 is inactive.
1: The first differential phase value calculation unit 960 operates.

The frequency deviation calculation unit 925U calculates the frequency deviation ΔF in the same way as when G4=0 and G4=1 in the frequency deviation calculation unit 925.

In the synchronization acquisition circuit 9U, the first accumulated value XA is the first differential correlation value WA when the first differential phase value calculation unit 960 is operating. When the first differential phase value calculation unit 960 is not operating, the first accumulated value XA is the first correlation value A.

The operation will be described. At the start of communication, the operation control unit 945U outputs control signals G4=1 and G3=ON. When the frequency deviation ΔF becomes small enough to be determined as zero while the first differential phase value calculation unit 960 is in operation, the operation control unit 945U outputs control signals G4=0 and G3=OFF. Whether the frequency deviation ΔF is small enough to be determined as zero is determined by comparing with the first threshold value _TH1 . When the frequency deviation ΔF becomes smaller than the first threshold value _TH1 (ΔF< _TH1 ), the first differential phase value calculation unit 960 is not operated and is inactivated.

The operation control unit 945U outputs a control signal in the following cases.
(A) If ΔF≧ _TH1 , output G4=1 and G3=ON so that the first differential phase value calculation unit 960 operates.
(a) If TH ₁ >ΔF, G4=0 and G3=OFF are output so that neither operates.

The first differential phase value calculation unit 960 divides one period of the received signal of the spreading code into MA parts, which is an integer equal to or greater than 3, and calculates the frequency deviation by obtaining the phase change between the complex numbers of the sum of the second accumulated values _GBm after despreading in the divided periods. Therefore, the synchronization sequence position of the spreading code can be obtained with higher accuracy than the conventional method shown in Patent Document 1, which divides one period of the received signal into two. The accuracy of obtaining the frequency deviation is also high.

DA, which is the number of pieces for calculating the sum of the second accumulated value GB _i after despreading, may be 1 or more. When DA=1, the outputs of two chip correlators 912(i) to (i+1) with consecutive numbers may be input to the first differential phase value calculation section 960(i). In this case, the unit first correlation value calculation unit 221 and the adder 913 may not be provided. When DA=1, the first differential phase value calculation section 960 can calculate the frequency deviation with the same accuracy as the second differential phase value calculation section 950 and obtain the synchronization sequence position of the spreading code.

Embodiment 9.
The configuration of a synchronization acquisition circuit according to the ninth embodiment will be described with reference to Fig. 69. Fig. 69 is a functional block diagram showing the configuration of a synchronization acquisition circuit according to the ninth embodiment. The ninth embodiment is a modification of the sixth embodiment so as not to have a second differential phase value calculation unit. Regarding Fig. 69, the differences from Fig. 61 for the sixth embodiment will be described.

The synchronization acquisition circuit 9V has modified CA correlation processing unit 910V, frequency deviation calculation unit 925V, and operation control unit 945V. The CA correlation processing unit 910V does not have a second differential phase value calculation unit 950 or a code selection unit 970.

The operation control unit 945V controls the operation of the first differential phase value calculation unit 960, the first differential phase value calculation unit 96C, and the frequency deviation calculation unit 925V. The operation control unit 945V outputs control signals G3, G4V, G5, G10, and G11. The operation control unit 945V differs from the operation control unit 945S in that it does not output control signals G1 and G2.

G4V, which controls the operation of the frequency deviation calculation unit 925V, takes the following value, for example: G4V is different from G4S output by the operation control unit 945S in that G4V does not take the value G4V=2.
(Meaning of the value of control signal G4V)
0: The first differential phase value calculation unit 960 and the first differential phase value calculation unit 96C are inactive.
1: The first differential phase value calculation unit 960 operates.
4: The first differential phase value calculation unit 96C operates.

The frequency deviation calculation unit 925V calculates the frequency deviation ΔF in the same way as the frequency deviation calculation unit 925S when G4S=0, G4S=1, and G4S=4.

In the synchronization acquisition circuit 9V, the first accumulated value XA is the first differential correlation value WA when the first differential phase value calculation unit 960 operates. When the first differential phase value calculation unit 96C operates, it is the first differential correlation value WH. When the first differential phase value calculation unit 960 and the first differential phase value calculation unit 96C do not operate, the first accumulated value XA is the first correlation value A.

The operation will be described. At the start of communication, the operation control unit 945V outputs control signals G4V=2, G5=G11=ON, and G3=G10=OFF. When the synchronization acquisition circuit 9V operates and becomes capable of calculating the frequency deviation ΔF, the operation control unit 945V changes the values of G3, G4V, G5, G10, and G11 according to the magnitude of ΔF. The operation control unit 945V uses a first threshold value _TH1 and a second threshold value _TH2 . Each threshold value is determined so that the relationship _TH2 < _TH1 is established.

The operation control section 945V outputs a control signal in the following cases.
(A) If ΔF≧ _TH1 , G4V=1, G5=G10=OFF, and G3=G11=ON are output so that the first differential phase value calculation unit 960 operates.
(a) If TH ₁ > ΔF≧TH ₂ , G4V=4, GG3=G11=OFF, and G5=G10=ON are output so that the first differential phase value calculation unit 96C operates.
(c) If TH ₂ > ΔF, output G4V=0, G3=G10=OFF, and G5=G11=ON so that none of them operates.

The first differential phase value calculation unit 96C divides one period of the received signal of the spreading code into MC parts, where MC is an integer equal to or greater than 3, and calculates the frequency deviation by obtaining the phase change between the complex numbers of the sum of the second integrated values _GBm after despreading in the divided periods. Therefore, the synchronization sequence position of the spreading code can be obtained with higher accuracy than the conventional method shown in Patent Document 1, which divides one period of the received signal into two parts.

There are MA=MC*DC first differential phase value calculation units 960. DC is an integer equal to or greater than 2. The first differential phase value calculation unit 960 has more units than the first differential phase value calculation unit 96C and divides the received signal for one period of the spreading code more finely, so that even when a larger frequency change ΔF occurs, the synchronization sequence position of the spreading code can be found with higher accuracy than with conventional methods. The accuracy of finding the frequency deviation is also improved.

Since the synchronization acquisition circuit 9V does not have a second differential phase value calculation unit 950, DA only needs to be 1 or greater. When DA=1, the first differential phase value calculation unit 960 operates in the same manner as the second differential phase value calculation unit 950. However, NA first differential phase value calculation units 960 are required. Having a second differential phase value calculation unit 950 simplifies the configuration.

Embodiment 10.
The configuration of a synchronization acquisition circuit according to embodiment 10 will be described with reference to Fig. 70. Fig. 70 is a functional block diagram showing the configuration of a synchronization acquisition circuit according to embodiment 10. Embodiment 10 is a case where embodiment 8 is modified so that a general spreading code, not limited to a cascade-connected spreading code, has a configuration equivalent to that of the first differential phase value calculation unit. Regarding Fig. 70, the points different from Fig. 68 for embodiment 8 will be described.

The synchronization acquisition circuit 9W does not have a CB correlation processing unit 901 or a CA correlation processing unit 910U. Instead, the synchronization acquisition circuit 9W has a correlation processing unit 921. The correlation processing unit 921 performs correlation processing between the received signal, the BB signal (BBI3+jBBQ3), and the spreading code CE. The BB signal is oversampled by a factor of two. There are two BB signals per chip, and the excess coefficient of the BB signal is 2. In addition, the frequency deviation calculation unit 925W and the operation control unit 945W have been modified. 2NE is the total number of time points obtained by multiplying the sequence length NE by the excess coefficient 2. Note that if the received signal is not oversampled, the total number of time points will be the same as the sequence length NE.

The spreading code CE is a spreading code such as an M sequence or a Gold code. The sequence length of the spreading code CE is NE, and the chip time is SE. Any spreading code may be used as long as it is a pseudo-random number that takes two values. The sequence length NE is expressed as the product of the number of units ME and the number of units DE. In other words, NE = DE * ME. The number of units ME is an integer greater than or equal to 3. The number of units DE is an integer greater than or equal to 2. 2DE is the number of units obtained by dividing the total number of time points 2NE by the number of units.

The correlation processing unit 921 has ME unit correlation value calculation units 231(1) to 221(ME), (ME-1) differential phase value calculation units 990(1) to (ME-1), a switch 996, and an adder 926. The correlation processing unit 921 has a total of 2NE DFFs 922. The 2NE DFFs 922 are connected in vertical row in numerical order. Each unit correlation value calculation unit 231(i) has 2DE DFFs 922. The unit correlation value calculation unit 231(1) has DFFs 922(1) to (2DE). The unit correlation value calculation unit 231(i) has DFFs 922(2DE*(i-1)+1) to (2DE*i). The unit correlation value calculation unit 231 (ME) has DFFs 922 (2NE-2DE+1) to (2NE). The DFF 922 (2DE) of the unit correlation value calculation unit 231 (1) is connected to the DFF 922 (2DE+1) belonging to the unit correlation value calculation unit 231 (2). The DFF 922 (2DE*i) of the unit correlation value calculation unit 231 (i) is connected to the DFF 922 (2DE*i+1) belonging to the unit correlation value calculation unit 231 (i+1). Therefore, each unit correlation value calculation unit 231 (i) is connected vertically in numerical order. A BB signal (BBI3+jBBQ3) is input to the DFF 922 (2ME) of the unit correlation value calculation unit 231 (2ME) every time SE/2 has elapsed.

Each unit correlation value calculation unit 231(i) has 2DE DFFs 922 (2DE*(i-1)+1) to (2DE*i), 2DE chip correlators 923 (2DE*(i-1)+1) to (2DE*i), and one adder 924(i). One chip correlator 923(i) multiplies the complex BB signal (BBI3[k]+jBBQ3[k]) held in DFF 922(k) by the spreading code CE[m] according to the following equation (14). m is calculated using the Gaussian symbol, m=[(k+1)/2]. The signal obtained by the multiplication is called the despread received signal GR.

The despread received signal GR[k] is calculated using the formula below: GR[k] = (BBI3[k] + jBBQ3[k]) * CB[m] (14)
The number k of the chip correlator 923(k) is the same as the number k of the DFF 922(k) that supplies the BB signal. Since the BB signal is oversampled by a factor of two, the spreading code CE[m] is supplied to the chip correlator 923(2m-1) and the chip correlator 923(2m).

Adder 924(i) calculates the sum of GR 2DE*(i-1) _{+1 to GR 2DE*i output by 2DE chip correlators 923 (2DE*(i-1) +1} ) to (2DE*i). The sum of GR _2DE*(i-1)+1 to GR _2DE*i calculated by adder 924(i) is called unit correlation value UE _i . Unit correlation value UE _i is the output of unit correlation value calculation unit 231(i).

The unit correlation value UE _i is a complex number representing the sum of the number of units (2DE) of consecutive despread received signals GR. The unit correlation value calculation units 231(1) to (NE) are the number of unit correlation value calculation units (ME) ordered by the number of despread received signals used in the calculation to calculate the unit correlation value.

The differential phase value calculation unit 990(i) receives the unit correlation values UE _i and UE _i+1 output by the unit correlation value calculation units 231(i), (i+1). The differential phase value calculation unit 990(i) is controlled by the control signal G3W to operate or not. When G3W=ON, the differential phase value calculation unit 990(i) operates and calculates the phase difference between UE _i and UE _i+1 and the differential phase value VE _i having the amplitude of the unit amount. When G3W=OFF, the differential phase value calculation unit 990(i) does not operate and outputs UE _i+1 . The differential phase value calculation unit 990(i) is controlled by the operation control unit 945W to output either the differential phase value VE _i or the unit correlation value UE _i+1 . The output of the differential phase value calculation unit 990(i) is referred to as a unit integrated value _UWEi .

The differential phase value VE _i is a complex number representing the phase difference between the unit correlation value UE _i+1 and the immediately previous unit correlation value UE _i . The differential phase value calculation section 990(i) calculates the differential phase value VE _i .

The switch 996 is provided between the output of the unit correlation value calculation unit 231(1) and the adder 926. The on/off of the switch 996 is controlled by the control signal G5 output by the operation control unit 945W. The control signal G5 is turned on when the control signal G3W that controls the operation of the differential phase value calculation unit 990 is turned off. When the control signal G5 is turned on, the switch 996 is turned on. When the control signal G3W is turned on, the control signal G5 is turned off and the switch 996 is turned off. When the switch 996 is turned on, it outputs the unit correlation value _UE1 . When the switch 996 is turned off, it outputs zero. By controlling the on/off of the switch 996 in this way, the correlation value E can be calculated including the unit correlation value UE1 output by the unit correlation value calculation unit 231( ₁ ).

The adder 926 adds the unit integrated values UWE ₁ to UWE _ME-1 output by the (ME-1) differential phase value calculation units 990(1) to (ME-1) and outputs the output of the switch 996, and outputs the addition result. The adder 926 has an adder for the real part of the complex number and an adder for the imaginary part. When the differential phase value calculation unit 990(i) operates to output the differential phase value VE _i , the output of the adder 926 is the differential correlation value WE which is the sum of the differential phase values VE ₁ to VE _ME-1 . The adder 926 when calculating the differential correlation value WE is a differential correlation value calculation unit. When the differential phase value calculation unit 990(i) does not operate to output the unit correlation value UE _i+1 , the switch 996 is turned on, and the output of the adder 926 is the correlation value E which is the sum of the unit correlation values UE ₁ to UE _ME . The adder 926 used for calculating the correlation value E is a correlation value accumulating section. The output of the adder 926 is the output of the correlation processing section 921. The differential correlation value WE or correlation value E output by the correlation processing section 921 is called an accumulated value XE.

The switch 996 may be omitted. If the switch 996 is not present, the unit correlation value UE- ₁ is not added to the correlation value E output by the adder 926. When the differential phase value calculation section 990 does not operate, the unit correlation value UE- _i may be output. In that case, the switch 996 is provided between the output of the unit correlation value calculation unit 231 (ME-1) and the adder 926.

As in the first modification of the first embodiment, the correlation value E may be calculated by multiplying the oversampled received signal by each of the received signals of the number of sequence lengths selected to have chip time intervals and each of the spreading codes determined according to the position in the sequence length of the chip to which each of the received signals belongs. In that case, the correlation value E represents the sum of the number of despread received signals GR of the sequence length NE. The total number of time points or sequence length is called the despread number. The number of units is the number obtained by dividing the despread number by the number of units. The number obtained by subtracting the number of units from the despread number is called the difference number.

The adder 926 is a correlation value accumulator that calculates a correlation value E, which is a complex number representing the sum of 2NE despread received signals GR. If the switch 996 is not present, the correlation value E becomes a complex number representing the sum of 2NE-2DE despread received signals GR, where 2NE-2DE is the number of differences. The adder 926 may be any device that calculates a sum of despread received signals GR that is equal to or greater than the number of differences and equal to or less than the number of despreads.

The configuration of the differential phase value calculation unit will be described with reference to FIG. 71. FIG. 71 is a diagram showing the configuration of the differential phase value calculation unit of the synchronization acquisition circuit according to embodiment 10. The differential phase value calculation unit 990 has a similar configuration to the first differential phase value calculation unit 960, except that the signs are different. The differential phase value calculation unit 990(i) has an amplitude phase conversion unit 991, an amplitude phase conversion unit 992, a subtractor 993, an amplitude phase inverse conversion unit 994, and a SEL unit 995.

The differential phase value calculation unit 990(i) receives the unit correlation values UE _i+1 and UE _i every time SE/2 elapses. The amplitude and phase conversion unit 991 converts the unit correlation value UE _i+1 expressed in rectangular coordinates into amplitude and phase polar coordinate values. The input unit correlation value UE _i+1 is expressed as UE _i+1 =UEI _i+1 +jUEQ _i+1 . The amplitude and phase conversion unit 991 calculates the amplitude |UE _i+1 | and phase θ _UE(i+1) of the unit correlation value UE _i+1 using the following equations.
|UE _i+1 |=√(UEI _i+1 ² +UEQ _i+1 ² )
θ _UE(i+1) = sin ^-1 (UEQ _i+1 /|UE _i+1 |)

The amplitude-phase converter 992 converts the unit correlation value UE _i expressed in Cartesian coordinates into amplitude and phase polar coordinate values. The amplitude-phase converter 992 calculates the amplitude |UE _i | and phase θ _UE(i) of the unit correlation value UE _i using the following equations.
|UE _i |=√(UEI _i ² +UEQ _i ² )
θ _UE(i) = sin ⁻¹ (UEQ _i /|UE _i |)

The phase θ _UE(i+1) output by the amplitude phase converter 991 and the phase θ _UE(i) output by the amplitude phase converter 992 are input to a subtractor 993. The subtractor 993 outputs a phase difference Δθ _UE(i) calculated by the following equation.
Δθ _UE(i) = θ _UE(i+1) -θ _UE(i)

The amplitude/phase inverse converter 994 receives the phase difference Δθ _UE(i) and outputs a differential phase value VE _i =VEI _i +jVEQ _i which is a complex number having a unit amplitude.
VE _i =exp(jΔθ _UE(i) )
VEI _i = cos(Δθ _UE(i) )
VEQ _i = sin(Δθ _UE(i) )
The differential phase value VE _i is a complex number that exists on a unit circle in the complex plane.

The SEL unit 995 receives the unit correlation value UE _i+1 and the differential phase value VE _i . The SEL unit 995 receives the control signal G3W from the operation control unit 945W. When the control signal G3W is ON, the SEL unit 995 outputs the differential phase value VE _i . When the control signal G3W is OFF, the SEL unit 995 outputs the unit correlation value UE _i+1 . The output of the SEL unit 995 is the output of the differential phase value calculation unit 990(i). When the control signal G3W is ON, the differential phase value calculation unit 990(i) outputs the differential phase value VE _i . When the control signal G3W is OFF, the differential phase value calculation unit 990(i) outputs the unit correlation value UE _i+1 .

The operation control unit 945W controls the operation of the differential phase value calculation unit 990, the switch 996, and the frequency deviation calculation unit 925W. The operation control unit 945W outputs control signals G3W, G4W, and G5. The operation control unit 945W differs from the operation control unit 945 in that it does not output control signals G1 and G2, but outputs G5. The operation control unit 945W controls whether or not to operate the differential phase value calculation unit 990.

G4W, which controls the operation of the frequency deviation calculation unit 925W, takes the following value, for example: G4W is different from G4 output by the operation control unit 945 in that G4W does not take on the value G4W=2.
(Meaning of the value of control signal G4W)
0: The differential phase value calculation unit 990 is inactive.
1: The differential phase value calculation unit 990 operates.

The frequency deviation calculation unit 925W calculates the frequency deviation ΔF based on the integrated value XE output by the correlation processing unit 921. The frequency deviation calculation unit 925W receives a control signal G4W from the operation control unit 945W. The frequency deviation calculation unit 925W calculates the frequency deviation ΔF using a method according to the value of G4W.

When the differential phase value calculation unit 990 does not operate (G4W=0), the integrated value XE is the correlation value E. The frequency deviation calculation unit 925W receives the correlation value E every time SE/2 elapses. The frequency deviation calculation unit 925W finds a linear function that minimizes the square error that approximates the time change in the phase of the correlation value E input in the latest determined period TX. Based on the slope E _incl of the linear function, the frequency deviation ΔF=E _incl /(2π) is calculated. The slope E _incl is a value proportional to the frequency change rate, which is the time change in the frequency deviation. The frequency deviation calculation unit 925W calculates the frequency deviation ΔF based on the time change rate of the phase of the correlation value E.

When the differential phase value calculation unit 990 operates (G4W=1), the integrated value XE is the differential correlation value WE. When the differential phase value calculation unit 990 operates (G4W=1), the phase of WE is the phase change caused by the frequency deviation ΔF in the time DE*SE. The average of the differential correlation values WE input during the period TX is represented as WE _AV . When G4W=1, the frequency deviation calculation unit 925W calculates ΔF as ΔF=WE _AV /(2π*DE*SE).

The operation will be described. At the start of communication, the operation control unit 945W outputs control signals G3W=ON, G4W=1, and G5=OFF. When the frequency deviation ΔF becomes small enough to be determined as zero while the differential phase value calculation unit 990 is operating, the operation control unit 945W outputs control signals G3W=OFF, G4W=0, and G5=ON. Whether the frequency deviation ΔF is small enough to be determined as zero is determined by comparing with the first threshold value _TH1 . When the frequency deviation ΔF becomes smaller than the first threshold value _TH1 (ΔF< _TH1 ), the operation control unit 945W disables the differential phase value calculation unit 990.

The operation control section 945W outputs a control signal in the following cases.
(A) If ΔF≧ _TH1 , G4W=1, G3W=ON, and G5=OFF are output so that the differential phase value calculation unit 990 operates.
(a) If TH ₁ >ΔF, G4W=0, G3W=OFF, and G5=ON are output so that the differential phase value calculation unit 990 does not operate.

The differential phase value calculation unit 990 divides one period of the received signal of the spreading code into ME parts, where ME is an integer number equal to or greater than 3, and calculates the frequency deviation by determining the phase change between the complex numbers of the sum of the despread received signal GR in the divided periods. Therefore, the synchronization sequence position of the spreading code can be determined with higher accuracy than the conventional method shown in Patent Document 1, which divides one period of the received signal into two. The accuracy of determining the frequency deviation is also high.

Below, we will explain the variations of the tenth embodiment. Each variation can be freely combined with other variations. Each variation and a free combination of multiple variations can also be applied to other embodiments.

13th variant:
The configuration of a thirteenth modified example of the synchronization acquisition circuit according to embodiment 10 will be described with reference to Fig. 72. Fig. 72 is a functional block diagram showing the configuration of a thirteenth modified example of the synchronization acquisition circuit according to embodiment 10. In the thirteenth modified example, when differential phase value calculation section 990A does not operate, unit correlation value _UEi is output.

Compared to the synchronization acquisition circuit 9W, the synchronization acquisition circuit 9WA has a modified correlation processing unit 921A. The correlation processing unit 921A has a differential phase value calculation unit 990A. In addition, a switch 996 is provided between the output of the unit correlation value calculation unit 231 (ME-1) and the adder 926.

The configuration of the differential phase value calculation unit 990A will be described with reference to Figure 73. Figure 73 is a diagram showing the configuration of the differential phase value calculation unit of a thirteenth modified example that modifies the synchronization acquisition circuit according to embodiment 10. Regarding Figure 73, the differences from Figure 71 in the case of embodiment 10 will be described.

The SEL unit 995 receives the unit correlation value _UEi and the differential phase value _VEi . When the control signal G3W is ON, the SEL unit 995 outputs the differential phase value _VEi . When the control signal G3W is OFF, the SEL unit 995 outputs the unit correlation value UEi ₊₁ . That is, when the control signal G3W is ON, the differential phase value calculation unit 990A(i) outputs the differential phase value _VEi . When the control signal G3W is OFF, the differential phase value calculation unit 990A(i) outputs the unit correlation value _UEi .

The synchronization acquisition circuit 9WA operates in the same manner as the synchronization acquisition circuit 9W, and provides the same effect.

Variant No. 14.
The configuration of a 14th modified example of the synchronization acquisition circuit according to embodiment 10 will be described with reference to Fig. 74. Fig. 74 is a functional block diagram showing the configuration of a 14th modified example of the synchronization acquisition circuit according to embodiment 10. The 13th modified example does not have the switch 996. The absence of the switch 996 simplifies the configuration of the synchronization acquisition circuit.

Compared to the synchronization acquisition circuit 9W, the synchronization acquisition circuit 9WB has a modified correlation processing unit 921B and an operation control unit 945WB. The correlation processing unit 921B differs from the correlation processing unit 921 in that it does not have a switch 996. The operation control unit 945WB controls the operation of the differential phase value calculation unit 990 and the frequency deviation calculation unit 925W. The operation control unit 945WB outputs control signals G3W and G4W.

The adder 926 adds the unit accumulated values UWE ₁ to UWE _ME-1 output by the (ME-1) differential phase value calculation units 990(1) to (ME-1) and outputs an accumulated value XE which is the addition result. When the differential phase value calculation unit 990 operates, the accumulated value XE is a differential correlation value WE which is the sum of the differential phase values VE ₁ to VE _ME-1 . When the differential phase value calculation unit 990 does not operate, the accumulated value XE is a correlation value E which is the sum of the unit correlation values UE ₁ to UE _ME-1 . Since UE _ME is not added to the correlation value E, the correlation value E output by the correlation processing unit 921A may not be more accurate than the correlation value output by the correlation processing unit 921.

The operation will be described. At the start of communication, the operation control unit 945WB outputs control signals G3W=ON and G4W=1. When the frequency deviation ΔF becomes small enough to be determined as zero while the differential phase value calculation unit 990 is operating, the operation control unit 945WB outputs control signals G3W=OFF and G4W=0. Whether the frequency deviation ΔF is small enough to be determined as zero is determined by comparing with the second threshold value _TH2 . When the frequency deviation ΔF becomes smaller than the second threshold value _TH2 (ΔF< _TH2 ), the differential phase value calculation unit 990 is not operated and is inactivated.

The operation control section 945W outputs a control signal in the following cases.
(A) If ΔF≧ _TH2 , G4W=1 and G3W=ON are output so that the differential phase value calculation unit 990 operates.
(a) If TH ₂ >ΔF, G4W=0 and G3W=OFF are output so that the differential phase value calculation unit 990 does not operate.

Even when the frequency deviation ΔF is large, the synchronization acquisition circuit 9WB can calculate the frequency deviation with higher accuracy than before and determine the synchronization sequence position of the spreading code.

When ΔF≧ _TH2 , the acquisition circuit 9WB operates in the same manner as the acquisition circuit 9W. When _TH2 >ΔF, the acquisition circuit 9WB operates in substantially the same manner as the acquisition circuit 9WB. The correlation value E used by the acquisition circuit 9WB does not include UE _ME . Therefore, when _TH2 >ΔF, the acquisition circuit 9WB may have a lower accuracy in determining the synchronization sequence position of the spreading code. The acquisition circuit 9WB has a simpler configuration than the acquisition circuit 9W.

Embodiment 11.
The configuration of a synchronization acquisition circuit according to an eleventh embodiment will be described with reference to FIG. 75. FIG. 75 is a functional block diagram showing the configuration of a synchronization acquisition circuit according to an eleventh embodiment. In the eleventh embodiment, the tenth embodiment is modified so that the differential phase value calculation unit is provided in two stages. Regarding FIG. 75, the differences from FIG. 70 for the tenth embodiment will be described. Here, it is assumed that the number of units ME=DH*MH. MH is an integer of 3 or more, and DH is an integer of 2 or more. MH is called the number of two-stage units. MH-1 is called the number of two-stage differences. DH is called the number of two-stage units. 2NE/MH is called the number of two-stage units. 2DH*(MH-1)=2NE-2NE/MH is called the number of two-stage differences.

The synchronization acquisition circuit 9Y has modified correlation processing section 921Y, frequency offset calculation section 925Y, and operation control section 945Y. The correlation processing section 921Y also has MH adders 927, (MH-1) differential phase value calculation sections 99E, and a switch 997. One adder 927 sums up the unit integrated values UWE output by DH differential phase value calculation sections 990. However, adder 927(1) sums up (DH-1) UWEs and the output of switch 996. The DH differential phase value calculation sections 990 summed by one adder 927 have consecutive numbers. In other words, adder 927(1) sums up UWE ₁ to UWE _DH-1 output by differential phase value calculation sections 990(1) to (DH-1) and the output of switch 996. For i greater than 1, an adder 927(i) calculates the sum of UWE _DH*i-DH to UWE DH* _{i-1 output from differential phase value calculation units 990 (DH*i-DH) to (DH*i-1} ). The output of adder 927(i) is called unit correlation value UH _i .

The switch 996 is provided between the output of the unit correlation value calculation unit 231(1) and the adder 927(1). The on/off of the switch 996 is controlled by the control signal G5 output by the operation control unit 945Y. The control signal G5 is turned on when the control signal G3W that controls the operation of the differential phase value calculation unit 990 is off. When the control signal G5 is input as ON, the switch 996 is turned on. When the control signal G3W is on, the control signal G5 is turned off and the switch 996 is turned off. When the switch 996 is on, it outputs the unit correlation value _UE1 . When the switch 996 is off, it outputs zero. By controlling the on/off of the switch 996 in this way, the correlation value E can be calculated including the unit correlation value _UE1 output by the unit correlation value calculation unit 231(1).

The switch 996 is provided between the output of the most recent unit correlation value calculation unit 231(1) and the adder 927(1), or between the output of the most recent unit correlation value calculation unit 231(ME) and the adder 927(MH), and switches between an input complex number or zero and outputs it. When the differential phase value calculation unit 990(i) outputs the previous unit correlation value UE _i , the output of the most recent unit correlation value calculation unit 231(ME) is input to the switch 996. When the differential phase value calculation unit 990(i) outputs the newer unit correlation value UE _i+1 , the output of the most recent unit correlation value calculation unit 231(1) is input to the switch 996.

The switch 997 is provided between the adder 927(1) and the adder 926. The on/off of the switch 997 is controlled by a control signal G11 output by the operation control unit 945Y. The control signal G11 is turned on when the control signal G10Y that controls the operation of the differential phase value calculation unit 99E is turned off. When the control signal G11 is input, the switch 997 is turned on. When the control signal G10Y is on, the control signal G11 is turned off and the switch 997 is turned off. When the switch 997 is on, it outputs the unit correlation value UH _i . When the switch 997 is off, it outputs zero. By controlling the on/off of the switch 997 in this way, the correlation value E can be calculated including the unit correlation value UH ₁ output by the adder 927(1).

The switch 997 is a second switch that is provided between the output of the most recent adder 927(1) and the adder 926, or between the output of the most recent adder 927(MH) and the adder 926, and switches between an input complex number or zero and outputs it. When the differential phase value calculation unit 99E(i) outputs the earlier unit correlation value UH _i , the output of the most recent adder 927(MH) is input to the switch 997. When the differential phase value calculation unit 99E(i) outputs the newer unit correlation value UH _i+1 , the output of the most recent adder 927(1) is input to the switch 997.

The differential phase value calculation unit 99E(i) receives the unit correlation values UH _i+1 and UH _i, which are complex numbers, and calculates a differential phase value VH _i having a phase difference between UH _i+1 and UH _i and a unit amount of amplitude. When the differential phase value calculation unit 990 operates, the differential phase value calculation unit 99E(i) does not calculate the differential phase value VH _i . The differential phase value calculation unit 99E(i) is controlled by the operation control unit 945Y and outputs a unit accumulated value UWH _i , which is either the differential phase value VH _i or the unit correlation value UH _i+1 . The differential phase value calculation unit 99E(i) calculates the differential phase value VH _i, which is a complex number having a phase difference between the unit correlation value UH _i+1 and the previous unit correlation value UH _i . The differential phase value calculation unit 99E(i) may uniformly switch between the unit correlation value UH _i and the differential phase value VH _i and output the same. The differential phase value calculation unit 990 is called a first-stage differential phase value calculation unit, and the differential phase value calculation unit 99E is called a second-stage differential phase value calculation unit.

The configuration of the second-stage differential phase value calculation unit will be described with reference to FIG. 76. FIG. 76 is a diagram showing the configuration of the second-stage differential phase value calculation unit of the synchronization acquisition circuit according to the sixth embodiment. The differential phase value calculation unit 99E(i) has a configuration similar to that of the differential phase value calculation unit 990(i). The differential phase value calculation unit 99E(i) differs in that the SEL unit 965 is controlled by a control signal G10Y and in the variables representing the signals. The SEL unit 965 of the differential phase value calculation unit 990(i) is controlled by a control signal G3W. The differential phase value calculation unit 990 and the differential phase value calculation unit 99E are controlled so that neither operates or only one of them operates.

The signal processed by the differential phase value calculation unit 99E(i) is expressed by a variable different from that of the differential phase value calculation unit 990(i). The unit correlation values UH _i and UH _i+1 are input to the differential phase value calculation unit 99E(i). The differential phase value calculation unit 99E(i) calculates the differential phase value VH _i . The differential phase value calculation unit 99E(i) outputs the unit accumulated value UWH _i , which is the differential phase value VH _i or the unit correlation value UH _i+1 .

The adder 926 adds the unit accumulated values UWH ₁ to UWH _MH-1 output by the (MH-1) differential phase value calculation units 99E(1) to (MH-1) and the output of the switch 997, and outputs an accumulated value XE which is the addition result. When the differential phase value calculation unit 990 operates, the accumulated value XE is a differential correlation value WE which is the sum of the differential phase values VE ₁ to VE _ME-1 . When the differential phase value calculation unit 99E operates, the accumulated value XE is a differential correlation value WH which is the sum of the differential phase values VH ₁ to VH _MH-1 . When the differential phase value calculation unit 990 and the differential phase value calculation unit 99E do not operate, the accumulated value XE is a correlation value E which is the sum of the unit correlation values UE ₁ to UE _ME .

The unit correlation value UH _i is a second-stage unit correlation value that is a complex number representing the sum of consecutive despread received signals GR of the number of second-stage units. The adders 927(1) to (MH) are second-stage unit correlation value calculation units of the number (MH) of second-stage units ordered by the despread received signals used in the calculation to calculate the second-stage unit correlation value.

The differential phase value VH _i is a two-stage differential phase value that is a complex number having a phase difference between the second-stage unit correlation value UH _i+1 and the previous two-stage unit correlation value UH _i . The differential phase value calculation unit 99E(i) is a two-stage differential phase value calculation unit that calculates the two-stage differential phase value.

The differential correlation value WH is a two-stage differential correlation value which is the sum of the two-stage differential phase values VH ₁ to VH _MH-1 . The sum of the two-stage differential phase values VH ₁ to VH _MH-1 is the sum of despread received signals that is equal to or greater than the two-stage difference number and equal to or less than the despread number. When the differential phase value calculation unit 99E is operating, the adder 926 is a two-stage differential correlation value calculation unit that calculates the two-stage differential correlation value.

The operation control unit 945Y outputs control signals G3W, G4Y, G5, G10Y, and G11. G3W, which controls the differential phase value calculation unit 990, takes the value ON/OFF as in the case of the tenth embodiment. G4Y, which controls the operation of the frequency deviation calculation unit 925Y, takes the following value, for example. The operation control unit 945Y controls whether to operate either the differential phase value calculation unit 990 or the differential phase value calculation unit 99E, or to operate neither of them.
(Meaning of the value of control signal G4Y)
0: The differential phase value calculation unit 990 and the differential phase value calculation unit 99E are inactive.
1: The differential phase value calculation unit 990 operates.
4: The differential phase value calculation unit 99E operates.

The frequency deviation calculation unit 925Y operates similarly to the frequency deviation calculation unit 925W when G4Y = 0 or G4Y = 1. When G4Y = 4, the frequency deviation calculation unit 925Y calculates ΔF as follows: ΔF = WA _AV / (π*DE*DH*SE).

The operation will be described. At the start of communication, the operation control unit 945Y outputs control signals G4Y=2, G5=G11=ON, and G3W=G10Y=OFF. When the synchronization acquisition circuit 9Y operates and the frequency deviation ΔF can be calculated, the operation control unit 945Y changes the values of G3W, G4Y, G5, G10Y, and G11 according to the magnitude of ΔF. The operation control unit 945Y uses a first threshold _TH1 and a second threshold _TH2 . Each threshold is determined so that the relationship _TH2 < _TH1 is established. The period when G3W=ON is defined as the period of precise detection 1. The period when G10Y=ON is defined as the period of precise detection 2.

In the synchronization acquisition circuit 9Y, when the differential phase value calculation unit 990 operates, the accumulated value XE is the differential correlation value WE. When the differential phase value calculation unit 99E operates, the accumulated value XE is the differential correlation value WH, which is a two-stage differential correlation value. When the differential phase value calculation unit 990 and the differential phase value calculation unit 99E do not operate, the accumulated value XE is the correlation value E.

The operation control unit 945Y outputs a control signal in the following cases.
(A) If ΔF≧ _TH1 (precise detection 1), G4Y=1, G3W=G11=ON, and G5=G10Y=OFF are output so that the differential phase value calculation unit 990 operates.
(a) If _TH1 > _{.DELTA.F.gtoreq.TH2} (precise detection 2), G4Y=4, G3W=G11=OFF, and G5=G10Y=ON are output so that the differential phase value calculation unit 99E operates.
(c) If TH ₂ > ΔF, G4Y=0, G3W=G10Y=OFF, and G5=G11=ON are output so that none of the controls operates.

The acquisition circuit 9Y operates in the same manner as the acquisition circuit 9W during the period of precise detection 1. When the frequency deviation ΔF becomes smaller than the first threshold value _TH1 , the period of precise detection 2 begins and the second-stage differential phase value calculator 99E operates.

The first differential phase value calculation unit 96C divides one period of the received signal of the spreading code into MH parts, which is an integer equal to or greater than 3, and calculates the frequency deviation by obtaining the phase change between the complex numbers of the sum of the despread received signal _GRm in the divided periods. Therefore, the synchronization sequence position of the spreading code can be obtained with higher accuracy than the conventional method shown in Patent Document 1, which divides one period of the received signal into two. The accuracy of obtaining the frequency deviation is also high.

There are ME=DE*MH differential phase value calculation units 990, where DE is an integer equal to or greater than 2. There are more differential phase value calculation units 990 than differential phase value calculation unit 99E, and they divide the received signal for one period of the spreading code more finely, so that even when a larger frequency change ΔF occurs, the frequency deviation can be calculated with higher accuracy than with conventional methods to find the synchronization sequence position of the spreading code.

Even when the frequency deviation ΔF is large, the synchronization acquisition circuit 9Y can calculate the frequency deviation with higher accuracy than before and determine the synchronization sequence position of the spread code. When the frequency deviation ΔF becomes smaller, the synchronization acquisition circuit 9Y can change the level at which the phase change is detected more finely than the synchronization acquisition circuit 9W, and can determine the synchronization sequence position of the spread code with higher accuracy. The accuracy of determining the frequency deviation is also high.

It is possible to freely combine the various embodiments, modify the various embodiments, omit some of the components, or freely combine the various embodiments with some of the components omitted or modified.

1 Spread spectrum receiver 2 Analog receiving section 3 ADC section (Analog Digital Converter)
4 Quadrature detection section 5 Timing corrector 6 AGC (Auto Gain Control)
7 Despreading section 8 Synchronization tracking circuit 9, 9A, 9B, 9C, 9D, 9E, 9F, 9G, 9H, 9J, 9K, 9L, 9M, 9N, 9P, 9Q, 9R, 9S, 9T, 9U, 9V, 9W, 9WA, 9WB, 9Y Synchronization acquisition circuit

21 BPF (Band Pass Filter)
22 Amplification section (AMP)
23 Low-pass filter (LPF)
41 First multiplier 42 Second multiplier 43 First low-pass filter (first LPF)
44 Second low pass filter (second LPF)
45 cos/-sin converter 46 Numerical Controlled Oscillator (NCO)
49 adder,
51, 52 FIR filter (Finite Impulse Response filter)
53 Filter coefficient update 54 Numerically controlled oscillator (NCO)
61a, 61b Multipliers 63a, 63b Squaring circuit 64 Adder 65 10 log ₁₀ converter 66 Subtractor 67 Multiplier 68 LF (Loop Filter)
69 10 ^x/20 converter 71, 72, 73, 74, 75, 76 Multiplier 77, 78 1 sample delay element (DFF)
79 Spreading code generating unit 81, 82, 83, 84 Squaring circuit 85, 86 Adder
87 Subtractor
88a, 88b Multiplier
89 LF (Loop Filter)

121, 121A, 121B Delay processing units 122, 122A, 122B, 122L Second correlation value calculation units 221, 221C, 221D Unit first correlation value calculation unit 223 Write control unit 224 Memory unit 225 Read control unit

231 Unit correlation value calculation unit

901, 901A, 901B, 901L CB correlation processing unit 902 Delay element (DFF)
903 chip correlator (second despreading received signal calculation unit, despreading received signal calculation unit)
904, 904L Adder 905 Unit second differential phase value calculation unit 906 Switch (second switch)
907 Adder (second adder)

910, 910A, 910B, 910C, 910D, 910E, 910F, 910G, 910H, 910K, 910Q, 910R, 910S, 910T, 910U, 910V CA correlation processing unit 911, 911B Delay circuit 912 Chip correlator (second accumulated value calculation unit after despreading, received signal calculation unit after despreading)
913 Adder 914 Adder (first adder, first correlation value accumulator, difference correlation value calculator, first total value calculator, two-stage difference correlation value calculator)
914F Adder (first adder, first sum calculation unit)
915 Adder 916 Switch 917 Adder

921, 921A, 921B Correlation processing unit 922 Delay element (DFF)
923 chip correlator 924 adder 926 adder (differential correlation value calculation unit, correlation value accumulation unit)
927 Adder

920 Power calculation unit 925, 925F, 925J, 925K, 925N, 925P, 925Q, 925R, 925S, 925T, 925U, 925V, 925W, 925Y Frequency deviation calculation unit 930, 930B Averaging processing unit (power storage unit)
940, 940B Peak detection and determination units 945, 945F, 945G, 945H, 945J, 945K, 945L, 945M, 945N, 945P, 945Q, 945R, 945S, 945T, 945U, 945V, 945W, 945Y Operation control unit

950, 950E, 950P, 950Q, 950R Second differential phase value calculation unit 951 Amplitude phase conversion units 952, 952 ₂ , 952 ₃ Delay circuit 953 Subtractor 954 Amplitude phase inverse conversion unit 955 SEL unit (selection circuit)
956 Complex conjugate unit 957 Complex multiplier 960, 960E, 960H First differential phase value calculation unit (first selection output unit)
96C: First differential phase value calculation unit 961: Amplitude/phase conversion unit 962: Amplitude/phase conversion unit 963: Subtractor 964: Amplitude/phase inverse conversion unit 965: SEL unit (selection circuit)
966 Complex conjugate unit 967 Complex multipliers 970, 970Q, 970R Sign selection units 971, ₉₇₁₂ , ₉₇₁₃ Subtraction units 972, ₉₇₂₂ , ₉₇₂₃ Delay elements (DFF)
973 SEL section (selection circuit)

980 Accumulation addition unit 981 SEL unit 982 Accumulation addition circuit 983 SEL unit 984 Control circuit 98A Data acquisition unit 98B Adder 98C Delay element (DFF)
98D Hold section

990, 99E Differential phase value calculation unit 991 Amplitude phase conversion unit 992 Amplitude phase conversion unit 993 Subtractor 994 Amplitude phase inverse conversion unit 995 SEL unit (selection circuit)
996 Switch (first switch)
997 Switch (second switch)

1001 Spreading code A generator 1002 Spreading code B generator 1003 Multiplier

G1, G1Q, G1R Control signal (for controlling the second differential phase value calculation unit)
G2, G2Q, G2R Control signal (for controlling the code selection section)
G3 Control signal (for controlling the first differential phase value calculation unit)
G3W Control signal (for controlling the differential phase value calculation section)
G4, G4F, G4J, G4L, G4M, G4N, G4Q, G4R, G4S, G4T, G4U, G4V, G4W, G4Y Control signal (for controlling the frequency deviation calculation section)
G5 Control signal (for controlling switch 996)
G6 Control signal (for controlling the switch between the first correlation value and the first differential correlation value)
G7 Control signal (for controlling the unit second differential phase value calculation unit)
G8 Control signal (for controlling the on/off of switch 906)
G9 Control signal (for controlling the cumulative addition section)
G10 Control signal Control signal (for controlling the first differential phase value calculation unit in the second stage)
G10Y Control signal Control signal (for controlling the second stage differential phase value calculation unit)
G11 Control signal (for controlling switch 997)

A first correlation value,
B Second correlation value

CA first spreading code,
CB the second spreading code;
CD is a differential code determined from the first spreading code,
CX: the spreading code (CA or CD) output by the code selection unit 970;

DA: Number of first units DB: Number of second units DC: Number of second-stage units MA: Number of first divisions (number of units)
MB Second division number MC Second stage first division number (number of second stage units)
NA: First sequence length NB: Second sequence length NC: Third sequence length (cascade connection sequence length, sequence length)

SA First chip time SB Second chip time (chip time)

TA: Time for one period of the first spreading code CA; TB: Time for one period of the second spreading code CB; TP: Time for one period of the cascade-connected spreading code PN

UA unit first correlation value UB unit second correlation value

VA First differential phase value VB Second differential phase value VC Differential phase value

UWA unit first accumulated value (unit first correlation value UA or first differential phase value VA)

EA: unit first correlation value FA: first differential phase value HA: unit first integrated value (unit first correlation value EA or first differential phase value FA)
WH first differential correlation value (second-stage differential correlation value, second-stage first differential correlation value)

WA First differential correlation value (differential correlation value)
WB second difference correlation value (difference correlation value)

VUB unit second differential phase value WUB unit second differential correlation value XUB unit second integrated value (second correlation value B or unit second differential correlation value WUB)

XA: first integrated value (first correlation value A, first differential correlation value WA, second differential correlation value WB, or differential phase value VC)
XB: second integrated value (second correlation value B or second differential phase value VB)

SE Tip Time

E Correlation value CE Spreading code NE Sequence length DE Number of units DH Number of second-stage units ME Number of units MH Number of second-stage units UE Unit correlation value VE Differential phase value WE Differential correlation value UWE Unit integrated value (unit correlation value UE or differential phase value VE)
XE: integrated value UH; unit correlation value VH; differential phase value UWH: unit integrated value (unit correlation value UH or differential phase value VH)

Claims (72)

A synchronization acquisition circuit for receiving a signal spread with a spreading code which has a sequence length which is a product of a number of units which is an integer of 3 or more and an integer of 2 or more and is a pseudorandom number which takes a binary value which changes with a chip time, the synchronization acquisition circuit determining a synchronization sequence position which is a position in the sequence length of the spreading code to be multiplied by a received signal of the number of the sequence length at discrete time points having an interval of the chip time, comprising:
a despread received signal calculation unit that calculates, for the received signal expressed as a complex number by an in-phase component and an orthogonal component having a phase difference of 90 degrees from the in-phase component, and in which the number of excess coefficients is included in one chip, a total number of time points obtained by multiplying the sequence length by the excess coefficient included in consecutive chips of the number of sequence lengths, or a number of the received signals of the number of sequence lengths selected to have an interval of the chip time, by each of the spreading codes determined according to the position in the sequence length of the chip to which each of the received signals belongs; and
a unit correlation value calculation unit for calculating a unit correlation value which is the sum of the consecutive despread received signals of the number of units obtained by dividing the number of despread signals by the number of units;
a correlation value accumulator that calculates a correlation value that is the sum of the despread received signals, the number of which is equal to or greater than a difference obtained by subtracting the number of units from the number of despread signals and is equal to or less than the number of despread signals;
a differential phase value calculation unit that calculates a differential phase value, which is a complex number having a phase difference between the unit correlation value and the immediately previous unit correlation value;
an operation control unit that controls whether or not the differential phase value calculation unit is operated;
a differential correlation value calculation unit that calculates a differential correlation value that is the sum of the differential phase values;
a power calculation unit that calculates power of the integrated value which is the correlation value or the differential correlation value, the integrated value being the differential correlation value when the differential phase value calculation unit operates, and being the correlation value when the differential phase value calculation unit does not operate;
a power storage unit that stores the power calculated by shifting the received signal by one time point for a total number of time points;
a peak detection and determination unit that determines the synchronization sequence position based on the position at which the power stored in the power storage unit takes a maximum value. The synchronization acquisition circuit according to claim 1, comprising a unit correlation value calculation unit for the number of units ordered by the despread received signal used for calculation. The synchronization acquisition circuit according to claim 1 or 2, in which the number of units can take two or more different values. The synchronization acquisition circuit according to any one of claims 1 to 3, wherein the differential phase value calculation unit calculates the differential phase value having a determined amplitude. The synchronization acquisition circuit according to any one of claims 1 to 3, wherein the differential phase value calculation unit calculates the differential phase value by multiplying the complex conjugate of one of two input complex numbers by the other complex number. The operation control unit is
When the frequency deviation is equal to or greater than a first threshold value, the differential phase value calculation unit is operated;
6. The synchronization acquisition circuit according to claim 1, wherein the differential phase value calculation unit is not operated when the frequency deviation is smaller than the first threshold value. When the differential phase value calculation unit is in operation, the frequency deviation is calculated based on the phase of the differential correlation value;
7. The synchronization acquisition circuit according to claim 6, further comprising a frequency deviation calculation unit that calculates the frequency deviation based on a time rate of change of the phase of the correlation value in a determined period when the differential phase value calculation unit does not operate. a second-stage unit correlation value calculation unit for calculating a second-stage unit correlation value which is a sum of consecutive despread received signals of a number of second-stage units, the number of second-stage units being an integer obtained by dividing the number of despread pieces by a number of second-stage units, the number of second-stage units being a positive integer smaller than the number of units;
a two-stage differential phase value calculation unit that calculates a two-stage differential phase value that is a complex number having a phase difference between the second-stage unit correlation value and the immediately previous second-stage unit correlation value;
a two-stage difference correlation value calculation unit that calculates a two-stage difference correlation value that is a sum of the two-stage difference phase values,
the correlation value accumulator calculates the correlation value, which is a complex number representing a sum of the despread received signals, the number of which is equal to or greater than a second-stage difference number obtained by subtracting the number of second-stage units from the number of despreads, and is equal to or less than the number of despreads;
the operation control unit controls whether to operate either the differential phase value calculation unit or the two-stage differential phase value calculation unit, or whether to operate neither of them;
the integrated value when the two-stage difference phase value calculation unit is operating is the two-stage difference correlation value,
6. The synchronization acquisition circuit according to claim 1, wherein the power calculation section calculates the power of the integrated value which is any one of the correlation value, the differential correlation value, and the two-stage differential correlation value. The synchronization acquisition circuit according to claim 8, wherein the two-stage differential phase value calculation unit calculates the two-stage differential phase value having a determined amplitude. The synchronization acquisition circuit according to claim 8, wherein the two-stage differential phase value calculation unit calculates the two-stage differential phase value by multiplying the complex conjugate of one of the two input complex numbers by the other complex number. The operation control unit is
When the frequency deviation is equal to or greater than a first threshold value, the differential phase value calculation unit is operated;
When the frequency deviation is smaller than a second threshold value that is determined to be smaller than the first threshold value, the differential phase value calculation unit and the second-stage differential phase value calculation unit are not operated,
11. The synchronization acquisition circuit according to claim 8, further comprising: a second threshold value calculating unit that operates when the frequency deviation is smaller than the first threshold value and is equal to or larger than the second threshold value. When the differential phase value calculation unit or the two-stage differential phase value calculation unit is operating, the frequency deviation is calculated based on the phase of the differential correlation value;
and a frequency deviation calculation unit that calculates the frequency deviation based on a time rate of change of the phase of the correlation value in a determined period when the differential phase value calculation unit and the two-stage differential phase value calculation unit are not operating. the spreading code is a cascade-concatenated spreading code which is a pseudo-random number taking a binary value that changes with a first chip time and has a sequence length which is a product of the number of units and a first number of units which is an integer equal to or greater than 2, and which is obtained by multiplying a first spreading code which is a pseudo-random number taking a binary value that changes with a first chip time and has a sequence length which is a product of the number of units and a first number of units which is an integer equal to or greater than 2, by a second spreading code which is a pseudo-random number taking a binary value that changes with a chip time obtained by dividing the first chip time by the second sequence length;
a second number of despread received signals calculation unit for the second number of time points or the second sequence length, which calculates second despread received signals that are complex numbers obtained by multiplying the second number of time points obtained by multiplying the second sequence length by the excess coefficient included in consecutive chips of the second sequence length, or each of the received signals of the number of the second sequence length selected to have an interval of the chip time, by each of the second spreading codes determined in accordance with the position in the second sequence length of the chip to which each of the received signals belongs;
a second correlation value accumulator configured to calculate a second correlation value which is a sum of the second despread reception signals of the second despread number ;
a second accumulated value storage unit configured to store a second accumulated value, which is the second correlation value calculated by shifting the received signal by one time point, for a stored number of second correlation values, the stored number being equal to or greater than an integer obtained by multiplying the second number of time points by a minimum number of devices, the minimum number being an integer obtained by subtracting 1 from the first sequence length ;
a post-despreading second accumulated value calculation unit for the number of first sequence lengths, which receives as input each of the second accumulated values for the number of first sequence lengths calculated at each of the first chip times and each of the first spreading codes, and calculates a post-despreading second accumulated value, which is a complex number obtained by multiplying each of the second accumulated values by each of the first spreading codes;
3. The synchronization acquisition circuit according to claim 1, wherein said unit correlation value calculation section calculates said unit correlation value which is a sum of said first unit number of successive second accumulated values after despreading. The integrated value calculating unit further includes an accumulating unit that accumulates the integrated value a predetermined number of times for each integrated value calculated by shifting the received signal by one time point,
the operation control unit controls whether or not the cumulative addition unit is operated;
14. The synchronization acquisition circuit according to claim 1, wherein the power calculation unit calculates the power of the integrated value output by the cumulative addition unit when the cumulative addition unit operates, and calculates the power of the integrated value when the cumulative addition unit does not operate. a first spreading code which has a first sequence length which is a product of a first division number which is an integer equal to or greater than 3 and a first unit number which is an integer equal to or greater than 2 and which is a pseudorandom number taking a binary value which changes with a first chip time, and a second spreading code which has a second sequence length which is a pseudorandom number taking a binary value which changes with a chip time obtained by dividing the first chip time by the second sequence length, the first spreading code being a pseudorandom number taking a binary value which changes with the chip time, the second spreading code being a pseudorandom number taking a binary value which changes with the chip time, the first spreading code being a product of a first sequence length and a second sequence length, the second spreading code being a pseudorandom number taking a binary value which changes with the chip time, the second spreading code being a pseudorandom number taking a binary value which changes with the chip time,
a second despreading received signal calculation unit for a second number of times that is the second sequence length, which calculates a second despreading received signal that is a complex number obtained by multiplying the second sequence length by the second number of time points obtained by multiplying the second sequence length by the excess coefficient, or a second despreading received signal that is a complex number obtained by multiplying each of the received signals of the number of the second sequence length selected to have an interval of the chip time, by each of the second spreading codes determined in accordance with the position of a chip to which each of the received signals belongs in the second sequence length; and
a second correlation value accumulator configured to calculate a second correlation value which is a sum of the second despread reception signals of the second despread number ;
a second accumulated value storage unit configured to store a second accumulated value, which is the second correlation value calculated by shifting the received signal by one time point, the second accumulated value being a stored number equal to or greater than a number obtained by multiplying the second number of time points by a minimum number of devices, which is an integer obtained by subtracting 1 from the first sequence length;
a second accumulated value calculation unit after despreading for the number of first sequence lengths, which receives as input each of the second accumulated values for the number of first sequence lengths calculated at each of the first chip times and each of the first spreading codes, and calculates a second accumulated value after despreading, which is a complex number obtained by multiplying each of the second accumulated values by each of the first spreading codes;
a first correlation value accumulating unit that calculates a first correlation value which is a sum of the second accumulated values after despreading, the number of which is equal to or larger than a first difference number, which is an integer obtained by subtracting the first unit number from the first sequence length, and is equal to or smaller than the first sequence length;
a unit first correlation value calculation unit, the unit first correlation value being a sum of the first unit number of consecutive despread second accumulated values, the unit first correlation value calculation unit being the first division number ordered by the despread second accumulated values used in the calculation;
a first differential phase value calculation unit for calculating a first differential phase value which is a complex number having a phase difference between the unit first correlation value and the previous unit first correlation value, the first differential number being an integer obtained by subtracting 1 from the first division number;
a first difference correlation value calculation unit that calculates a first difference correlation value that is a sum of the first difference phase values in the first difference number ;
an operation control unit that controls whether to operate the first differential phase value calculation unit;
a power calculation unit that calculates power of the first accumulated value, which is the first correlation value or the first differential correlation value, and which is the first differential correlation value when the first differential phase value calculation unit operates and is the first correlation value when the first differential phase value calculation unit does not operate;
a power storage unit configured to store the power in a number corresponding to a total number of time points, the total number of time points being a product of the second time point number and the first sequence length, the power being calculated by shifting the received signal by one time point at a time;
a peak detection and determination unit that determines the synchronization sequence position based on the position at which the power stored in the power storage unit takes a maximum value. The synchronization acquisition circuit according to claim 15, wherein the first differential phase value calculation unit calculates the first differential phase value having a determined amplitude. The synchronization acquisition circuit according to claim 15, wherein the first differential phase value calculation unit calculates the first differential phase value by multiplying the complex conjugate of one of two input complex numbers by the other complex number. The operation control unit is
When the frequency deviation is equal to or greater than a first threshold value, the first differential phase value calculation unit is operated;
16. The synchronization acquisition circuit according to claim 15, wherein the first differential phase value calculation unit is not operated when the frequency deviation is smaller than the first threshold value. When the first differential phase value calculation unit is operating, the frequency deviation is calculated based on the phase of the first differential correlation value;
and a frequency deviation calculation unit that calculates the frequency deviation based on a time rate of change of the phase of the first correlation value in a determined period when the first differential phase value calculation unit does not operate. a two-stage unit first correlation value calculation unit for calculating a two-stage unit first correlation value which is a sum of two-stage first unit number of consecutive despread received signals, the two-stage first division number being an integer obtained by dividing the first sequence length by a two-stage first division number which is a positive integer smaller than the first division number, the two-stage first division number being an integer, the two-stage first division number being an integer, the two-stage first division number being an integer smaller than the first division number;
a second-stage first differential phase value calculation unit for calculating a second-stage first differential phase value which is a complex number having a phase difference between the second-stage first correlation value and the immediately preceding second-stage first correlation value, the second-stage first differential number being an integer obtained by subtracting 1 from the second-stage first division number;
a second-stage first difference correlation value calculation unit that calculates a second-stage first difference correlation value that is a sum of the second-stage first difference phase values of the number of second-stage first differences ,
the operation control unit controls to operate either one of the first differential phase value calculation unit and the second stage first differential phase value calculation unit, or to operate neither of them;
the first integrated value when the second-stage first differential phase value calculation unit operates is the second-stage first differential correlation value,
18. The synchronization acquisition circuit according to claim 15, wherein the power calculation section calculates the power of the first integrated value, which is any one of the first correlation value, the first differential correlation value, and the second-stage first differential correlation value. The synchronization acquisition circuit according to claim 20, wherein the second-stage first differential phase value calculation unit calculates the second-stage first differential phase value having a determined amplitude. The synchronization acquisition circuit according to claim 20, wherein the second-stage first differential phase value calculation unit calculates the second-stage first differential phase value by multiplying the complex conjugate of one of two input complex numbers by the other complex number. The operation control unit is
When the frequency deviation is equal to or greater than a first threshold value, the first differential phase value calculation unit is operated;
when the frequency deviation is smaller than a second threshold value that is determined to be smaller than the first threshold value, the first differential phase value calculation unit and the second stage first differential phase value calculation unit are not operated,
23. The synchronization acquisition circuit according to claim 20, wherein the second stage first differential phase value calculation unit is operated when the frequency deviation is smaller than the first threshold value and is equal to or larger than the second threshold value. When the first differential phase value calculation unit is operating, the frequency deviation is calculated based on the phase of the first differential correlation value;
When the second-stage first differential phase value calculation unit operates, the frequency deviation is calculated based on the phase of the second-stage first differential correlation value;
and a frequency deviation calculation unit that calculates the frequency deviation based on a time rate of change of the phase of the first correlation value in a determined period when the first differential phase value calculation unit and the second stage first differential phase value calculation unit are not operating. The method further includes an accumulating unit that accumulates the first accumulated value a predetermined number of times for each of the first accumulated values calculated by shifting the reception signal by one time point,
the operation control unit controls whether or not the cumulative addition unit is operated;
25. The synchronization acquisition circuit according to claim 15, wherein the power calculation unit calculates the power of the first accumulated value output by the cumulative addition unit when the cumulative addition unit is operating, and calculates the power of the first accumulated value when the cumulative addition unit is not operating. the spreading code is a cascade-concatenated spreading code which is a pseudo-random number taking a binary value that changes with a first chip time and has a first sequence length equal to the number of units, and which is obtained by multiplying a second spreading code which has a second sequence length and is a pseudo-random number taking a binary value that changes with a chip time obtained by dividing the first chip time by the second sequence length, the pseudo-random number having the sequence length being a product of the first sequence length and the second sequence length,
a second number of despread received signals calculation unit for the second number of time points or the second sequence length, which calculates second despread received signals that are complex numbers obtained by multiplying the second number of time points obtained by multiplying the second sequence length by the excess coefficient included in consecutive chips of the second sequence length, or each of the received signals of the number of the second sequence length selected to have an interval of the chip time, by each of the second spreading codes determined in accordance with the position in the second sequence length of the chip to which each of the received signals belongs;
a second correlation value accumulator configured to calculate a second correlation value which is a sum of the second despread reception signals of the second despread number;
a second differential phase value calculation unit, the operation of which is controlled by the operation control unit, which calculates a second differential phase value, which is a complex number having a phase difference between the second correlation value and the second correlation value calculated using the received signal at a point in time that is a first delay time that is a time obtained by multiplying the first chip time by a number of delay chips, the number being an integer equal to or greater than 1, prior to the received signal used when calculating the second correlation value;
a second accumulated value storage unit configured to store second accumulated values, the second correlation value or the second differential phase value, calculated by shifting the received signal by one time point, the second accumulated value being a stored number that is equal to or greater than an integer obtained by multiplying the second number of time points by a minimum number of devices, the minimum number being an integer obtained by subtracting 1 from the first sequence length;
a post-despreading second accumulated value calculation unit for the number of first sequence lengths, which receives input of the second accumulated values for the number of first sequence lengths calculated at the time points of the first chip time, and when the second differential phase value calculation unit operates, receives input of each first differential code, which is a spreading code having the first sequence length determined from the first spreading code, and which is a spreading code taking two values: a unchanged value indicating that each of the first spreading codes has the same value as the first spreading code preceding the number of delay chips, and a changed value indicating that the first spreading code has a different value from the first spreading code preceding the number of delay chips, and when the second differential phase value calculation unit does not operate, receives input of each of the first spreading codes, and calculates a post-despreading second accumulated value which is a complex number obtained by multiplying each of the second accumulated values by the first differential code or each of the first spreading codes;
a first sum calculation unit that calculates a first sum which is a sum of the second accumulated values after despreading for the number of the first sequence lengths ;
the second despreading received signal calculation unit and the second despreading accumulated value calculation unit constitute the despreading received signal calculation unit;
the second correlation value accumulating unit constitutes the unit correlation value calculating unit;
the second differential phase value calculation unit constitutes the differential phase value calculation unit,
the first sum value calculation unit is the differential correlation value calculation unit when the second differential phase value calculation unit operates , and the first sum value calculation unit is the correlation value accumulation unit when the second differential phase value calculation unit does not operate,
The acquisition circuit according to claim 1 , wherein the power calculation section calculates the power of the first sum value. A synchronization acquisition circuit for receiving a signal spread with a cascade-concatenated spreading code, the cascade-concatenated spreading code having a sequence length that is a product of a first sequence length and a second sequence length, the cascade-concatenated spreading code being a pseudo-random number taking a binary value that changes with a first chip time, the pseudo-random number having a first sequence length and being obtained by multiplying a first spreading code, the first spreading code being a pseudo-random number taking a binary value that changes with a chip time obtained by dividing the first chip time by the second sequence length, the cascade-concatenated spreading code being a pseudo-random number taking a binary value that changes with the chip time ... pseudo-random number being a product of the first sequence length and the second sequence length, the pseudo-random number being a pseudo-random number taking a binary value that changes with the chip time, the synchronization acquisition circuit for determining a synchronization sequence position, the position in the sequence length, of the cascade-concatenated spreading code to be multiplied by a received signal having the number of the sequence length at discrete time points having an interval of the chip time,
a second despreading received signal calculation unit for a second number of times that is the second sequence length, which calculates a second despreading received signal that is a complex number obtained by multiplying the second sequence length by the second number of time points obtained by multiplying the second sequence length by the excess coefficient, or a second despreading received signal that is a complex number obtained by multiplying each of the received signals of the number of the second sequence length selected to have an interval of the chip time, by each of the second spreading codes determined in accordance with the position of a chip to which each of the received signals belongs in the second sequence length; and
a second correlation value accumulator configured to calculate a second correlation value which is a sum of the second despread reception signals of the second despread number ;
a second differential phase value calculation unit that calculates a second differential phase value, which is a complex number having a phase difference between the second correlation value and the second correlation value calculated using the received signal at a point in time a first delay time, which is a time obtained by multiplying the first chip time by a delay chip number, which is an integer equal to or greater than 1, prior to the received signal used when calculating the second correlation value;
an operation control unit that controls whether to operate the second differential phase value calculation unit;
a second accumulated value storage unit configured to store second accumulated values, the second correlation value or the second differential phase value, calculated by shifting the received signal by one time point, the second accumulated value being a stored number equal to or greater than a number obtained by multiplying the second number of time points by a minimum number of devices, the minimum number being an integer obtained by subtracting 1 from the first sequence length;
a post-despreading second accumulated value calculation unit for the number of first sequence lengths, which receives input of the second accumulated values for the number of first sequence lengths calculated at the time points of the first chip time, and when the second differential phase value calculation unit operates, receives input of each first differential code, which is a spreading code having the first sequence length determined from the first spreading code, and which is a spreading code taking two values: a unchanged value indicating that each of the first spreading codes has the same value as the first spreading code preceding the number of delay chips, and a changed value indicating that the first spreading code has a different value from the first spreading code preceding the number of delay chips, and when the second differential phase value calculation unit does not operate, receives input of each of the first spreading codes, and calculates a post-despreading second accumulated value which is a complex number obtained by multiplying each of the second accumulated values by the first differential code or each of the first spreading codes;
a first sum calculation unit that calculates a first sum which is a sum of the second accumulated values after despreading for the number of the first sequence lengths ;
a power calculation unit that calculates the first total power;
a power storage unit configured to store the power in a number corresponding to a total number of time points, the total number of time points being a product of the second time point number and the first sequence length, the power being calculated by shifting the received signal by one time point at a time;
a peak detection and determination unit that determines the synchronization sequence position based on the position at which the power stored in the power storage unit takes a maximum value. 28. The synchronization acquisition circuit according to claim 26, wherein the second differential phase value calculation section calculates the second differential phase value having a determined amplitude. 27. The synchronization acquisition circuit according to claim 26 , wherein the second differential phase value calculation unit calculates the second differential phase value by multiplying a complex conjugate of one of two input complex numbers by the other complex number. The operation control unit is
When the frequency deviation is equal to or greater than a first threshold value, the second differential phase value calculation unit is operated;
30. The synchronization acquisition circuit according to claim 26, wherein when the frequency deviation is smaller than the first threshold value, the second differential phase value calculation unit is not operated. The synchronization acquisition circuit according to any one of claims 26 to 29, wherein the number of delay chips can take two or more different values. The synchronization acquisition circuit of claim 31, wherein the number of delay chips is a first number of delay chips and a second number of delay chips that is greater than the first number of delay chips. The operation control unit is
When the frequency deviation is equal to or greater than a fourth threshold, the second differential phase value calculation unit is operated with the first number of delay chips;
When the frequency deviation is smaller than a first threshold value that is determined to be smaller than the fourth threshold value, the second differential phase value calculation unit is not operated,
33. The synchronization acquisition circuit according to claim 32, wherein when the frequency deviation is smaller than a fourth threshold value and is equal to or larger than the first threshold value, the second differential phase value calculation unit is operated with the second number of delay chips. When the second differential phase value calculation unit is operating, the frequency deviation is calculated based on the phase of the first sum value;
and a frequency deviation calculation unit that calculates the frequency deviation based on a time rate of change of the phase of the first total value in a determined period when the second differential phase value calculation unit does not operate. a cumulative addition unit that cumulatively adds the first sum value a predetermined number of times for each of the first sum values calculated by shifting the received signal by one time point,
the operation control unit controls whether or not the cumulative addition unit is operated;
35. The synchronization acquisition circuit according to claim 26, wherein the power calculation unit calculates the power of the first sum value output by the cumulative addition unit when the cumulative addition unit operates, and calculates the power of the first sum value when the cumulative addition unit does not operate. the first sequence length is a product of a first division number, which is an integer of 3 or more, and a first unit number, which is an integer of 2 or more;
a unit first correlation value calculation unit, the unit first correlation value being a sum of the first unit number of consecutive despread second accumulated values, the unit first correlation value calculation unit being a number of the first division number ordered by the despread second accumulated values used in the calculation;
a first differential phase value calculation unit for calculating a first differential phase value which is a complex number having a phase difference between the unit first correlation value and the previous unit first correlation value, the first differential number being an integer obtained by subtracting 1 from the first division number;
a first difference correlation value calculation unit that calculates a first difference correlation value that is a sum of the first difference phase values in the first difference number ;
the operation control unit controls whether or not to operate the first differential phase value calculation unit ,
33. The synchronization acquisition circuit according to claim 26, wherein the power calculation unit calculates the power of the first integrated value, which is the first sum value or the first differential correlation value, and which is the first differential correlation value when the first differential phase value calculation unit operates and is the first sum value when the first differential phase value calculation unit does not operate . a first spreading code which has a first sequence length which is a product of a first division number which is an integer equal to or greater than 3 and a first unit number which is an integer equal to or greater than 2 and which is a pseudorandom number taking a binary value which changes with a first chip time, and a second spreading code which has a second sequence length which is a pseudorandom number taking a binary value which changes with a chip time obtained by dividing the first chip time by the second sequence length, the first spreading code being a pseudorandom number taking a binary value which changes with the chip time, the second spreading code being a pseudorandom number taking a binary value which changes with the chip time, the first spreading code being a product of a first sequence length and a second sequence length, the second spreading code being a pseudorandom number taking a binary value which changes with the chip time, the second spreading code being a pseudorandom number taking a binary value which changes with the chip time,
a second despreading received signal calculation unit for a second number of times that is the second sequence length, which calculates a second despreading received signal that is a complex number obtained by multiplying the second sequence length by the second number of time points obtained by multiplying the second sequence length by the excess coefficient, or a second despreading received signal that is a complex number obtained by multiplying each of the received signals of the number of the second sequence length selected to have an interval of the chip time, by each of the second spreading codes determined in accordance with the position of a chip to which each of the received signals belongs in the second sequence length; and
a second correlation value accumulator configured to calculate a second correlation value which is a sum of the second despread reception signals of the second despread number;
a second differential phase value calculation unit that calculates a second differential phase value, which is a complex number having a phase difference between the second correlation value and the second correlation value calculated using the received signal at a point in time a first delay time, which is a time obtained by multiplying the first chip time by a delay chip number, which is an integer equal to or greater than 1, prior to the received signal used when calculating the second correlation value;
a second accumulated value storage unit configured to store second accumulated values, the second correlation value or the second differential phase value, calculated by shifting the received signal by one time point, the second accumulated value being a stored number equal to or greater than a number obtained by multiplying the second number of time points by a minimum number of devices, the minimum number being an integer obtained by subtracting 1 from the first sequence length;
a post-despreading second accumulated value calculation unit for the number of first sequence lengths, which receives input of the second accumulated values for the number of first sequence lengths calculated at the time points of the first chip time, and when the second differential phase value calculation unit operates, receives input of each first differential code, the first differential code being a spread code having the first sequence length determined from the first spreading code, and the first differential code being a spread code taking two values: a unchanged value indicating that each of the first spreading codes has the same value as the first spreading code preceding the number of delay chips, and a changed value indicating that the first spreading code has a different value from the first spreading code preceding the number of delay chips, and when the second differential phase value calculation unit does not operate, receives input of each of the first spreading codes, and calculates a post-despreading second accumulated value which is a complex number obtained by multiplying each of the second accumulated values by the first differential code or each of the first spreading codes;
a first sum calculation unit that calculates a first sum which is a sum of the second accumulated values after despreading, the number of which is equal to or greater than a first difference number, which is an integer obtained by subtracting the first unit number from the first sequence length, and is equal to or less than the first sequence length;
a unit first correlation value calculation unit, the unit first correlation value being a sum of the first unit number of consecutive despread second accumulated values, the unit first correlation value calculation unit being the first division number ordered by the despread second accumulated values used in the calculation;
a first differential phase value calculation unit for calculating a first differential phase value which is a complex number having a phase difference between the unit first correlation value and the previous unit first correlation value, the first differential number being an integer obtained by subtracting 1 from the first division number;
an operation control unit that controls whether to operate the second differential phase value calculation unit and the first differential phase value calculation unit;
a first difference correlation value calculation unit that calculates a first difference correlation value that is a sum of the first difference phase values in the first difference number;
a power calculation unit that calculates power of the first integrated value, which is the first sum or the first difference correlation value, and which is the first difference correlation value when the first difference phase value calculation unit operates and is the first sum when the first difference phase value calculation unit does not operate;
a power storage unit configured to store the power in a number corresponding to a total number of time points, the total number of time points being a product of the second time point number and the first sequence length, the power being calculated by shifting the received signal by one time point at a time;
a peak detection and determination unit that determines the synchronization sequence position based on the position at which the power stored in the power storage unit takes a maximum value. 38. The acquisition circuit according to claim 37, wherein the second differential phase value calculation section calculates the second differential phase value having a determined amplitude. 38. The synchronization acquisition circuit according to claim 37, wherein the second differential phase value calculation unit calculates the second differential phase value by multiplying a complex conjugate of one of two input complex numbers by the other complex number. 40. The clock acquisition circuit according to claim 37, wherein the number of delay chips can take two or more different values. 41. The acquisition circuit of claim 40, wherein the number of delay chips is a first number of delay chips and a second number of delay chips that is greater than the first number of delay chips. a first selection output unit provided for each of the first differential phase value calculation units, for uniformly switching and outputting either one of the first unit correlation values, which is uniformly determined among the two unit first correlation values input to each of the first differential phase value calculation units, or the first differential phase value;
a first adder that calculates a sum of outputs of the first selection output unit;
the first adder operates as the first sum calculation unit that calculates the first sum when each of the first selection output units outputs the unit first correlation value;
the first adder operates as the first differential correlation value calculation unit that calculates the first differential correlation value when each of the first selection output units outputs the first differential phase value;
42. The synchronization acquisition circuit according to claim 37, wherein the operation control section uniformly controls whether each of the first selection output sections outputs the unit first correlation value or the first differential phase value. a first switch that is provided between an output of the first unit correlation value calculation unit that is the most recent or the latest and that is the first adder, and that switches between an input complex number and zero and outputs the input complex number or zero;
When the first selection output unit outputs the earlier unit first correlation value, a latest output of the unit first correlation value calculation unit is input to the first switch, and when the first selection output unit outputs a newer unit first correlation value, an output of the earliest unit first correlation value calculation unit is input to the first switch. The operation control unit:
When each of the first selection output units outputs the unit first correlation value, the first switch is controlled to output an input complex number;
43. The clock acquisition circuit of claim 42 , wherein the first switch is controlled to output zero when each of the first selection output sections outputs the first differential phase value. 44. The synchronization acquisition circuit according to claim 37 , wherein the first differential phase value calculation section calculates the first differential phase value having a determined amplitude. 44. The synchronization acquisition circuit according to claim 37 , wherein the first differential phase value calculation unit calculates the first differential phase value by multiplying a complex conjugate of one of two input complex numbers by the other complex number . The operation control unit is
When the frequency deviation is equal to or greater than a first threshold value, the second differential phase value calculation unit is operated;
when the frequency deviation is smaller than a second threshold value that is determined to be smaller than the first threshold value, the first differential phase value calculation unit and the second differential phase value calculation unit are not operated,
46. The synchronization acquisition circuit according to claim 37 , wherein the first differential phase value calculation unit is operated when the frequency deviation is smaller than the first threshold value and is equal to or larger than the second threshold value. When the second differential phase value calculation unit is operating, the frequency deviation is calculated based on the phase of the first sum value;
When the first differential phase value calculation unit is operating, the frequency deviation is calculated based on the phase of the first differential correlation value;
and a frequency deviation calculation unit that calculates the frequency deviation based on a time rate of change of the phase of the first sum value in a determined period when the second differential phase value calculation unit and the first differential phase value calculation unit are not operating. The operation control unit is
When a frequency change rate, which is a time change of a frequency deviation, is equal to or greater than a change rate threshold, operating the second differential phase value calculation unit and the first differential phase value calculation unit;
operating the second differential phase value calculation unit when the frequency change rate is smaller than the change rate threshold and the frequency deviation is equal to or larger than a first threshold;
when the frequency change rate is smaller than the change rate threshold and the frequency deviation is smaller than a second threshold that is determined to be smaller than the first threshold, the first differential phase value calculation unit and the second differential phase value calculation unit are not operated,
46. The synchronization acquisition circuit according to claim 37 , wherein the first differential phase value calculation unit is operated when the frequency change rate is smaller than the change rate threshold and the frequency deviation is smaller than the first threshold and equal to or larger than the second threshold. When the second differential phase value calculation unit and the first differential phase value calculation unit are operating, the frequency change rate is calculated based on the phase of the first differential correlation value, and the frequency deviation is calculated based on a value obtained by integrating the phase of the first differential correlation value;
When the second differential phase value calculation unit does not operate and the first differential phase value calculation unit operates, the frequency deviation is calculated based on the phase of the first differential correlation value, and the frequency change rate is calculated based on a time change in the phase of the first differential correlation value;
When the first differential phase value calculation unit does not operate and the second differential phase value calculation unit operates, the frequency deviation is calculated based on the phase of the first sum, and the frequency change rate is calculated based on a time change in the phase of the first sum;
49. The synchronization acquisition circuit according to claim 48, further comprising a frequency deviation calculation unit which, when the first differential phase value calculation unit and the second differential phase value calculation unit are not operating, approximates a change over time in the phase of the first total value in a determined period by a quadratic function of time, calculates the frequency change rate based on a quadratic coefficient, and calculates the frequency deviation based on the period and the frequency change rate. a two-stage unit first correlation value calculation unit that calculates a two-stage unit first correlation value, which is a sum of consecutive second accumulated values after despreading for a number of two-stage first units, the number being an integer obtained by dividing the first sequence length by a two-stage first division number, the two-stage first division number being a positive integer smaller than the first division number; and
a second-stage first differential phase value calculation unit for calculating a second-stage first differential phase value which is a complex number having a phase difference between the second-stage first correlation value and the immediately preceding second-stage first correlation value, the second-stage first differential number being an integer obtained by subtracting 1 from the second-stage first division number;
a second-stage first difference correlation value calculation unit that calculates a second-stage first difference correlation value that is a sum of the second-stage first difference phase values of the number of second-stage first differences ,
the operation control unit controls to operate either one of the first differential phase value calculation unit and the second stage first differential phase value calculation unit, or to operate neither of them;
the first integrated value when the second-stage first differential phase value calculation unit operates is the second-stage first differential correlation value,
46. The synchronization acquisition circuit according to claim 37 , wherein the power calculation section calculates the power of the first integrated value, which is any one of the first sum value, the first differential correlation value, and the second-stage first differential correlation value. 51. The acquisition circuit according to claim 50 , wherein the second-stage first differential phase value calculation section calculates the second-stage first differential phase value having a determined amplitude. 51. The synchronization acquisition circuit according to claim 50, wherein the second-stage first differential phase value calculation unit calculates the second-stage first differential phase value by multiplying a complex conjugate of one of two input complex numbers by the other complex number. The operation control unit is
When the frequency deviation is equal to or greater than a first threshold value, the second differential phase value calculation unit is operated;
when the frequency deviation is smaller than a second threshold value that is determined to be smaller than the first threshold value, not operating the second differential phase value calculation unit, the first differential phase value calculation unit, and the second stage first differential phase value calculation unit,
activating the first differential phase value calculation unit when the frequency deviation is equal to or greater than a fifth threshold value that is determined to be smaller than the first threshold value and larger than the second threshold value, and is smaller than the first threshold value;
53. The synchronization acquisition circuit according to claim 50 , wherein the second stage first differential phase value calculation unit is operated when the frequency deviation is smaller than the fifth threshold value and larger than the second threshold value. The operation control unit is
When the frequency deviation is equal to or greater than a fourth threshold, the second differential phase value calculation unit is operated with the first number of delay chips;
When the frequency deviation is equal to or greater than a first threshold value that is determined to be smaller than the fourth threshold value, operating the second differential phase value calculation unit with the second number of delay chips;
when the frequency deviation is smaller than a second threshold value that is determined to be smaller than the first threshold value, not operating the second differential phase value calculation unit, the first differential phase value calculation unit, and the second stage first differential phase value calculation unit,
activating the first differential phase value calculation unit when the frequency deviation is equal to or greater than a fifth threshold value that is determined to be smaller than the first threshold value and larger than the second threshold value, and is smaller than the first threshold value;
The synchronization acquisition circuit according to any one of claims 50 to 52 when dependent on claim 41 , wherein the second stage first differential phase value calculation unit is operated when the frequency deviation is smaller than the fifth threshold value and larger than the second threshold value. When the second differential phase value calculation unit is operating, the frequency deviation is calculated based on the phase of the first sum value;
When the first differential phase value calculation unit is operating, the frequency deviation is calculated based on the phase of the first differential correlation value;
When the second-stage first differential phase value calculation unit operates, the frequency deviation is calculated based on the phase of the second-stage first differential correlation value;
and a frequency deviation calculation unit that calculates the frequency deviation based on a time rate of change of the phase of the first sum value in a determined period when the second differential phase value calculation unit, the first differential phase value calculation unit, and the second stage first differential phase value calculation unit do not operate. The operation control unit is
When a frequency change rate, which is a time change of a frequency deviation, is equal to or greater than a change rate threshold, operating the second differential phase value calculation unit and the first differential phase value calculation unit;
operating the second differential phase value calculation unit when the frequency change rate is smaller than the change rate threshold and the frequency deviation is equal to or larger than a first threshold;
when the frequency change rate is smaller than the change rate threshold and the frequency deviation is smaller than a second threshold that is determined to be smaller than the first threshold, the first differential phase value calculation unit, the second stage first differential phase value calculation unit, and the second differential phase value calculation unit are not operated,
operating the first differential phase value calculation unit when the frequency change rate is smaller than the change rate threshold and the frequency deviation is equal to or greater than a fifth threshold that is smaller than the first threshold and larger than the second threshold, and is smaller than the first threshold;
53. The synchronization acquisition circuit according to claim 50, wherein the second stage first differential phase value calculation unit is operated when the frequency change rate is smaller than the change rate threshold and the frequency deviation is smaller than the fifth threshold and larger than the second threshold . The operation control unit is
When a frequency change rate, which is a time change of a frequency deviation, is equal to or greater than a change rate threshold, operating the second differential phase value calculation unit and the first differential phase value calculation unit;
operating the second differential phase value calculation unit with the first number of delay chips when the frequency change rate is smaller than the change rate threshold and the frequency deviation is equal to or larger than a fourth threshold;
operating the second differential phase value calculation unit with the second number of delay chips when the frequency change rate is smaller than the change rate threshold and the frequency deviation is equal to or larger than a first threshold that is smaller than the fourth threshold;
when the frequency change rate is smaller than the change rate threshold and the frequency deviation is smaller than a second threshold that is determined to be smaller than the first threshold, the first differential phase value calculation unit, the second stage first differential phase value calculation unit, and the second differential phase value calculation unit are not operated,
operating the first differential phase value calculation unit when the frequency change rate is smaller than the change rate threshold and the frequency deviation is equal to or greater than a fifth threshold that is smaller than the first threshold and larger than the second threshold, and is smaller than the first threshold;
53. The synchronization acquisition circuit according to claim 50, wherein the second stage first differential phase value calculation unit is operated when the frequency change rate is smaller than the change rate threshold and the frequency deviation is smaller than the fifth threshold and larger than the second threshold . When the second differential phase value calculation unit and the first differential phase value calculation unit are operating, the frequency change rate is calculated based on the phase of the first differential correlation value, and the frequency deviation is calculated based on a value obtained by integrating the phase of the first differential correlation value;
When the second differential phase value calculation unit and the second stage first differential phase value calculation unit are not operating and the first differential phase value calculation unit is operating, the frequency deviation is calculated based on the phase of the first differential correlation value, and the frequency change rate is calculated based on a time change in the phase of the first differential correlation value;
When the second differential phase value calculation unit and the first differential phase value calculation unit do not operate and the second-stage first differential phase value calculation unit operates, the frequency deviation is calculated based on the phase of the second-stage first differential correlation value, and the frequency change rate is calculated based on a time change in the phase of the second-stage first differential correlation value;
When the first differential phase value calculation unit and the second stage first differential phase value calculation unit are not operating and the second differential phase value calculation unit is operating, the frequency deviation is calculated based on the phase of the first sum, and the frequency change rate is calculated based on a time change in the phase of the first sum,
58. The synchronization acquisition circuit according to claim 56 or 57, further comprising a frequency deviation calculation unit which, when the first differential phase value calculation unit, the second differential phase value calculation unit, and the second-stage first differential phase value calculation unit do not operate, approximates a time change in the phase of the first total value in a determined period by a quadratic function of time, calculates the frequency change rate based on a quadratic coefficient, and calculates the frequency deviation based on the period and the frequency change rate. the second sequence length is a product of a second division number, which is an integer of 3 or more, and a second unit number, which is an integer of 2 or more,
a unit second correlation value accumulator for calculating a unit second correlation value which is a sum of the second unit number of despread received signals calculated using the second unit number of consecutive second spreading codes, the unit second correlation value accumulator being the number of units ordered by the second spreading codes used for calculation;
a unit second differential phase value calculation unit, the number of which is the second division number minus 1, for calculating a unit second differential phase value which is a complex number having a phase difference between the unit second correlation value and the unit second correlation value immediately preceding the unit second correlation value;
a unit second differential correlation value calculation unit that calculates a unit second differential correlation value that is a sum of the unit second differential phase values,
the operation control unit controls to operate either one of the unit second differential phase value calculation unit and the second differential phase value calculation unit, or to operate neither of the unit second differential phase value calculation unit and the second differential phase value calculation unit;
When the unit second differential phase value calculation unit operates, the unit second differential correlation value is stored in the second integrated value storage unit,
50. The synchronization acquisition circuit according to claim 26 , wherein when the unit second differential phase value calculation section does not operate, the second integrated value is stored in the second integrated value storage section. the second sequence length is a product of a second division number, which is an integer of 3 or more, and a second unit number, which is an integer of 2 or more,
a unit second correlation value accumulator for calculating a unit second correlation value which is a sum of the second unit number of despread received signals calculated using the second unit number of consecutive second spreading codes, the unit second correlation value accumulator being the number of units ordered by the second spreading codes used for calculation;
a unit second differential phase value calculation unit for calculating a unit second differential phase value, which is a complex number having a phase difference between the unit second correlation value and the unit second correlation value immediately preceding the unit second correlation value;
a second selection output unit provided for each of the unit second differential phase value calculation units, for uniformly switching and outputting either one of the unit second correlation values uniformly determined among the two unit second correlation values input to each of the unit second differential phase value calculation units or the unit second differential phase value;
a second adder that outputs a sum of the outputs of the second selection output unit;
the operation control unit uniformly controls whether each of the second selection output units outputs the unit second correlation value or the second differential phase value;
the second adder operates as the second correlation value accumulator that calculates the second correlation value when each of the second selection output units outputs the unit second correlation value;
the second adder operates as the unit second differential correlation value calculation unit that calculates the unit second differential correlation value when each of the second selection output units outputs the unit second differential phase value;
When the unit second differential phase value calculation unit operates, the unit second differential correlation value is stored in the second integrated value storage unit,
46. The synchronization acquisition circuit according to claim 26, wherein when the unit second differential phase value calculation unit does not operate, the second integrated value is stored in the second integrated value storage unit. a second switch that is provided between an output of the first or latest unit second correlation value accumulating unit and the second adder, and that switches between an input complex number or zero and outputs the input complex number or zero;
When the second selection output unit outputs the earlier unit second correlation value, the latest output of the unit second correlation value accumulator is input to the second switch, and when the second selection output unit outputs the newer unit second correlation value, the earliest output of the unit second correlation value accumulator is input to the second switch. The operation control unit:
When each of the second selection output units is controlled to output the unit second correlation value, the second switch is controlled to output an input complex number;
61. The synchronization acquisition circuit according to claim 60 , wherein when each of the second selection output sections is controlled to output the unit second differential phase value, the second switch is controlled to output zero. 62. The synchronization acquisition circuit according to claim 59 , wherein the unit second differential phase value calculation section calculates the unit second differential phase value having a determined amplitude. 62. The synchronization acquisition circuit according to claim 59 , wherein the unit second differential phase value calculation unit calculates the unit second differential phase value by multiplying a complex conjugate of one of two input complex numbers by the other complex number. The operation control unit is
activating the unit second differential phase value calculation unit when the frequency deviation is equal to or greater than a third threshold value that is determined to be greater than the first threshold value;
When the frequency deviation is smaller than the third threshold value and is equal to or larger than the first threshold value, operating the second differential phase value calculation unit ;
64. The synchronization acquisition circuit according to claim 59, when dependent on claim 26, wherein the unit second differential phase value calculation unit and the second differential phase value calculation unit are not operated when the frequency deviation is smaller than the first threshold value. When the second differential phase value calculation unit or the unit second differential phase value calculation unit is operating, the frequency deviation is calculated based on the phase of the first sum value;
65. The synchronization acquisition circuit of claim 64, further comprising a frequency deviation calculation unit that calculates the frequency deviation based on a time rate of change of the phase of the first total value in a determined period when the second differential phase value calculation unit and the unit second differential phase value calculation unit do not operate. The operation control unit is
activating the unit second differential phase value calculation unit when the frequency deviation is equal to or greater than a third threshold value that is determined to be greater than the first threshold value;
When the frequency deviation is smaller than the third threshold value and is equal to or larger than the first threshold value, operating the second differential phase value calculation unit;
when the frequency deviation is smaller than a second threshold value that is determined to be smaller than the first threshold value, the unit second differential phase value calculation unit, the second differential phase value calculation unit, and the first differential phase value calculation unit are not operated,
The synchronization acquisition circuit according to any one of claims 59 to 63 when dependent on any one of claims 37 to 45 , wherein the first differential phase value calculation unit is operated when the frequency deviation is smaller than the first threshold value and is equal to or larger than the second threshold value . When the first differential phase value calculation unit is operating, the frequency deviation is calculated based on the phase of the first differential correlation value;
When the second differential phase value calculation unit or the unit second differential phase value calculation unit is operating, the frequency deviation is calculated based on the phase of the first sum value;
67. The synchronization acquisition circuit of claim 66, further comprising: a frequency deviation calculation unit that calculates the frequency deviation based on a time rate of change of the phase of the first total value in a determined period when the second differential phase value calculation unit, the first differential phase value calculation unit, and the unit second differential phase value calculation unit are not operating. The operation control unit is
activating the unit second differential phase value calculation unit when the frequency deviation is equal to or greater than a third threshold value that is determined to be greater than the first threshold value;
operating the second differential phase value calculation unit and the first differential phase value calculation unit when a frequency change rate, which is a time change of a frequency deviation, is equal to or greater than a change rate threshold value and the frequency deviation is smaller than the third threshold value;
operating the second differential phase value calculation unit when the frequency change rate is smaller than the change rate threshold and the frequency deviation is smaller than the third threshold and equal to or larger than the first threshold;
when the frequency change rate is smaller than the change rate threshold and the frequency deviation is smaller than a second threshold that is determined to be smaller than the first threshold, the unit second differential phase value calculation unit, the second differential phase value calculation unit, and the first differential phase value calculation unit are not operated,
64. The synchronization acquisition circuit according to claim 59 , wherein the first differential phase value calculation unit is operated when the frequency change rate is smaller than the change rate threshold and the frequency deviation is smaller than the first threshold and equal to or larger than the second threshold. When the second differential phase value calculation unit and the first differential phase value calculation unit are operating, the frequency change rate is calculated based on the phase of the first differential correlation value, and the frequency deviation is calculated based on a value obtained by integrating the phase of the first differential correlation value,
When the unit second differential phase value calculation unit and the second differential phase value calculation unit are not operating and the first differential phase value calculation unit is operating, the frequency deviation is calculated based on the phase of the first differential correlation value, and the frequency change rate is calculated based on a time change in the phase of the first differential correlation value;
When the first differential phase value calculation unit does not operate and the unit second differential phase value calculation unit or the second differential phase value calculation unit operates, the frequency deviation is calculated based on the phase of the first sum, and the frequency change rate is calculated based on a time change in the phase of the first sum,
69. The synchronization acquisition circuit of claim 68, further comprising a frequency deviation calculation unit which, when the unit second differential phase value calculation unit, the second differential phase value calculation unit, and the first differential phase value calculation unit are not operating, approximates a time change in the phase of the first total value in a determined period by a quadratic function of time, calculates the frequency change rate based on a quadratic coefficient, and calculates the frequency deviation based on the period and the frequency change rate. The operation control unit is
when a frequency change rate, which is a time change of a frequency deviation, is equal to or greater than a change rate threshold and the frequency deviation is equal to or greater than a third threshold that is greater than the first threshold, the second unit differential phase value calculation unit and the first differential phase value calculation unit are operated;
when the frequency change rate is equal to or greater than the change rate threshold and the frequency deviation is smaller than the third threshold, operating the second differential phase value calculation unit and the first differential phase value calculation unit;
operating the unit second differential phase value calculation unit when the frequency change rate is smaller than the change rate threshold and the frequency deviation is equal to or larger than the third threshold;
operating the second differential phase value calculation unit when the frequency change rate is smaller than the change rate threshold and the frequency deviation is smaller than the third threshold and equal to or larger than the first threshold;
when the frequency change rate is smaller than the change rate threshold and the frequency deviation is smaller than a second threshold that is determined to be smaller than the first threshold, the unit second differential phase value calculation unit, the second differential phase value calculation unit, and the first differential phase value calculation unit are not operated,
64. The synchronization acquisition circuit according to claim 59 , wherein the first differential phase value calculation unit is operated when the frequency change rate is smaller than the change rate threshold and the frequency deviation is smaller than the first threshold and equal to or larger than the second threshold. When the unit second differential phase value calculation unit or the second differential phase value calculation unit and the first differential phase value calculation unit are operating, the frequency change rate is calculated based on the phase of the first differential correlation value, and the frequency deviation is calculated based on a value obtained by integrating the phase of the first differential correlation value,
When the unit second differential phase value calculation unit and the second differential phase value calculation unit are not operating and the first differential phase value calculation unit is operating, the frequency deviation is calculated based on the phase of the first differential correlation value, and the frequency change rate is calculated based on a time change in the phase of the first differential correlation value;
When the first differential phase value calculation unit does not operate and the unit second differential phase value calculation unit or the second differential phase value calculation unit operates, the frequency deviation is calculated based on the phase of the first sum, and the frequency change rate is calculated based on a time change in the phase of the first sum,
71. The synchronization acquisition circuit according to claim 70, further comprising a frequency deviation calculation unit which, when the unit second differential phase value calculation unit, the second differential phase value calculation unit, and the first differential phase value calculation unit are not operating, approximates a time change in the phase of the first total value in a determined period by a quadratic function of time, calculates the frequency change rate based on a quadratic coefficient, and calculates the frequency deviation based on the period and the frequency change rate. The method further includes an accumulating unit that accumulates the first accumulated value a predetermined number of times for each of the first accumulated values calculated by shifting the reception signal by one time point,
the operation control unit controls whether or not the cumulative addition unit is operated;
72. The synchronization acquisition circuit according to claim 36, wherein the power calculation unit calculates the power of the first accumulated value output by the cumulative addition unit when the cumulative addition unit is operating, and calculates the power of the first accumulated value when the cumulative addition unit is not operating.

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