JP7586441B2 - Multiply-and-accumulate unit - Google Patents

Description

The present invention relates to a multiply-and-accumulate calculator. More specifically, the present invention relates to a multiply-and-accumulate calculator using a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC).

Digital calculations are based on product-sum calculations. Furthermore, AI processors, which have been the subject of fierce competition in recent years, use neurocalculation. Figure 15 is a conceptual diagram of neurocalculation in an AI processor. Note that neurocalculation requires multiple layers, but Figure 15 only shows the basic input layer, hidden layer, and output layer.

As shown in Fig. 15, product-sum operations are performed between each layer in neuro-operation. As an example, the operation between the input layer and the hidden layer is shown below. If the input layer vector is X and the connection coefficient matrix is W ⁽⁰⁾ , the hidden layer vector Y is expressed by the following formula 1.

When one element _yj of the output layer in the above formula 1 is focused on, it is expressed by the following formula 2, and it can be seen that a product-sum operation process is performed.

In a neuroprocessor, when the number of nodes in each layer is N, ^N2 product-sum operations are required in each layer. For example, in image recognition with 100 x 100 pixels, N = ¹⁰⁴ , ^N2 = ¹⁰⁸ , and 100 million product-sum operations are required per layer. For this reason, it is an urgent task for neuroprocessors to increase the operation speed while reducing the energy consumption of operations.

Figure 16 is a diagram showing the configuration of a conventional multiply-accumulate calculator using digital circuits. As shown in Figure 16, in a typical conventional digital multiply-accumulate calculator, input X is input to each flip-flop (F/F) via a bus. Also, in the multiply-accumulate calculator shown in Figure 16, multipliers (MUL) are arranged two-dimensionally, and each element of input X and each element of input W are input to each multiplier, and each element of input X is multiplied by each element of input W in the multiplier. The multiplication outputs are then input sequentially to adders (ADD) via a bus, where cumulative addition is performed.

K. Uenishi, et al., “FPGA Implementation of a Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines,” Circuits and Systems, 2016, 7, 2132-2141, Scientific Research Publishing.

However, the conventional digital multiply-and-accumulate unit described above has problems with the operation speed and energy consumption of the multiplier, and the operation speed and energy consumption of the cumulative adder. In particular, the cumulative adder has issues with its slow operation speed and large energy consumption because the output of the multiplier is sent to the cumulative adder sequentially via a bus.

Therefore, the present invention aims to provide a multiply-and-accumulate calculator that has a high calculation speed and low energy consumption.

The inventors conducted extensive experimental studies to solve the above-mentioned problems, and as a result, have arrived at the following findings. Analog calculations use physical phenomena, and it is possible to obtain calculation results instantly and with low energy consumption. However, analog calculations have been rarely used in the past, as their calculation accuracy is insufficient compared to digital calculations. On the other hand, for multiply-and-accumulate calculations in neuroprocessors, an accuracy of around 8 bits is considered sufficient for most applications, and so the inventors have investigated the application of analog calculations.

As a result, they found that by using a voltage output DAC such as a resistive digital-to-analog converter (RDAC) to generate a voltage proportional to the input X, and then using a capacitive DAC in which a capacitance ratio corresponding to the digital value of each matrix element W is set between the input/output terminals and between the output terminal and ground with this voltage as the analog input, the output voltage Y becomes the product of the input X and each matrix element W. By adopting this configuration, the capacitance required to achieve 8-bit accuracy is extremely small at around 4fF, and since carry propagation does not occur, unlike in a digital multiplier, it can be operated at high speed with low energy consumption.

Furthermore, the voltage at the node where the output terminals of the capacitive DAC string are commonly connected is the sum of the voltages due to the law of conservation of charge, making it possible to add multiple inputs instantly with almost no energy consumption. Specifically, adding 100 inputs in parallel is completed in an instant. This voltage is converted to a digital value by the ADC. In this way, the inventor has discovered a method for performing multiply-and-add operations at high speed and with low energy by performing multiplication and addition operations in analog while the input and output are digital values, which led to the present invention.

That is, the product-sum calculator according to the present invention comprises: a voltage output digital-to-analog conversion unit which is composed of a plurality of digital-to-analog converters and receives as input a vector having a plurality of digital values as elements and a matrix having a plurality of digital values as elements and converts the digital value of each element of the vector into an analog voltage; a capacitive digital-to-analog conversion unit which is composed of a plurality of digital-to-analog converters and receives as input each output voltage of the voltage output digital-to-analog converter string and sets a capacitance ratio between the input/output terminals and between the output terminal and ground corresponding to the digital value of each element of the matrix; and an analog-to-digital conversion unit which is composed of a plurality of analog-to-digital converters and receives as input an analog voltage of a node commonly connected to each output terminal of the capacitive digital-to-analog conversion units and converts it into a digital value, and the output of the analog-to-digital conversion unit is an output vector.
In the multiply-add calculator of the present invention, the matrix having the multiple digital values as elements may be a one-dimensional vector, and the output value from each digital-to-analog converter of the voltage output digital-to-analog conversion unit may be an inner product of a first vector and the one-dimensional vector.
In the product-sum calculator of the present invention, the capacitive digital-to-analog conversion unit outputs a differential signal, and each analog-to-digital converter of the analog-to-digital conversion unit receives an analog input of a differential voltage of a pair of nodes commonly connected to each output end of the capacitive digital-to-analog conversion unit, which is converted into a digital value.
In this case, each analog-to-digital converter in the analog-to-digital conversion section samples the differential voltage of the pair of nodes onto a pair of capacitors, extracts a common-mode signal by shorting the terminals between the pair of capacitors, and cancels the common-mode component by subtracting it from the differential voltage of the pair of nodes.
Alternatively, the capacitive digital-to-analog conversion section may set a capacitance ratio corresponding to the digital value of each element between the input/output terminals and between the output terminal and ground using a binary-weighted capacitance for the output.
Furthermore, the product-sum calculator of the present invention may use weighting resistors in each of the digital-to-analog converters constituting the voltage output digital-to-analog conversion section.
In this case, each digital-to-analog converter constituting the voltage output digital-to-analog conversion unit can be configured, for example, with equal resistances using a thermometer code for the most significant bits, and with binary-weighted R-2R ladder-type resistances for the remaining lower bits.
Alternatively, each digital-to-analog converter constituting the voltage output digital-to-analog conversion section may be configured so that the connection of the least significant bit resistor to the ground terminal can be opened.
Meanwhile, in the multiply-and-accumulate calculator of the present invention, input data to the voltage output digital-to-analog converter and the capacitive digital-to-analog converter are stored in memory cells, and the input data can be obtained from the output of a sense amplifier that senses the logic state.
In this case, input data to the memory cells may be in a differential format, transmitted using a low amplitude bus with an amplitude lower than the power supply voltage, and converted to a larger amplitude by the sense amplifier to drive the bit lines of the memory cells.
The memory cells may be, for example, SRAM.
Alternatively, the memory cells may be non-volatile, for example, MRAM may be used as the non-volatile memory cells.

According to the present invention, an output vector can be obtained from the output values of multiple analog-digital converters in an analog-digital conversion section, and an extremely large number of product-sum operations can be performed simultaneously in parallel, thereby realizing a product-sum operator that operates with lower energy and at higher speeds than conventional product-sum operators that use digital operators.

FIG. 2 is a diagram illustrating a configuration of a multiply-add calculator according to the first embodiment of the present invention. FIG. 1A is a circuit diagram of a resistance-type DAC used in the voltage output digital-to-analog conversion unit 11 shown in FIG. 1, and FIG. 2 is a circuit diagram of a CDAC used in the capacitive digital-to-analog conversion unit 12 shown in FIG. 1 . 1A and 1B are diagrams showing a circuit illustrating the principle of a product-sum operation using a CDAC and its operation, where A shows a reset mode and B shows an execution mode. FIG. 1 is a circuit diagram of a differential CDAC. 2 is a circuit diagram of a successive approximation type ADC used in the analog-to-digital conversion unit 13 shown in FIG. 1 . 2 is a timing chart showing an operation of the product-sum calculator shown in FIG. 1 . FIG. 11 is a circuit diagram of a successive approximation type ADC used in a product-sum calculator according to a first modified example of the first embodiment of the present invention. 9A to 9C are operational circuit diagrams showing a method for removing a common-mode voltage in the SAR ADC shown in FIG. 8. FIG. 11 is a circuit diagram of a resistive DAC used in a product-sum calculator according to a second modified example of the first embodiment of the present invention. 2 is an equivalent circuit for calculating the response speed and power consumption in the product-sum calculator according to the first embodiment of the present invention. FIG. 13 is a diagram showing a data input circuit to a DAC used in a multiply-accumulate calculator according to a second embodiment of the present invention. 12. A and B are circuit diagrams of the memory cell shown in FIG. 12, and C is a circuit diagram of the sense amplifier. FIG. 13 is a diagram showing the voltage of the input bus to the memory cell shown in FIG. 12. FIG. 1 is a conceptual diagram of neuro-computation in an AI processor. FIG. 1 is a diagram showing a configuration of a conventional multiply-accumulate calculator using a digital circuit.

Hereinafter, the embodiment of the present invention will be described in detail with reference to the attached drawings. Note that the present invention is not limited to the embodiment described below.

(First embodiment)
First, a multiply-accumulate calculator according to a first embodiment of the present invention will be described. The multiply-accumulate calculator of this embodiment receives two input digital value strings as inputs, one of which is converted to a voltage string using a voltage output digital-to-analog converter (DAC), and the other input is input to a capacitive digital-to-analog converter (CDAC). In this multiply-accumulate calculator, multiplication is performed by a CDAC that uses a voltage as an analog input, and simultaneous addition is performed by connecting the outputs of multiple CDACs in common, and the voltage of this node is analog-to-digital converted in an analog-to-digital converter (ADC) to obtain a digital output value.

Figure 1 is a diagram showing the configuration of a multiply-and-accumulate calculator of this embodiment. As shown in Figure 1, the multiply-and-accumulate calculator 1 of this embodiment is provided with a voltage output digital-to-analog conversion unit 11 having multiple DACs, a capacitive digital-to-analog conversion unit 12 having multiple CDACs, and an analog-to-digital conversion unit 13 having multiple ADCs. In the multiply-and-accumulate calculator 1 of this embodiment, a vector X having multiple digital values as each element is input to each DAC of the voltage output digital-to-analog conversion unit 11 via a bus. In addition, the digital values of each element of the matrix W are input to each CDAC arranged two-dimensionally in the capacitive digital-to-analog conversion unit 12.

Fig. 2A is a circuit diagram of a resistive DAC used in the voltage output digital-analog conversion unit 11 shown in Fig. 1, and Fig. 2B is a circuit diagram of a current type DAC. The voltage output digital-analog conversion unit 11 can be realized by using, for example, an R-2R resistive DAC as shown in Fig. 2A or a current type DAC as shown in Fig. 2B. When the power supply voltage of the inverter is V _DD and the inverted input data of each inverter is D (D is 0 or 1), the output voltage V ₀ of the R-2R resistive DAC is expressed by the following formula 3.

Fig. 2A shows an example of a 4-bit resolution, and because this resistance-type DAC uses only an inverter and two types of resistors R and 2R, it can realize a very compact voltage output digital-to-analog converter. On the other hand, a voltage output digital-to-analog converter can also be realized using a current-type DAC shown in Fig. 2B. In this case, a voltage output digital-to-analog converter can be realized by using a current source to pass a current corresponding to the input data through load resistors R _L.

Fig. 3 is a circuit diagram of a CDAC used in the capacitive digital-analog conversion unit 12 shown in Fig. 1. The capacitive digital-analog conversion unit 12 can use, for example, the CDAC shown in Fig. 3. This CDAC is connected to a switch S that selects ground or an input voltage according to input data D, and a binary-weighted capacitance at the output terminal. When the input voltage is _Vin , the output voltage _Vout can be calculated by the following formula 4.

If the input bit of the resistive DAC is _Xi and the input bit of the CDAC is _Wi , then the output voltage _Vout is expressed by the following equation 5 based on the above equations 3 and 4. This indicates that the input value X and the input value W are multiplied.

Next, the additivity of signals in the common connection line of the CDAC, which is the input to the analog-digital conversion unit 13, will be described. Figures 4A and 4B are diagrams showing the operation of a circuit showing the principle of product-sum calculation using a CDAC. The CDAC shown in Figures 4A and 4B has two capacitances, a capacitance value WC proportional to an input value W normalized to 1, and a capacitance value (1-W)C obtained by subtracting the input value W from 1, which are connected in parallel. One terminal of each of these two capacitances is commonly connected to an output line, and the other terminal is connected to switches S _a and S _b that select an input voltage or ground.

This CDAC has two operation modes: "reset" shown in Fig. 4A and "run" shown in Fig. 4B. As shown in Fig. 4A, in the reset mode, all the switches S _a and S _b select the ground, and the output line is connected to the ground by the switch S _0. Therefore, the charge of each capacitance is reset to zero. On the other hand, as shown in Fig. 4B, in the run mode, the switch S _b remains in the ground state, and the switch S _a selects the input voltage V _DD X. If the voltage of the output line at this time is V _OS , the following formula 6 holds according to the law of conservation of charge.

When the voltage V _os is calculated from the above formula 6, the following formula 7 is obtained, and the outputs of n CDACs are added simultaneously.

The output voltage is automatically normalized to a voltage between 0 and _VDD .

As described above, by using the physical phenomenon of conservation of charge, multiple additions can be performed instantaneously. Moreover, by configuring the CDAC differentially, it is possible to easily handle values of both positive and negative polarities. Figure 5 is a circuit diagram of a differential CDAC. As shown in Figure 5, the input signal of the differential CDAC is a bipolar input signal with w taking the value expressed by the following formula 8, and η is a bias value, and the relationship shown in the following formula 9 is established with the input signal W of the standardized CDAC used up to now.

The bias value η can take the widest range when it is 0.5. Because of the differential configuration, the values W _a and W _b input to each CDAC are expressed by the following formula 10.

At this time, the output voltage V _{os_p} of the pair of signal lines is expressed by the following Equation 11 from Equation 7 above.

Similarly, the output voltage _{Vos_n} is given by the following formula 12.

Therefore, the differential output V _{os — d} =V _{os — p} -V _{os — n} is given by the following formula 13, and a bipolar signal of both positive and negative polarities that is not dependent on the bias value η is obtained.

The differential output may be obtained by subjecting the voltages V _{os_p} and V _{os_n} to analog-to-digital conversion and then subtracting the converted output values using a digital subtractor; however, it is more reasonable to use a differential ADC, since the converted output value itself is a conversion of only the differential component.

ADCs of various conversion methods can be used for the analog-digital conversion unit 13, but a successive approximation register ADC (SAR ADC) using a CDAC is particularly compact, consumes less energy, and is practical. Fig. 6 is a circuit diagram of a SAR ADC used for the analog-digital conversion unit 13. In the SAR ADC shown in Fig. 6, when switch _S0 is closed, switch _S1 selects the input signal _Vin , and switches _S1 to _S5 select the input signal, the charge _Qs at the output end of the CDAC connected to the input end of the comparator is expressed by the following formula 14, where _Vb is the bias voltage of the comparator.

On the other hand, when the switch _S0 is opened, the switch _S1 to S4 selects the reference voltage _Vref , and the switches _S1 to _S4 are controlled to set the voltage at the input end of the comparator to _Vx , α to an arbitrary value between 0 and 1, α to be the capacitance connected to the reference voltage, and the remaining 1-α to be the capacitance connected to ground, according to the law of conservation of charge, the charge _Qs at the output end of the CDAC is expressed by the following equation 15.

Here, the input voltage V _x −V _b of the comparator is expressed by the following formula 16.

That is, in this SAR ADC switch, if the switches S ₁ to S ₄ are controlled to obtain α and the input voltage of the comparator is operated so as to approach 0, analog-to-digital conversion becomes possible.

7 is a timing chart showing the operation of the multiply-and-accumulate calculator of this embodiment. As shown in FIG. 7, in the multiply-and-accumulate calculator of this embodiment, two input data values X and W of the DAC shown by the input signal D _in are input in synchronization with the clock CLK. The node commonly connecting the output terminals of the capacitive digital-to-analog conversion unit 12 becomes the ground potential for a short period of time, and the charge of each capacitance of the CDAC is reset.

When the node is released and input data is given to the CDAC, a voltage appears at the node that corresponds to the sum of the inner product of the input data value X and the input data value W. The ADC samples this node voltage and then performs an analog-to-digital conversion operation. The output D _out is basically output with a delay of two clocks from the input signal D _in .

As described above in detail, the multiply-and-accumulate calculator of this embodiment has a voltage output digital-to-analog conversion unit, a capacitive digital-to-analog conversion unit, and an analog-to-digital conversion unit, and the output value of the analog-to-digital conversion unit is used as an output vector, so that an output vector can be obtained from the output values of multiple ADCs, and an extremely large number of multiply-and-accumulate operations can be performed simultaneously in parallel, thereby speeding up the operation and reducing power consumption. As a result, a multiply-and-accumulate calculator that operates with low energy and can operate at high speed compared to conventional multiply-and-accumulate calculators using digital calculators can be realized. As a result of the inventor's calculations, the multiply-and-accumulate calculator of this embodiment was able to operate with low energy consumption of about 1/300 compared to normal digital multiply-and-accumulate operations in 8-bit multiply-and-accumulate operations.

(First Modification of the First Embodiment)
Next, some improvements for improving the performance of the multiply-accumulate calculator of the first embodiment of this invention will be described. Fig. 8 is a circuit diagram of a SAR ADC used in the multiply-accumulate calculator according to the first modification of the first embodiment of the present invention. Since the SAR ADC shown in Fig. 6 is a single input, the SAR ADC shown in Fig. 8 is more suitable for differential input. The SAR ADC shown in Fig. 8 is capable of removing a common voltage that depends on a signal, and the portion surrounded by a dashed line in Fig. 8 is a circuit newly added to the SAR ADC in Fig. 6.

Next, the operation of this modified example will be described. Figures 9A to 9C are operational circuit diagrams showing a method of removing the common mode voltage of the SAR ADC shown in Figure 8. In the multiply-accumulate calculator of this modified example, first, as shown in Figure 9A, switch _S0 is shorted, switch _Ss selects input signals V _{os_p} and V _{os_n} , and switches S _bias of newly added capacitances C _{c_p} and C _{c_n} are grounded, and switch S _com selects input signals V _{os_p} and V _{os_n} , respectively.

In this state, the charges Q _{x — p} and Q _{x — n} at the input terminals of the comparators are expressed by the following formula 17 using the above formulas 11 and 12 as input signals.

Furthermore, the capacitance values of the cancellation capacitances C _{c_p} and C _{c_n} for removing the common voltage enclosed by the dashed line are equal to _Cu , and therefore the charges Q _{c_p} and Q _{c_n} of the cancellation capacitances C _{c_p} and C _{c_n} are expressed by the following formula 18.

Next, as shown in FIG. 9B, when the switch S _com is controlled to short-circuit the capacitors C _{c_p} and C _{c_n} , from Equation 18 above, each charge is expressed by Equation 19 below.

9C, the switch _S0 is opened, the switch _Scom selects the input terminal of the comparator, and the switch _Sbias selects the voltage V _DD . The charges _Qxp and _Qxn at the input terminal of the comparator are expressed by Equation 20 from Equation 17 and Equation 18 above, and the common-mode component is removed.

Moreover, V _{x_p} and V _{x_n} of the input terminals of the comparator satisfy the following formula 21.

As a result, V _{x — p} and V _{x — n} are given by the following formula 22, and an ideal operation in which the midpoint of the voltage is (V _DD /2) can be realized.

Furthermore, the differential voltage V _{x — p} −V _{x — n} is given by the following formula 23, and the bias component is cancelled out, making it possible to realize ideal analog-to-digital conversion.

(Second Modification of the First Embodiment)
Next, a second modification of the first embodiment of the present invention will be described. Fig. 10 is a circuit diagram of a resistive DAC used in the product-sum calculator of this modification. Instead of the DAC using weighted resistors shown in Fig. 2, a resistive DAC in which the upper few bits shown in Fig. 10 are configured with equal resistors using a thermometer code and the remaining lower bits are binary-weighted R-2R ladder-type resistors is used, making it possible to reduce power consumption under conditions where the output resistance is constant.

When the output resistance is R ₀ and the number of upper bits configured with equal resistance using a thermometer code is M, the average current I _ave flowing through this resistive DAC can be expressed by the following equation 24.

In other words, when equal resistance using a thermometer code of M=1 is used for the upper 4 bits, the average current can be reduced to about 33% compared to when equal resistance is not used. Therefore, the multiply-accumulate calculator of this modified example can reduce power consumption without reducing the operating speed. In addition, by providing a switch S when all bits are "1" and opening the connection to the ground terminal of the resistor of the least bit, the current flowing through the circuit can be set to zero, which is effective in further reducing power consumption.

[Expected performance of the first embodiment and its modifications]
Next, the performance of the multiply-and-accumulate calculator described above will be described. The multiply-and-accumulate calculator of this embodiment can calculate the amount of calculation per unit of power consumption from the time response and power consumption of the resistive DAC and CDAC. First, the capacitance value is determined. The following formula 25 is established from the relationship between the quantization noise at the resolution N of the CDAC and the thermal noise defined by the capacitance. In the following formula 25, C is the capacitance, V _DD is the full-scale voltage, k is the Boltzmann coefficient, and T is the absolute temperature.

From the above formula 25, the capacitance C can be calculated as the following formula 26.

In neurocomputing, it is said that a resolution N of about 8 bits is sufficient, so if N=8, the absolute temperature T is 300° K, and the full-scale voltage V _DD is 1.0 V, then the capacitance C is 3.45 fF.

Fig. 11 shows an equivalent circuit for calculating the response speed and power consumption. As shown in Fig. 11, when the output resistance is R ₀ , the response time constant τ is expressed by the following formula 27, taking into consideration that two CDACs are required due to the differential configuration and that the capacitance seen from the output resistance is a series capacitance obtained by dividing the capacitance C by two.

Considering that a time of 5τ is required for an 8-bit precision operation, and since the current expressed by the above formula 24 is consumed, the energy E _D required for the operation can be calculated from the following formula 28, with M in the above formula 24 set to 4 or more. Specifically, when V _DD =1.0V, it is 1×10 ⁻¹⁵ (J), and when V _DD =0.5V, it is 0.25×10 ⁻¹⁵ (J).

TOPS/W is used as an index representing the power efficiency of a computing unit. Considering that the operation involves two operations, multiplication and addition, from the following formula 29, the power efficiency is 2000 TOPS/W when V _DD =1.0 V, and 8000 TOPS/W when V _DD =0.5 V.

The power efficiency of current digital 8-bit precision arithmetic units is about 25 TOPs/W, so theoretically it is possible to obtain a power efficiency of about 300 times. Therefore, the multiply-accumulate unit of the present invention has a much higher power efficiency than conventional digital multiply-accumulate units, and can significantly reduce the power consumption of the neuroprocessor.

Second Embodiment
Next, a multiply-accumulate calculator according to a second embodiment of the present invention will be described. The multiply-accumulate calculator of this embodiment is an improvement over the multiply-accumulate calculator of the first embodiment described above in terms of the data input method for the voltage-type DAC and CDAC. Normally, data is input to the multiply-accumulate calculator via a bus. However, the bus has a large load capacity, so the energy consumption during data transmission increases significantly. In addition, the operation speed is slowed down due to the long wiring delay time. For this reason, unless the data input method is devised, it is difficult to fully utilize the low energy and high speed characteristics of the multiply-accumulate calculator of the present invention.

Therefore, in the multiply-and-accumulate calculator of this embodiment, data for the voltage-type DAC and CDAC is input directly from the memory without going through a bus. Figure 12 is a diagram showing a data input circuit to the DAC used in the multiply-and-accumulate calculator of this embodiment. Providing the data input circuit shown in Figure 12 enables low-energy and high-speed data input to the DAC.

Figures 13A and 13B are circuit diagrams of the memory cell shown in Figure 12, and Figure 13C is a circuit diagram of a sense amplifier. Figure 13A is an SRAM memory cell. SRAM memory cells can be manufactured using logic processes, making them easy to integrate. Figure 13B is a non-volatile memory cell. Many non-volatile memory cells have a change in resistance value, and representative examples include MRAM using a magnetic thin film and ReRAM using a phase change, but other memories can also be used. Making the memory non-volatile prevents frequent data transfer and allows it to operate with extremely low energy. In addition, in neurocomputing, the coupling coefficient W is obtained during learning, and the value does not change thereafter, so non-volatile memory is suitable.

Figure 13C shows a sense amplifier circuit. The sense amplifier amplifies the slight input potential difference to the full swing voltage by positive feedback operation. This allows the slight potential difference on the bit line from the memory cell to be amplified to the full swing voltage and input to the DAC. As shown in Figure 12, data input to the memory cell is performed via a bus. For this reason, data input to the memory cell consumes significantly more energy and has a long delay time due to wiring delays, slowing down the operating speed.

Figure 14 is a diagram showing the voltage of the input bus to the memory cell. In the multiply-and-accumulate calculator of this embodiment, the bus uses a differential configuration as shown in Figure 12, has a low amplitude of about 0.1 V as shown in Figure 14, and is amplified to the full swing voltage by the sense amplifier. By using such a configuration, the energy consumption of the bus can be reduced to about 1/10, and the data transmission speed can be improved by several times.

In the multiply-and-accumulate calculator of this embodiment, input data to the voltage output digital-analog conversion unit and the capacitive digital-analog conversion unit is stored in memory cells and is obtained from the output of a sense amplifier that senses the logical state of the memory cells. Input data to the memory is in differential format and transmitted using a low amplitude bus whose amplitude is lower than the power supply voltage, and is converted to a larger amplitude by the sense amplifier to drive the bit lines of the memory cells. This allows digital input to the DAC to be performed at high speed with low energy, thereby realizing a multiply-and-accumulate calculator that operates with low energy and has a high operating speed.

1 Product-accumulator 11 Voltage output digital-to-analog conversion unit 12 Capacitive digital-to-analog conversion unit 13 Analog-to-digital conversion unit

Claims (12)

a voltage output digital-to-analog conversion unit that is composed of a plurality of digital-to-analog converters, receives a vector having a plurality of digital values as elements and a matrix having a plurality of digital values as elements, and converts the digital values of each element of the vector into an analog voltage;
a capacitive digital-analog conversion unit which is composed of a plurality of digital-analog converters, to which each output voltage of the voltage output digital-analog converter row is input, and a capacitance ratio corresponding to the digital value of each element of the matrix is set between input/output terminals and between an output terminal and ground;
an analog-to-digital conversion unit which is composed of a plurality of analog-to-digital converters and receives an analog voltage of a node commonly connected to each output terminal of the capacitive digital-to-analog conversion unit and converts it into a digital value;
having
the capacitive digital-to-analog converter outputs a differential signal;
a differential voltage of a pair of nodes commonly connected to each output end of the capacitive digital-analog conversion unit is input to each analog-to-digital converter of the analog-to-digital conversion unit, and is converted into a digital value;
A multiply-and-accumulate calculator that uses the output of the analog-to-digital converter as an output vector. the matrix having the plurality of digital values as elements is a one-dimensional vector,
2. The multiply-add calculator according to claim 1, wherein each digital-to-analog converter of the voltage output digital-to-analog conversion unit outputs an inner product of a first vector and the one-dimensional vector. 2. The multiply-accumulate calculator according to claim 1, wherein each analog-to-digital converter of the analog-to- digital conversion unit samples the differential voltage of the pair of nodes onto a pair of capacitances, extracts a common-mode signal by shorting terminals of the pair of capacitances, and cancels the common-mode component by subtracting it from the differential voltage of the pair of nodes. The multiply-and-accumulate calculator according to claim 1, wherein the capacitive digital-to-analog conversion unit uses binary-weighted capacitance for the output to set a capacitance ratio corresponding to the digital value of each element between the input/output terminals and between the output terminal and ground. The multiply-and-accumulate calculator according to claim 1, in which weighted resistors are used in each digital-to-analog converter that constitutes the voltage output digital-to-analog conversion unit. The multiply-add calculator according to claim 5, wherein each of the digital-to-analog converters constituting the voltage output digital-to-analog conversion unit has several upper bits configured with equal resistances using a thermometer code, and the remaining lower bits are configured with binary-weighted R-2R ladder-type resistances. 6. The multiply-accumulate calculator according to claim 5 , wherein each of the digital-to-analog converters constituting the voltage output digital-to-analog conversion unit is configured so that a connection to the ground terminal of a resistor of a least significant bit can be opened. The multiply-and-accumulate calculator according to claim 1, wherein the input data of the voltage output digital-to-analog conversion unit and the capacitive digital-to-analog conversion unit is stored in memory cells and is obtained from the output of a sense amplifier that senses the logic state of the memory cells. 9. The multiply-add calculator according to claim 8, wherein input data to the memory cells is in differential format, transmitted using a low-amplitude bus whose amplitude is lower than a power supply voltage, and converted to a larger amplitude by the sense amplifier to drive the bit lines of the memory cells . 9. The multiply-accumulate calculator according to claim 8, wherein the memory cells are SRAMs. 9. The multiply-accumulate calculator according to claim 8 , wherein the memory cells are non-volatile. 12. The multiply-accumulate calculator according to claim 11, wherein the non-volatile memory cell is an MRAM.

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