JP7586965B2 - Light-emitting device - Google Patents

Description

The present invention relates to an object, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, a manufacture, or a composition of matter. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a storage device, a data processing device, a driving method thereof, or a manufacturing method thereof. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof.

The specific configurations proposed for active matrix display devices using light-emitting elements vary depending on the manufacturer, but typically, each pixel is provided with at least a light-emitting element, a transistor (switching transistor) that controls the input of a video signal to the pixel, and a transistor (driving transistor) that controls the value of a current supplied to the light-emitting element.

By making all the transistors in a pixel have the same polarity, it is possible to omit a step of adding an impurity element that imparts one conductivity to a semiconductor film in a manufacturing process of the transistors. Patent Document 1 listed below describes a light-emitting device type display in which pixels are composed of only n-channel transistors.

JP 2003-195810 A

In a light-emitting device, the drain current of a driving transistor is supplied to a light-emitting element, so if there is variation in the threshold voltage of the driving transistor between pixels, the variation is reflected in the luminance of the light-emitting element. Therefore, proposing a pixel configuration that can correct the current value of the driving transistor in anticipation of the variation in threshold voltage is an important issue in improving the image quality of a light-emitting device.

In view of the above technical background, it is an object of the present invention to provide a light-emitting device in which variation in luminance between pixels due to variation in threshold voltage of a driving transistor can be suppressed.

Note that one object of one embodiment of the present invention is to provide a novel semiconductor device or the like. Note that the description of these objects does not preclude the existence of other objects. Note that one embodiment of the present invention is
It is not necessary to solve all of these problems. Problems other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract problems other than these from the description in the specification, drawings, claims, etc.

A light-emitting device according to one embodiment of the present invention includes a transistor having a first gate and a second gate overlapping with each other with a semiconductor film therebetween, a first capacitor that holds a potential difference between one of a source and a drain of the transistor and the first gate, a second capacitor that holds a potential difference between one of the source and a drain of the transistor and the second gate, and a switch that controls electrical continuity between the second gate of the transistor and a wiring;
and a light emitting element to which the drain current of the transistor is supplied.

According to one embodiment of the present invention, it is possible to provide a light-emitting device in which variation in luminance between pixels due to variation in threshold voltage of a transistor is suppressed.

According to one embodiment of the present invention, a novel semiconductor device or the like can be provided. Note that the description of these effects does not preclude the existence of other effects.
It is not necessary for the invention to have all of these effects. Effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc.

FIG. 2 is a diagram showing the configuration of a pixel. FIG. 2 is a diagram showing the configuration of a pixel. FIG. 2 is a diagram showing the configuration of a pixel. FIG. 2 is a diagram showing the configuration of a pixel. 4 is a timing chart showing the operation of a pixel. FIG. FIG. 4 is a timing chart showing the operation of a pixel. FIG. 13 is a graph showing the relationship between Vbg and Vth. FIG. 2 shows a configuration of a pixel portion. FIG. 2 is a diagram showing the configuration of a pixel portion and a selection circuit. Schematic diagram of the monitor circuit. FIG. 2 is a diagram showing the configuration of a pixel. FIG. 2 is a diagram showing the configuration of a pixel. FIG. 2 is a diagram showing the configuration of a pixel. 4 is a timing chart showing the operation of a pixel. FIG. 2 is a diagram showing the configuration of a pixel. FIG. 2 is a diagram showing the configuration of a pixel. 1A to 1C are cross-sectional views illustrating a method for manufacturing a light-emitting device. 1A to 1C are cross-sectional views illustrating a method for manufacturing a light-emitting device. 1A to 1C are cross-sectional views illustrating a method for manufacturing a light-emitting device. FIG. FIG. Electronic devices illustration. FIG. 1A and 1B are diagrams illustrating a configuration of an information processing device using a light-emitting device. FIG. 1 is a top view showing a structure of a transistor. 1 is a cross-sectional view illustrating a structure of a transistor. FIG. 1 is a top view showing a structure of a transistor. 1 is a cross-sectional view illustrating a structure of a transistor. FIG. 1 is a top view showing a structure of a transistor. 1 is a cross-sectional view illustrating a structure of a transistor. FIG. 2 is a diagram showing the configuration of a pixel. 1 is a cross-sectional view illustrating a structure of a transistor. FIG. 2 is a diagram showing the configuration of a pixel. FIG. 2 is a diagram showing the configuration of a pixel. FIG. 2 is a diagram showing the configuration of a pixel. FIG. 2 is a diagram showing the configuration of a pixel. FIG. 2 is a diagram showing the configuration of a pixel. FIG. 2 shows a configuration of a pixel portion. FIG. 2 shows a configuration of a pixel portion. FIG. 13 shows characteristics of a transistor. 1A and 1B are diagrams showing the configuration and operation of a pixel. FIG. 1 is a diagram showing a configuration of a display device. FIG. FIG. 13 shows characteristics of a transistor.

Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

In this specification, a light-emitting device refers to a module in which a panel in which a light-emitting element is formed in each pixel and an IC including a driving circuit or a controller are mounted on the panel.
Furthermore, a light-emitting device according to one embodiment of the present invention includes, in its category, an element substrate corresponding to one form before a light-emitting element is completed in a process of manufacturing the light-emitting device, and the element substrate includes a transistor and a pixel electrode to which a voltage is supplied via the transistor for each of a plurality of pixels.

The source of a transistor means a source region that is a part of the semiconductor film that functions as an active layer, or a source electrode that is electrically connected to the semiconductor film. Similarly, the drain of a transistor means a drain region that is a part of the semiconductor film, or a drain electrode that is electrically connected to the semiconductor film. The gate means a gate electrode.

The source and drain of a transistor are referred to differently depending on the conductivity type of the transistor and the level of the potential applied to each terminal. In general, in an n-channel transistor, a terminal to which a low potential is applied is called a source, and a terminal to which a high potential is applied is called a drain. In addition, in a p-channel transistor, a terminal to which a low potential is applied is called a drain, and a terminal to which a high potential is applied is called a source. In this specification, for convenience,
The connection relationship of a transistor may be explained on the assumption that the source and drain are fixed, but in reality the names of the source and drain are interchangeable according to the above-mentioned potential relationship.

Furthermore, in the present specification, etc., when it is explicitly stated that X and Y are connected, the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected are also considered to be disclosed in the present specification, etc.
Therefore, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence.
Connections other than those shown in the drawings or text are also deemed to be described in the drawings or text.

Here, X and Y are objects (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.).

An example of a case where X and Y are directly connected is a case where an element (e.g., a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display element, a light-emitting element, a load, etc.) that enables an electrical connection between X and Y is not connected between X and Y, and is a case where X and Y are connected without an element (e.g., a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display element, a light-emitting element, a load, etc.) that enables an electrical connection between X and Y.

As an example of a case where X and Y are electrically connected, one or more elements (e.g., a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display element, a light-emitting element, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on/off. That is, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows. Alternatively, the switch has a function of selecting and switching a path through which a current flows. The case where X and Y are electrically connected includes the case where X and Y are directly connected.

An example of a case where X and Y are functionally connected is a circuit that enables the functional connection between X and Y (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.), a signal conversion circuit (a DA conversion circuit, an AD conversion circuit, a gamma correction circuit, etc.), a potential level conversion circuit (a power supply circuit (a step-up circuit, a step-down circuit, etc.), a level shifter circuit that changes the potential level of a signal, etc.)
One or more of the following may be connected between X and Y: a voltage source, a current source, a switching circuit, an amplifier circuit (a circuit that can increase the signal amplitude or the amount of current, such as an operational amplifier, a differential amplifier circuit, a source follower circuit, a buffer circuit, etc.), a signal generating circuit, a memory circuit, a control circuit, etc. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.
When X and Y are functionally connected, there are two cases: when X and Y are directly connected, and when X and Y are directly connected.
and the case where they are electrically connected to each other.

In addition, when it is explicitly stated that X and Y are electrically connected, it is assumed that the present specification discloses the following cases: when X and Y are electrically connected (i.e., when they are connected with another element or circuit between X and Y), when X and Y are functionally connected (i.e., when they are functionally connected with another circuit between X and Y), and when X and Y are directly connected (i.e., when they are connected without another element or circuit between X and Y). In other words, when it is explicitly stated that X and Y are electrically connected, it is assumed that the present specification discloses the same content as when it is explicitly stated only that they are connected.

Example of pixel configuration
1 illustrates an example of a configuration of a pixel 10 in a light-emitting device according to one embodiment of the present invention. The pixel 10 illustrated in FIG. 1 includes a transistor 11, a switch 16, a capacitor 13, a capacitor 18, and a light-emitting element 14.

The light emitting element 14 is a light emitting diode (LED) or an organic light emitting diode (OLED).
The category includes elements whose luminance is controlled by a current or a voltage, such as an organic light emitting diode (OLED). For example, an OLED includes an EL layer and
The light emitting element 14 has at least an anode and a cathode. The EL layer is composed of a single layer or multiple layers provided between the anode and the cathode, and at least a light emitting layer containing a light emitting substance is included among these layers. The EL layer produces electroluminescence by a current supplied when the potential difference between the cathode and the anode becomes equal to or higher than the threshold voltage Vthe of the light emitting element 14. The electroluminescence includes light emission (fluorescence) when returning from a singlet excited state to a ground state and light emission (phosphorescence) when returning from a triplet excited state to a ground state.

In addition, one of the anode and cathode of the light-emitting element 14 functions as a pixel electrode, and the other functions as a common electrode. In Fig. 1, the configuration of the pixel 10 is illustrated in which the anode of the light-emitting element 14 is used as a pixel electrode, and the cathode of the light-emitting element 14 is used as a common electrode.

The transistor 11 has a second gate overlapping the first gate with a semiconductor film interposed therebetween, in addition to a normal gate (first gate). In FIG. 1, the first gate is illustrated as G1, and the second gate is illustrated as G2.

The potential of the first gate of the transistor 11 is controlled in accordance with an image signal supplied from the wiring SL.
It has a function of controlling the supply of the L potential.

The switch 16 can be configured using a single transistor or a plurality of transistors, or the switch 16 may be configured using a capacitor in addition to a single transistor or a plurality of transistors.

The capacitor 13 has a function of holding a potential difference between the second gate of the transistor 11 and one of the source and drain of the transistor 11. The capacitor 18 has a function of holding a potential difference between the first gate of the transistor 11 and one of the source and drain of the transistor 11.

1 illustrates an example in which the transistor 11 is an n-channel type, in which one of the source and the drain of the transistor 11 is electrically connected to the anode of the light-emitting element 14. The other of the source and the drain of the transistor 11 is electrically connected to a wiring VL, and the cathode of the light-emitting element 14 is electrically connected to a wiring CL.
The potential of the wiring VL is higher than the potential of the wiring CL plus the threshold voltage Vthe of the light-emitting element 14 and the threshold voltage Vth of the transistor 11. Thus, when the value of the drain current of the transistor 11 is determined in accordance with an image signal, the drain current is supplied to the light-emitting element 14, causing the light-emitting element 14 to emit light.

When the transistor 11 is a p-channel type, as shown in FIG.
One of the source and drain of the transistor 11 is electrically connected to the cathode of the light-emitting element 14. The other of the source and drain of the transistor 11 is electrically connected to a wiring VL, and the anode of the light-emitting element 14 is electrically connected to a wiring CL. The potential of the wiring CL is higher than the potential of the wiring VL plus the threshold voltage Vthe of the light-emitting element 14 and the threshold voltage Vth of the transistor 11. Similarly to the case where the transistor 11 is an n-channel type, when the transistor 11 is a p-channel type, when the value of the drain current of the transistor 11 is determined according to an image signal, the drain current is supplied to the light-emitting element 14, causing the light-emitting element 14 to emit light.

In one embodiment of the present invention, before determining the value of the drain current of the transistor 11 in accordance with an image signal, the threshold voltage Vth of the transistor 11 is corrected by controlling the voltage Vbg between one of the source and drain of the transistor 11 and the second gate, thereby preventing variation in the threshold voltage Vth of the transistor 11 between pixels 10.

Specifically, the transistor 11 is made normally on by supplying the potential of the wiring BL to the second gate of the transistor 11 via the switch 16. For example, if the transistor 11 is an n-channel type, increasing the voltage Vbg shifts the threshold voltage Vth in the negative direction, and the transistor 11 is made normally on. On the other hand, if the transistor 11 is a p-channel type, decreasing the voltage Vbg shifts the threshold voltage Vth in the positive direction, and the transistor 11 is made normally on.

9 shows the relationship between the voltage Vbg and the threshold voltage Vth when the transistor 11 is an n-channel type. The threshold voltage Vth of the transistor 11 when the voltage Vbg is 0 is set to Vth0. When the voltage Vbg is shifted from 0 in the positive direction to Vbg1, the threshold voltage Vth shifts from Vth0 in the negative direction to Vth1 (Vth1<0).

When the transistor 11 is in a normally-on state, the gate voltage Vgs, which is the potential difference between the first gate of the transistor 11 and one of the source and drain, is kept at a constant value, and the drain current of the transistor 11 is
The configuration is as follows:

With the above configuration, the charge stored in the second gate of the transistor 11 and the capacitor 13 is transferred, and the potential of one of the source and drain of the transistor 11 is shifted. As the potential of one of the source and drain of the transistor 11 is shifted, the voltage Vb
As g changes, the threshold voltage of the transistor 11 shifts in the direction toward normally-off. For example, if the transistor 11 is an n-channel type, the voltage Vbg shifts in the negative direction, and the threshold voltage Vth shifts in the positive direction. Also, if the transistor 11 is a p-channel type, the voltage Vbg shifts in the positive direction, and the threshold voltage Vth shifts in the negative direction.

Finally, when the threshold voltage Vth of the transistor 11 approaches the gate voltage Vgs, which is kept at a constant value, the drain current converges to 0, and the transistor 11 turns off. The threshold voltage Vth of the transistor 11 at this time is Vth2. As shown in Fig. 9, when the voltage Vbg becomes Vbg2, the drain current of the transistor 11, whose gate voltage Vgs is kept at a constant value, converges to 0. As a result, the threshold voltage Vth is corrected to Vth2. The potential difference ΔV0 is held in the capacitance element 13.

In one embodiment of the present invention, the above structure can prevent variation in the threshold voltage of the transistor 11 among the pixels 10 from affecting the value of the drain current of the transistor 11. As a result, variation in luminance among the pixels can be suppressed.

FIG. 1 illustrates a configuration of the pixel 10 in which the threshold voltage Vth of the transistor 11 can be corrected by controlling the voltage Vbg between one of the source or drain of the transistor 11 and the second gate. However, the threshold voltage Vt of the transistor 11 can be corrected by controlling the voltage Vgs between the one of the source or drain of the transistor 11 and the first gate.
It is also possible to make it possible to correct h.

33 shows an example of the configuration of a pixel 10 in which the threshold voltage Vth of a transistor 11 can be corrected by controlling the voltage Vgs. In the pixel 10 shown in FIG. 33, the potential of the second gate of the transistor 11 is controlled in accordance with an image signal supplied from a wiring SL. The switch 16 has a function of controlling the supply of the potential of the wiring BL to the first gate of the transistor 11. The capacitor 13 is connected between the first gate of the transistor 11 and the
The capacitor 18 has a function of holding a potential difference between the second gate of the transistor 11 and one of the source and drain of the transistor 11. In one embodiment of the present invention, with the above structure, before the value of the drain current of the transistor 11 is determined in accordance with an image signal, a voltage Vgs between the first gate and one of the source and drain of the transistor 11 is controlled to correct the threshold voltage Vth of the transistor 11, thereby preventing variation in the threshold voltage Vth of the transistor 11 among pixels 10.

Specific pixel configuration example 1
FIG. 2A shows an example of a specific configuration of the pixel 10 shown in FIG.

A pixel 10 shown in FIG. 2A includes switches 15 to 17 and a capacitor 18 in addition to a transistor 11, a switch 12, a capacitor 13, and a light-emitting element 14.

Specifically, in the pixel 10 shown in FIG. 2A , the wiring SL is electrically connected to a first gate of the transistor 11 through the switch 15. The wiring SL is also electrically connected to a pixel electrode of the light-emitting element 14 through the switches 15 and 12. One of the source and drain of the transistor 11 is electrically connected to the pixel electrode of the light-emitting element 14, and the other of the source and drain is electrically connected to a wiring VL. A second gate of the transistor 11 is electrically connected to a wiring BL through a switch 16. The pixel electrode of the light-emitting element 14 is electrically connected to a wiring IL through a switch 17. One of a pair of electrodes of the capacitor 13 is electrically connected to the second gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light-emitting element 14.
One of a pair of electrodes of the capacitor 18 is electrically connected to the first gate of the transistor 11, and the other is electrically connected to a pixel electrode of the light-emitting element 14.
The common electrode of the pixel 4 is electrically connected to a wiring CL.

Next, FIG. 2(B) shows, as an example, another specific configuration of the pixel 10 shown in FIG. 1.

The pixel 10 shown in FIG. 2B has a different configuration from the pixel 10 shown in FIG. 2A in that the pixel 10 further includes a switch 19 .

Specifically, in the pixel 10 shown in FIG. 2B, the wiring SL is electrically connected to the first gate of the transistor 11 through the switch 15.
The transistor 11 is electrically connected to a pixel electrode of the light-emitting element 14 through the switch 12 and the switch 19. One of the source and drain of the transistor 11 is electrically connected to the pixel electrode of the light-emitting element 14 through the switch 19, and the other of the source and drain is electrically connected to the wiring VL. The second gate of the transistor 11 is electrically connected to the wiring BL through the switch 16. The pixel electrode of the light-emitting element 14 is electrically connected to the wiring IL through the switches 17 and 19. One of a pair of electrodes of the capacitor 13 is electrically connected to the second gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light-emitting element 14 through the switch 19. One of a pair of electrodes of the capacitor 18 is electrically connected to the first gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light-emitting element 14 through the switch 19. The common electrode of the light-emitting element 14 is electrically connected to the wiring CL.

Next, a configuration example of the pixel 10 shown in Fig. 2A in the case where transistors are used as the switches in the pixel 10 will be described. Fig. 3A shows a configuration example of the pixel 10 in the case where transistors are used as the switch 12 and the switches 15 to 17 in the pixel 10 shown in Fig. 2A.

A pixel 10 shown in FIG. 3A includes a transistor 11, a transistor 12t functioning as a switch 12, transistors 15t to 17t functioning as switches 15 to 17, respectively, a capacitor 13, a capacitor 18, and a light-emitting element 14.

Specifically, the transistor 15t has a gate electrically connected to the wiring GLa, one of a source and a drain electrically connected to the wiring SL, and the other of the source and the drain electrically connected to the first gate of the transistor 11. The transistor 12t has a gate electrically connected to the wiring GLb, one of a source and a drain electrically connected to the pixel electrode of the light-emitting element 14, and the other of the source and the drain electrically connected to the first gate of the transistor 11.
The transistor 11 has a source and a drain electrically connected to a pixel electrode of the light-emitting element 14, and the other of the source and drain electrically connected to a wiring VL. The transistor 16t has a gate electrically connected to a wiring GLb, one of a source and a drain electrically connected to a wiring BL, and the other of the source and drain electrically connected to a second gate of the transistor 11. The transistor 17t has a gate electrically connected to a wiring GLd, one of a source and a drain electrically connected to a wiring IL, and the other of the source and drain electrically connected to the pixel electrode of the light-emitting element 14.

One of a pair of electrodes of the capacitor 13 is electrically connected to the second gate of the transistor 11, and the other is electrically connected to a pixel electrode of the light-emitting element 14. One of a pair of electrodes of the capacitor 18 is electrically connected to the first gate of the transistor 11, and the other is electrically connected to a pixel electrode of the light-emitting element 14. A common electrode of the light-emitting element 14 is electrically connected to the wiring CL.

Next, a configuration example of the pixel 10 shown in Fig. 2B in the case where a transistor is used as each switch in the pixel 10 will be described. Fig. 3B shows a configuration example of the pixel 10 in the case where a transistor is used as each of the switch 12, the switches 15 to 17, and the switch 19 in the pixel 10 shown in Fig. 2B.

A pixel 10 shown in Figure 3 (B) includes a transistor 11, a transistor 12t functioning as a switch 12, transistors 15t to 17t functioning as switches 15 to 17, respectively, a transistor 19t functioning as a switch 19, a capacitor 13, a capacitor 18, and a light-emitting element 14.

Specifically, the transistor 15t has a gate electrically connected to a wiring GLa, one of its source and drain electrically connected to a wiring SL, and the other of its source and drain electrically connected to a first gate of the transistor 11. The transistor 12t has a gate electrically connected to a wiring GLb, one of its source and drain electrically connected to one of the source and drain of the transistor 19t, and the other of its source and drain electrically connected to a first gate of the transistor 11. The transistor 11 has one of its source and drain electrically connected to one of the source and drain of the transistor 19t, and the other of its source and drain electrically connected to a wiring VL. The transistor 16t has a gate electrically connected to a wiring GLb, one of its source and drain electrically connected to a wiring BL,
The other of the source and the drain is electrically connected to a second gate of the transistor 11. The gate of the transistor 17t is electrically connected to a wiring GLd, one of the source and the drain is electrically connected to a wiring IL, and the other of the source and the drain is electrically connected to one of the source and the drain of the transistor 19t.
The other of the source and drain is electrically connected to a pixel electrode of the light emitting element 14 .

One of a pair of electrodes of the capacitor 13 is electrically connected to the second gate of the transistor 11, and the other is electrically connected to one of the source and drain of the transistor 19t.
and the other is electrically connected to one of the source and drain of the transistor 19t. The common electrode of the light-emitting element 14 is electrically connected to the wiring CL.

Next, the switch 12 and the switches 15 to 17 of the pixel 10 shown in FIG.
FIG. 4A shows another example of the configuration of the pixel 10 in the case where transistors are used as the drain and drain electrodes.

The pixel 10 shown in FIG. 4A is different from the pixel 1 shown in FIG. 3B in that one of the source and the drain of the transistor 16t is electrically connected to the wiring VL instead of the wiring BL.
The configuration is different from 0.

Next, the switch 12 and the switches 15 to 17 of the pixel 10 shown in FIG.
FIG. 4B shows another example of the configuration of the pixel 10 in which transistors are used as the gate electrode 14 and the switch 19.

The pixel 10 illustrated in FIG. 4B has a different configuration from the pixel 10 illustrated in FIG. 3B in that a gate of a transistor 17t is electrically connected to a wiring GLa instead of a wiring GLd.

<Specific pixel operation example 1>
Next, the operation of a pixel of a light-emitting device according to one embodiment of the present invention will be described using the pixel 10 illustrated in FIG. 3B as an example.

FIG. 5 is a timing chart of potentials input to the wirings GLa to GLd and
5 is a timing chart of the potential of the image signal Vdata input to the pixel 10 shown in FIG.
6 and 7 are schematic diagrams showing the operation of the pixel 10 in each period. However, in order to easily show the operation of the pixel 10, transistors other than the transistor 11 are illustrated as switches in FIG. 6 and FIG. 7.

First, in a period t1, a low-level potential is applied to the wiring GLa, a high-level potential is applied to the wiring GLb, a low-level potential is applied to the wiring GLc, and a high-level potential is applied to the wiring GLd. Therefore, as shown in FIG 6A, the transistors 12t, 16t, and 17t are turned on, and the transistors 15t and 19t are turned off.

A potential Vano is applied to the wiring VL, a potential V0 is applied to the wiring BL, a potential V1 is applied to the wiring IL, and a potential Vcat is applied to the wiring CL electrically connected to the common electrode of the light-emitting element 14. Thus, a potential V1 is applied to the first gate (denoted as node A) of the transistor 11, a potential V0 is applied to the second gate (denoted as node B) of the transistor 11, and a potential V1 is applied to one of the source and drain (denoted as node C) of the transistor 11.
is given.

The potential Vano is a potential Vcat multiplied by the threshold voltage Vthe of the light emitting element 14 and the potential Vt of the transistor 11.
It is desirable to set the potential higher than the sum of the threshold voltage Vth of the potential V0
is set to a value at node C to shift the threshold voltage Vth of the transistor 11 in the negative direction.
Specifically, as shown in FIG.
When g is 0, the threshold voltage Vth of the transistor 11 is Vth0.
The voltage Vbg corresponding to the potential difference between node A and node C is set to Vbg1. As a result, in period t1, the threshold voltage Vth of transistor 11 becomes Vth1. With the above configuration, transistor 11 is normally on, so that even if the potential difference between node A and node C, i.e., the gate voltage of transistor 11, is zero, transistor 11 can be turned on.

In addition, when the transistor 11 is a p-channel type, it is desirable that the potential V0 is sufficiently low with respect to the node C so as to shift the threshold voltage Vth of the transistor 11 in the positive direction. With the above configuration, the transistor 11 is normally on, so that the transistor 11 can be turned on even if the potential difference between the nodes A and C, i.e., the gate voltage of the transistor 11, is zero.

Next, in a period t2, a low-level potential is applied to the wiring GLa, a high-level potential is applied to the wiring GLb, a low-level potential is applied to the wiring GLc, and a low-level potential is applied to the wiring GLd. Therefore, as shown in FIG. 6B, the transistors 12t and 16t are turned on, and the transistors 15t, 17t, and 19t are turned off.

A potential Vano is applied to the wiring VL, and a potential V0 is applied to the wiring BL. Thus, the state in which the potential V0 is applied to the node B is maintained, and at the start of the period t2, the threshold voltage Vth of the transistor 11 remains shifted in the negative direction from Vth1, so that the transistor 11 is on. During the period t2, the current path between the wiring VL and the wiring IL is blocked by the switch 17, so that the potentials of the nodes A and C start to rise due to the drain current of the transistor 11. When the potential of the node C rises, the potential of the node B
The voltage Vbg corresponding to the potential difference between node A and node B becomes lower, and the threshold voltage Vt
h shifts in the positive direction. Finally, the threshold voltage Vt
When h approaches 0, the transistor 11 turns off. When the threshold voltage Vth of the transistor 11 is 0, the potential difference between the node B and the node C is V0-V2.

That is, when the potential difference between nodes B and C is V0-V2, the threshold voltage Vth of transistor 11 is corrected to 0 so that the drain current converges to 0 for a gate voltage of 0. The potential difference V0-V2 between nodes B and C is applied to capacitive element 13.

Next, in a period t3, a high-level potential is applied to the wiring GLa, a low-level potential is applied to the wiring GLb, a low-level potential is applied to the wiring GLc, and a high-level potential is applied to the wiring GLd. Therefore, as shown in FIG. 7A, the transistors 15t and 17t are turned on, and the transistors 12t, 16t, and 19t are turned off.

The wiring VL is connected to a potential Vano, and the wiring SL is connected to a potential Vdata
The wiring IL is applied with a potential V1. Since the node B is in a floating state, the potential of the node C changes from the potential V2 to the potential V1, so that the capacitance element 13
As a result, the potential of node B changes from V0 to V0+V1-V2.
Since a potential difference V0-V2 is held at node A, the threshold voltage Vth of the transistor 11 is maintained at 0. In addition, a potential Vdata is applied to node A, and the gate voltage of the transistor 11 becomes Vdata-V1.

Next, in a period t4, a low-level potential is applied to the wiring GLa, a low-level potential is applied to the wiring GLb, a high-level potential is applied to the wiring GLc, and a low-level potential is applied to the wiring GLd. Therefore, as shown in FIG. 7B, the transistor 19t is turned on, and the transistors 12t, 15t, 16t, and 17t are turned off.

In addition, a potential Vano is applied to the wiring VL, and a potential Vcat is applied to the wiring CL electrically connected to the common electrode of the light-emitting element 14.
When the potential of node C changes to V3, node A becomes Vd
The potential of the node A is V0-V2+V3, and the potential of the node B is V0-V2+V3. Even if the potentials of the nodes A, B, and C change, the potential difference V0-V2 is held in the capacitor 13.
The capacitance element 18 holds a potential difference Vdata-V1.
A drain current flows between the gate and drain electrodes L, the value of which corresponds to the gate voltage of the transistor 11. The luminance of the light-emitting element 14 is determined according to the value of the drain current.

In the light-emitting device having the pixel 10 shown in FIG. 3B, the other of the source and the drain of the transistor 11 is electrically separated from the second gate of the transistor 11.
The potentials of the transistors 11 and 12 can be controlled individually. Therefore, when the transistor 11 is normally on, that is, when the original threshold voltage Vth0 of the transistor 11 has a negative value, charge can be accumulated in the capacitor 13 until the potential of one of the source and drain of the transistor 11 becomes higher than the potential V0 of the second gate in the period t2. Therefore, in the light-emitting device according to one embodiment of the present invention, even if the transistor 11 is normally on, the threshold voltage Vth can be corrected to 0 in the period t2 so that the drain current converges to 0 for a gate voltage of 0.

Therefore, the other of the source and drain of the transistor 11 and the second
The gates of the pixels 1 and 2 shown in FIGS. 3A, 3B, and 4B are electrically isolated from each other.
In a light-emitting device having the above-mentioned GaN-type GaN layer, even if the transistor 11 is normally on, for example, when an oxide semiconductor is used for the semiconductor film of the transistor 11, display unevenness can be reduced and high-quality display can be performed.

Note that, although examples of the circuit configuration are shown in FIG. 2A and FIG. 2B, one embodiment of the present invention is not limited thereto. For example, the switch can be arranged in various locations. For example, in the case of FIG. 6A, the configuration is as shown in FIG. 36A, in the case of FIG. 6B, the configuration is as shown in FIG. 36B, in the case of FIG. 7A, the configuration is as shown in FIG. 37A, and in the case of FIG. 7B, the configuration is as shown in FIG. 37B. In each case, the switch may be arranged in an appropriate location so as to achieve such a configuration.

The above is the correction of the threshold voltage in the pixel 10 (hereinafter referred to as internal correction).
Next, the operation of the pixel 10 will be described in a case where, in addition to the internal correction, the luminance variation among the pixels 10 caused by the variation in the threshold voltage is suppressed by the correction of the image signal (hereinafter, referred to as external correction).

8 shows a timing chart of potentials input to the wirings GLa to GLd and a timing chart of the potential of the image signal Vdata input to the wiring SL when external correction is performed in addition to internal correction, taking the pixel 10 shown in FIG 3B as an example. Note that the timing chart shown in FIG 8 illustrates a case where all the transistors included in the pixel 10 shown in FIG 3B are n-channel transistors.

First, from period t1 to period t4, the pixel 10 operates in accordance with the above description, similarly to the timing chart shown in FIG.

Next, in a period t5, a low-level potential is applied to the wiring GLa, a low-level potential is applied to the wiring GLb, a low-level potential is applied to the wiring GLc, and a high-level potential is applied to the wiring GLd. Therefore, the transistor 17t is turned on, and the transistor 12
t, transistor 15t, transistor 16t, and transistor 19t are turned off.

A potential Vano is applied to the wiring VL, and a potential V1 is applied to the wiring IL.
Furthermore, the wiring IL is electrically connected to a monitor circuit.

By the above operation, the drain current of the transistor 11 is
The drain current flowing through the wiring IL is supplied to a monitor circuit via the wiring IL. The monitor circuit generates a signal including a value of the drain current as information, using the drain current flowing through the wiring IL. In the light-emitting device according to one embodiment of the present invention, the potential V
The value of data can be corrected.

It is not necessary that the external correction operation performed in the period t5 is always performed after the period t4. For example, in a light emitting device, the operation in the period t5 may be performed after the operations in the periods t1 to t4 are repeated a number of times. Also, after the operation in the period t5 is performed in one row of pixels 10, an image signal corresponding to the minimum gradation value 0 may be written to the row of pixels 10 in which the operation was performed, thereby putting the light emitting elements 14 into a non-emitting state, and then the operation in the period t5 may be performed in the pixels 10 in the next row.

It should be noted that even when external correction is performed without internal correction, it is possible to correct not only the variation in the threshold voltage of the transistor 11 present between the pixels 10, but also the variation in the electrical characteristics of the transistor 11 other than the threshold voltage, such as mobility. However, when internal correction is performed in addition to external correction, the correction of the negative or positive shift in the threshold voltage is performed by internal correction. Therefore, external correction only needs to correct the variation in the electrical characteristics of the transistor 11 other than the threshold voltage, such as mobility. Therefore, when internal correction is performed in addition to external correction, the amplitude of the potential of the image signal after correction is
This makes it possible to prevent a situation in which the potential difference of the image signal between gradation values becomes large due to the potential amplitude of the image signal being too large, making it difficult to express changes in luminance in an image with a smooth gradation, and thus prevents deterioration in image quality.

In the case of the pixel 10 shown in FIG. 3A, the wiring GLa and the wiring GL shown in FIG.
3A, in order to prevent the drain current of the transistor 11 from flowing to the light-emitting element 14, the threshold voltage Vthe of the light-emitting element 14 and the threshold voltage Vth of the transistor 15t are set to Vca, Vb, and Vc in the period t2.
It is desirable to make it lower than the potential added to t.

In the case of the pixel 10 shown in FIG. 4A, the wiring GLa and the wiring GL shown in FIG.
The operation can be performed in the same manner according to the timing chart of potentials applied to the wirings GLb, GLc, GLd, and SL.

In the case of the pixel 10 shown in FIG. 4B, the wiring GLa and the wiring GL shown in FIG.
The operation can be performed in the same manner according to a timing chart of potentials applied to the wirings GLb, GLc, and SL.

For example, when external correction is not performed, the wiring IL may be connected to the wiring CL. Alternatively, the wiring IL and the wiring CL may be combined into one wiring, and the wiring IL may be omitted. This allows the number of wirings to be reduced. As an example, FIG. 38A shows an example in which the wiring IL is omitted in FIG. 2A. Similarly, FIG. 38B shows an example in which the present invention is applied to FIG. 2B. The same can be applied to other drawings.

Example of pixel section and selection circuit configuration
Next, FIG. 10 illustrates an example of a structure of a pixel portion of a light-emitting device according to one embodiment of the present invention.
10, the pixel section 40 has a plurality of pixels 10 arranged in a matrix. The pixel section 40 includes a wiring GL, a wiring SL, a wiring VL, a wiring BL, a wiring IL, and a wiring CL.
Each of the pixels 10 is electrically connected to at least one of the wirings GL, at least one of the wirings SL, at least one of the wirings VL, at least one of the wirings BL, at least one of the wirings IL, and a wiring CL.

The type and number of the wirings can be determined depending on the configuration, number and arrangement of the pixels 10. Specifically, in the case of the pixel section 40 shown in FIG. 10, the pixels 10 in x columns and y rows are electrically connected in a matrix shape.
This illustrates an example in which a plurality of wirings SL indicated by wirings SL1 to SLx, a plurality of wirings VL indicated by wirings VL1 to VLx, a plurality of wirings BL indicated by wirings BL1 to BLx, a plurality of wirings IL indicated by wirings IL1 to ILx, and one wiring CL are arranged within a pixel portion 40.

Each wiring GL shown in FIG. 10 includes all or a plurality of wirings GLa, GLb, GLc, and GLd.

In addition, as shown in Fig. 10, when the pixels 10 are connected in a matrix, for example, when the operation of Fig. 6(A), Fig. 6(B), Fig. 7(B), etc. is performed in one row, for example, the operation of Fig. 7(A) can be performed in another row.
6B can be executed for a sufficiently long period of time, so that the correction can be performed with high accuracy.

Note that, when the operations of FIG. 6A, FIG. 6B, etc. and the operation of FIG. 7A, etc. are not performed simultaneously in different rows, for example, the wiring BL may be connected to the wiring SL. Alternatively, for example, the wiring BL and the wiring SL may be combined into one wiring, and the wiring BL may be omitted. This makes it possible to reduce the number of wirings. As an example, FIG. 39A shows a case where the wiring BL is omitted in FIG. 2A. Similarly, an example of the case where the wiring BL is applied to FIG. 2B is as follows:
This is shown in Fig. 39(B). The same can be applied to other figures.

In addition, in FIG. 7A and the like, during the period in which the potential Vdata of the image signal is input, the operation of applying the potential difference V0-V2 between the nodes B and C to the capacitor 13 as shown in FIG. 6B is not performed, so that in FIG. 7A and the like, the potential Vdata of the image signal can be input to the pixels in a dot sequential manner. An example of this case is shown in FIG. 40. The switches 60A, 60B, 60C, and the like are turned on in sequence while being controlled by the circuit 61. As a result, dot sequential driving can be performed. Here, the circuit 61 has a function of being able to output a waveform that is shifted one by one. For example, the circuit 61 has a function as a shift register. Therefore, the switches 60A, 60B, 6
0C, the circuit 61 can also be said to have a function as a source line driver circuit.

Alternatively, as another example, among the multiple wirings SL indicated by the wirings SL1 to SLx, one of the multiple wirings may be selected to input the potential Vdata of the image signal. For example, the wirings SL1 and SL2 may be selected by the switches 62A and 62B, and the wirings SL3 and SL4 may be selected by the switches 62C and 62D.
An example of the case where the wiring 63A is selected from the wiring 63B and the wiring 63C is selected from the wiring 63D is shown in Fig. 41. In Fig. 41, when the wiring 63A is selected, the switches 62A and 62C are turned on, and when the wiring 63B is selected, the switches 62B and 62D are turned on. Here, an example is shown in which one of two wirings SL is selected, but one embodiment of the present invention is not limited to this. One of more wirings SL may be selected.

11 shows an example of a connection configuration between a pixel portion 40 and a selection circuit 41 of a light-emitting device having a function of performing external correction. The selection circuit 41 has a function of selecting either a wiring 42 to which a potential V1 is applied or a connection terminal TER with a monitor circuit. The selection circuit 41 can bring the wiring IL into electrical continuity with either the selected wiring 42 or the connection terminal TER.

Specifically, the selection circuit 41 illustrated in FIG. 11 includes a switch 43 that controls the supply of the potential V1 of the wiring 42 to one wiring IL, and a switch 44 that controls electrical continuity between the one wiring IL and a connection terminal TER.

<Monitor circuit configuration example>
Next, a configuration example of the monitor circuit 45 is shown in FIG. 12. The monitor circuit 45 shown in FIG.
The circuit includes an operational amplifier 46 , a capacitance element 47 , and a switch 48 .

One of a pair of electrodes of the capacitor 47 is connected to the inverting input terminal (−) of the operational amplifier 46, and the other of the pair of electrodes of the capacitor 47 is connected to the output terminal of the operational amplifier 46. The switch 48 has a function of discharging charges stored in the capacitor 47, and specifically, has a function of controlling the electrical conduction state between the pair of electrodes of the capacitor 47. A non-inverting input terminal (+) of the operational amplifier 46 is connected to a wiring 49, and a potential V1 is supplied to the wiring 49.

In one embodiment of the present invention, in order to perform internal correction, the monitor circuit 45 functions as a voltage follower when the potential V1 is supplied to the wiring IL of the pixel 10. Specifically, by turning on the switch 48, the potential V1 supplied to the wiring 49 can be supplied to the wiring IL through the monitor circuit 45.

In addition, when a current is extracted from the pixel 10 through the wiring IL in order to perform external correction, the monitor circuit 45 is first made to function as a voltage follower to apply a potential V
After supplying the current from the pixel 10, the monitor circuit 45 is made to function as an integrating circuit to convert the current taken out from the pixel 10 into a voltage.
The potential V1 supplied to the switch 48 is supplied to the wiring IL via the monitor circuit 45, and then the switch 48 is turned off. When the drain current extracted from the pixel 10 is supplied to the wiring TER while the switch 48 is in the off state, charge is accumulated in the capacitor 47, and a voltage is generated between a pair of electrodes of the capacitor 47. Since the voltage is proportional to the total amount of the drain current supplied to the wiring TER, a potential corresponding to the total amount of the drain current within a predetermined period is applied to the wiring OUT connected to the output terminal of the operational amplifier 46.

Specific pixel configuration example 2
FIG. 13A shows an example of a specific configuration of the pixel 10 shown in FIG.

A pixel 10 shown in FIG. 13A includes switches 15 to 17 and a capacitor 18 in addition to a transistor 11, a capacitor 13, and a light-emitting element 14.

Specifically, in the pixel 10 shown in FIG. 13A, the wiring SL is electrically connected to the first gate of the transistor 11 through the switch 15. One of the source and drain of the transistor 11 is electrically connected to the pixel electrode of the light-emitting element 14, and the other of the source and drain is electrically connected to the wiring VL. The second gate of the transistor 11 is electrically connected to the wiring BL through the switch 16. The pixel electrode of the light-emitting element 14 is electrically connected to the wiring IL through the switch 17. One of a pair of electrodes of the capacitor 13 is electrically connected to the second gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light-emitting element 14. One of a pair of electrodes of the capacitor 18 is electrically connected to the first gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light-emitting element 14. The common electrode of the light-emitting element 14 is electrically connected to the wiring CL.

Next, FIG. 13B shows, as an example, another specific configuration of the pixel 10 shown in FIG.

The pixel 10 shown in FIG. 13B is similar to the pixel 10 shown in FIG. 13A in that it further includes a switch 19.
1. The pixel 10 shown in FIG.

Specifically, in the pixel 10 shown in FIG. 13B, the wiring SL is electrically connected to the first gate of the transistor 11 through the switch 15. One of the source and drain of the transistor 11 is electrically connected to a pixel electrode of the light-emitting element 14 through the switch 19, and the other of the source and drain is electrically connected to the wiring VL. A second gate of the transistor 11 is electrically connected to the wiring BL through the switch 16. A pixel electrode of the light-emitting element 14 is electrically connected to the wiring IL through the switches 17 and 19. One of a pair of electrodes of the capacitor 13 is the second gate of the transistor 11.
One of a pair of electrodes of the capacitor 18 is electrically connected to the first gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light-emitting element 14 via the switch 19.
The common electrode of the light-emitting element 14 is electrically connected to the pixel electrode of the light-emitting element 14. The common electrode of the light-emitting element 14 is electrically connected to the wiring CL.

Next, a configuration example of the pixel 10 shown in FIG. 13A in the case where transistors are used as the switches is described. A configuration example of the pixel 10 shown in FIG. 13A in the case where transistors are used as the switches 15 to 17 is described.
As shown in A).

A pixel 10 shown in FIG. 14A includes a transistor 11, transistors 15t to 17t each functioning as a switch 15 to a switch 17, and a capacitor 1
3, a capacitance element 18, and a light-emitting element 14.

Specifically, the transistor 15t has a gate electrically connected to the wiring GLa, one of a source and a drain electrically connected to the wiring SL, and the other of the source and the drain electrically connected to the first gate of the transistor 11.
The other of the source and drain is electrically connected to the pixel electrode of the light-emitting element 14 and to the wiring VL. The gate of the transistor 16t is electrically connected to the wiring GLb, one of the source and drain is electrically connected to the wiring BL, and the other of the source and drain is electrically connected to the second gate of the transistor 11. The gate of the transistor 17t is electrically connected to the wiring GLd, one of the source and drain is electrically connected to the wiring IL, and the other of the source and drain is electrically connected to the pixel electrode of the light-emitting element 14.

One of a pair of electrodes of the capacitor 13 is electrically connected to the second gate of the transistor 11, and the other is electrically connected to a pixel electrode of the light-emitting element 14. One of a pair of electrodes of the capacitor 18 is electrically connected to the first gate of the transistor 11, and the other is electrically connected to a pixel electrode of the light-emitting element 14. A common electrode of the light-emitting element 14 is electrically connected to the wiring CL.

Next, a configuration example of the pixel 10 shown in FIG. 13B in the case where transistors are used as the switches is described.
A configuration example is shown in FIG.

The pixel 10 shown in FIG. 14B includes a transistor 11, transistors 15t to 17t each functioning as a switch 15 to a switch 17, and a switch 1
The pixel includes a transistor 19t having the functions of the pixel 9, a capacitor 13, a capacitor 18, and a light-emitting element 14.

Specifically, the transistor 15t has a gate electrically connected to a wiring GLa, one of its source and drain electrically connected to a wiring SL, and the other of its source and drain electrically connected to a first gate of the transistor 11. The transistor 11 has one of its source and drain electrically connected to one of the source and drain of the transistor 19t, and the other of its source and drain electrically connected to a wiring VL. The transistor 16t has a gate electrically connected to a wiring GLb, one of its source and drain electrically connected to a wiring BL, and the other of its source and drain electrically connected to a second gate of the transistor 11. The transistor 17t has a gate electrically connected to a wiring GL
In the pixel 19d, one of the source and the drain is electrically connected to the wiring IL, and the other of the source and the drain is electrically connected to one of the source and the drain of a transistor 19t. The transistor 19t has a gate electrically connected to the wiring GLc and the other of the source and the drain electrically connected to a pixel electrode of the light-emitting element 14.

One of a pair of electrodes of the capacitor 13 is electrically connected to the second gate of the transistor 11, and the other is electrically connected to one of the source and drain of the transistor 19t.
and the other is electrically connected to one of the source and drain of the transistor 19t. The common electrode of the light-emitting element 14 is electrically connected to the wiring CL.

Next, FIG. 15A shows another example of the configuration of the pixel 10 in the case where transistors are used as the switches 15 to 17 of the pixel 10 shown in FIG. 13B.

The pixel 10 illustrated in FIG. 15A has a different configuration from the pixel 10 illustrated in FIG. 14B in that one of a source and a drain of a transistor 16t is electrically connected to a wiring VL rather than to a wiring BL.

Next, the switches 15 to 17 and the switch 1 of the pixel 10 shown in FIG.
FIG. 15B shows another example of the configuration of the pixel 10 when transistors 9 and 10 are used.
As shown in.

In the pixel 10 shown in FIG. 15B, the gate of the transistor 17t is connected to the wiring
The pixel 10 in FIG. 14B has a different configuration from the pixel 10 in FIG. 14B in that the pixel 10 is electrically connected to the wiring GLa.

<Specific pixel operation example 2>
Next, the operation of a pixel of a light-emitting device according to one embodiment of the present invention will be described using the pixel 10 illustrated in FIG. 14B as an example.

FIG. 16 is a timing chart of potentials input to the wirings GLa to GLd and
1 and a timing chart of the potential of the image signal Vdata input to the input terminal L.
The timing chart shown in FIG. 6 illustrates a case where all the transistors included in the pixel 10 shown in FIG. 14B are n-channel transistors.

First, in a period t1, a high-level potential is applied to the wiring GLa, a high-level potential is applied to the wiring GLb, a low-level potential is applied to the wiring GLc, and a high-level potential is applied to the wiring GLd, so that the transistors 15t, 16t, and 17t are turned on and the transistor 19t is turned off.

A potential V4 is applied to the wiring SL, a potential Vano is applied to the wiring VL, a potential V0 is applied to the wiring BL, a potential V1 is applied to the wiring IL, and a potential Vcat is applied to the wiring CL electrically connected to the common electrode of the light-emitting element 14.
A potential V4 is applied to the second gate of the transistor 11 (denoted as node B)
A potential V0 is applied to one of the source and drain of the transistor 11 (denoted as a node C), and a potential V1 is applied to one of the source and drain of the transistor 11 (denoted as a node C).

The potential Vano is a potential Vcat multiplied by the threshold voltage Vthe of the light emitting element 14 and the potential Vt of the transistor 11.
It is desirable to set the potential higher than the sum of the threshold voltage Vth of the potential V0
is set to a value at node C to shift the threshold voltage Vth of the transistor 11 in the negative direction.
Specifically, as shown in FIG.
If the threshold voltage Vth of transistor 11 is Vth0 when g is 0, then in period t1, the voltage Vbg corresponding to the potential difference between node B and node C is set to Vbg1, thereby setting the threshold voltage Vth of transistor 11 to Vth1. With the above configuration, transistor 11 is normally on, so that even if the potential difference between node A and node C, i.e., the gate voltage of transistor 11, is V4-V1, transistor 11 can be turned on.

In addition, when the transistor 11 is a p-channel type, it is desirable that the potential V0 is sufficiently low with respect to the node C so as to shift the threshold voltage Vth of the transistor 11 in the positive direction. With the above configuration, the transistor 11 is normally on, so that the transistor 11 can be turned on even if the potential difference between the nodes A and C, that is, the gate voltage of the transistor 11, is V4-V1.

Next, in a period t2, a low-level potential is applied to the wiring GLa, a high-level potential is applied to the wiring GLb, a low-level potential is applied to the wiring GLc, and a low-level potential is applied to the wiring GLd. Therefore, the transistor 16t is turned on, and the transistor 15
t, transistor 17t, and transistor 19t are turned off.

A potential Vano is applied to the wiring VL, and a potential V0 is applied to the wiring BL. Thus, the state in which the potential V0 is applied to the node B is maintained, and at the start of the period t2, the threshold voltage Vth of the transistor 11 remains shifted in the negative direction from Vth1, so that the transistor 11 is on. During the period t2, the current path between the wiring VL and the wiring IL is blocked by the switch 17, so that the potentials of the nodes A and C start to rise due to the drain current of the transistor 11. When the potential of the node C rises, the potential of the node B
The voltage Vbg corresponding to the potential difference between node A and node B becomes lower, and the threshold voltage Vt
h shifts in the positive direction. Finally, the threshold voltage Vt
The transistor 11 turns off when h approaches the gate voltage V4-V1 of the transistor 11. When the threshold voltage Vth of the transistor 11 is V4-V1, the potential difference between the nodes B and C is V0-V2.

That is, when the potential difference between the nodes B and C is V0-V2, the transistor 11 has its threshold voltage Vt
The potential difference V0-V2 between the nodes B and C is applied to the capacitive element 13.

Next, in a period t3, a high-level potential is applied to the wiring GLa, a low-level potential is applied to the wiring GLb, a low-level potential is applied to the wiring GLc, and a high-level potential is applied to the wiring GLd. Therefore, the transistors 15t and 17t are turned on, and the transistors 16t and 19t are turned off.

The wiring VL is connected to a potential Vano, and the wiring SL is connected to a potential Vdata
The wiring IL is applied with a potential V1. Since the node B is in a floating state, the potential of the node C changes from the potential V2 to the potential V1, so that the capacitance element 13
As a result, the potential of node B changes from V0 to V0+V1-V2.
Since the potential difference V0-V2 is held in the
The potential Vdata is applied to the node A, and the potential Vdata is maintained at −V1.
The gate voltage of 1 is Vdata-V1.

Next, in a period t4, a low-level potential is applied to the wiring GLa, a low-level potential is applied to the wiring GLb, a high-level potential is applied to the wiring GLc, and a low-level potential is applied to the wiring GLd. Therefore, the transistor 19t is turned on, and the transistor 15
t, transistor 16t, and transistor 17t are turned off.

In addition, a potential Vano is applied to the wiring VL, and a potential Vcat is applied to the wiring CL electrically connected to the common electrode of the light-emitting element 14.
When the potential of node C changes to V3, node A becomes Vd
The potential of the node A is V0-V2+V3, and the potential of the node B is V0-V2+V3. Even if the potentials of the nodes A, B, and C change, the potential difference V0-V2 is held in the capacitor 13.
The capacitance element 18 holds a potential difference Vdata-V1.
A drain current flows between the gate and drain electrodes L, the value of which corresponds to the gate voltage of the transistor 11. The luminance of the light-emitting element 14 is determined according to the value of the drain current.

14B, the other of the source and drain of the transistor 11 and the second gate of the transistor 11 are electrically separated, and therefore the potentials of the source and drain of the transistor 11 and the second gate of the transistor 11 can be controlled individually. Therefore, when the transistor 11 is normally on, that is, when the original threshold voltage Vth0 of the transistor 11 has a negative value, charge can be accumulated in the capacitor 13 until the potential of one of the source and drain of the transistor 11 becomes higher than the potential V0 of the second gate in the period t2. Therefore, in the light-emitting device according to one embodiment of the present invention, even if the transistor 11 is normally on, the threshold voltage Vth can be corrected to V4-V1 so that the drain current converges to 0 with respect to the gate voltage V4-V1 in the period t2.

Therefore, the other of the source and drain of the transistor 11 and the second
In a light-emitting device having the pixel 10 shown in FIGS. 14A, 14B, and 15B in which the gate of the transistor 11 is electrically separated from the gate of the transistor 11, for example, when an oxide semiconductor is used for the semiconductor film of the transistor 11, even if the transistor 11 is normally on, display unevenness can be reduced and high-quality display can be performed.

The above corresponds to an example of the operation of the pixel 10 including the internal correction. Next, in addition to the internal correction,
The operation of the pixel 10 in the case where the luminance variation among the pixels 10 caused by the variation in the threshold voltage is suppressed by external correction will be described.

Taking the pixel 10 shown in Figure 14 (B) as an example, when external correction is performed in addition to internal correction, the pixel 10 operates in accordance with the above-mentioned description from period t1 to period t4, similar to the timing chart shown in Figure 16.

Next, in a period t5 after the period t4, a low-level potential is applied to the wiring GLa.
A low-level potential is applied to the wiring GLb, a low-level potential is applied to the wiring GLc, and a low-level potential is applied to the wiring G
A high-level potential is applied to Ld, so that the transistor 17t is turned on and the transistors 15t, 16t, and 19t are turned off.

A potential Vano is applied to the wiring VL, and a potential V1 is applied to the wiring IL.
Furthermore, the wiring IL is electrically connected to a monitor circuit.

By the above operation, the drain current of the transistor 11 is
The drain current flowing through the wiring IL is supplied to a monitor circuit via the wiring IL. The monitor circuit generates a signal including a value of the drain current as information, using the drain current flowing through the wiring IL. In the light-emitting device according to one embodiment of the present invention, the potential V
The value of data can be corrected.

It is not necessary that the external correction operation performed in the period t5 is always performed after the period t4. For example, in a light emitting device, the operation in the period t5 may be performed after the operations in the periods t1 to t4 are repeated a number of times. Also, after the operation in the period t5 is performed in one row of pixels 10, an image signal corresponding to the minimum gradation value 0 may be written to the row of pixels 10 in which the operation was performed, thereby putting the light emitting elements 14 into a non-emitting state, and then the operation in the period t5 may be performed in the pixels 10 in the next row.

Note that the pixel 10 shown in Fig. 14A can also be operated in the same manner according to the timing chart of potentials applied to the wirings GLa, GLb, GLd, and SL shown in Fig. 16. The external correction operation can also be performed in the same manner as the pixel shown in Fig. 14B. However, in the case of the pixel 10 shown in Fig. 14A, it is preferable to set the potential V0 lower than the potential obtained by adding the threshold voltage Vthe of the light-emitting element 14 and the threshold voltage Vth of the transistor 15t to the potential Vcat so that the drain current of the transistor 11 does not flow to the light-emitting element 14 during the period t2.

In the case of the pixel 10 illustrated in FIG. 15A , potentials are applied to the wirings GLa, GLb, GLc, GLd, and SL according to the timing chart illustrated in FIG.
In addition, the operation of external correction can be performed in the same manner as in the pixel shown in FIG.

15B can be operated in a similar manner in accordance with the timing chart of potentials applied to the wirings GLa, GLb, GLc, and SL shown in Fig. 16. The external correction operation can also be performed in a similar manner to the pixel shown in Fig. 14B.

<Transistor Configuration Example 1>
Next, a transistor in which a channel formation region is formed using an oxide semiconductor film (OS transistor) will be described.

27A, 27B, and 27C show top views (layout diagrams) of three transistors (TA1, TA2, and TB1) with different device structures and their respective circuit symbols. FIG. 28 is a cross-sectional view of the transistors (TA1, TA2, and TB1). It shows a cross-sectional view of the transistor TA1 taken along the lines a1-a2 and b1-b2, and a cross-sectional view of the transistor TA2 taken along the lines a3-
Cross-sectional views taken along lines a4 and b3-b4, and lines a5-a6 of transistor TB1;
The cross-sectional views taken along the line b5-b6 are shown in Fig. 28(A) and Fig. 28(B). The cross-sectional structures of these transistors in the channel length direction are shown in Fig. 28(A), and the cross-sectional structures in the channel width direction are shown in Fig. 28(B).

As shown in Figures 28A and 28B, the transistors (TA1, TA2, and TB1) are integrated on the same insulating surface, and these transistors can be fabricated in the same fabrication process. Note that, in order to clarify the device structure, electrical connections between the gate (G), source (S), and drain (D) of each transistor and wiring for supplying potential and power are omitted here.

Transistor TA1 ( FIG. 27A ) and transistor TA2 ( FIG. 27B ) are transistors having a gate (G) and a back gate (BG). One of the gate (G) and the back gate (BG) corresponds to a first gate, and the other corresponds to a second gate. Transistors TA1 and TA2 have a structure in which the back gate is connected to the gate. Transistor TB1 ( FIG. 27C ) is a transistor that does not have a BG.
As shown in Fig. 28, these transistors (TA1, TA2, TB1) are formed on a substrate 30. The configurations of these transistors will be described below with reference to Figs.

(Transistor TA1)
The transistor TA1 includes a gate electrode GE1, a source electrode SE1, a drain electrode DE1, a backgate electrode BGE1, and an oxide semiconductor film OS1.

In the following description, the transistor TA1 is referred to as TA1, and the back gate is referred to as BG.
An element or a component of an element may be abbreviated to OS1 or OS1 film, for example, by referring to the oxide semiconductor film OS1. Signals, potentials, circuits, and the like may also be abbreviated in the same manner.

In this embodiment, the channel length of an OS transistor is the distance between a source electrode and a drain electrode. The channel width of an OS transistor is the width of the source electrode or the drain electrode in a region where the oxide semiconductor film overlaps with the gate electrode. The channel length of transistor TA1 is La1, and the channel width is Wa1.

The film OS1 overlaps with the electrode GE1 via the insulating film 34. A pair of electrodes (SE1, DE1) are formed in contact with the upper surface and side surfaces of the film OS1. As shown in FIG.
The film OS1 has a portion that does not overlap with the electrode GE1 and the pair of electrodes (SE1, DE1). The length of the film OS1 in the channel length direction is longer than the channel length La1, and the length of the film OS1 in the channel width direction is longer than the channel width Wa1.

An insulating film 35 is formed to cover the film OS1, the electrode GE1, the electrode SE1, and the electrode DE1. An electrode BGE1 is formed on the insulating film 35. The electrode BGE1 is provided so as to overlap the film OS1 and the electrode GE1. Here, as an example, the electrode BGE1 is provided so as to have the same shape as the electrode GE1 and to be disposed at the same position as the electrode GE1. The electrode BGE1 contacts the electrode GE1 at an opening CG1 penetrating the insulating films 34, 35, and 36. With this structure, the gate and backgate of the transistor TA1 are electrically connected.

By connecting the back gate electrode BGE1 to the gate electrode GE1, the on-current of the transistor TA1 can be increased. By providing the back gate BGE1, the strength of the transistor TA1 can be improved.
E1 acts as a reinforcing member to make the transistor TA1 less likely to break.

The film OS1 including the channel formation region has a multi-layer structure, and here, as an example, a three-layer structure including three oxide semiconductor films (31, 32, and 33). The oxide semiconductor films constituting the film OS1 are preferably metal oxide films containing at least one of the same metal element, and preferably In
Examples of metal oxides containing In that can form a semiconductor film of a transistor include an In-Ga oxide film and an In-M-Zn oxide film (wherein M is Al, Ga,
Representative examples of the metal oxide film include Y, Zr, La, Ce, and Nd. Films in which other elements or materials are added to such metal oxide films can also be used.

"32" is a film that constitutes the channel forming region of the transistor TA1.
"33" also constitutes a channel formation region of a transistor TA2 and a transistor TB1, which will be described later. Therefore, an oxide semiconductor film having an appropriate composition may be used depending on the electrical characteristics (e.g., field-effect mobility, threshold voltage, etc.) required for the transistor TA2 and the transistor TB1. For example, it is preferable to adjust the composition of a metal element that is a main component of the oxide semiconductor films 31 and 32 so that a channel is formed at "33".

In the transistor TA1, by forming a channel in the region “32”, the channel formation region can be prevented from being in contact with the insulating films 34 and 35. In addition, by forming the oxide semiconductor films 31 and 32 as metal oxide films containing at least one of the same metal elements, the region “32” can be prevented from being in contact with the insulating films 34 and 35.
It is possible to make it difficult for interface scattering to occur at the interface between "31" and "32" and at the interface between "33" and "33". This makes it possible to make the field effect mobility of transistor TA1 higher than that of transistor TA2 and transistor TB1, and also to increase the drain current (on-current) in the on-state.

(Transistor TA2)
The transistor TA2 has a gate electrode GE2, a source electrode SE2, a drain electrode DE2, a backgate electrode BGE2, and an oxide semiconductor film OS2. The electrode BGE2 is in contact with the electrode GE2 through an opening CG2 penetrating the insulating films 34 to 36. The transistor TA2 is a modified example of the transistor TA1, and differs from the transistor TA1 in that the film OS2 has a single-layer structure formed of the oxide semiconductor film 33, but is otherwise similar to the transistor TA1. Here, the channel length La2 and the channel width Wa2 of the transistor TA2 are
The channel length La1 and the channel width Wa1 of the first transistor are set to be equal to those of the first transistor.

(Transistor TB1)
The transistor TB1 has a gate electrode GE3, a source electrode SE3, a drain electrode DE3, and an oxide semiconductor film OS3. The transistor TB1 is a modified example of the transistor TA2. Like the transistor TA2, the film OS3 has a single-layer structure made of an oxide semiconductor film 33. The transistor TB1 differs from the transistor TA2 in that it does not have a back gate electrode. The layout of the film OS3 and the electrodes (GE3, SE3, DE3) is also different. As shown in FIG. 27C , the region of the film OS3 that does not overlap with the electrode GE3 is the electrode SE3 or the electrode DE3.
3. Therefore, the channel width Wb1 of the transistor TB1 is
The channel length Lb1 is determined by the width of the electrode SE, like the transistor TA2.
3 and the electrode DE3, and here, the channel length La2 of the transistor TA2
It's longer than that.

[Insulating film]
The insulating films 34, 35 and 36 are formed on the transistors (TA1, TA2
, TB1) are formed. The insulating films 34, 35, and 36 are formed of a single layer or multiple layers of insulating films. The insulating film 34 is a film that constitutes the gate insulating film of the transistors (TA1, TA2, TB1). The insulating films 35 and 36 are films that constitute the gate insulating film on the back channel side of the transistors (TA1, TA2, TB1). The insulating film 36 on the top surface is preferably formed of a material that functions as a protective film for the transistors formed on the substrate 30. The insulating film 36 may be provided as appropriate. In order to insulate the third-layer electrode BGE1 from the second-layer electrodes (SE1, DE1), it is sufficient that at least one insulating film layer exists between them.

The insulating films 34 to 36 can be formed of a single layer insulating film or a multilayer insulating film having two or more layers. Examples of insulating films constituting the insulating films 34 to 36 include aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide,
Examples of the insulating film include films made of lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. Furthermore, these insulating films can be formed by using a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method.

[Oxide Semiconductor Film]
Here, an oxide semiconductor film that constitutes a semiconductor film of an OS transistor is described. When a semiconductor film has a multilayer structure like the film OS1, the oxide semiconductor films that constitute the multilayer structure are preferably metal oxide films that contain at least one of the same metal element, and preferably contain In.

For example, when "31" is an In-Ga oxide film, the atomic ratio of In is made smaller than the atomic ratio of Ga. When it is an In-M-Zn oxide film (M is Al, Ga, Y, Zr, La, Ce, or Nd), the atomic ratio of In is made smaller than the atomic ratio of M. In this case, it is possible to make the atomic ratio of Zn the largest.

For example, when "32" is an In-Ga oxide film, the atomic ratio of In is made larger than the atomic ratio of Ga. When it is an In-M-Zn oxide film, the atomic ratio of In is made larger than the atomic ratio of M. In the In-M-Zn oxide film, it is preferable that the atomic ratio of In is made larger than the atomic ratios of M and Zn.

For example, when "33" is an In--Ga oxide film, the atomic ratio of In is made the same as or smaller than the atomic ratio of Ga. When it is an In-M-Zn oxide film, the atomic ratio of In is made the same as the atomic ratio of M. In this case, the atomic ratio of Zn can be made larger than those of In and M. Here, "33" is also a film that constitutes the channel formation regions of transistors TA2 and TB1, which will be described later.

The atomic ratio of the oxide semiconductor films 31 to 33 can be adjusted by adjusting the atomic ratio of constituent materials of a target when the films are formed by a sputtering method.
When the oxide semiconductor films 31 to 33 are formed by a sputtering method, the flow rate ratio of source gases or the like can be adjusted. Hereinafter, a target used for film formation will be described taking as an example a case where In-M-Zn oxide films are formed by a sputtering method as the oxide semiconductor films 31 to 33. A target made of In-M-Zn oxide is used to form these films.

If the atomic ratio of the metal elements of the target "31" is In:M:Zn=x1:y1:z1 _, it is preferable that x1/y1 is 1/6 or more and less than 1. Also, z1/y1 is 1/
It is preferably 3 or more and 6 or less, and more preferably 1 or more and 6 or less.

Representative examples of the atomic ratio of the metal elements in the target are In:M:Zn=1:3:2, In
:M:Zn=1:3:4, In:M:Zn=1:3:6, In:M:Zn=1:3:8,
In:M:Zn=1:4:4, In:M:Zn=1:4:5, In:M:Zn=1:4:
6, In:M:Zn=1:4:7, In:M:Zn=1:4:8, In:M:Zn=1:
5:5, In:M:Zn=1:5:6, In:M:Zn=1:5:7, In:M:Zn=
Examples include In:M:Zn = 1:5:8, In:M:Zn = 1:6:8, etc.

If the atomic ratio of the metal elements of the target "32" is In:M:Zn = x2:y2:z2 _, then x2/y2 is preferably greater than 1 and equal to or less than 6. Also, z2/y2 is preferably greater than 1 and equal to or less than 6. Representative examples of atomic ratios of the metal elements of the target include In:M:Zn = 2:1:1.5, In:M:Zn = 2:1:2.3, In:M:Z
n=2:1:3, In:M:Zn=3:1:2, In:M:Zn=3:1:3, In:M
:Zn = 3:1:4, etc.

If the atomic ratio of the metal elements of the target “33” is In:M:Zn=x3:y3:z3 _, it is preferable that x3/y3 is 1/6 or more and 1 or less. Also, z3/y3 is 1/
It is preferably 3 or more and 6 or less, and more preferably 1 or more and 6 or less. Representative examples of the atomic ratio of the metal elements in the target include In:M:Zn=1:1:1, In:M:Zn=1:1:1.
2, In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1:
3:6, In:M:Zn=1:3:8, In:M:Zn=1:4:4, In:M:Zn=
1:4:5, In:M:Zn=1:4:6, In:M:Zn=1:4:7, In:M:Z
n=1:4:8, In:M:Zn=1:5:5, In:M:Zn=1:5:6, In:M
:Zn=1:5:7, In:M:Zn=1:5:8, In:M:Zn=1:6:8, etc.

In the target for forming the In-M-Zn oxide film, the atomic ratio of metal elements is In:M:
When Zn=x:y:z, it is preferable that 1≦z/y≦6 be satisfied, because a CAAC-OS film is easily formed as an In-M-Zn oxide film.

As the oxide semiconductor films 31 to 33, oxide semiconductor films with low carrier density are used. For example, oxide semiconductor films with carrier density of 1×10 ¹⁷ particles/cm ³ or less, preferably 1×10 ¹⁵ particles/cm ³ or less, further preferably 1×10 ¹³ particles/cm ³ or less are used as the oxide semiconductor films 31 to 33. In particular, the oxide semiconductor film 31
For the oxide semiconductor film 33, an oxide semiconductor film having a carrier density of less than 8×10 ¹¹ particles/cm ³ , more preferably less than 1×10 ¹¹ particles/cm ³ , further preferably less than 1×10 ¹⁰ particles/cm ³ and 1×10 ⁻⁹ particles/cm ³ or more is preferably used.

By using an oxide semiconductor film with a low impurity concentration and a low density of defect states as the oxide semiconductor films 31 to 33, a transistor with better electrical characteristics can be manufactured. Here, a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor has a low impurity concentration and a low density of defect states (few oxygen vacancies). A high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor has a small number of carrier generation sources, and therefore the carrier density can be reduced in some cases. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film rarely has electrical characteristics in which the threshold voltage is negative (also referred to as normally-on). In addition, a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has the following characteristics:
Since the density of defect states is low, the density of trap states may also be low. In addition, a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor film has a significantly small off-current, and even in an element having a channel width of 1×10 ⁶ μm and a channel length L of 10 μm, the off-current is equal to or less than the measurement limit of a semiconductor parameter analyzer, that is, 1×10 ⁻¹³ A or less, when the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1 V to 10 V. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film has small fluctuations in electrical characteristics and is highly reliable. Examples of impurities include hydrogen, nitrogen, an alkali metal, and an alkaline earth metal.

Hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to metal atoms to form water, and oxygen vacancies are formed in the lattice from which oxygen has been removed (or in the portion from which oxygen has been removed). When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. When part of the hydrogen bonds with oxygen bonded to metal atoms, electrons serving as carriers may be generated.
Therefore, a transistor including an oxide semiconductor containing hydrogen tends to have normally-on characteristics.

For this reason, it is preferable that the oxide semiconductor films 31 to 33 have as little oxygen vacancy as possible and hydrogen as possible reduced.
The hydrogen concentration obtained by SS Spectrometry was set to 5×10 ¹⁹ atoms.
/cm ³ or less, more preferably 1×10 ¹⁹ atoms/cm ³ or less, 5×10 ¹⁸ atoms/cm 3 or less
less than 1×10 ¹⁸ atoms/cm ³ , preferably 1×10 18 atoms/cm ³ or less, more preferably 5×10 ¹⁷ atoms/cm ³ or less, and even more preferably 1×10 ¹⁶ atoms/cm
The number must be ³ or less.

When the oxide semiconductor films 31 to 33 contain silicon or carbon, which is one of the Group 14 elements, oxygen vacancies in the films are increased, and these films become n-type. For this reason, the concentration of silicon or carbon in the oxide semiconductor films 31 to 33 (concentration obtained by secondary ion mass spectrometry) is set to 2×10 ^{18 atoms/cm 3 or less, preferably 2×10 18} atoms/cm ³ or less.
×10 ¹⁷ atoms/cm ³ or less.

In the oxide semiconductor films 31 to 33, the concentrations of alkali metals or alkaline earth metals measured by secondary ion mass spectrometry were 1×10 ¹⁸ atoms/cm
The concentration of alkali metal or alkaline earth metal is preferably 2×10 ¹⁶ atoms/cm ³ or ^less . When an alkali metal or an alkaline earth metal is bonded to an oxide semiconductor, carriers may be generated, which may increase the off-state current of a transistor. For this reason, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor films 31 to 33.

When the oxide semiconductor films 31 to 33 contain nitrogen, electrons that serve as carriers are generated, the carrier density is increased, and the oxide semiconductor films 31 to 33 tend to have n-type conductivity. Therefore, a transistor using an oxide semiconductor that contains nitrogen tends to have normally-on characteristics.
The nitrogen content in the oxide semiconductor film 33 is preferably reduced as much as possible; for example, the nitrogen concentration measured by secondary ion mass spectrometry is preferably 5×10 ¹⁸ atoms/cm ³ or less.

The oxide semiconductor films 31 to 33 have been described above; however, the present invention is not limited to these, and oxide semiconductor films having appropriate compositions may be used depending on the semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistors required.
It is preferable that the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, etc. of 3 be appropriate.

The transistor TA1 can have a high field-effect mobility because a channel is formed in the oxide semiconductor film 32 in which the atomic ratio of In is greater than the atomic ratio of Ga or M (M is Al, Ga, Y, Zr, La, Ce, or Nd). Typically, the field-effect mobility is greater than 10 cm ² /Vs and less than 60 cm ² /Vs, and preferably 15 cm ² /Vs or more and less than 50 cm ² /Vs. Therefore, when the transistor TA1 is used in a circuit of an active matrix display device, it is suitable for a drive circuit that requires high-speed operation.

The transistor TA1 is preferably provided in a light-shielded region. By providing the transistor TA1 having high field-effect mobility in a driver circuit, the drive frequency can be increased, thereby achieving a display device with higher resolution.

The transistors TA2 and TB1, whose channel formation regions ^are formed of the oxide semiconductor film 33, have a lower field effect mobility than the transistor TA1.
The transistors TA2 and TB1 do not have the oxide semiconductor film 32 and are therefore less susceptible to degradation ^by light than the transistor TA1, and thus have a smaller increase in off-state current due to light irradiation. Therefore, the transistors TA2 and TB1, whose channel formation region is formed using the oxide semiconductor film 33, are suitable for a pixel portion that is irradiated with light.

The transistor TA1 has the following characteristics in comparison with the transistor TA2 that does not include the oxide semiconductor film 32:
When exposed to light, the current in the off state tends to increase. This is one of the reasons why the transistor TA1 is suitable for a peripheral driver circuit that is less affected by light than a pixel section that cannot be sufficiently shielded from light. Of course, transistors with configurations like the transistors TA2 and TB1 can also be provided in the driver circuit.

Although the transistors (TA1, TA2, and TB1) and the oxide semiconductor films 31 to 33 have been described above, the present invention is not limited thereto, and the configuration of the transistor may be changed depending on required semiconductor characteristics and electrical characteristics of the transistor. For example, the presence or absence of a backgate electrode, the stacked structure of the oxide semiconductor film, the shapes and arrangements of the oxide semiconductor film, the gate electrode, the source electrode, and the drain electrode, and the like can be changed as appropriate.

(Structure of oxide semiconductor)
Next, the structure of the oxide semiconductor will be described.

In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the angle also includes the case of an angle of -5° or more and 5° or less.
"Substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases in which the angle is 85° or more and 95° or less. "Substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is referred to as a hexagonal crystal system.

Oxide semiconductor films are classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films, or into, for example, crystalline oxide semiconductors and amorphous oxide semiconductors.

Note that the non-single-crystal oxide semiconductor can be a CAAC-OS (C Axis Aligned
Examples of crystalline oxide semiconductors include single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, microcrystalline oxide semiconductors, and amorphous oxide semiconductors. Examples of crystalline oxide semiconductors include single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and microcrystalline oxide semiconductors.

First, we will explain the CAAC-OS film.

The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts aligned along the c-axis.

Transmission Electron Microscope (TEM)
A bright-field image and a combined analysis image of the diffraction pattern of the CAAC-OS film (
By observing the TEM image (also called a high-resolution TEM image), multiple crystal regions can be confirmed.
On the other hand, a clear boundary between crystal parts, that is, a grain boundary, cannot be confirmed even in a high-resolution TEM image. Therefore, it can be said that a decrease in electron mobility due to grain boundaries is unlikely to occur in the CAAC-OS film.

When a high-resolution TEM image of a cross section of the CAAC-OS film is observed from a direction approximately parallel to the sample surface,
It can be seen that the metal atoms are arranged in layers in the crystal part. Each layer of metal atoms is
The shape of the CAAC-OS film reflects the unevenness of a surface on which the CAAC-OS film is formed (also referred to as a surface on which the CAAC-OS film is formed) or a top surface thereof, and the CAAC-OS film is arranged in parallel to the surface on which the CAAC-OS film is formed or the top surface thereof.

On the other hand, when a high-resolution TEM image of a planar surface of a CAAC-OS film is observed from a direction substantially perpendicular to the sample surface, it can be seen that metal atoms are arranged in a triangular or hexagonal shape in the crystal parts, but no regularity is observed in the arrangement of metal atoms between different crystal parts.

When a CAAC-OS film is subjected to structural analysis using an X-ray diffraction (XRD) apparatus, for example, in an out-of-plane analysis of a CAAC-OS film having InGaZnO ₄ crystals, a peak may appear at a diffraction angle (2θ) of about 31°. This peak is attributed to the (009) plane of the InGaZnO ₄ crystals, and therefore it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation, and the c-axis faces a direction approximately perpendicular to the surface on which the CAAC-OS film is formed or the top surface.

In addition, in an out-of-plane analysis of a CAAC-OS film containing InGaZnO ₄ crystals, a peak may appear at 2θ near 36° in addition to the peak at 2θ near 31°. The peak at 2θ near 36° indicates that crystals without c-axis orientation are contained in part of the CAAC-OS film. It is preferable that the CAAC-OS film shows a peak at 2θ near 31° and does not show a peak at 2θ near 36°.

The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities.
These are elements other than the main components of the oxide semiconductor film, such as silicon and transition metal elements. In particular, elements such as silicon that bond more strongly with oxygen than metal elements constituting the oxide semiconductor film take oxygen from the oxide semiconductor film, thereby disrupting the atomic arrangement of the oxide semiconductor film and causing a decrease in crystallinity. Heavy metals such as iron and nickel, argon, and carbon dioxide have a large atomic radius (or molecular radius), and therefore, when contained inside the oxide semiconductor film, they disrupt the atomic arrangement of the oxide semiconductor film and cause a decrease in crystallinity. Note that impurities contained in the oxide semiconductor film may become carrier traps or carrier generation sources.

The CAAC-OS film is an oxide semiconductor film with a low density of defect states. For example, oxygen vacancies in the oxide semiconductor film can become carrier traps or can trap hydrogen and become a carrier generation source.

An oxide semiconductor film having a low impurity concentration and a low density of defect states (few oxygen vacancies) is called a highly pure intrinsic film or a substantially highly pure intrinsic film. An oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic can have a low carrier density because it has a small number of carrier generation sources.
The transistor including the oxide semiconductor film has electrical characteristics in which the threshold voltage is negative (
The oxide semiconductor film is also called normally-on. In addition, a highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor film has few carrier traps. Therefore, a transistor using the oxide semiconductor film has small fluctuations in electrical characteristics and is highly reliable. Note that charges trapped in carrier traps in the oxide semiconductor film take a long time to be released and may behave as if they are fixed charges. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high density of defect states may have unstable electrical characteristics.

Furthermore, in a transistor using a CAAC-OS film, change in electrical characteristics due to irradiation with visible light or ultraviolet light is small.

Next, the microcrystalline oxide semiconductor film will be described.

The microcrystalline oxide semiconductor film has a region where a crystal part can be confirmed in a high-resolution TEM image and a region where a clear crystal part cannot be confirmed. The crystal parts contained in the microcrystalline oxide semiconductor film often have a size of 1 nm to 100 nm, or 1 nm to 10 nm. In particular, an oxide semiconductor film having nanocrystals (nc), which are microcrystals having a size of 1 nm to 10 nm, or 1 nm to 3 nm, is referred to as nc
-OS (nanocrystalline oxide semiconductor)
In the nc-OS film, the grain boundaries may not be clearly identified in a high-resolution TEM image, for example.

The nc-OS film has periodic atomic arrangement in a microscopic region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS film has no regularity in crystal orientation between different crystal parts. Therefore, no orientation is observed in the entire film. Therefore, the nc-OS film may be indistinguishable from an amorphous oxide semiconductor film depending on the analysis method. For example, when an X-ray having a diameter larger than that of a crystal part is used for the nc-OS film, the nc-OS film is subjected to X-ray diffraction (XRD) to obtain a crystal orientation pattern of the nc-OS film.
When a structural analysis is performed using a .D apparatus, no peak indicating a crystal plane is detected in the out-of-plane analysis. When an nc-OS film is subjected to electron diffraction (also referred to as selected area electron diffraction) using an electron beam with a probe diameter larger than the crystal part (for example, 50 nm or more), a diffraction pattern like a halo pattern is observed. On the other hand, when an nc-OS film is subjected to nanobeam electron diffraction using an electron beam with a probe diameter close to or smaller than the size of the crystal part, a spot is observed. When an nc-OS film is subjected to nanobeam electron diffraction, a region of high brightness that draws a circle (ring shape) is sometimes observed. Also,
When nanobeam electron diffraction is performed on the nc-OS film, a plurality of spots are observed within a ring-shaped region in some cases.

The nc-OS film is an oxide semiconductor film with higher regularity than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than an amorphous oxide semiconductor film.
In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts.
The S film has a higher density of defect states than the CAAC-OS film.

Next, we will explain the amorphous oxide semiconductor film.

An amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and which does not have a crystal part, such as an oxide semiconductor film having an amorphous state like quartz.

In amorphous oxide semiconductor films, no crystalline parts can be seen in high-resolution TEM images.

When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of-phase
In the analysis by the Lane method, no peak indicating a crystal plane is detected. In addition, when electron diffraction is performed on the amorphous oxide semiconductor film, a halo pattern is observed. In addition, when nanobeam electron diffraction is performed on the amorphous oxide semiconductor film, no spots are observed, but a halo pattern is observed.

Note that the oxide semiconductor film may have a structure that shows physical properties between an nc-OS film and an amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly referred to as an amorphous-like oxide semiconductor (a-like OS).
The electrode is called a "conductor film."

In the a-like OS film, voids may be observed in a high-resolution TEM image. The high-resolution TEM image includes a region where a crystal part can be clearly identified and a region where a crystal part cannot be identified.
In some cases, crystallization occurs due to a small amount of electron irradiation, which is observed in TEM observation, and growth of crystalline parts is observed. On the other hand, in a high-quality nc-OS film, crystallization due to a small amount of electron irradiation, which is observed in TEM observation, is hardly observed.

The size of the crystal parts of the a-like OS film and the nc-OS film was measured using a high-resolution T
This can be done using EM images. For example, _InGaZnO4 crystals have a layered structure,
Two Ga-Zn-O layers are placed between the In-O layers. The unit lattice of the InGaZnO ₄ crystal has a structure in which a total of nine layers, including three In-O layers and six Ga-Zn-O layers, are stacked in the c-axis direction. Therefore, the distance between these adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane, and the value is 0.29 nm from crystal structure analysis.
Therefore, by focusing on the lattice fringes in the high-resolution TEM image, it is possible to determine that in the area where the spacing between the lattice fringes is 0.28 nm or more and 0.30 nm or less, each lattice fringe is InG
This corresponds to the ab plane of the _aZnO4 crystal.

In addition, the density of an oxide semiconductor film may differ depending on the structure. For example, when the composition of a certain oxide semiconductor film is known, the density of the oxide semiconductor film can be determined by comparing the composition with the density of a single crystal having the same composition.
The structure of the oxide semiconductor film can be estimated.
The density of the like-OS film is 78.6% or more and less than 92.3%. For example, the density of the nc-OS film and the CAAC-OS film is 92.3% or more and less than 10% with respect to the density of a single crystal.
Note that an oxide semiconductor film having a density of less than 78% of the density of a single crystal is
The film formation itself is difficult.

The above will be described using a specific example. For example, in an oxide semiconductor film that satisfies the atomic ratio of In:Ga:Zn=1:1:1, single crystal InGaZnO ₄ having a rhombohedral crystal structure is
The density of In is 6.357 g/ ^cm3 . Therefore, for example, In:Ga:Zn=1:1:1
In the oxide semiconductor film that satisfies the [atomic ratio], the density of the a-like OS film is 5.0 g
/cm ³ or more and less than 5.9 g/cm ^3. For example, In:Ga:Zn=1:1:
In the oxide semiconductor film that satisfies the atomic ratio of 1, the density of the nc-OS film and the CAAC-
The density of the OS film is greater than or equal to 5.9 g/cm ³ and less than 6.3 g/cm ³ .

There may be cases where single crystals of the same composition do not exist. In such cases, the density corresponding to a single crystal of a desired composition can be calculated by combining single crystals of different compositions in any ratio. The density of a single crystal of a desired composition may be calculated using a weighted average of the ratio of the single crystals of different compositions combined. However, it is preferable to calculate the density by combining as few types of single crystals as possible.

Note that the oxide semiconductor film may be a stacked film including two or more of an amorphous oxide semiconductor film, an a-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example.

As described above, OS transistors can achieve extremely excellent off-state current characteristics.

[Substrate 30]
Various substrates can be used as the substrate 30, and there is no particular limitation. Examples of the substrate 30 include a semiconductor substrate (e.g., a single crystal substrate or a silicon substrate), an SOI
Substrate, glass substrate, quartz substrate, plastic substrate, metal substrate, stainless steel substrate,
Examples of the substrate include a substrate having a stainless steel foil, a tungsten substrate, a substrate having a tungsten foil, a flexible substrate, a laminated film, a paper containing a fibrous material, or a base film. An example of a glass substrate is barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. Examples of the flexible substrate, laminated film, base film, or the like are as follows. For example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (
Examples of the material include plastics such as PE (polyethylene stearate copolymer), synthetic resins such as acrylic, polypropylene, polyester, polyvinyl fluoride, polyvinyl chloride, polyamide, polyimide,
Examples of the substrate include aramid, epoxy, inorganic vapor deposition film, and paper. In particular, by manufacturing a transistor using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, it is possible to manufacture a transistor with small variations in characteristics, size, shape, and the like, high current capability, and small size. By configuring a circuit using such transistors, it is possible to reduce the power consumption of the circuit or to increase the integration of the circuit.

Before forming the gate electrodes (GE1, GE2, GE3), a base insulating film may be formed on the substrate 30. Examples of the base insulating film include silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide, and aluminum oxynitride. By using silicon nitride, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide, or the like as the base insulating film, the substrate 30 can be easily formed.
Impurities (typically, alkali metal, water, hydrogen, or the like) are removed from the oxide semiconductor film (OS1-OS3
) can be suppressed.

[Gate electrodes (GE1, GE2, GE3)]
The gate electrodes (GE1, GE2, GE3) are single-layer conductive films or multilayer films in which two or more conductive films are stacked. The conductive films formed as the gate electrodes (GE1, GE2, GE3) can be formed using a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. A metal element selected from any one or more of manganese and zirconium may also be used. An alloy film combining one or more selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium with aluminum, or a nitride film may also be used. A conductive material having light transmitting properties, such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide containing silicon oxide, can also be applied.

For example, an aluminum film containing silicon can be formed as the gate electrodes (GE1, GE2, GE3). When the gate electrodes (GE1, GE2, GE3) have a two-layer structure, for example, a titanium film may be formed on an aluminum film, a titanium film may be formed on a titanium nitride film, a tungsten film may be formed on a titanium nitride film, or a tungsten film may be formed on a tantalum nitride film or a tungsten nitride film.
When 3) is to have a three-layer structure, for example, a titanium film may be formed, an aluminum film may be laminated on the titanium film, and a titanium film may be further formed on the aluminum film.

The gate electrodes (GE1, GE2, GE3) are formed by a method such as sputtering, vacuum deposition, pulsed laser deposition (PLD), or thermal CVD.

The tungsten film can be formed by a film forming apparatus using ALD. In this _case , _WF6 gas and _B2H6 gas are repeatedly introduced in sequence to form an initial tungsten film, and then _WF6 gas and _H2 gas are simultaneously introduced to form a tungsten film.
_SiH4 gas may be used in place of _{2H6 gas} .

The gate electrodes GE1-GE3 can be formed by the above-mentioned method, as well as by electrolytic plating, printing, ink-jet printing, or the like.

[Insulating film 34 (gate insulating film)]
An insulating film 34 is formed to cover the gate electrodes GE1-GE3. The insulating film 34 is a single-layer insulating film or an insulating film having a multi-layer structure of two or more layers. The insulating film formed as the insulating film 34 is
Examples of the insulating film include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film.
In this specification, an oxynitride is a material having a higher oxygen content than nitrogen, and a nitride oxide is a material having a higher nitrogen content than oxygen.

The insulating film formed as the insulating film 34 may be, for example, an insulating film made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga-Zn-based metal oxide, etc. Examples of such insulating films include hafnium silicate (HfSiO _x ), hafnium silicate with nitrogen added (HfSi _x O _y N _z ), hafnium aluminate with nitrogen added (Hf
It is possible to form a film made of a high-k material such as Al _x O _y N _z , hafnium oxide, yttrium oxide, etc. By using a high-k material, it is possible to reduce gate leakage of a transistor.

The insulating film 34 is a film that constitutes a gate insulating film, and therefore is an oxide semiconductor film (OS1, OS2,
In order to improve the interface characteristics between the layers (OS1, OS2, and OS3) and the gate insulating film, the region of the insulating film 34 in contact with these layers (OS1, OS2, and OS3) is preferably formed of an oxide insulating film or an oxynitride insulating film. For example, the uppermost film of the insulating film 34 may be a silicon oxide film or a silicon oxynitride film.

The thickness of the insulating film 34 may be, for example, 5 nm to 400 nm, preferably 10 nm to 300 nm, and more preferably 50 nm to 250 nm.

When the oxide semiconductor films (OS1, OS2, and OS3) are formed by a sputtering method, an RF power supply, an AC power supply, a DC power supply, or the like can be used as appropriate as a power supply for generating plasma.

The sputtering gas may be a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed gas of rare gas and oxygen. In the case of a mixed gas of rare gas and oxygen, it is preferable to increase the gas ratio of oxygen to rare gas.

Further, a target may be appropriately selected depending on the composition of the oxide semiconductor film (OS1, OS2, or OS3) to be formed.

When a sputtering method is used to form the oxide semiconductor films (OS1, OS2, and OS3), the substrate temperature is set to 150° C. or higher and 750° C. or lower, preferably 150° C. or higher and 450° C. or lower, further preferably 200° C. or higher and 350° C. or lower, so that a CAAC-OS film can be formed as the oxide semiconductor films 31 and 32.

In addition, it is preferable to apply the following conditions to form a CAAC-OS film.

By suppressing the inclusion of impurities during film formation, it is possible to suppress the destruction of the crystal state due to impurities. For example, this can be achieved by reducing the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber. Also, this can be achieved by reducing the concentration of impurities in the film formation gas. Specifically, this can be achieved by reducing the dew point to -
A deposition gas having a temperature of 80° C. or less, preferably −100° C. or less, is used.

In addition, it is preferable to reduce plasma damage during film formation by increasing the oxygen ratio in the film formation gas and optimizing the power. The oxygen ratio in the film formation gas is preferably 30 volume % or more, and more preferably 100 volume %.

The oxide semiconductor film is formed while being heated, or after the oxide semiconductor film is formed,
By performing heat treatment, the hydrogen concentration in the oxide semiconductor film can be reduced to 2×10 ²⁰ atoms/cm ³ or less, preferably 5×10 ¹⁹ atoms/cm ³ or less, more preferably 1×10 ¹⁹ atoms/cm 3 or less.
ms/cm3 ^or less, less than 5× ¹⁰¹⁸ atoms/ ^cm3 , preferably 1× ¹⁰¹⁸ a
The concentration can be set to 1×10 17 atoms/cm ³ or less, more preferably 5×10 ¹⁷ atoms/cm ³ or less, and further preferably 1×10 ¹⁶ atoms/cm ³ or less.

The heat treatment is performed at a temperature higher than 350° C. and lower than 650° C., preferably at 450° C. or higher and 600° C. or lower, so that the CAAC conversion rate described later is 70% or higher and lower than 100%, preferably 80%.
or more and less than 100%, preferably 90% or more and less than 100%, more preferably 95% or more and less than 98%.
% or less. In addition, it is possible to obtain an oxide semiconductor film with a reduced content of hydrogen, water, and the like. That is, an oxide semiconductor film with a low impurity concentration and a low density of defect states can be formed.

An oxide semiconductor film can be formed by a film formation apparatus using ALD. For example, InG
When forming _aZnOx (X>0) film, In( _CH3 ) ₃ gas and _O3 gas are repeatedly introduced in sequence to form an _InO2 layer, then Ga( _CH3 ) ₃ gas and _O3 gas are simultaneously introduced to form a GaO layer, and then Zn( _CH3 ) ₂ gas and _O3 gas are simultaneously introduced to form a ZnO layer. Note that the order of these layers is not limited to this example. Also, by mixing these gases, an _InGaO2 layer, an _InZnO2 layer, a GaInO layer, a ZnInO layer, a GaZnO layer, etc. may be formed.
A mixed compound layer such as a ZnO layer may be formed. Although _H2O gas bubbled with an inert gas such as Ar may be used instead of _O3 gas, it is preferable to use _O3 gas that does not contain H. In( _CH3 ) ₃ gas may be used instead _of In( _C2H5 ) ₃ gas. In addition, _Ga ( _CH3 ) ₃ gas may be used instead of Ga( _C2H5 ) ₃ gas. In addition, Z
Alternatively, n(CH ₃ ) ₂ gas may be used.

The oxide semiconductor film 32 and the oxide semiconductor film 33 are films in which channels of transistors are formed, and their thicknesses can be set to 3 nm to 200 nm.
The thickness of the oxide semiconductor film 31 can be, for example, 3 nm to 100 nm, preferably 3 nm to 30 nm, and more preferably 3 nm to 15 nm.
The oxide semiconductor film 31 is preferably formed thinner than the oxide semiconductor film 32 and the oxide semiconductor film 33.

Here, the oxide semiconductor films 31, 32, and 33 are formed by sputtering an In—Ga—Zn film.
The ratio of the oxide semiconductor film 31 to the oxide semiconductor film 32 is 3:1:2, and the ratio of the oxide semiconductor film 33 is 1:1:1.2 or 1:1:1. The thicknesses of the oxide semiconductor films 31, 32, and 33 are 5 nm and 35 nm, respectively.
m, 35 nm.

[Source electrode, drain electrode]
The electrodes (SE1, DE1, SE2, DE2, SE3, DE3) are gate electrodes (GE1, GE
2, GE3).

For example, a copper-manganese alloy film having a thickness of 50 nm, a copper film having a thickness of 400 nm, and a copper film having a thickness of 100 nm
m copper-manganese alloy film, and then stacking these films by a sputtering method.
It is possible to form a three-layered electrode (SE1, DE1, SE2, DE2, SE3, DE3).

Transistors that operate at high speed, such as transistors used in driving circuits of light-emitting devices, include transistors (TA1, TA2) or transistors (TA3, TA4,
It is preferable to shorten the channel length, such as in the case of the transistor (SE1, DE1, SE2, DE2, STC1). The channel length of such a transistor is preferably less than 2.5 μm. For example, it may be 2.2 μm or less. In the transistor of this embodiment, the channel length is determined by the distance between the source electrode and the drain electrode, so the minimum value of the channel length is determined by the distance between the electrodes (SE1, DE1, SE2, DE2, STC1).
In the transistor of this embodiment, the channel length can be set to, for example, 0.5 μm or more, or 1.0 μm or more.

[Insulating films 35, 36]
For example, a two-layer insulating film can be formed as "35".
The first layer of the film of ".5" is called insulating film 35a, and the second layer is called insulating film 35b.

The insulating film 35a may be an oxide insulating film made of, for example, silicon oxide or an oxide insulating film containing nitrogen and having few defects. Typical examples of the oxide insulating film containing nitrogen and having few defects include a silicon oxynitride film and an aluminum oxynitride film.

An oxide insulating film with few defects has a first signal with a g value of 2.037 or more and 2.039 or less, a second signal with a g value of 2.001 or more and 2.002 or less in a spectrum obtained by ESR measurement at 100K or less, and a third signal with a g value of 2.001 or more and 2.003 or less.
A second signal having a g value of 1.003 or less and a third signal having a g value of 1.964 to 1.966 are observed.
The split width of the first signal and the third signal is about 5 m in the X-band ESR measurement.
The first signal has a g value of 2.037 to 2.039, and the second signal has a g value of 2.0
The sum of the spin densities of the second signal having a g value of 1.01 or more and 2.003 or less and the third signal having a g value of 1.964 or more and 1.966 or less is less than 1×10 ¹⁸ spins/cm ³ , typically 1×10 ¹⁷ spins/cm ³ or more and less than 1×10 ¹⁸ spins/cm ³ .

In the ESR spectrum at 100K or less, a first signal has a g value of 2.037 or more and 2.039 or less, a second signal has a g value of 2.001 or more and 2.003 or less, and a second signal has a g value of 1.
The third signal of 0.964 or more and 1.966 or less corresponds to a signal caused by nitrogen oxides (NOx, x is 0 or more and 2 or less, preferably 1 or more and 2 or less). Representative examples of nitrogen oxides include:
That is, the first signal has a g value of 2.037 to 2.039, the second signal has a g value of 2.001 to 2.003, and the third signal has a g value of 1.96
It can be said that the smaller the total spin density of the third signal is in the range of 4 to 1.966, the smaller the content of nitrogen oxide in the oxide insulating film.

Since the insulating film 35a contains a small amount of nitrogen oxide, the insulating film 35a and the layer (OS
In this case, it is possible to reduce carrier traps at the interface with the silicon oxide (OS1, OS2, or OS3). As a result, a shift in the threshold voltage of the transistor can be reduced, and fluctuations in the electrical characteristics of the transistor can be reduced.

In order to improve the reliability of the transistor, the insulating film 35a is formed by SIMS (Secondary Induction Mass Spectroscopy).
The nitrogen concentration measured by ion mass spectrometry was 6× ^10
0 / ^cm3 or less. This is because the insulating film 35 is
This is because nitrogen oxides are less likely to be produced in a.

As an example of the insulating film 35a, an oxide insulating film containing nitrogen and having a small amount of defects is
A silicon oxynitride film can be formed by the D method. In this case, the source gas is
It is preferable to use a deposition gas containing silicon and an oxidizing gas. Representative examples of deposition gas containing silicon include silane, disilane, trisilane, silane fluoride, etc. Examples of oxidizing gas include dinitrogen monoxide and nitrogen dioxide.

The ratio of the oxidizing gas to the deposition gas is more than 20 times and less than 100 times, preferably 40
By using a CVD method with a pressure in the treatment chamber of less than 100 Pa, preferably less than or equal to 50 Pa, an oxide insulating film containing nitrogen and with few defects can be formed as the insulating film 35a.

The insulating film 35b can be formed using, for example, an oxide insulating film containing more oxygen than the stoichiometric composition. When the oxide insulating film containing more oxygen than the stoichiometric composition is heated, some of the oxygen is released. When the oxide insulating film containing more oxygen than the stoichiometric composition is heated, the amount of released oxygen, calculated as oxygen atoms, is 1.0×10 ¹⁸ atoms/cm ³ or more, preferably 3.0×10 ²⁰ atoms/cm 3 or more, as determined by TDS analysis.
The oxide insulating film has a resistivity of ms/cm ³ or more. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or more and 700° C. or less, or 100° C. or more and 500° C. or less.

The insulating film 35b has a thickness of 30 nm to 500 nm, preferably 50 nm to 400 nm.
The insulating film 35 may be made of silicon oxide, silicon oxynitride, or the like having a thickness of 00 nm or less.
When b is formed using an oxide insulating film containing more oxygen than the stoichiometric composition, a silicon oxynitride film can be formed by a CVD method as the oxide insulating film containing more oxygen than the stoichiometric composition.

When a silicon oxide film or a silicon oxynitride film is formed as the insulating film 35b, the film can be formed under the following conditions: A substrate placed in an evacuated processing chamber of a plasma CVD apparatus is maintained at 180° C. to 280° C., more preferably 200° C. to 240° C., and a source gas is introduced into the processing chamber to maintain the pressure in the processing chamber at 100 Pa to 250 Pa.
a or less, more preferably 100 Pa or more and 200 Pa or less, and the electrode provided in the processing chamber is provided with a pressure of 0.17 W/cm2 or ^more and 0.5 W/cm2 ^or less, more preferably 0.25 W/cm
A high frequency power of ² or more and 0.35 W/cm2 ^or less is supplied.

The insulating film 36 is a film having a blocking effect against at least hydrogen and oxygen. More preferably, the insulating film 36 has a blocking effect against oxygen, hydrogen, water, alkali metals, alkaline earth metals, and the like. Typically, a nitride insulating film such as silicon nitride may be formed. In addition to a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, an aluminum nitride oxide film, and the like may also be used.

As a film constituting the insulating film 36, an oxide insulating film having a blocking effect against oxygen, hydrogen, water, and the like may be provided. Examples of such an oxide insulating film include aluminum oxide,
Examples of the oxide include aluminum oxide, gallium oxide, gallium oxide nitride, yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride.

The thickness of the insulating film 36 may be set to 50 nm or more and 300 nm or less, and preferably 100
By forming the insulating film 36 having a blocking effect against oxygen, hydrogen, water, and the like, diffusion of oxygen from the oxide semiconductor films 31 to 33 to the outside and entry of hydrogen, water, and the like from the outside into the oxide semiconductor films 31 to 33 can be prevented.

When forming a silicon nitride film as the insulating film 36 by plasma CVD, it is preferable to use a deposition gas containing silicon, nitrogen, and ammonia as source gases. By using these source gases, ammonia dissociates in the plasma to generate active species. The active species breaks the bonds between silicon and hydrogen and the triple bonds of nitrogen contained in the deposition gas containing silicon. As a result, the bonds between silicon and nitrogen are promoted, and a dense silicon nitride film with fewer bonds between silicon and hydrogen and fewer defects can be formed. On the other hand, if the amount of ammonia relative to nitrogen in the source gas is large, the decomposition of the deposition gas containing silicon and nitrogen does not proceed, and silicon and hydrogen bonds remain, resulting in increased defects.
In addition, a rough silicon nitride film is formed. For these reasons, it is preferable that the flow rate ratio of nitrogen to ammonia in the source gas is set to 5 or more and 50 or less, and more preferably 10 or more and 50 or less.

After the insulating film 35 is formed, heat treatment may be performed. The temperature of the heat treatment is typically
150° C. or higher and lower than the substrate distortion point, preferably 200° C. or higher and 450° C. or lower, more preferably 3
The heat treatment is performed at a temperature of 350° C. or higher and 450° C. or lower. By the heat treatment, oxygen contained in the oxide insulating film which constitutes the second layer of the insulating film 35 can be moved to the oxide semiconductor films 31 to 33, thereby reducing oxygen vacancies contained in these films. The heat treatment may be performed in a mixed gas atmosphere containing nitrogen and oxygen at a heating temperature of 350° C. for one hour.

After the insulating film 36 is formed, heat treatment may be performed in order to release hydrogen and the like from the oxide semiconductor films 31 to 33. This heat treatment may be performed in a mixed gas atmosphere containing nitrogen and oxygen at a heating temperature of 350° C. for one hour, for example.

[Backgate electrode]
The back gate electrodes (BGE1, BGE2) can be formed in the same manner as the gate electrodes (GE1, GE2, GE3).

Below are some other examples of transistor configurations.

(Transistors TA3, TA4)
29A and 29B are top views (layout diagrams) of the transistors TA3 and TA4, respectively, and their circuit symbols.
A cross-sectional view taken along lines a9-a10 and b9-b10 of A4 is shown.

The transistor TA3 includes a gate electrode GE4, an oxide semiconductor film OS4, a source electrode SE4,
The transistor TA3 has a drain electrode DE4 and a back gate electrode BGE4. The transistor TA3 is a modified example of the transistor TA1, and is different from the transistor TA1 in that the electrode BGE4 is in contact with the electrode GE4 at two openings CG4 and CG5.
As shown in FIG. 30B, the film OS4 is disposed between the electrode GE4 and the gate electrode GE4 in the channel width direction.
and electrode BGE4, which can further improve the strength of the transistor TA3.

The transistor TA4 includes a gate electrode GE5, an oxide semiconductor film OS5, a source electrode SE5,
The transistor TA4 has a drain electrode DE5 and a back gate electrode BGE5. The transistor TA4 is a modification of the transistor TA2, in which the electrode BGE5 is not connected to the electrode GE5.
For example, a signal for controlling the conductive state of the transistor TA4 is input to the electrode GE5, and a signal for controlling the conductive state of the transistor TA4 is input to the electrode BGE5.
It is possible to input a signal or potential that corrects the threshold voltage of the transistor.

(Transistors TC1, TB2, TD1)
31A, 31B, and 31C are top views (layout diagrams) of the transistors TC1, TB2, and TD1, respectively, and their circuit symbols.
11b12 line, a13-a14 line and b13-b1 line of transistor TB2
A cross-sectional view taken along line 4, and lines a15-a16 and b15-b16 of transistor TD1
A cross-sectional view along a line is shown.

The transistor TC1 includes a gate electrode GE6, an oxide semiconductor film OS6, a source electrode SE6,
The drain electrode DE6 and the back gate electrode BGE6 are provided.
G6 is in contact with the electrode GE6. The transistor TC1 is a modified example of the transistor TA1, and the film OS6 has a two-layer structure. The film OS6 is composed of "32" and "33". The transistor TC1 is also a transistor whose channel formation region is composed of "32" like the transistor TA1. Therefore, the transistor TC1 is also a transistor with a high field effect mobility like the transistor TA1, and typically has a field effect mobility of 10 c
m ² /Vs or more and less than 60 cm ² /Vs, preferably 15 cm ² /Vs or more and 50 cm
² /Vs. Therefore, the transistor TC1 and the transistor TA1
Similarly, the present invention is suitable for transistors that are operated at high speeds, such as in driving circuits.

The transistor TB2 includes a gate electrode GE7, an oxide semiconductor film OS7, a source electrode SE7,
The drain electrode DE7 and the back gate electrode BGE7 are provided.
The transistor TB2 is a modified example of the transistor TB1, and differs from the transistor TB2 in that it has an electrode BGE7.
Since the transistor 2 has an electrode BGE7 connected to the electrode GE7, the transistor 2 has a higher on-state current than the transistor TB1 and has improved mechanical strength.

The transistor TD1 includes a gate electrode GE8, an oxide semiconductor film OS8, a source electrode SE8,
and a drain electrode DE8. The transistor TD1 is a modification of the transistor TB1, in which the entire film OS8 overlaps the electrode GE8 and does not have a portion outside the edge of the electrode GE8. In this way, the transistor TD1 has a film OS8 similar to that of the transistor TB1.
Since the SiO 2 film has a structure that is less exposed to light than the SiO 2 film, the SiO 2 film is suitable for use in a pixel portion.

Films (insulating film, oxide semiconductor film, metal oxide film, conductive film, etc.) constituting the transistors TA1, TA2, and TB1 can be formed by sputtering, chemical vapor deposition (CVD), vacuum evaporation, or pulsed laser deposition (PLD). Alternatively, they can be formed by coating or printing. Representative film formation methods include sputtering and plasma enhanced chemical vapor deposition (PECVD), but thermal CVD may also be used. Examples of thermal CVD methods include metal-organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD).

In the thermal CVD method, the pressure in the chamber is set to atmospheric pressure or reduced pressure, and a source gas and an oxidizing agent are simultaneously fed into the chamber, and the gas and the oxidizing agent are reacted near or on the substrate to deposit the film on the substrate. In this way, the thermal CVD method is a film formation method that does not generate plasma, and therefore has the advantage that defects due to plasma damage are not generated.

In the ALD method, the pressure inside the chamber is set to atmospheric pressure or reduced pressure, and source gases for reaction are sequentially introduced into the chamber, and the order of gas introduction is repeated to form a film. For example,
Two or more kinds of source gases are supplied to the chamber in sequence by switching each switching valve (also called high-speed valve), and an inert gas (argon, nitrogen, etc.) is introduced simultaneously with or after the first source gas so that the multiple source gases are not mixed, and then the second source gas is introduced. When the inert gas is introduced simultaneously, the inert gas serves as a carrier gas, and the inert gas may be introduced simultaneously with the introduction of the second source gas. Alternatively, instead of introducing the inert gas, the first source gas may be exhausted by vacuum evacuation, and then the second source gas may be introduced. The first source gas is adsorbed on the surface of the substrate to form a first monoatomic layer, and reacts with the second source gas introduced later, so that the second monoatomic layer is stacked on the first monoatomic layer to form a thin film.

By controlling the gas introduction sequence and repeating the process several times until the desired thickness is achieved, a thin film with excellent step coverage can be formed. The thickness of the thin film can be adjusted by the number of times the gas introduction sequence is repeated, allowing precise film thickness adjustment, which is suitable for the production of fine transistors.

〈Specific pixel configuration example 3〉

17 shows an example of a specific configuration of the pixel 10 shown in FIG. 1. The pixel 10 shown in FIG. 17 is different from the pixel 10 shown in FIG. 4A in the position of the transistor 19t. Specifically,
The pixel 10 shown in FIG. 17 has a different configuration from the pixel 10 shown in FIG. 4A in that a transistor 19t is connected between a wiring VL and the other of the source and drain of the transistor 11 and one of the source and drain of the transistor 16t.

Fig. 18 shows an example of a specific configuration of the pixel 10 shown in Fig. 1. The pixel 10 shown in Fig. 18 differs from the pixel 10 shown in Fig. 15A in the position of a transistor 19t. Specifically, the pixel 10 shown in Fig. 18 differs from the pixel 10 shown in Fig. 15A in that the transistor 19t is connected between the wiring VL and the other of the source and drain of the transistor 11 and between the source and drain of the transistor 16t.

In the pixel 10 of the light-emitting device according to one embodiment of the present invention, a transistor other than the transistor 11 may have at least a gate on one side of a semiconductor film, but may further have another gate overlapping with the gate via a semiconductor film. When a transistor other than the transistor 11 has a pair of gates, if one of the pair of gates is a back gate, the same potential may be applied to the normal gate and the back gate, or a fixed potential such as a ground potential may be applied only to the back gate.
By controlling the potential applied to the back gate, the threshold voltage of the transistor can be controlled. In addition, by providing the back gate, the channel formation region can be increased, and the drain current can be increased. In addition, by providing the back gate, a depletion layer can be easily formed in the semiconductor film, and therefore the S value can be improved.

<Transistor Configuration Example 2>
The transistor used in the light-emitting device according to one embodiment of the present invention may have a channel formation region in a semiconductor film or a semiconductor substrate of amorphous, microcrystalline, polycrystalline, or single-crystalline silicon or germanium, etc. When a transistor is formed using a thin film of silicon, the thin film may be made of amorphous silicon manufactured by a vapor phase growth method such as a plasma CVD method or a sputtering method, polycrystalline silicon obtained by crystallizing amorphous silicon by a process such as laser annealing, or single-crystalline silicon obtained by injecting hydrogen ions or the like into a single-crystalline silicon wafer to peel off the surface layer.

34 is a cross-sectional view of a transistor including a thin silicon film that can be used in a light-emitting device according to one embodiment of the present invention. In FIG. 34, an n-channel transistor 70
and a p-channel transistor 71.

The transistor 70 is formed by forming a conductive film 73 functioning as a gate on a substrate 72 having an insulating surface.
an insulating film 74 over the conductive film 73; a semiconductor film 75 overlapping with the conductive film 73 with the insulating film 74 interposed therebetween; an insulating film 76 over the semiconductor film 75; conductive films 77a and 77b overlapping with the semiconductor film 75 with the insulating film 76 interposed therebetween and functioning as gates; an insulating film 78 over the conductive films 77a and 77b; an insulating film 79 over the insulating film 78;
9, a conductive film 80 and a conductive film 81 are electrically connected to the semiconductor film 75 and function as a source or a drain.

The conductive film 77b has a width in the channel length direction shorter than that of the conductive film 77a, and the conductive films 77a and 77b are stacked in this order from the insulating film 76 side. The semiconductor film 75 has a channel formation region 82 at a position overlapping with the conductive film 77b, a pair of LDD (light doped drain) regions 83 positioned to sandwich the channel formation region 82 therebetween, and a pair of impurity regions 84 positioned to sandwich the channel formation region 82 and the LDD region 83 therebetween. The pair of impurity regions 84 function as a source region or a drain region.
The DD region 83 and the impurity region 84 are doped with an impurity element that imparts n-type conductivity to the semiconductor film 75, such as boron (B), aluminum (Al), or gallium (Ga).

In addition, the transistor 71 includes a conductive film 85 functioning as a gate, an insulating film 74 over the conductive film 85, a semiconductor film 86 overlapping with the conductive film 85 with the insulating film 74 interposed therebetween, an insulating film 76 over the semiconductor film 86, and a semiconductor film 86 overlapping with the insulating film 76 interposed therebetween, over a substrate 72 having an insulating surface.
A conductive film 87a and a conductive film 87b overlap with each other and function as a gate.
a and the conductive film 87b, an insulating film 79 on the insulating film 78, and a conductive film 88 and a conductive film 89 which are electrically connected to the semiconductor film 86 in openings provided in the insulating film 78 and the insulating film 79 and function as a source or a drain.

The conductive film 87b has a width in the channel length direction shorter than that of the conductive film 87a, and the conductive films 87a and 87b are stacked in this order from the insulating film 76 side. The semiconductor film 75 has a channel formation region 90 at a position overlapping with the conductive film 87b, and a pair of impurity regions 91 positioned to sandwich the channel formation region 90 therebetween. The pair of impurity regions 91 function as a source region or a drain region. The impurity regions 91 impart p-type conductivity to the semiconductor film 86.
Impurity elements such as phosphorus (P) and arsenic (As) are added to the silicon substrate.

The semiconductor film 75 or the semiconductor film 86 may be crystallized by various techniques. Examples of the various crystallization methods include a laser crystallization method using laser light and a crystallization method using a catalytic element. Alternatively, a crystallization method using a catalytic element and a laser crystallization method may be combined. When a substrate having excellent heat resistance such as quartz is used as the substrate 72, a crystallization method that combines a thermal crystallization method using an electric furnace, a lamp annealing crystallization method using infrared light, a crystallization method using a catalytic element, and high-temperature annealing at about 950° C. may be used.

<Method 1 for manufacturing a light-emitting device>
Next, a method for manufacturing the light-emitting device 400 according to one embodiment of the present invention will be described with reference to FIGS.
This will be explained using:

First, an insulating film 420 is formed over a substrate 462, and a first element layer 410 is formed over the insulating film 420 (see FIG. 19A). The first element layer 410 includes a semiconductor element.
Alternatively, in the first element layer 410, in addition to a semiconductor element, a display element or a part of a display element such as a pixel electrode may be provided.

The substrate 462 must have at least a heat resistance sufficient to withstand subsequent heat treatments. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 462.
It may also be used as 62.

When a glass substrate is used as the substrate 462, it is preferable to form an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a silicon nitride oxide film between the substrate 462 and the insulating film 420 because contamination from the glass substrate can be prevented.

For the insulating film 420, for example, an organic resin film such as an epoxy resin, an aramid resin, an acrylic resin, a polyimide resin, a polyamide resin, or a polyamideimide resin can be used. Among them, it is preferable to use a polyimide resin because of its high heat resistance. For example,
When a polyimide resin is used, the film thickness of the polyimide resin is 3 nm to 20 μm, preferably 500 nm to 2 μm. When a polyimide resin is used as the insulating film 420, it can be formed by a spin coating method, a dip coating method, a doctor blade method, or the like. For example, when a polyimide resin is used as the insulating film 420, a part of the film using the polyimide resin can be removed by a doctor blade method to obtain an insulating film 420 having a desired thickness.

Note that the temperature in the manufacturing process of the first element layer 410 is preferably from room temperature to 300° C. For example, the insulating film or conductive film using an inorganic material included in the first element layer 410 is preferably formed at a film formation temperature of from 150° C. to 300° C., further preferably from 200° C. to 270° C. In addition, the insulating film or the like using an organic resin material included in the first element layer 410 is preferably formed at a film formation temperature of from room temperature to 100° C.

In addition, the oxide semiconductor film of the transistor included in the first element layer 410 may be formed using the above-described CA
It is preferable to use AC-OS for the oxide semiconductor film of the transistor.
When S is used, for example, when the light emitting device 400 is bent, cracks or the like are less likely to occur in the channel formation region, and resistance to bending can be increased.

In addition, it is preferable to use indium tin oxide to which silicon oxide is added as the conductive film included in the first element layer 410 because cracks or the like are less likely to occur in the conductive film when the light-emitting device 400 is bent.

Next, the first element layer 410 and a temporary support substrate 466 are bonded to each other using a peeling adhesive 464, and the insulating film 420 and the first element layer 410 are peeled off from the substrate 462. As a result, the insulating film 420 and the first element layer 410 are provided on the temporary support substrate 466 side (see FIG. 19B).
.

The temporary support substrate 466 may be a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate,
A metal substrate or the like can be used. A plastic substrate having heat resistance capable of withstanding the processing temperature of this embodiment mode may be used, or a flexible substrate such as a film may be used.

As the peeling adhesive 464, an adhesive that can chemically or physically separate the temporary support substrate 466 and the element layer 410 when necessary, such as an adhesive that is soluble in water or a solvent, or an adhesive that can be plasticized by exposure to ultraviolet light, etc., is used.

Note that the transfer step to the temporary support substrate 466 can be performed by using various methods as appropriate. For example, the insulating film 420 can be weakened by irradiating the insulating film 420 with laser light 468 from the side of the substrate 462 where the insulating film 420 is not formed, that is, the lower side shown in FIG. 19B, and then the substrate 462 and the insulating film 420 can be peeled off. In addition, by adjusting the irradiation energy density of the laser light 468, a region where the adhesion between the substrate 462 and the insulating film 420 is high and a region where the adhesion between the substrate 462 and the insulating film 420 is low may be formed separately before peeling.

Note that, although the method of peeling off at the interface between the substrate 462 and the insulating film 420 is described as an example in this embodiment, the present invention is not limited to this. For example, peeling off at the interface between the insulating film 420 and the first element layer 410 may also be performed.

In addition, the liquid is allowed to penetrate into the interface between the substrate 462 and the insulating film 420 to remove the insulating film 420 from the substrate 462.
0 may be peeled off. Alternatively, a liquid may be permeated into the interface between the insulating film 420 and the first element layer 410 to peel off the first element layer 410 from the insulating film 420. As the liquid, for example, water, a polar solvent, or the like may be used. By permeating a liquid into the interface at which the insulating film 420 is peeled off, specifically, the interface between the substrate 462 and the insulating film 420 or the interface between the insulating film 420 and the first element layer 410, it is possible to suppress the influence of static electricity and the like that is generated due to peeling and applied to the first element layer 410.

Next, the first substrate 401 is bonded to the insulating film 420 using the adhesive layer 418 (FIG. 19(
See C).

Next, the peeling adhesive 464 is dissolved or plasticized, and the peeling adhesive 464 and the temporary supporting substrate 466 are removed from the first element layer 410 (see FIG. 19D).

It is preferable to remove the peeling adhesive 464 with water, a solvent, or the like so that the surface of the first element layer 410 is exposed.

By the above steps, the first element layer 410 can be fabricated on the first substrate 401.

Next, the second substrate 4 is formed by the same method as the steps shown in FIGS.
05, an adhesive layer 412 on the second substrate 405, an insulating film 440 on the adhesive layer 412, and
Then, an element layer 411 is formed (see FIG. 20A).

The insulating film 440 included in the second element layer 411 can be formed using a material similar to that of the insulating film 420, that is, an organic resin here.

Next, a sealing layer 432 is filled between the first element layer 410 and the second element layer 411, and the first element layer 410 and the second element layer 411 are attached to each other (see FIG. 20B).

For example, solid sealing can be achieved by the sealing layer 432. However, a flexible configuration is preferable for the sealing layer 432. For example, a glass material such as glass frit, a curable resin that cures at room temperature such as a two-liquid mixed resin, a photocurable resin, a thermosetting resin, or other resin material can be used for the sealing layer 432.

By the above steps, the light emitting device 400 can be produced.

<Method 2 for manufacturing a light-emitting device>
Next, another method for manufacturing the light-emitting device 400 according to one embodiment of the present invention will be described with reference to Fig. 21. Note that a structure in which inorganic insulating films are used as the insulating films 420 and 440 will be described with reference to Fig. 21.

First, a peeling layer 463 is formed over a substrate 462. Next, an insulating film 420 is formed over the peeling layer 463, and a first element layer 410 is formed over the insulating film 420 (see FIG. 21A).

The peeling layer 463 may have a single layer or a stacked structure containing an element selected from tungsten, molybdenum, titanium, tantalum, niobium, nickel, cobalt, zirconium, zinc, ruthenium, rhodium, palladium, osmium, iridium, and silicon, an alloy material containing the element, or a compound material containing the element. In the case of a layer containing silicon, the crystal structure of the layer containing silicon may be any of amorphous, microcrystalline, polycrystalline, and single crystalline.

The peeling layer 463 can be formed by a sputtering method, a PECVD method, a coating method, a printing method, etc. Note that the coating method includes a spin coating method, a droplet discharging method, and a dispensing method.

When the peeling layer 463 has a single-layer structure, it is preferable to form a layer containing tungsten, molybdenum, or a mixture of tungsten and molybdenum. Alternatively, a layer containing an oxide or oxynitride of tungsten, a layer containing an oxide or oxynitride of molybdenum, or a layer containing an oxide or oxynitride of a mixture of tungsten and molybdenum may be formed. Note that the mixture of tungsten and molybdenum corresponds to, for example, an alloy of tungsten and molybdenum.

In addition, when forming a laminated structure of a layer containing tungsten and a layer containing tungsten oxide as the peeling layer 463, it is possible to utilize the fact that a layer containing tungsten oxide is formed at the interface between the tungsten layer and the insulating layer by forming a layer containing tungsten and forming an insulating layer made of oxide on the layer containing tungsten. In addition, the surface of the layer containing tungsten may be subjected to thermal oxidation treatment, oxygen plasma treatment, nitrous oxide (N ₂ O) plasma treatment, treatment with a solution having a strong oxidizing power such as ozone water, or the like to form a layer containing tungsten oxide. In addition, the plasma treatment or heat treatment may be performed in an atmosphere of oxygen, nitrogen, or nitrous oxide alone, or a mixed gas atmosphere of the gas and other gases. The peeling layer 463 may be formed by the above-mentioned plasma treatment or heat treatment.
By changing the surface state of the peeling layer 463, it is possible to control the adhesion between the peeling layer 463 and the insulating film 420 to be formed later.

For example, an inorganic insulating film having low moisture permeability, such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, or an aluminum oxide film, can be used for the insulating film 420. The inorganic insulating film can be formed by, for example, a sputtering method, a PECVD method, or the like.

Next, the first element layer 410 and a temporary support substrate 466 are bonded to each other using a peeling adhesive 464, and the insulating film 420 and the first element layer 410 are peeled off from the peeling layer 463. As a result, the insulating film 420 and the first element layer 410 are provided on the temporary support substrate 466 side (see FIG. 21B ).

Note that various methods can be appropriately used for the transfer step to the temporary support substrate 466. For example, when a layer including a metal oxide film is formed at the interface between the peeling layer 463 and the insulating film 420, the metal oxide film can be weakened by crystallization, and the insulating film 420 can be peeled off from the peeling layer 463. When the peeling layer 463 is formed of a tungsten film, the tungsten film may be etched with a mixed solution of ammonia water and hydrogen peroxide water to perform peeling.

Alternatively, the insulating film 420 may be peeled off from the peeling layer 463 by penetrating a liquid into the interface between the peeling layer 463 and the insulating film 420. As the liquid, for example, water, a polar solvent, or the like can be used. By penetrating a liquid into the interface at which the insulating film 420 is peeled off, specifically, the interface between the peeling layer 463 and the insulating film 420, the influence of static electricity or the like that is generated due to peeling and applied to the first element layer 410 can be suppressed.

Next, the first substrate 401 is bonded to the insulating film 420 using an adhesive layer 418 (FIG. 21C).
reference).

Next, the peeling adhesive 464 is dissolved or plasticized, and the peeling adhesive 464 and the temporary support substrate 466 are removed from the first element layer 410 (see FIG. 21D).

It is preferable to remove the peeling adhesive 464 with water, a solvent, or the like so that the surface of the first element layer 410 is exposed.

By the above steps, the first element layer 410 can be fabricated on the first substrate 401.

Next, the second substrate 4 is formed by the same method as the steps shown in FIGS.
05, an adhesive layer 412 on the second substrate 405, an insulating film 440 on the adhesive layer 412, and
Then, a sealing layer 432 is filled between the first element layer 410 and the second element layer 411, and the first element layer 410 and the second element layer 411 are attached to each other.

Finally, the anisotropic conductive film 380 and the FPC 408 are attached to the connection electrodes 360. If necessary, an IC chip or the like may be mounted.

By the above steps, the light emitting device 400 can be produced.

<Cross-sectional structure of light-emitting device>
22 shows an example of a cross-sectional structure of a pixel portion of a light-emitting device according to one embodiment of the present invention. Note that in FIG. 22, the transistor 11, the capacitor 18, and the like included in the pixel 10 shown in FIG.
1 and 2 show cross-sectional structures of the light-emitting element 14 .

Specifically, the light-emitting device shown in FIG. 22 has a transistor 11 and a capacitor element 18 disposed on a substrate 500.
The transistor 11 includes a conductive film 501 functioning as a first gate, an insulating film 502 over the conductive film 501, a semiconductor film 503 overlapping with the conductive film 501 with the insulating film 502 therebetween, a conductive film 504 and a conductive film 505 functioning as a source or a drain electrically connected to the semiconductor film 503, an insulating film 550 over the semiconductor film 503, the conductive film 504, and the conductive film 505, and a conductive film 551 overlapping with the conductive film 501 with the insulating film 550 therebetween and functioning as a second gate.

The capacitor 18 includes a conductive film 501 which functions as an electrode, an insulating film 502 over the conductive film 501, and a conductive film 504 which overlaps with the conductive film 501 with the insulating film 502 interposed therebetween and which functions as an electrode.

The insulating film 502 may be a single layer or a stack of insulating films containing one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide.
An oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

In addition, an insulating film 511 is provided over the semiconductor film 503, the conductive film 504, and the conductive film 505. When an oxide semiconductor is used for the semiconductor film 503, the insulating film 511 is
It is preferable to use a material capable of supplying oxygen to the insulating film 5.
By using the insulating film 511 as the insulating film 503, oxygen contained in the insulating film 511 can be moved to the semiconductor film 503, thereby reducing the amount of oxygen vacancies in the semiconductor film 503. The oxygen contained in the insulating film 511 can be efficiently moved to the semiconductor film 503 by performing heat treatment after the insulating film 511 is formed.

An insulating film 520 is provided over the insulating film 511, and a conductive film 524 is provided over the insulating film 520. The conductive film 524 is connected to the conductive film 504 in an opening provided in the insulating film 511 and the insulating film 520.

An insulating film 525 is provided over the insulating film 520 and the conductive film 524. The insulating film 525 is
The insulating film 525 has an opening at a position overlapping with the conductive film 524.
An insulating film 526 is provided at a position different from the opening of the insulating film 525.
An EL layer 527 and a conductive film 528 are stacked in this order over the insulating film 526. A portion where the conductive film 524 and the conductive film 528 overlap with the EL layer 527 sandwiched therebetween functions as the light-emitting element 14. One of the conductive film 524 and the conductive film 528 functions as an anode and the other functions as a cathode.

The light emitting device also has a substrate 530 that faces the substrate 500 with the light emitting element 14 sandwiched therebetween. A shielding film 531 having a function of shielding light is provided on the substrate 530, i.e., on the surface of the substrate 530 that is closer to the light emitting element 14. The shielding film 531 is provided on the light emitting element 1.
The substrate 53 has an opening in a region overlapping the light emitting element 14.
A colored layer 532 that transmits visible light in a specific wavelength range is provided on the substrate 530 .

<Appearance of the light-emitting device>
23A is a perspective view showing an example of the appearance of a light-emitting device according to one embodiment of the present invention. The light-emitting device shown in Fig. 23A includes a panel 1601, a circuit board 1602 provided with a controller, a power supply circuit, an image processing circuit, an image memory, a CPU, and the like, and a connection portion 1603. The panel 1601 includes a pixel portion 1604 in which a plurality of pixels are provided, a driver circuit 1605 that selects the plurality of pixels for each row, and a driver circuit 1606 that controls input of an image signal Sig to the pixels in the selected row.

Various signals and a power supply potential are input to the panel 1601 from the circuit board 1602 via the connection portion 1603. The connection portion 1603 is connected to an FPC (Flexible Printed Circuit).
The FPC with the chip mounted on it can be used as a CO
This is called COF tape, and the use of COF tape allows for higher density mounting in a smaller area. When using COF tape for the connection portion 1603, a part of the circuits in the circuit board 1602, or a part of the driver circuit 1605 or 1606 of the panel 1601, may be formed on a separately prepared chip, and the chip may be connected to the COF tape by using a COF (chip on film) method.

FIG. 23B is a perspective view showing an example of the appearance of a light-emitting device using the COF tape 1607.
As shown in.

The chip 1608 is a semiconductor bare chip (IC, LSI, etc.) having terminals such as bumps on its surface. Furthermore, CR parts can also be mounted on the COF tape 1607, and the circuit board 1602
The area of the flexible substrate can be reduced. A plurality of wiring patterns are formed on the flexible substrate in correspondence with the terminals of the chip to be mounted. The chip 1608 is positioned and placed on the flexible substrate having the wiring patterns by a bonder device or the like, and is mounted by thermocompression bonding.

23B shows an example of one COF tape 1607 on which one chip 1608 is mounted, but this is not particularly limited. Although multiple rows of chips can be mounted on one or both sides of one COF tape 1607, in order to reduce costs, it is preferable to mount one row of chips to reduce the number of chips to be mounted, and more preferably, it is preferable to mount only one chip.

<Example of circuit board configuration>
25 shows an external view of the circuit board 2003. The circuit board 2003 has a Bluetooth (registered trademark) compliant IEEE802.15.1 on an FPC 2201 having a slit 2211.
) standard communication device 2101, microcomputer 2102, storage device 2103, FPGA 2
104, a DA converter 2105, a charging control IC 2106, and a level shifter 2107 are provided. The circuit board 2003 is electrically connected to the light-emitting device according to one embodiment of the present invention through an input/output connector 2108. The FPC 2201 has a slit 2211.
By providing the FPC 2201, the flexibility of the circuit board 2003 using the FPC 2201 is increased.

By using a flexible substrate in the light-emitting device according to one embodiment of the present invention, the circuit board 200
The light emitting device can be curved together with the flexible substrate 2003. Therefore, the light emitting device using the flexible substrate and the circuit substrate 2003 can be repeatedly deformed to fit the shape of the part where it is worn, and are therefore suitable for use in electronic devices that can be worn on the body, such as on the arm or leg.

<Configuration Example of Information Processing Device>
FIG. 26A is a schematic diagram illustrating the appearance of a data processing device 1000 of one embodiment of the present invention.
26B is a cross-sectional view illustrating a cross-sectional structure taken along line X1-X2 in FIG. 26A. In addition, FIG. 26C and FIG. 26D are cross-sectional views illustrating a cross-sectional structure of the information processing device 1 according to one embodiment of the present invention.
26(D) is a schematic diagram for explaining the appearance of FIG. 26(E) and FIG. 26(C).
26(C) is a schematic diagram illustrating the front of the information processing device 1000. FIG. 26(D) is a schematic diagram illustrating the front of the information processing device 1000.
1 is a schematic diagram illustrating the rear surface of .00.

As shown in Fig. 26(C) and Fig. 26(D), the position input unit 1001 or the display unit 1002 may be provided not only on the front surface of the information processing device 1000, but also on the side surface or rear surface. Also, the position input unit 1001 or the display unit 1002 may be provided on the top surface of the information processing device 1000. Also, the position input unit 1001 or the display unit 1002 may be provided on the front surface of the information processing device 1000.
0 may be provided on the bottom surface.

In addition to the position input unit 1001, the surface of the housing 1003 may have hardware buttons, external connection terminals, and the like.

With this configuration, it is possible to display not only on a surface parallel to the front of the housing 1003 as in conventional information processing devices, but also on the side surfaces of the housing 1003. In particular, providing display areas along two or more side surfaces of the housing 1003 is preferable because it further increases the diversity of display.

The display area arranged along the front surface of the information processing device and the display areas arranged along the sides may be used as independent display areas to display different images, or any two of them ...
For example, an image displayed in a display area arranged along the front surface of the information processing device may be continuously displayed in a display area provided along a side surface of the information processing device.

The arithmetic device 1005 is provided inside the housing 1003.
The arithmetic device 1005 is provided at a position separated from the display portion 1002. In FIG.

The position input unit 1001, for example, includes a first area 1001(1) and a second area 100
A second region 1001(2) facing the first region 1001(1) and a second region 1001(2) facing the first region 1001(1) and the second region 1001(2) facing the second region 1001(1)
The insulating film has flexibility that allows it to be folded so as to form a first region 1001(1), a third region 1001(3), and a fourth region 1001(4) opposed to the third region 1001(3) between the first region 1001(2) and the second region 1001(3) (see FIG. 26(B)). As another example, the insulating film has flexibility that allows it to be folded so as to form a first region 1001(1), a third region 1001(3), and a fourth region 1001(4) opposed to the third region 1001(3) (see FIG. 26(E)).

As another example, the insulating film 1002 may have flexibility such that it can be bent so as to form a third region 1001(3), a fifth region 1001(5), and a fourth region 1001(4) opposite the third region 1001(3).

The arrangement of the second region 1001(2) facing the first region 1001(1) is not limited to being directly opposite the first region 1001(1), but may also include an arrangement in which the second region 1001(2) faces the first region 1001(1) at an angle. The arrangement of the fourth region 1001(4) facing the third region 1001(3) is not limited to being directly opposite the third region 1001(3), but may also include an arrangement in which the fourth region 1001(4) faces the third region 1001(3).
This also includes an arrangement in which the area faces the area 1001(3) at an angle.

The display unit 1002 includes at least a first area 1001(1), a second area 1001(2),
It is disposed so as to overlap a part of the third region 1001(3) or the fourth region 1001(4).

The information processing device 1000 includes a flexible position input unit 100 that detects an object in proximity or in contact with the object.
1. The position input unit 1001 is configured to include, for example, a first area 1001 (
1), a second region 1001(2) facing the first region, and the first region 1001(1).
A third region 1001 (3) overlapping the display unit 1002 is disposed between the second region 1001 (2).
) and can be folded so as to form. This makes it possible to know whether, for example, the palm or any of the fingers of the hand is close to the first region 1001(1) or the second region 1001(2). As a result, a human interface with excellent operability can be provided. Alternatively, a novel information processing device with excellent operability can be provided.

A resin having a thickness sufficient to provide flexibility can be used as a substrate for the display unit 1002. Examples of the resin include polyester, polyolefin, polyamide, polyimide, aramid, epoxy, polycarbonate, and acrylic resins. Examples of normal substrates that do not have flexibility include glass substrates, quartz substrates, and semiconductor substrates.

<Examples of electronic device configurations>
The light-emitting device according to one embodiment of the present invention is applicable to a display device, a notebook personal computer, an image reproducing device including a recording medium (typically, a DVD: Digital Versatile Disc,
Other examples of electronic devices in which the light-emitting device according to one embodiment of the present invention can be used include mobile phones, portable game consoles, portable information terminals, e-books, cameras such as video cameras and digital still cameras, and goggle displays (head-mounted displays).
, navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer-combination machines, automated teller machines (ATMs), vending machines, etc. Specific examples of these electronic devices are shown in FIG.

24A shows a display device including a housing 5001, a display portion 5002, a support stand 5003, and the like. A light-emitting device according to one embodiment of the present invention can be used for the display portion 5002.
The display device includes all display devices for displaying information, such as those for personal computers, those for receiving TV broadcasts, and those for displaying advertisements.

FIG. 24B shows a portable information terminal, which includes a housing 5101, a display portion 5102, and operation keys 5103.
The light-emitting device according to one embodiment of the present invention can be used for the display portion 5102.

24C shows a display device including a curved housing 5701, a display portion 5702, and the like. By using a flexible substrate for the light-emitting device according to one embodiment of the present invention, the light-emitting device can be used for the display portion 5702 supported by the curved housing 5701, and a flexible, lightweight, and easy-to-use display device can be provided.

FIG. 24D shows a portable game machine, which includes a housing 5301, a housing 5302, a display portion 5303,
The display unit 5304 includes a microphone 5305, a speaker 5306, operation keys 5307, a stylus 5308, and the like. The light-emitting device according to one embodiment of the present invention can be used for the display unit 5303 or the display unit 5304. By using the light-emitting device according to one embodiment of the present invention for the display unit 5303 or the display unit 5304, a portable game machine that is comfortable to use and unlikely to deteriorate in quality can be provided. Note that although the portable game machine shown in FIG. 24D includes two display units 5303 and 5304, the number of display units included in the portable game machine is not limited to this.

24E shows an e-book reader which includes a housing 5601, a display portion 5602, and the like. The light-emitting device according to one embodiment of the present invention can be used for the display portion 5602. By using a flexible substrate, the light-emitting device can be made flexible; therefore, a flexible, lightweight, and easy-to-use e-book reader can be provided.

24F shows a mobile phone, in which a housing 5901 is provided with a display portion 5902, a microphone 5907, a speaker 5904, a camera 5903, an external connection portion 5906, and operation buttons 5905. The light-emitting device according to one embodiment of the present invention can be used for the display portion 5902.
In addition, when the light-emitting device according to one embodiment of the present invention is formed over a flexible substrate,
The light emitting device can be applied to a display portion 5902 having a curved surface as shown in FIG.

Example
In this embodiment, a display device manufactured using the pixel shown in the above embodiment mode will be described.

First, the characteristics of the transistor used in the pixel were measured.
The OS transistor is formed using an AC-OS film. The CAAC-OS film is an In—Ga
It was formed using Zn oxide.

FIG. 42A shows the measurement results of the IV characteristics of an OS transistor.
The measurement results are shown when the drain voltage (Vds) was 0.1 V and 10 V. Note that the OS transistor had a channel length L of 6 μm and a channel width W of 6 μm. A backgate was provided in the OS transistor, and the measurement was performed when the backgate-source voltage (Vbgs) was 0 V.

The measurement was performed at 20 points on the same substrate. The median threshold voltage of the OS transistor obtained by the measurement was 4.38 V, and the variation in the threshold voltage was 3σ=0.88 V.

By providing a back gate, a drain induced barrier (DIBL) is realized.
In the case of a single gate structure without a back gate, the channel length modulation coefficient was about 0.05 V ⁻¹ , whereas in the case of a back gate, it was about 0.009 V ⁻¹ , and the saturation property was improved.

Next, the measurement results of the Vbgs dependence of the threshold voltage Vth of the OS transistor are shown in FIG.
42B is a graph in which the I-V characteristics of an OS transistor are measured while Vbgs is changed with the source potential of the OS transistor being fixed, and the threshold voltage is calculated from the measurement results and plotted. Note that FIG. 42B shows the measurement results when Vds=10 V.

It can be seen that when Vbgs changes to the positive side, the threshold voltage shifts to the negative side, and when Vbgs changes to the negative side, the threshold voltage shifts to the positive side.
It can be seen that the threshold voltage shifts linearly with respect to Vbgs. The amount of shift in threshold voltage also depends on the thickness of the interlayer film between the channel section and the back gate section and the dielectric constant of the interlayer film. The thicker the interlayer film is and the lower the dielectric constant is, the smaller the effect of Vbgs on the threshold voltage becomes.

A pixel was constructed using the above OS transistor. FIG. 43A shows a circuit configuration of the pixel. The pixel shown in FIG. 43A corresponds to the pixel 10 shown in FIG. 3B and FIG. 4B. The pixel shown in FIG. 43A was driven according to the timing chart shown in FIG. 43B to correct the threshold voltage. The above embodiment can be referred to for the operation of correcting the threshold voltage. In the period I, G3 is at a high level, Tr4 is in an on state, and the source potential of the driving transistor DrTr is a potential obtained by adding the CATHODE potential to the OLED threshold Vth _OLED .

The specifications of the display device manufactured using the above pixels are shown in Table 1. The resolution of the display device is 302.
The aperture ratio was 61%. The scan driver was built into the glass.
The source driver uses a COF.

The display device was a top-emission type using a white EL element and a color filter (CF). The structure of the display device is shown in FIG.

The white EL element had a layered structure as shown in Fig. 44(B) . The white EL element had a two-layer tandem element structure in which a light-emitting unit made of a blue fluorescent material and a light-emitting unit made of green and red phosphorescent materials were connected in series.

Figure 45 shows a display image of the display device that was actually manufactured. There was no unevenness in the display image.
You can see that it is displayed correctly.

46 shows the calculation results when the threshold voltage of the driving transistor DrTr shown in FIG. 43A is changed. Here, ΔVth on the horizontal axis of the graph is the amount of Vth shift due to the correction of the threshold voltage. Also, Vgs-Vth on the vertical axis of the graph is the shift amount of Vth due to the correction of the threshold voltage in the period IV of FIG. 43B.
This is a value obtained by subtracting the threshold voltage of the driving transistor DrTr after the threshold voltage correction from the Vgs of the driving transistor DrTr during the light emission period of . If the threshold voltage correction is performed normally, the value of Vgs-Vth does not depend on the threshold voltage, so the slope of the graph will be 0.

From the calculation results shown in FIG. 46, Vgs in the range of ΔVth from −1.5 V to +1.5 V
It can be seen that the variation in the −Vth value is suppressed to about 10% of the value of Vgs−Vth when ΔVth=0.

In addition, in the pixel shown in FIG. 43A, if the threshold voltage Vth of the OLED is Vth _OLED , when the threshold voltage Vth of the driving transistor DrTr is a positive value, Vth=0 to V0
It is possible to correct the range in which the potential of −(Cathode+Vth _OLED ) is shifted to the positive side. When the threshold voltage of the driving transistor DrTr is a negative value, Vt
It is possible to correct the variation in threshold voltage from h=0 to a range shifted to the negative side by the potential of Anode-V0. Also, when the variation in the threshold voltage of the driving transistor DrTr falls within a range of positive values, the power supply of V0 can be Anode. In this case, it is possible to reduce the number of power supply lines V0 in the pixel by one.

As described above, by using the present invention, a display device in which the threshold voltage is corrected and display unevenness is reduced can be manufactured.

10 Pixel 11 Transistor 12 Switch 12t Transistor 13 Capacitor 14 Light-emitting element 15 Switch 15t Transistor 16 Switch 16t Transistor 17 Switch 17t Transistor 18 Capacitor 19 Switch 19t Transistor 30 Substrate 31 Oxide semiconductor film 31-32 Oxide semiconductor film 32 Oxide semiconductor film 33 Oxide semiconductor film 34 Insulating film 35 Insulating film 35a Insulating film 35b Insulating film 36 Insulating film 40 Pixel portion 41 Selection circuit 42 Wiring 43 Switch 44 Switch 45 Monitor circuit 46 Operational amplifier 47 Capacitor 48 Switch 49 Wiring 60A Switch 60B Switch 60C Switch 61 Circuit 62A Switch 62B Switch 62C Switch 63A Wiring 63B Wiring 70 Transistor 71 Transistor 72 Substrate 73 Conductive film 74 Insulating film 75 Semiconductor film 76 Insulating film 77a Conductive film 77b Conductive film 78 Insulating film 79 Insulating film 80 Conductive film 81 Conductive film 82 Channel formation region 83 LDD region 84 Impurity region 85 Conductive film 86 Semiconductor film 87a Conductive film 87b Conductive film 88 Conductive film 89 Conductive film 90 Channel formation region 91 Impurity region 360 Connection electrode 380 Anisotropic conductive film 400 Light emitting device 401 Substrate 405 Substrate 408 FPC
410 Element layer 411 Element layer 412 Adhesive layer 418 Adhesive layer 420 Insulating film 432 Sealing layer 440 Insulating film 462 Substrate 463 Peeling layer 464 Peeling adhesive 466 Temporary support substrate 468 Laser light 500 Substrate 501 Conductive film 502 Insulating film 503 Semiconductor film 504 Conductive film 505 Conductive film 511 Insulating film 520 Insulating film 524 Conductive film 525 Insulating film 526 Insulating film 527 EL layer 528 Conductive film 530 Substrate 531 Shielding film 532 Coloring layer 550 Insulating film 551 Conductive film 802 IEEE
1000 Information processing device 1001 Position input section 1001 (1) First area 1001 (2) Second area 1001 (3) Third area 1001 (4) Fourth area 1002 Display section 1003 Housing 1005 Arithmetic device 1601 Panel 1602 Circuit board 1603 Connection section 1604 Pixel section 1605 Driver circuit 1606 Driver circuit 1607 COF tape 1608 Chip 2003 Circuit board 2101 Communication device 2102 Microcomputer 2103 Storage device 2104 FPGA
2105 DA converter 2106 Charging control IC
2107 Level shifter 2108 Input/output connector 2201 FPC
2211 Slit 5001 Housing 5002 Display section 5003 Support stand 5101 Housing 5102 Display section 5103 Operation keys 5301 Housing 5302 Housing 5303 Display section 5304 Display section 5305 Microphone 5306 Speaker 5307 Operation keys 5308 Stylus 5601 Housing 5602 Display section 5701 Housing 5702 Display section 5901 Housing 5902 Display section 5903 Camera 5904 Speaker 5905 Button 5906 External connection section 5907 Microphone

Claims (3)

A light-emitting device including a transistor, first to fourth switches, a first capacitor, a second capacitor, and a light-emitting element,
the first switch has one terminal electrically connected to a first wiring and the other terminal electrically connected to a first gate of the transistor;
one of a source and a drain of the transistor is electrically connected to a second wiring, and the other of the source and the drain is electrically connected to a first electrode of the light-emitting element;
the second switch has one terminal electrically connected to the first gate of the transistor and the other terminal electrically connected to the first electrode of the light-emitting element;
the third switch has one terminal electrically connected to a third wiring and the other terminal electrically connected to the second gate of the transistor;
the fourth switch has one terminal electrically connected to a fourth wiring and the other terminal electrically connected to a first electrode of the light-emitting element;
the first capacitance element has a first electrode electrically connected to a first gate of the transistor and a second electrode electrically connected to the other of the source and the drain of the transistor;
the second capacitance element has a first electrode electrically connected to the second gate of the transistor and a second electrode electrically connected to the other of the source and the drain of the transistor;
The light emitting element has a second electrode electrically connected to the fourth wiring,
a first period during which the third switch is in an on state and the fourth switch is in an off state;
a second period during which the third switch is in an off state and the fourth switch is in an on state;
the first wiring has a function of supplying an image signal;
The second wiring has a function of supplying a first potential,
the third wiring has a function of supplying a second potential;
The fourth wiring has a function of supplying a third potential. A light-emitting device including a transistor, first to fourth switches, a first capacitor, a second capacitor, and a light-emitting element,
the first switch has one terminal electrically connected to a first wiring and the other terminal electrically connected to a first gate of the transistor;
one of a source and a drain of the transistor is electrically connected to a second wiring, and the other of the source and the drain is electrically connected to a first electrode of the light-emitting element;
the second switch has one terminal electrically connected to the first gate of the transistor and the other terminal electrically connected to the first electrode of the light-emitting element;
the third switch has one terminal electrically connected to a third wiring and the other terminal electrically connected to the second gate of the transistor;
the fourth switch has one terminal electrically connected to a fourth wiring and the other terminal electrically connected to a first electrode of the light-emitting element;
the first capacitance element has a first electrode electrically connected to a first gate of the transistor and a second electrode electrically connected to the other of the source and the drain of the transistor;
the second capacitance element has a first electrode electrically connected to a second gate of the transistor and a second electrode electrically connected to the other of the source and the drain of the transistor;
The light emitting element has a second electrode electrically connected to the fourth wiring,
a first period during which the third switch is in an on state and the fourth switch is in an off state;
a second period during which the third switch is in an off state and the fourth switch is in an on state;
the first wiring has a function of supplying an image signal;
The second wiring has a function of supplying a first potential,
the third wiring has a function of supplying a second potential;
the fourth wiring has a function of supplying a third potential;
The transistor is a light-emitting device having an oxide semiconductor film in a channel formation region. A light-emitting device including a transistor, first to fourth switches, a first capacitor, a second capacitor, and a light-emitting element,
the first switch has one terminal electrically connected to a first wiring and the other terminal electrically connected to a first gate of the transistor;
one of a source and a drain of the transistor is electrically connected to a second wiring, and the other of the source and the drain is electrically connected to a first electrode of the light-emitting element;
the second switch has one terminal electrically connected to the first gate of the transistor and the other terminal electrically connected to the first electrode of the light-emitting element;
the third switch has one terminal electrically connected to a third wiring and the other terminal electrically connected to the second gate of the transistor;
the fourth switch has one terminal electrically connected to a fourth wiring and the other terminal electrically connected to a first electrode of the light-emitting element;
the first capacitance element has a first electrode electrically connected to a first gate of the transistor and a second electrode electrically connected to the other of the source and the drain of the transistor;
the second capacitance element has a first electrode electrically connected to a second gate of the transistor and a second electrode electrically connected to the other of the source and the drain of the transistor;
The light emitting element has a second electrode electrically connected to the fourth wiring,
a first period during which the third switch is in an on state and the fourth switch is in an off state;
a second period during which the third switch is in an off state and the fourth switch is in an on state;
the first wiring has a function of supplying an image signal;
The second wiring has a function of supplying a first potential,
the third wiring has a function of supplying a second potential;
the fourth wiring has a function of supplying a third potential;
the transistor includes an oxide semiconductor film in a channel formation region,
The light-emitting device, wherein the oxide semiconductor film is a metal oxide containing In.

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