JP7587147B2 - Programmable Logic Controller - Google Patents

Description

The present invention relates to a programmable logic controller used in fields such as industrial equipment.

As an example of this type of programmable logic controller (hereinafter referred to as PLC), one that is known is one that includes a microcomputer with a non-volatile memory and a CPU that reads a program from the memory and performs calculations, as seen in Patent Document 1. The CPU has calculation functions such as arithmetic calculations and logical calculations.

JP 2016-45712 A

As a configuration for achieving functional safety for PLCs, there are PLCs equipped with multiple microcomputers. Anomalies can occur in the calculation functions of the CPU that constitutes this PLC. For this reason, it is necessary to periodically diagnose whether or not an abnormality has occurred in the CPU. The following is an example of such anomaly diagnosis method.

In each microcomputer, the expected value of the calculation result when a specific calculation is executed is stored in memory. In each microcomputer, the CPU executes the specific calculation. Then, in each microcomputer, the CPU compares the calculation result with the expected value to diagnose whether or not an abnormality has occurred.

Here, there are many types of calculations that can be performed in a microcontroller. In this case, it is necessary to store in memory the expected values of the calculation results when each of the many calculations is performed. As a result, the memory capacity used for abnormality diagnosis increases. In a PLC equipped with multiple microcontrollers, the memory capacity of each microcontroller increases, and the increase in memory capacity used for abnormality diagnosis becomes significant. For example, if abnormality diagnosis is performed infrequently, it is not desirable to have a significant increase in memory capacity used for abnormality diagnosis. An increase in memory capacity increases the cost of the memory, which in turn increases the cost of the PLC.

The present invention was made in consideration of the above circumstances, and its main objective is to provide a programmable logic controller that can properly diagnose CPU abnormalities while reducing the memory capacity used for abnormality diagnosis.

A first invention is a first microcomputer having a non-volatile memory and a first CPU that reads a program from the memory and performs a calculation;
A programmable logic controller including a second microcomputer having a second CPU,
the program includes a diagnostic routine for diagnosing whether or not an abnormality has occurred in at least one of the first CPU and the second CPU;
When the first CPU starts execution of the diagnostic routine,
The first CPU is
performing a first operation on an operand based on an opcode;
Transmitting an opcode used in the first operation to the second CPU;
The second CPU is
performing a second operation on the operand based on the received opcode;
Transmitting a result of the second operation to the first CPU;
The first CPU is
by comparing a result of the first calculation with a result of the second calculation received, it is determined whether or not the abnormality has occurred;
If it is determined that no abnormality has occurred, the opcode generated by incrementing or decrementing the opcode used in the current first operation is set as the opcode to be used in the next first operation.

In the first invention, the PLC is provided with a first and second microcomputer as a configuration for realizing functional safety for the PLC. A program is stored in the memory constituting the first microcomputer, and the program includes a diagnostic routine for diagnosing whether or not an abnormality has occurred in at least one of the first and second CPUs. When the first CPU constituting the first microcomputer starts executing the diagnostic routine, the following processing is performed.

The first CPU executes a first operation that processes the operands based on the opcode, and transmits the opcode used in the first operation to the second CPU constituting the second microcomputer. The second CPU executes a second operation that processes the operands based on the received opcode, and transmits the result of the second operation to the first CPU.

The first CPU compares the result of the first operation with the result of the received second operation to diagnose whether an abnormality has occurred in at least one of the first and second CPUs. In this case, since there is no need to store in memory the expected values of the operation results corresponding to each of the multiple opcodes, the memory capacity used for abnormality diagnosis can be reduced.

Here, the opcode as machine language is represented by binary data consisting of two or more bit strings. Among the bit strings that make up the opcode, a new opcode is generated by incrementing the target increment bit (e.g., the least significant bit) or decrementing the target decrement bit, and the new opcode specifies a different operation from the opcode before the increment or decrement. In other words, by performing a process such as incrementing or decrementing the base opcode, a different opcode to be diagnosed can be generated. In this case, the scale of the diagnostic routine can be reduced, for example by reducing the number of lines of the program in the diagnostic routine.

In consideration of this, when the first CPU determines that no abnormality has occurred, it sets the opcode generated by incrementing or decrementing the opcode used in the current first operation as the opcode to be used in the next first operation. This makes it possible to suitably reduce the memory capacity used for abnormality diagnosis, compared to a configuration in which the expected values of the operation results when each operation to be diagnosed is executed is stored in memory, or a configuration in which list data of multiple opcodes to be diagnosed is stored in memory.

In this way, according to the first invention, it is possible to properly diagnose abnormalities in the CPU while reducing the memory capacity used for abnormality diagnosis.

The number of microcomputers that a PLC has may be two or more. When there are three or more microcomputers, for example, one of the microcomputers may be a first microcomputer and the rest may be second microcomputers, and the first invention may be applied.

Here, the first invention can be embodied, for example, as a second invention. In the second invention, the first CPU repeatedly executes the increment or decrement until a condition is met that indicates that the first operation for each opcode to be diagnosed is completed.

In a third aspect, in the first or second aspect, the first CPU transmits an opcode and an operand used in the first arithmetic operation to the second CPU;
The second CPU executes, as the second operation, an operation of performing a process based on the received opcode on the received operand.

According to the third invention, the operands used in the first and second operations can be made common, thereby improving the accuracy of CPU abnormality diagnosis.

A fourth aspect of the present invention is the third aspect of the present invention, wherein the second microcomputer has a non-volatile memory;
The diagnostic routine is not stored in the memory of the second microcomputer.

In the fourth invention, the diagnostic routine is stored only in the memory of the first microcomputer out of the first and second microcomputers. This allows the memory capacity of the second microcomputer to be reduced, and thus the memory capacity of the PLC to be reduced in an advantageous manner.

FIG. 1 is an overall configuration diagram of a control system according to an embodiment. 4 is a flowchart showing a procedure for a CPU abnormality diagnosis process. FIG. 4 is a diagram showing an example of an opcode that specifies an operation to be diagnosed. FIG. 13 is a diagram showing an example of an opcode that defines an operation to be diagnosed according to another embodiment.

Below, an embodiment of the PLC according to the present invention will be described with reference to the drawings. The PLC of this embodiment constitutes a control system for industrial equipment such as robots and belt conveyors.

As shown in FIG. 1, the PLC 100 includes a first microcomputer 10 and a second microcomputer 20. Each of the microcomputers 10 and 20 is housed in a housing provided for the PLC 100.

The control system includes an input device 110 and a controlled device 120. The controlled device 120 includes, for example, a machine tool such as an articulated robot, and a conveyor belt. The input device 110 includes, for example, a sensor that detects the state of the controlled device 120 (for example, current, voltage, rotation speed), and an emergency switch that stops the operation of the controlled device 120. The first microcomputer 10 and the second microcomputer 20 control the controlled device 120.

The first microcomputer 10 includes a first CPU 11, a first RAM 12, a first ROM 13 which is a non-volatile memory, and a first communication unit 14 which functions as an interface unit. The first CPU 11 includes an ALU (Arithmetic Logic Unit) and an internal register. In this embodiment, the first ROM 13 is a flash memory.

The first ROM 13 stores programs and the like executed by the first CPU 11. The first RAM 12 is a working memory used when the first CPU 11 executes programs.

The second microcomputer 20 includes a second CPU 21, a second RAM 22, a second ROM 23 which is a non-volatile memory, and a second communication unit 24 which functions as an interface unit. The second CPU 21 includes an ALU and an internal register. In this embodiment, the second ROM 23 is a flash memory.

The first microcontroller 10 and the second microcontroller 20 can communicate with each other via the first communication unit 14 and the second communication unit 24, for example, by serial communication.

In this embodiment, of the first ROM 13 and the second ROM 23, only the first ROM 13 stores a diagnostic routine for diagnosing whether an abnormality has occurred in the calculation function of at least one of the first CPU 11 and the second CPU 21. When the first CPU 11 starts executing the diagnostic routine, an abnormality diagnosis process is executed (see FIG. 2). This process is executed periodically, for example, once an hour.

The operations to be diagnosed include arithmetic operation instructions and logical operation instructions. Arithmetic operation instructions include addition/subtraction instructions, multiplication/division instructions, shift operation instructions, and comparison instructions. For example, an addition instruction is an instruction that performs addition between a first operand and a second operand.

Figure 3 shows multiple (15 are shown) arithmetic functions to be diagnosed in this embodiment. Figure 3 also shows the mnemonic corresponding to each opcode indicating the arithmetic function, the meaning of the operation in the case of integer operation and floating-point operation, and the condition flag. In this embodiment, the opcode to be diagnosed is represented by binary data consisting of a 4-bit string, and the operand is represented by binary data. However, the opcode is not limited to a 4-bit string, and may be, for example, a 3-bit string or a string of 5 or more bits.

As shown in FIG. 2, in step S10, the first CPU 11 writes a diagnostic routine from among the programs stored in the first ROM 13 to the first RAM 12 and executes the diagnostic routine. This starts the abnormality diagnosis process.

In step S11, the first CPU 11 executes a first operation that performs processing on an operand based on a first opcode that specifies the arithmetic function to be diagnosed. Referring to FIG. 3, the first opcode is "0000".

In step S12, the first CPU 11 transmits the opcode and operands used in the first operation in step S11 to the second CPU 21 via the first communication unit 14 and the second communication unit 24.

In step S21, the second CPU 21 determines whether or not the opcode and operands transmitted from the first CPU 11 by the processing of step S12 have been received. If the second CPU 21 determines that they have not been received, it proceeds to step S20.

If the second CPU 21 determines that an opcode and an operand have been received, the process proceeds to step S22. The second CPU 21 executes a second operation in which processing based on the received opcode is applied to the received operand.

In step S23, the second CPU 21 transmits the result of the second calculation performed in step S22 to the first CPU 11 via the second communication unit 24 and the first communication unit 14.

In step S13, the first CPU 11 waits until it receives the calculation result of the second calculation in step S22. If the first CPU 11 determines that it has received the calculation result of the second calculation, it proceeds to step S14 and compares the calculation result of the first calculation in step S11 with the received calculation result of the second calculation. If the first CPU 11 determines that the calculation result of the first calculation matches the calculation result of the second calculation, it determines that the calculation functions of both the first CPU 11 and the second CPU 21 are normal. On the other hand, if the first CPU 11 determines that the calculation result of the first calculation does not match the calculation result of the second calculation, it determines that an abnormality has occurred in the calculation function of at least one of the first CPU 11 and the second CPU 21.

Specifically, if the first CPU 11 determines that the absolute value of the difference between the calculation result (calculated value) of the first calculation and the calculation result (calculated value) of the second calculation is equal to or less than a threshold value, it determines that the calculation results match, and if it determines that the absolute value is greater than the threshold value, it determines that the calculation results do not match. The threshold value may be set to, for example, the maximum value of the error that can occur in the calculations of steps S11 and S22.

If the first CPU 11 determines that the operation is normal, it proceeds to step S15 and determines whether or not abnormality diagnosis has been completed for all target opcodes. Referring to FIG. 3, if the first CPU 11 determines that the opcode used in the first calculation in step S11 this time is "1110", it determines that abnormality diagnosis has been completed.

If the first CPU 11 determines that the abnormality diagnosis is complete, the process proceeds to step S16, where the first CPU 11 notifies the second CPU 21 of the completion of the diagnosis via the first communication unit 14 and the second communication unit 24. After that, the first CPU 11 temporarily ends the series of processes shown in FIG. 2.

The second CPU 21 determines whether or not the diagnosis completion notification transmitted by the processing of step S16 has been received. If the second CPU 21 determines that the diagnosis completion notification has not been received, the process proceeds to step S21. On the other hand, if the second CPU 21 determines that the diagnosis completion notification has been received, the process of FIG. 2 is temporarily terminated.

If the first CPU 11 determines in step S15 that the abnormality diagnosis is not complete, the process proceeds to step S17, where it increments the opcode used in the current first calculation in step S11. Specifically, the first CPU 11 sets the least significant bit of the opcode as the increment bit, and increments the increment bit by "b0001". Note that "b" is a notation indicating that the number is a binary number. The first CPU 11 then proceeds to step S11. As a result, the incremented opcode is used in the next first calculation in step S11. For example, if the opcode used in the current first calculation is "0000", the opcode newly generated by the process in step S17 becomes "0001", and this opcode is used in the next first calculation.

On the other hand, if the first CPU 11 determines in step S14 that an abnormality has occurred, the process proceeds to step S18. In step S18, the first CPU 11 notifies a higher-level control device (not shown) of the occurrence of an abnormality with respect to the PLC 100.

In the next step S19, the first CPU 11 notifies the second CPU 21 via the first communication unit 14 and the second communication unit 24 that the diagnosis has ended.

In step S20, the second CPU 21 determines whether or not the diagnosis end notification transmitted by the processing of step S19 has been received. If the second CPU 21 determines that the diagnosis end notification has not been received, the process proceeds to step S21. On the other hand, if the second CPU 21 determines that the diagnosis end notification has been received, the process temporarily ends the series of processes shown in FIG. 2. In other words, if it is determined that an abnormality has occurred in one of the multiple calculation functions to be diagnosed, the abnormality diagnosis process is forcibly interrupted.

The present embodiment described above provides the following advantages:

When the first CPU 11 determines in step S14 that no abnormality has occurred, in step S17, it increments the opcode used in the first operation until the condition for completing the diagnosis is met in step S15. The first CPU 11 uses the opcode generated by the increment as the opcode to be used in the next first operation. This makes it possible to suitably reduce the memory capacity used for abnormality diagnosis compared to a configuration in which the expected value of the operation result when each operation to be diagnosed is executed is stored in the first ROM 13, or a configuration in which list data of multiple opcodes to be diagnosed is stored in the first ROM 13. This makes it possible to, for example, eliminate the need to provide an external nonvolatile memory for each microcomputer 10, 20, thereby making it possible to reduce the size of the housing of the PLC 100 and, ultimately, the size of the PLC 100.

In step S12, the first CPU 11 transmits the opcode and operands used in the first operation to the second CPU. In step S22, the second CPU executes an operation that applies processing based on the received opcode to the received operands. This allows the operands used in the first operation in step S11 and the second operation in step S22 to be standardized, thereby improving the accuracy of CPU abnormality diagnosis.

Of the first ROM 13 and the second ROM 23, the diagnostic routine is stored only in the first ROM 13. This allows the memory capacity required for the second microcomputer 20 to be reduced.

<Other embodiments>
The above embodiment may be modified as follows.

-The multiple calculation functions stored in the first ROM 13 may be divided into multiple groups, and the abnormality diagnosis process shown in FIG. 2 may be executed for each group. FIG. 4 shows an example of a 5-bit opcode. The calculation functions shown in FIG. 4 are divided into a first group of No. 1 to 3, a second group of No. 4 to 7, and a third group of No. 8 to 11.

When abnormality diagnosis processing is performed for the first group, in step S17 of FIG. 2, the first CPU 11 sets the third least significant bit of the opcode as the increment bit and increments the increment bit to "b00100".

When abnormality diagnosis processing is performed for the second group, the first CPU 11 changes the increment bit from the increment bit for the first group in step S17. In detail, the first CPU 11 sets the least significant bit of the opcode as the increment bit, and increments the increment bit by "b00001".

When abnormality diagnosis processing is performed for the third group, in step S17, the first CPU 11 sets the third least significant bit of the opcode as the increment bit and increments the increment bit to "b00100".

- The above-mentioned diagnostic routine may also be stored in the second ROM 23. In this case, the processing on the first CPU 11 side shown in FIG. 2 is executed by the second CPU 21, and the processing on the second CPU 21 side shown in FIG. 2 is executed by the first CPU 11. In this case, the second CPU 21 executes the first calculation, the first CPU 11 executes the second calculation, and the second CPU 21 determines whether or not there is an abnormality.

- In step S17 of FIG. 2, the first CPU 11 may set the least significant bit of the opcode used in this first operation as a decrement bit and execute a decrement on that decrement bit. In this case, in the first step S11 after the start of the abnormality diagnosis process, the first CPU 11 may set the first opcode that serves as the base to, for example, "1110" in FIG. 3.

-An electronic device that includes a first microcomputer and a second microcomputer and performs the control process for the controlled device and the abnormality diagnosis process described above is not limited to a programmable logic controller.

10, 20...first and second microcomputers, 11, 21...first and second CPUs, 13, 23...first and second ROMs, 100...PLC.

Claims (2)

a first microcomputer having a non-volatile memory and a first CPU that reads a program from the memory and performs calculations;
A programmable logic controller including a non-volatile memory and a second microcomputer having a second CPU,
the program includes a diagnostic routine for diagnosing whether or not an abnormality has occurred in at least one of the first CPU and the second CPU;
When the first CPU starts execution of the diagnostic routine,
The first CPU is
performing a first operation on an operand based on an opcode;
Sending an opcode and an operand used in the first operation to the second CPU;
The second CPU is
performing a second operation on the received operand based on the received opcode;
Transmitting a result of the second operation to the first CPU;
The first CPU is
by comparing a result of the first calculation with a result of the second calculation received, it is determined whether or not the abnormality has occurred;
When it is determined that the abnormality has not occurred, the opcode generated by incrementing or decrementing the opcode used in the current first operation is set as the opcode to be used in the next first operation ;
The diagnostic routine is not stored in the memory of the second microcomputer . The programmable logic controller according to claim 1, wherein the first CPU repeatedly executes the increment or the decrement until a condition is met that the first operation for each opcode to be diagnosed is completed.

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