JP7587428B2 - Wiring Board - Google Patents

Description

The present invention relates to a wiring board.

Patent Document 1 discloses a multilayer wiring board having a pad portion formed on an insulating layer and bonded to a semiconductor element. A solder resist is provided on the insulating layer, and the pad portion is arranged so as to be separated from the solder resist during the opening of the solder resist.

JP 2004-22713 A

Stress may occur in the pad portion and the underlying insulating layer formed as disclosed in Patent Document 1 due to the difference in thermal expansion coefficient between the pad portion made of metal such as copper and the insulating layer made mainly of resin, and due to external forces applied from external components connected to the pad portion. In particular, in the pad portion that is disposed away from the solder resist as disclosed in Patent Document 1, it is thought that stress due to the difference in thermal expansion coefficient between the metal and resin is likely to concentrate on the interface between the pad portion and the insulating layer and on the insulating layer near the end of the pad portion. Defects such as cracks and interfacial peeling may occur at the points where stress is concentrated.

The wiring board of the present invention includes a first insulating layer, a conductor layer formed on the surface of the first insulating layer, and a solder resist layer formed on the surface of the first insulating layer and on the conductor layer, the solder resist layer having an opening that exposes at least a portion of the conductor layer, and has a first surface and a second surface that is the opposite surface to the first surface. The conductor layer includes a conductor pad exposed by the opening, and the surface of the conductor pad facing away from the first insulating layer and the entire side surface of the conductor pad are exposed without being covered by the solder resist layer, and the edge of the conductor pad is spaced from the surface of the first insulating layer.

According to an embodiment of the present invention, it is possible to suppress the occurrence of defects in the surrounding area while ensuring the required size of exposed area in the conductor pad provided on the wiring board.

FIG. 1 is a cross-sectional view showing an example of a wiring board according to an embodiment of the present invention. FIG. 1 is a plan view showing an example of a wiring board according to an embodiment of the present invention. FIG. 2 is an enlarged view of part III in FIG. 1 . FIG. 4 is an enlarged view of part IV in FIG. 3 . FIG. 11 is a cross-sectional view showing another example of an edge portion of a conductor pad in an embodiment of the present invention. FIG. 11 is a cross-sectional view showing another example of an edge portion of a conductor pad in an embodiment of the present invention. 4A to 4C are cross-sectional views showing an example of a state during a manufacturing process of the wiring board according to the embodiment of the present invention. 4A to 4C are cross-sectional views showing an example of a state during a manufacturing process of the wiring board according to the embodiment of the present invention. 4A to 4C are cross-sectional views showing an example of a state during a manufacturing process of the wiring board according to the embodiment of the present invention. 4A to 4C are cross-sectional views showing an example of a state during a manufacturing process of the wiring board according to the embodiment of the present invention. 4A to 4C are cross-sectional views showing an example of a state during a manufacturing process of the wiring board according to the embodiment of the present invention. 4A to 4C are cross-sectional views showing an example of a state during a manufacturing process of the wiring board according to the embodiment of the present invention.

A wiring board according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional view of wiring board 1, which is an example of a wiring board according to an embodiment, and FIG. 2 shows a plan view of wiring board 1 from the underside in FIG. 1. FIG. 1 is a cross-sectional view taken along line I-I in FIG. 2. FIG. 3 shows an enlarged view of part III in FIG. 1.

As shown in FIG. 1, the wiring board 1 includes an insulating layer 20 and conductor layers and insulating layers alternately stacked on both sides of the insulating layer 20. On the upper surface 20a of the insulating layer 20, three conductor layers 31 and two insulating layers 21 are alternately stacked, and an insulating layer 23 is further stacked thereon. A conductor layer (second conductor layer) 33 is formed on the insulating layer 23. On the lower surface 20b, which is the opposite surface of the upper surface 20a of the insulating layer 20, three conductor layers 32 and two insulating layers 22 are alternately stacked, and an insulating layer (first insulating layer) 2 is further stacked thereon. A conductor layer (first conductor layer) 3 is formed on the surface 2a of the insulating layer 2. A solder resist layer 40 (second solder resist layer) is formed on the insulating layer 2 and the conductor layer 33. A solder resist layer 4 (first solder resist layer) is formed on the insulating layer 2 and the conductor layer 3. The wiring board 1 of the embodiment includes at least an insulating layer 2, a conductor layer 3 formed on the surface 2a of the insulating layer 2, and a solder resist layer 4 formed on the surface 2a of the insulating layer 2 and on the conductor layer 3.

The wiring board 1 has two surfaces extending in a direction perpendicular to the thickness direction of the wiring board 1, a first surface 11, and a second surface 12 opposite the first surface 11. The thickness direction of the wiring board 1 is also simply referred to as the "Z direction" below. In the wiring board 1, the insulating layer 23, the conductor layer 33, and the solder resist layer 40 are formed on the first surface 11 side of the wiring board 1 and form the surface layer portion of the first surface 11 side of the wiring board 1. The first surface 11 is composed of exposed surfaces perpendicular to the Z direction in the insulating layer 23, the conductor layer 33, and the solder resist layer 40. In addition, the insulating layer 2, the conductor layer 3, and the solder resist layer 4 are formed on the second surface 12 side of the wiring board 1 and form the surface layer portion of the second surface 12 side of the wiring board 1. The second surface 12 is composed of exposed surfaces perpendicular to the Z direction in the insulating layer 2, the conductor layer 3, and the solder resist layer 4.

A through-hole conductor 20c is formed in the insulating layer 20, connecting the conductor layer 31 and the conductor layer 32. The insulating layer 20, the conductor layer 31 on its upper surface 20a, and the conductor layer 32 on its lower surface 20b constitute the core substrate of the wiring board 1. The insulating layer 2 and the insulating layers 21 to 23 each have a via conductor 2v formed therein, connecting the conductor layers sandwiching the insulating layer 2 and the insulating layers 21 to 23, respectively.

The insulating layer 2 and the insulating layers 20 to 23 are each formed using an insulating resin such as an epoxy resin, a bismaleimide triazine resin (BT resin), or a phenolic resin. Each insulating layer may contain a reinforcing material (core material) such as glass fiber and/or an inorganic filler such as silica.

The solder resist layers 4, 40 are formed using any insulating resin, such as epoxy resin or polyimide resin. The solder resist layer 40 has an opening 40a that exposes a part or all of the conductor layer 33. In the example of FIG. 1, the opening 40a partially exposes the conductor layer 33. On the other hand, the solder resist layer 4 has an opening 4a that exposes at least a part of the conductor layer 3. In the examples of FIG. 1 and FIG. 2, the opening 4a exposes the entire conductor layer 3.

The conductor layer 3 and the conductor layers 31 to 33, the via conductor 2v, and the through-hole conductor 20c are formed using any metal such as copper or nickel, and are composed of, for example, a metal foil such as copper foil, and/or a metal film formed by plating or sputtering. Therefore, the conductor layer 3 and the conductor layers 31 to 33, the via conductor 2v, and the through-hole conductor 20c may have a multilayer structure having two or more metal layers. However, the conductor layer 3 and the conductor layers 31 to 33, the via conductor 2v, and the through-hole conductor 20c may have a single-layer structure including only a single metal layer.

In the wiring board 1 illustrated in FIG. 1 to FIG. 3, the conductor layer 3 is simplified in FIG. 1 for ease of viewing, but as shown in FIG. 3, it has a two-layer structure including a metal film 30a and a plating film 30b. The metal film 30a is formed on the surface 2a of the insulating layer 2, and the plating film 30b is formed on the surface of the metal film 30a opposite the insulating layer 2. The metal film 30a is formed, for example, by electroless plating or sputtering. The plating film 30b is formed, for example, by electrolytic plating using the metal film 30a as a power supply layer. Although not shown, the conductor layer 33, the conductor layer 31 and the conductor layer 32 formed on the insulating layer 21 or the insulating layer 22, the via conductor 2v, and the through-hole conductor 20c may also have a two-layer structure similar to that of the conductor layer 3 shown in FIG. 3.

Each conductor layer is patterned to have a predetermined conductor pad and/or wiring pattern. In the example of the wiring board 1 in FIG. 1, the conductor layer 33 is patterned to have a plurality of component mounting pads 33a. That is, the wiring board 1 includes a plurality of component mounting pads 33a formed on the first surface 11. In the example of FIG. 1, each component mounting pad 33a is a so-called SMD pad (Solder Mask Defined) type conductor pad. That is, the peripheral portion of each component mounting pad 33a is covered with the solder resist layer 40, and the portion other than the peripheral portion of each component mounting pad 33a is exposed to the opening 40a of the solder resist layer 40.

Each component mounting pad 33a is a conductor pad (second conductor pad) on whose surface a component E1 to be mounted on the wiring board 1 when the wiring board 1 is in use is placed. In other words, the first surface 11 is the component mounting surface of the wiring board 1. An electrode E11 of the component E1 is electrically and mechanically connected to the component mounting pad 33a via a bonding material (not shown) such as solder.

Examples of component E1 include electronic components such as active components, such as semiconductor integrated circuit devices and transistors, and passive components, such as electrical resistors. Component E1 may be a wiring material including fine wiring formed on a semiconductor substrate. However, component E1 is not limited to these.

In this embodiment, the conductor layer 3 includes a conductor pad 3a (first conductor pad). As shown in FIGS. 1 to 3, the conductor pad 3a is exposed by an opening 4a in the solder resist layer 4. Specifically, the surface 3a1 (first main surface) of the conductor pad 3a facing the opposite side of the insulating layer 2 and the entire side surface 3a2 of the conductor pad 3a are exposed without being covered by the solder resist layer 4. In other words, the conductor pad 3a is a so-called NSMD pad (Non-Solder Mask Defined) type conductor pad whose outer edge is not defined by an opening in the solder resist layer. The side surface 3a2 of the conductor pad 3a is a surface between the surface 3a3 (second main surface) facing the insulating layer 2 of the conductor pad 3a and the surface 3a1, which constitutes the outer edge of the conductor pad 3a in a plan view. Note that "plan view" means that an object such as the conductor pad 3a is viewed with a line of sight parallel to the Z direction. The surface 3a3 of the conductor pad 3a is also referred to below as the "rear surface 3a3 of the conductor pad 3a."

In the wiring board 1 of the example of FIG. 1, the second surface 12 may be a component mounting surface on which electronic components such as semiconductor integrated circuit devices are mounted, similar to the first surface 11. The second surface 12 may also be a connection surface that is connected to an external element E2 when the wiring board 1 itself is mounted on an external wiring board, for example, an external element E2 such as a motherboard of any electrical device. In other words, the wiring board 1 may form part of a package of a component E1, such as a semiconductor integrated circuit mounted on the first surface 11. In that case, the wiring board 1 may be mounted together with the component E1 on the external element E2, with the second surface 12 facing the external element E2, as shown in FIG. 1.

When the second surface 12 is a connection surface with the external element E2, the second surface 12 may have a connection portion with the external element E2. The wiring board 1 in the example of FIG. 1 is connected to the external element E2 at the conductor pad 3a. Therefore, the conductor pad 3a in the example of FIG. 1 is a connection pad that is connected to the external element E2 in the wiring board 1, and the connection pad with the external element E2 in the wiring board 1 in FIG. 1 consists of the conductor pad 3a. As described above, the entire surface 3a1 and the entire side surface 3a2 of the conductor pad 3a are exposed in the opening 4a without being covered by the solder resist layer 4. Therefore, the wiring board 1 and the external element E2 can be firmly connected over a large area.

The conductor pad 3a of the wiring board 1 has a rectangular planar shape as shown in FIG. 2. The "planar shape" is the shape of an object such as the conductor pad 3a in a planar view. Here, the "rectangle" means a shape surrounded by two parallel sides (line segments) and two parallel sides (line segments) perpendicular to the two sides. In this "rectangle," the two adjacent and perpendicular sides do not necessarily need to be in contact with each other at a right angle at the intersection, and the part (corner) near the intersection may have a chamfered shape such as C-chamfering or R-chamfering. In that case, the straight line part of each side of the "rectangle" in the above and following explanations preferably has a length of 1/3 or more of the distance between the other two sides perpendicular to that side. In the conductor pad 3a of the example in FIG. 2, all four corners of the conductor pad 3a in a planar view are R-chamfered.

The conductor pad 3a can be electrically and mechanically connected to the electrode E21 of the external element E2 by, for example, a bonding material B such as solder (see FIG. 3). As described above, the external element E2 can be a motherboard constituting any electrical device, or any electronic component having a package size larger than the wiring board 1. The conductor pad 3a can be connected to any substrate, electrical component, or mechanical component, including but not limited to these.

In the example of FIG. 1, the conductor pad 3a is larger than any of the multiple component mounting pads 33a provided on the first surface 11. For example, it is considered that an external element E2 larger than the component E1 is firmly connected to the wiring board 1 over a large area.

Although omitted in Figs. 1 and 2, the wiring board 1 includes a surface treatment layer 5 that covers the surface 3a1 and side 3a2 of the conductor pad 3a as shown in Fig. 3. The surface treatment layer 5 is a coating formed by, for example, anticorrosive treatment and/or antirust treatment of exposed parts such as the surface 3a1 and side 3a2 of the conductor pad 3a. The surface treatment layer 5 prevents corrosion, oxidation, etc. of the conductor pad 3a.

The surface treatment layer 5 is, for example, a metal coating containing a metal different from the conductor pad 3a, or an organic coating containing an organic substance such as an imidazole compound. When the conductor pad 3a is made of copper, the surface treatment layer 5 can be made of nickel, palladium, silver, gold, or an alloy thereof, or solder. In the example of FIG. 3, the surface treatment layer 5 has a two-layer structure including a lower layer 51 formed on the main body side of the conductor pad 3a and an upper layer 52 formed on the lower layer 51. The lower layer 51 is, for example, a nickel film or an alloy film of nickel and palladium, and the upper layer is, for example, a metal film made of gold.

As shown in FIG. 3, in the wiring board 1 of the embodiment, the edge of the conductor pad 3a is spaced from the surface 2a of the insulating layer 2. The "edge" of the conductor pad 3a is a frame-like portion that continuously or intermittently surrounds the center of the conductor pad 3a along the outer edge of the planar shape of the conductor pad 3a. The "edge" of the conductor pad 3a is an area whose distance from the outer edge of the conductor pad 3a is equal to or less than the length LW, and is a frame-like portion having the length LW as the width of each side. The length LW is, for example, 0.01×LD or more and 0.1×LD or less. Here, "LD" is the distance between two opposing sides of the conductor pad 3a in a direction parallel to the length LW.

Figure 4 shows an enlarged cross-section of the edge of the conductor pad 3a on the wiring board 1 (e.g., part IV in Figure 3). As shown in Figure 4, the edge of the conductor pad 3a is separated from the surface 2a of the insulating layer 2. In other words, at the edge of the conductor pad 3a, the conductor pad 3a is raised above the surface 2a of the insulating layer 2. The corner formed by the back surface 3a3 and the side surface 3a2 of the conductor pad 3a is cut out. Therefore, in the cross-sectional view shown in Figure 4, a cutout-shaped space G surrounded by a two-dot chain line is formed between the conductor pad 3a and the surface 2a of the insulating layer 2.

Because the edge of the conductor pad 3a is separated from the surface 2a of the insulating layer 2, the side 3a2 of the conductor pad 3a and the outer edge of the interface between the back surface 3a3 and the surface 2a of the insulating layer 2 (the outer edge of this interface is also simply called the "outer edge F") are not aligned in a line in the vertical direction of the surface 2a. In other words, the side 3a2 and the outer edge F do not overlap in a planar view. The outer edge F is located inside (towards the center) of the conductor pad 3a relative to the side 3a2. In addition, because the edge of the conductor pad 3a is separated from the surface 2a of the insulating layer 2, the lower end Q (the tip on the insulating layer 2 side) of the side 3a2 of the conductor pad 3a is not in contact with the surface 2a and is separated from the surface 2a.

As mentioned above, in conventional wiring boards, stress may occur in the conductor pad and the insulating layer below it due to the difference in thermal expansion coefficient between them or external force. The stress tends to concentrate on the edge of the conductor pad, which is the boundary between the area where the conductor pad exists and the area where it does not exist on the surface of the insulating layer. It is also considered that this stress tends to act in a direction along the surface of the conductor pad (for example, the side of the conductor pad) extending from the outer edge of the interface between the insulating layer and the conductor pad (outer edge F in the example of FIG. 4) away from the insulating layer. Therefore, unlike this embodiment, if the edge of the conductor pad is not away from the surface of the insulating layer below it, it is considered that the concentrated stress acts strongly in the direction along the side of the conductor pad, that is, in the direction perpendicular to the surface of the insulating layer below the conductor pad. Then, the stress acting strongly in the direction perpendicular to the surface of the insulating layer may cause cracks in the part of the insulating layer that contacts the side of the conductor pad, or interfacial peeling between the insulating layer and the conductor pad starting from the outer edge of the conductor pad may occur.

In contrast, in this embodiment, the edge of the conductor pad 3a is spaced from the surface 2a of the insulating layer 2. In the conductor pad 3a, the surface 3a4 extending from the outer edge F in a direction away from the surface 2a of the insulating layer 2 extends along a direction D2 inclined with respect to a direction D1 perpendicular to the surface 2a of the insulating layer 2. That is, the surface 3a4 of the conductor pad 3a, which is in contact with the surface 2a of the insulating layer 2 and extends in a direction away from the surface 2a, is in contact with the surface 2a at an angle θ smaller than a right angle with respect to the surface 2a. Therefore, it is considered that the stress that tends to concentrate on the edge of the conductor pad 3a acts strongly not in the direction D1 but in the direction D2 inclined with respect to the direction D1. It is considered that the stress acting in the direction D2 acts not only in the direction D1 perpendicular to the surface 2a of the insulating layer 2 but also in a dispersed manner in the direction D3 perpendicular to the direction D1. That is, it is believed that the stress acting on the insulating layer 2 in the direction D1 perpendicular to its surface 2a is reduced compared to when the edge of the conductor pad is not separated from the surface of the underlying insulating layer. Therefore, in this embodiment, it is believed that the occurrence of cracks in the insulating layer 2 and interfacial peeling between the insulating layer 2 and the conductor pad 3a are suppressed.

In particular, in the wiring board 1 illustrated in Figures 1 to 4, as described above, the conductor pad 3a is larger than any of the multiple component mounting pads 33a provided on the first surface 11. Therefore, its planar area is large, and the conductor pad 3a can have a relatively large interface with the insulating layer 2. Therefore, the stress concentrated on the edge of the conductor pad 3a is also likely to be excessive. This embodiment is considered to be particularly beneficial for conductor pads with a relatively large planar area such as the conductor pad 3a.

The angle θ between the surface 3a4 of the conductor pad 3a and the surface 2a of the insulating layer 2 is greater than 0° and less than 90°. For example, the angle θ is greater than or equal to 10° and less than or equal to 80°.

The length L (the distance from the side surface 3a2 to the outer edge F in a plan view) of the portion of the conductor pad 3a on the surface 2a of the insulating layer 2 that is separated from the surface 2a of the insulating layer 2 at the edge of the conductor pad 3a is preferably long from the viewpoint of mitigating the external force transmitted to the outer edge F via the conductor pad 3a. On the other hand, from the viewpoint of the adhesive strength between the conductor pad 3a and the insulating layer 2, it is considered that a short length L is preferable. The length L is, for example, 3 μm or more and 10 μm or less so that both the mitigation of the external force transmitted to the outer edge F and the securing of the adhesive strength of the conductor pad 3a are appropriately realized.

In the example of FIG. 4, the distance between the edge of the conductor pad 3a and the surface 2a of the insulating layer 2, which are spaced apart from each other, expands toward the periphery of the conductor pad 3a. In other words, the height (height from the surface 2a) of the notch-shaped space G that separates the edge of the conductor pad 3a from the surface 2a increases toward the periphery of the conductor pad 3a. That is, the surface of the part of the conductor pad 3a that is spaced apart from the surface 2a of the insulating layer 2 is inclined, not approximately parallel or approximately perpendicular to the side surface 3a2 or the back surface 3a3. Therefore, as described above, it is considered that the force in the peeling direction that may be applied to the interface between the edge of the conductor pad 3a that is spaced apart from the insulating layer 2 and the insulating layer 2 due to the thermal contraction of the conductor pad 3a is also distributed in the direction along the interface. It is presumed that interfacial peeling between the conductor pad 3a and the insulating layer 2 is less likely to occur.

Furthermore, in the example of FIG. 4, the corners formed by the back surface 3a3 and side surface 3a2 of the conductor pad 3a are rounded. The surface of the edge of the conductor pad 3a that is separated from the insulating layer 2 includes a curved surface. In other words, when the edge of the conductor pad 3a is not separated from the surface 2a of the insulating layer 2, the vicinity of the imaginary intersection line (point P in FIG. 4) between the back surface 3a3 and side surface 3a2 is rounded, and the conductor pad 3a has a curved portion on the surface near the intersection line. Because the edge of the conductor pad 3a is rounded, it is believed that cracks are less likely to occur not only in the insulating layer 2 but also in the surface treatment layer 5.

Specifically, the corners that should be formed by the side surface 3a2 of the conductor pad 3a and the underside of the plating film 30b (the surface facing the insulating layer 2) are rounded and have a curved surface. On the other hand, the end surface of the metal film 30a between the plating film 30b and the insulating layer 2 is approximately flat and is inclined toward the inner circumference of the conductor pad 3a as it approaches the insulating layer 2. Therefore, the end of the metal film 30a that constitutes the conductor pad 3a is also spaced from the surface 2a of the insulating layer 2.

When the surface treatment layer 5 is formed using a thermal expansion coefficient between that of the material constituting the conductor pad 3a and that of the insulating layer 2, it is believed that the stress generated in the insulating layer 2 and the conductor pad 3a is reduced compared to when the surface treatment layer 5 is not formed. Also, even if the surface treatment layer 5 is formed of a material whose difference in thermal expansion coefficient with the insulating layer 2 is greater than that of the conductor pad 3a, in this embodiment, since the edge of the conductor pad 3a is separated from the surface 2a of the insulating layer 2, it is believed that defects such as cracks are less likely to occur.

Furthermore, in the conductor pad 3a of the wiring board 1 of the example of Figures 1 to 4, as described above, the four corners in plan view are rounded, so there are fewer points of stress concentration due to differences in the thermal expansion coefficient between the conductor pad 3a and the insulating layer 2 compared to a conductor pad without rounded corners. Therefore, it is considered that defects such as cracks in the insulating layer 2 are even less likely to occur.

In this embodiment, the conductor pad 3a is a so-called NSMD type conductor pad, so that a large exposed portion is secured in the conductor pad 3a. This ensures a large connection area with an external element connected to the conductor pad 3a, and the external element can be firmly connected to the wiring board 1. On the other hand, as described with reference to Figures 1 to 4, the edge of the conductor pad 3a is separated from the insulating layer 2, so that defects such as cracks and interfacial peeling in the periphery of the conductor pad 3a can be suppressed.

5A and 5B show other examples of the edge of the conductor pad 3a. In the example of FIG. 5A, the conductor pad 3a has a flat portion 30b1 not only on the surface of the metal film 30a but also on the surface of the plating film 30b at the edge separated from the insulating layer 2. The surface of the edge of the conductor pad 3a in the example of FIG. 5A has curved portions 30b2 between the flat portion 30b1 and the side surface 3a2, and between the flat portion 30b1 and the surface of the plating film 30b on the insulating layer 2 side. The two curved portions 30b2 smoothly connect the flat portion 30b1 and the side surface 3a2, and the surface of the plating film 30b on the insulating layer 2 side and the flat portion 30b1. In the example of FIG. 5A, it is considered that defects such as cracks are unlikely to occur in the insulating layer 2 and/or the surface treatment layer 5.

The conductor pad 3a in the example of FIG. 5B has a flat portion 30b1 on the surface of the plating film 30b, like the conductor pad 3a in the example of FIG. 5A, but does not have the curved portion 30b2 shown in FIG. 5A. However, even in the example of FIG. 5B, the edge of the conductor pad 3a is spaced from the surface 2a of the insulating layer 2. Therefore, it is believed that the force acting in a direction perpendicular to the surface 2a is reduced when the edge of the conductor pad 3a is not spaced from the surface 2a. Therefore, it is believed that defects such as cracks are less likely to occur in the insulating layer 2 in the example of FIG. 5B as well.

The wiring board of the embodiment can be manufactured by any general method for manufacturing a wiring board. With reference to Figures 6A to 6G, an example of a manufacturing method will be outlined using the case where the wiring board 1 shown in Figure 1 is manufactured as an example.

As shown in FIG. 6A, a core substrate 10 is prepared, an insulating layer 21 is laminated on one surface 10a of the core substrate 10, and a conductor layer 31 is formed on the insulating layer 21. Similarly, an insulating layer 22 is laminated on the other surface 10b of the core substrate 10, and a conductor layer 32 is formed on the insulating layer 22. Then, lamination of each insulating layer and formation of a conductor layer are repeated on both surfaces of the core substrate 10, and an outermost insulating layer 23 and an outermost insulating layer 2 are formed on the one surface 10a and the other surface 10b of the core substrate 10.

In preparing the core substrate 10, for example, a double-sided copper-clad laminate including an insulating layer 20 is prepared. Then, the core substrate 10 is prepared by forming the conductor layers 31 and 32 including a predetermined conductor pattern on both sides of the insulating layer 20 by a subtractive method or the like, and forming the through-hole conductor 20c in the insulating layer 20. The insulating layers 21 and 22, and the conductor layers 31 and 32 on the insulating layer 21 or the insulating layer 22 are each formed by, for example, a general build-up substrate manufacturing method. For example, each insulating layer is formed by thermocompression bonding an epoxy resin on a film onto the core substrate 10 or each insulating layer and each conductor layer formed previously. In addition, each conductor layer is formed by any conductor pattern forming method, such as a semi-additive method or a full-additive method including the formation of a plating resist and pattern plating. In forming each conductor layer using a conductor pattern forming method such as a semi-additive method, a via conductor 2v can be formed in each insulating layer.

As shown in FIG. 6B, a metal film 30a is formed by electroless plating or sputtering on the surface 2a of the insulating layer 2 and in the through holes of the insulating layer 2 formed by irradiation with laser light or the like. A metal film 30a is also formed on the one surface 10a side of the core substrate 10 in a similar manner.

As shown in Figures 6B and 6C, a plating resist PR is provided on the metal film 30a. Figure 6C shows an enlarged view of the VIC portion of Figure 6B. In the plating resist PR provided on the insulating layer 2, an opening PR1 is formed in an area corresponding to the conductor pattern to be included in the conductor layer 3 (see Figure 6E).

The plating resist PR having each opening PR1 is formed using photolithography technology. First, a resist film that will become the plating resist PR is formed, for example, by laminating a negative photosensitive resin film over the entire surface of the metal film 30a. Then, an exposure mask EM that covers the area of the resist film where the opening PR1 is to be formed is placed on the resist film.

As shown in FIG. 6C, for example, ultraviolet light U is irradiated onto the resist film to be the plating resist PR through the exposure mask EM. The exposed portion PRa of the resist film that is not covered by the exposure mask EM becomes insoluble due to a crosslinking reaction. On the other hand, most of the non-exposed portion PRb of the resist film that is covered by the exposure mask EM remains soluble. However, among the portions directly under the exposure mask EM, the boundary portion BP adjacent to both the metal film 30a and the exposed portion PRa is exposed to the ultraviolet light U reflected by the metal film 30a and becomes insoluble. After that, the exposure mask EM is removed, and the non-exposed portion PRb is removed by development. However, the boundary portion BP remains together with the exposed portion PRa. As a result, the plating resist PR is formed having a mask portion in which the portion adjacent to the metal film 30a is widened by the boundary portion BP. The boundary portion BP can be formed, for example, by roughening the surface of the metal film 30a to moderately diffuse reflection of the ultraviolet light U. In the following description, the boundary portion BP is also referred to as the "widened portion BP" of the plating resist PR.

As shown in FIG. 6D, each conductor pattern of the conductor layer 3 is formed in the opening PR1 of the plating resist PR by electrolytic plating using the metal film 30a as a power supply layer. In the opening PR1 shown in FIG. 6D, a plating film 30b that constitutes the conductor pad 3a of the conductor layer 3 is formed. As shown in FIG. 6D, the plating film 30b is formed such that the portion adjacent to the metal film 30a at the edge is cut out by the widened portion BP of the plating resist PR. The plating resist PR is then removed.

As shown in Figures 6E and 6F, unnecessary portions of the metal film 30a exposed by removing the plating resist are removed by flash etching or the like. A conductor layer 3 having a predetermined conductor pattern such as conductor pads 3a is formed. A conductor layer 33 having a predetermined conductor pattern is formed on one surface 10a of the core substrate 10. Note that Figure 6F shows an enlarged view of the VIF portion of Figure 6E.

As shown in FIG. 6F, in the end face 30a1 (surface 3a4 of conductor pad 3a in FIG. 4) of the metal film 30a constituting conductor pad 3a, more is removed on the insulating layer 2 side than on the plating film 30b side. As a result, the end face 30a1 is inclined so as to approach the inner circumference of conductor pad 3a as it approaches the insulating layer 2 side. By making the portion of the edge of plating film 30b adjacent to the metal film 30a into a notched shape, different conditions can be created between the insulating layer 2 side and the plating film 30b side with regard to the wraparound of the etching solution. As a result, the end face 30a1 can be inclined as shown in FIG. 6F.

In the example of FIG. 6F, the edge of the plating film 30b near the metal film 30a has a notched shape, so the edge of the conductor pad 3a is spaced apart from the surface 2a of the insulating layer 2. Furthermore, the end face 30a1 of the metal film 30a is inclined toward the inner periphery of the conductor pad 3a as it approaches the insulating layer 2, so the edge of the conductor pad 3a is spaced apart from the insulating layer 2 over a longer range.

The shape of the plating film 30b shown in Figures 5A and 5B can also be formed by adjusting the roughness of the surface of the metal film 30a described above and adjusting the irradiation angle and luminous intensity of the ultraviolet light.

As shown in FIG. 1, the solder resist layer 40 is formed on the insulating layer 23 and the conductor layer 33, and the solder resist layer 4 is formed on the insulating layer 2 and the conductor layer 3. The solder resist layers 4, 40 are each provided with an opening 4a or an opening 40a. The solder resist layers 4, 40 are each formed by, for example, applying or spraying a photosensitive epoxy resin or polyimide resin, or laminating it in a film form. The openings 4a, 40a are then formed, for example, by exposure and development, or laser processing, etc.

A surface treatment layer 5 (see FIG. 3) may be formed on the surface of the conductor pad 3a exposed in the opening 4a and on the surface of the component mounting pad 33a exposed in the opening 40a. The surface treatment layer 5 may be formed, for example, by depositing a metal such as nickel, palladium, or gold on the surface of the conductor pad 3a and the surface of the component mounting pad 33a by electroless plating or electrolytic plating, or by applying a heat-resistant organic substance by spraying. By going through the above steps, the wiring board 1 of the example of FIG. 1 is completed.

The wiring board of the embodiment is not limited to those having the structure illustrated in each drawing, and the structure, shape, and material illustrated in this specification. The wiring board of the embodiment may have any laminated structure. For example, the wiring board of the embodiment may be a coreless board that does not include a core board. The wiring board of the embodiment may include any number of conductor layers and insulating layers. The wiring board of the embodiment may be a so-called double-sided board or a single-sided board. The conductor pattern 3a may not have a surface treatment layer 5. The conductor pads separated from the surface of the lower insulating layer at the edge portion may be provided on both surfaces of the wiring board as described above, or may be provided only on one surface. The solder resist layer 4 may cover the parts of the conductor layer 3 other than the conductor pads 3a while exposing the entire conductor pads 3a in the openings 4a. The component mounting pads 33a may be so-called NSMD pad type conductor pads. The conductor pads 3a may have parallel portions at the edge portion separated from the insulating layer 2, with a substantially constant distance from the surface 2a of the insulating layer 2. Additionally, the corners of the conductor pad 3a in plan view do not need to be chamfered.

1 Wiring board 11 First surface 12 Second surface 2 Insulating layer (first insulating layer)
2a Surface 20-23 Insulating layer 3 Conductive layer 3a Conductive pad 3a1 Surface 3a2 Side 3a3 Surface (rear)
31 to 33: Conductive layer 33a, component mounting pad 4, solder resist layer (first solder resist layer)
40 Solder resist layer (second solder resist layer)
4a, 40a Opening 5 Surface treatment layer E2 External element

Claims (9)

A first insulating layer;
a conductor layer formed on a surface of the first insulating layer;
a solder resist layer formed on the surface of the first insulating layer and on the conductor layer, the solder resist layer having an opening exposing at least a portion of the conductor layer;
A wiring board having a first surface and a second surface opposite to the first surface,
the conductor layer includes a conductor pad exposed by the opening;
a surface of the conductor pad facing away from the first insulating layer and an entire side surface of the conductor pad are exposed without being covered by the solder resist layer;
an edge of the contact pad is spaced from the surface of the first insulating layer;
The first surface is a component mounting surface on which components are mounted, and the conductor layer is formed on the second surface side . The wiring board according to claim 1, wherein the conductor pad has a rectangular planar shape. The wiring board according to claim 2, wherein the corners of the conductor pads in plan view are rounded. The wiring board according to claim 1, further comprising a surface treatment layer covering the conductor pads. 2. The wiring board according to claim 1 , further comprising a plurality of component mounting pads formed on the first surface,
The conductive pad on the conductive layer is larger than any of the component mounting pads. 2. The wiring board according to claim 1 , further comprising: a component mounting pad formed on the first surface; and a second solder resist layer provided on the first surface,
the second solder resist layer covers a peripheral portion of the component mounting pad,
The openings in the second solder resist layer expose the component mounting pads other than their peripheral edges. The wiring board according to claim 1, wherein the distance between the edge of the conductor pad that is spaced from the surface of the first insulating layer and the surface of the first insulating layer increases toward the outer periphery of the conductor pad. The wiring board according to claim 1, wherein the corners formed by the surface of the conductor pad facing the first insulating layer and the side surface of the conductor pad are rounded. The wiring board according to claim 1, wherein the surface of the edge of the conductor pad that is spaced from the surface of the first insulating layer includes a curved surface.

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