JP7587716B2 - Actions to improve device performance - Google Patents

Description

[0001] Embodiments of the present disclosure relate generally to semiconductor devices, systems, processes, apparatus, and manufacturing. More specifically, embodiments relate to processes for improving device performance in gate structures.

[0002] As metal oxide semiconductor field effect transistors (MOSFETs) are scaled down to achieve high device performance and low power consumption, the thickness of the traditional silicon dioxide (SiO ₂ ) gate dielectric has been reduced to its physical limit. As a result, to achieve further scaling, it is inevitable to replace the silicon dioxide gate dielectric with a high-k dielectric material. Among various high-k dielectric materials, hafnium oxide (HfO ₂ ) has been applied since the 45 nm MOSFET technology node due to its high dielectric constant and excellent thermal stability on silicon substrates. However, simply reducing the thickness of the high-k dielectric material layer to further scale the equivalent oxide thickness (EOT) beyond the 32 nm MOSFET technology node creates problems due to the increased leakage current through the high-k dielectric material layer.

[0003] Thus, there is a need for systems and methods that can be used to form thin (e.g., EOT less than 1 nm) high-k dielectric material layers having chemical structures that can be controlled to ensure desired structural and electrical properties.

[0004] One or more embodiments of the present disclosure relate to a method of forming a semiconductor device. In one or more embodiments, the method includes annealing a surface of a substrate to form a smooth surface, pre-cleaning the smooth surface to form a pre-cleaned surface, depositing a high-k dielectric layer on the pre-cleaned surface, performing a re-oxidation process to thermally oxidize the substrate, performing a plasma nitridation process to insert nitrogen atoms into the high-k dielectric layer to form a plasma-nitrided high-k dielectric layer, and performing a post-nitridation anneal process to passivate chemical bonds in the plasma-nitrided high-k dielectric layer.

[0005] One or more embodiments of the present disclosure relate to a method of forming a semiconductor device. In one or more embodiments, the method includes annealing a surface of a substrate to form a smooth surface, forming a high-k dielectric layer on the surface of the substrate, performing a re-oxidation process to thermally oxidize the surface of the substrate, performing a plasma nitridation process to insert nitrogen atoms into the high-k-κ dielectric layer to form a plasma-nitrided high-k dielectric layer, and performing a post-nitridation annealing process to passivate chemical bonds in the plasma-nitrided high-k dielectric layer.

[0006] Another embodiment of the present disclosure relates to a processing system. In one or more embodiments, the processing system includes a first processing chamber, a second processing chamber, a third processing chamber, a fourth processing chamber, and a fifth processing chamber, and a system controller, the system controller being configured to anneal a surface of a substrate to form a smooth surface in the first processing chamber, deposit a high-k dielectric layer on the surface of the substrate in the second processing chamber, expose the deposited high-k dielectric layer to a nitrogen plasma to form a plasma-nitrided high-k dielectric layer in the third processing chamber, perform a re-oxidation process to thermally oxidize a surface of the substrate in the fourth processing chamber, and anneal the plasma-nitrided high-k dielectric layer in the fifth processing chamber, and the substrate is transferred between the first, second, third, fourth, and fifth processing chambers without breaking the vacuum environment in the processing system.

[0007] So that the above features of the present disclosure can be understood in detail, a more detailed description of the present disclosure briefly summarized above can be made by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments of the present disclosure and therefore should not be considered as limiting its scope.

[0008] FIG. 1 is a schematic top view of an exemplary multi-chamber processing system in accordance with one or more embodiments. [0009] FIG. 1 is a process flow diagram of a method of forming a semiconductor structure according to one or more embodiments. [0010] FIG. 1 is a schematic diagram of a semiconductor structure according to one or more embodiments. [0011] FIG. 1 illustrates a process flow diagram of a method for forming a semiconductor structure according to one or more embodiments. [0012] FIG. 1 illustrates a schematic cross-sectional view of an exemplary substrate according to one or more embodiments. [0013] FIG. 1 is a process flow diagram of a method of forming a semiconductor structure according to one or more embodiments. [0014] Figures 7A and 7B are schematic diagrams of a semiconductor structure according to one or more embodiments.

[0015] For ease of understanding, wherever possible, identical reference numbers have been used to designate identical elements common to multiple figures. It is contemplated that components and features of one embodiment may be beneficially incorporated in other embodiments without further description.

[0016] Before describing some example embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of configuration or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0017] As the dimensions of gate structures decrease, new material structures are sought that provide improvements. The use of high-k dielectric materials increases the dielectric constant of the gate structure over conventional gate structures that use materials such as silicon oxide. However, as with silicon oxide, decreasing the thickness of the gate structure increases leakage current. For example, decreasing the effective oxide thickness increases gate leakage. Thus, the inverse relationship between gate leakage and effective oxide thickness can create limitations in the performance of the transistor and the devices that are fabricated.

[0018] High-k dielectric materials have the potential to provide greater channel mobility than silicon oxides of similar thickness. As the industry continues to pursue thinner effective oxide thicknesses without increasing gate leakage, efforts to maximize the dielectric constant (also called "kappa value") of known high-k materials are reaching limits due to morphological characteristics. Conventional techniques struggle to overcome the natural properties of high-k materials that may set an upper limit on kappa values, which may then lead to device retooling when incorporating new films.

[0019] The embodiments described herein provide systems and methods for improving the properties of high-k dielectric materials. Producing high-k dielectric materials that exhibit specific morphologies or grain structures may enable higher dielectric constants and associated improved device performance. To control grain formation in exemplary devices, treatments are performed to provide activated substrate surfaces that can induce specific grain growth, and may further stabilize the film after formation, resulting in a higher dielectric constant.

[0020] The embodiments described herein provide a hydrogen annealing process that smooths the surface of a substrate, e.g., silicon, prior to film deposition. During a subsequent high temperature annealing process, the hydrogen-silicon bonds are broken and the hydrogen is passivated. This differs from standard hydrogen passivation processes, in which the hydrogen-silicon bonds are maintained throughout the formation of the final device.

[0021] As used in this specification and the appended claims, the term "substrate" refers to a surface or a portion of a surface on which a process acts. It will be understood by those skilled in the art that a reference to a substrate can also refer to only a portion of a substrate, unless the context clearly indicates otherwise. Furthermore, a reference to deposition on a substrate can refer to both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0022] "Substrate" as used herein refers to any substrate or material surface formed on a substrate on which a film processing is performed during a manufacturing process. For example, substrate surfaces on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. The substrate may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and/or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in this disclosure, any of the disclosed film processing steps may be performed on an underlayer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include the underlayer as the context indicates. Thus, for example, when a film/layer or partial film/layer is deposited on a substrate surface, the exposed surface of the newly deposited film/layer becomes the substrate surface.

[0023] As used herein and in the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gas species capable of reacting with the substrate surface.

[0024] Figure 1 is a schematic top view of an example of a multi-chamber processing system 100 according to some examples of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 with respective transfer robots 112, 114, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As described in detail herein, wafers in the processing system 100 can be processed in and transferred between the various chambers without exposing the wafers to an ambient environment outside the processing system 100 (e.g., an ambient atmospheric environment that may exist in a factory). For example, wafers can be processed in and transferred between the various chambers in a low pressure (e.g., about 300 Torr or less) or vacuum environment without breaking the low pressure or vacuum environment during the various processes performed on the wafers in the processing system 100. Thus, processing system 100 can provide an integrated solution for processing a portion of a wafer.

[0025] Examples of processing systems that may be suitably modified in accordance with the teachings provided herein include the Endura®, Producer®, or Centura® integrated processing systems available from Applied Materials, Inc., Santa Clara, Calif., or other suitable processing systems. It is contemplated that other processing systems (including those from other manufacturers) may be adapted to benefit from the aspects described herein.

[0026] In the example shown in FIG. 1, the factory interface 102 includes a docking station 140 and a factory interface robot 142 to facilitate transfer of wafers. The docking station 140 is configured to receive one or more front opening unified pods (FOUPs) 144. In some examples, each factory interface robot 142 generally includes a blade 148 disposed at one end of each factory interface robot 142 configured to transfer wafers from the factory interface 102 to the load lock chambers 104, 106.

[0027] The load lock chambers 104, 106 have respective ports 150, 152 coupled to the factory interface 102 and respective ports 154, 156 coupled to the transfer chamber 108. The transfer chamber 108 further has respective ports 158, 160 coupled to the holding chambers 116, 118 and respective ports 162, 164 coupled to the processing chambers 120, 122. Similarly, the transfer chamber 110 has respective ports 166, 168 coupled to the holding chambers 116, 118 and respective ports 170, 172, 174, 176 coupled to the processing chambers 124, 126, 128, 130. Ports 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, 176 can be, for example, slit valve openings with slit valves to pass wafers through by the transfer robots 112, 114 and provide a seal between the chambers to prevent gas from passing between the chambers. Generally, every port is open to transfer a wafer. The ports are otherwise closed.

[0028] The load lock chambers 104, 106, the transfer chambers 108, 110, the holding chambers 116, 118, and the processing chambers 120, 122, 124, 126, 128, 130 can be fluidly connected to a gas and pressure control system (not specifically shown). The gas and pressure control system can include one or more gas pumps (e.g., turbo pumps, cryopumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. In operation, the factory interface robot 142 transfers a wafer from the FOUP 144 to the load lock chamber 104 or 106 through the port 150 or 152. The gas and pressure control system then pumps down the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and the holding chambers 116, 118 at an internal low pressure or vacuum environment (which may include an inert gas). Thus, pumping down the load lock chambers 104 or 106 facilitates passing a wafer between, for example, the atmospheric environment of the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108.

[0029] With the wafer in the load lock chamber 104 or 106 pumped down, the transfer robot 112 transfers the wafer from the load lock chamber 104 or 106 to the transfer chamber 108 via the port 154 or 156. The transfer robot 112 can then transfer the wafer to either of the processing chambers 120, 122 via the respective ports 162, 164 for processing, and to the holding chambers 116, 118 via the respective ports 158, 160 for holding awaiting further transfer. Similarly, the transfer robot 114 can access the wafer in the holding chamber 116 or 118 via the port 166 or 168, and can transfer the wafer to either of the processing chambers 124, 126, 128, 130 via the respective ports 170, 172, 174, 176 for processing, and to the holding chambers 116, 118 via the respective ports 166, 168 for holding awaiting further transfer. Transfer and holding of the wafer within and between the various chambers can be done in a low pressure or vacuum environment provided by a gas and pressure control system.

[0030] The processing chambers 120, 122, 124, 126, 128, 130 may be any suitable chambers for processing wafers. In some embodiments, the processing chamber 120 may perform an annealing process, the processing chamber 122 may perform a cleaning process, and the processing chambers 124, 126, 128, 130 may perform an epitaxial growth process. In some examples, the processing chamber 122 may perform a cleaning process, the processing chamber 120 may perform an etching process, and the processing chambers 124, 126, 128, 130 may perform their respective epitaxial growth processes. The processing chamber 122 may be a SiCoNi™ pre-clean chamber available from Applied Materials of Santa Clara, California. The processing chamber 120 may be a Selectra™ etch chamber available from Applied Materials of Santa Clara, California.

[0031] A system controller 190 is coupled to the processing system 100 to control the processing system 100 or components thereof. For example, the system controller 190 can control the operation of the processing system 100 using direct control of the chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, 130 of the processing system 100 or by controlling controllers associated with the chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, 130. During operation, the system controller 190 enables data collection and feedback from each chamber to adjust the performance of the processing system 100.

[0032] The system controller 190 generally includes a central processing unit (CPU) 192, a memory 194, and support circuits 196. The CPU 192 can be one of any type of general-purpose processor that can be used in an industrial environment. The memory 194, or non-transitory computer-readable medium, is accessible by the CPU 192 and can be one or more memories, such as random access memory (RAM), read-only memory (ROM), a floppy disk, a hard disk, or other forms of digital storage, local or remote. The support circuits 196 are coupled to the CPU 192 and can include cache, clock circuits, input/output subsystems, power supplies, and the like. The various methods disclosed herein can generally be implemented by the CPU 192 executing computer instruction codes stored in the memory 194 (or the memory of a particular process chamber) as, for example, software routines under the control of the CPU 192. When the computer instruction codes are executed by the CPU 192, the CPU 192 controls each chamber to perform processing according to various schemes.

[0033] Other processing systems may have other configurations. For example, more or fewer processing chambers may be coupled to the transfer apparatus. In the illustrated example, the transfer apparatus includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and/or more or fewer holding chambers (e.g., no holding chambers) may be implemented as a transfer apparatus in a processing system.

2 is a process flow diagram of a method 200 for forming a semiconductor structure 300 according to one or more embodiments of the present disclosure. FIGS. 3A and 3B are cross-sectional views of a portion of the semiconductor structure 300 corresponding to various states of the method 200. It should be understood that FIGS. 3A and 3B show only a partial schematic view of the semiconductor structure 300, and that the semiconductor structure 300 may include any number of transistor sections and additional materials having the aspects shown in the figures. It should also be noted that although the method steps shown in FIG. 2 are described in sequence, other processing sequences including one or more method steps omitted and/or added and/or rearranged in another desired order are within the scope of the embodiments of the disclosure provided herein.

[0035] The method 200 begins with an annealing process in operation 205. The annealing process may include spike annealing the substrate in a hydrogen (H ₂ ) ambient at a temperature ranging from 500° C. to 700° C. The annealing 205 may include a spike thermal annealing process carried out in a rapid thermal processing chamber, such as, for example, a RADOX™ chamber available from Applied Materials, Inc., Santa Clara, Calif. The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1. Without intending to be bound by theory, it is believed that spike annealing the surface of the substrate 302 in a hydrogen (H ₂ ) ambient smoothes the substrate surface 302 prior to film deposition, improving channel mobility. In one or more embodiments, the annealing 205 serves a different purpose than the passivation annealing process. In one or more embodiments, to smooth the substrate surface 302, hydrogen (H ₂ ) is reacted with the substrate surface, e.g., silicon (Si), by annealing in an atmosphere of hydrogen (H ₂ ). In one or more embodiments, a subsequent high temperature annealing step breaks the hydrogen-silicon (H—Si) bonds and intentionally passivates the hydrogen after film deposition. In standard passivation processes, on the other hand, the hydrogen-silicon (H—Si) bonds are maintained at the end of the process.

[0036] In some embodiments, after annealing 205, a pre-cleaning process is performed in operation 210 to pre-clean the surface of substrate 302. The pre-cleaning process can include a wet process using an ozone ( _O3 ) pre-clean or a solution such as a Standard Clean 1 ( _SC1 ) solution containing _NH4OH (ammonium hydroxide), _H2O2 (hydrogen peroxide ₎ , and _H2O (water), or an oxidation of the surface of substrate 302 by a dry etching process, for example a SiConi™ remote plasma assisted dry etching process in which the surface of substrate 302 is exposed to _N2 , _NF3 , and NH3 plasma by-products.
In a particular embodiment, after the hydrogen ( _H2 ) anneal, the pre-clean process 210 includes an ozone ( _O3 ) pre-clean or an SC1 wet process to pre-clean the surface of the substrate 302. The pre-clean process may be performed in a pre-clean chamber, such as the process chambers 122 or 120 shown in FIG.

[0037] Although not shown in FIG. 2, in some embodiments, a pre-cleaning process 210 can be performed prior to annealing 205.

[0038] In operation 220, as shown in Figure 3A, an interface formation process is performed to form an interface layer 304 on the pre-cleaned surface of the substrate 302. The interface formation process may include a suitable thermal oxidation process, such as an enhanced in-situ steam generation (eISSG) process using nitrous oxide ( _N2O ) gas. The interface layer 304 formed in operation 220 is a thin amorphous silicon oxide ( _SiO2 ) layer having a thickness between about 3 Å and about 10 Å, e.g., about 5 Å, corresponding to one or more monolayers of silicon oxide. In some embodiments, the interface layer 304 may be formed by an in-situ steam generation (ISSG) process using _H2 and _O2 gases or a rapid thermal oxidation (RTO) process using _NH3 and _O2 gases. The interface layer 304 can act as a nucleation layer for a high-k dielectric material layer deposited thereon and improve the quality (e.g., interface state density, storage capacitance, frequency dispersion, leakage current, etc.) of the interface between the substrate 302 and the high-k dielectric material layer. The interface formation process can be performed in a process chamber, such as process chambers 120, 122, 124, 126, 128, or 130 shown in FIG.

[0039] In some embodiments, the interface formation process of operation 220 is omitted, and the interface layer 304 is not formed before depositing the high-k dielectric material layer on the substrate 302. In that case, the interface layer 304 is formed by a thermal oxidation process in operation 250 or operation 290, which will be described later, in which the substrate 302 is thermally oxidized through the high-k dielectric material layer deposited on the substrate 302. The interface layer 304 formed by the thermal oxidation process in operation 250 or operation 290 may be sufficiently thick to ensure reliable device characteristics (interface state density, storage capacitance, frequency dispersion, leakage current, etc.) and to reduce atomic diffusion from the high-k dielectric material layer to the substrate 302, and has a thickness between about 0.3 nm and about 1 nm, for example about 0.5 nm.

[0040] In operation 230, a deposition process is performed to deposit a high-k dielectric layer 306 on an exposed surface of the semiconductor structure 300 (i.e., the interfacial layer 304 if the interfacial layer 304 is formed in operation 220, or the substrate 302 if the interfacial layer 304 is not formed in operation 220, as shown in _FIG . 3B). The high-k dielectric layer 306 may be formed from a high-k dielectric material, such as hafnium dioxide ( _HfO2 ), zirconium dioxide ( _ZrO2 ), ytterbium oxide ( _Y2O3 ), or aluminum oxide ( _Al2O3 ). The deposition process may include an atomic layer deposition ( _ALD ) process in which a metal-containing precursor and an oxygen-containing precursor are alternately supplied to the exposed surface of the semiconductor structure 300. In some embodiments, the metal-containing precursor is purged prior to supplying the oxygen-containing precursor. The metal may be a transition metal such as hafnium (Hf), zirconium (Zr), titanium (Ti), a rare earth metal such as lanthanum (La), ytterbium (Yb), yttrium (Y), an alkaline earth metal such as strontium (Sr), or other metals such as aluminum (Al). The oxidizer may be any oxygen-containing precursor that may react with the metal. For example, the oxygen-containing precursor may be or may include water, diatomic oxygen, ozone, a hydroxyl-containing precursor or alcohol, a nitrogen- and oxygen-containing precursor, plasma-enhanced oxygen including locally or remotely enhanced oxygen, or any other material containing oxygen that may be incorporated into the metal to produce a layer of oxide of the metal on the substrate 302. In one example, the metal-containing precursor is hafnium tetrachloride (HfCl ₄ ) and the oxidizer is water (H ₂ O) to form a hafnium dioxide (HfO ₂ ) layer. The ALD process may be performed at a temperature between about 200° C. and about 400° C., for example, about 270° C. The high-k dielectric layer 306 deposited by the ALD process may be amorphous and have a thickness between about 10 Å and about 30 Å. The deposition process may be performed in a process chamber, such as process chambers 120, 122, 124, 126, 128, or 130 shown in FIG.

[0041] In operation 240, an optional annealing process is performed to harden and densify the as-deposited high-k dielectric layer 306. Crystallization of the as-deposited amorphous high-k dielectric layer 306 may occur. The post-deposition annealing process may include a thermal annealing process in an inert atmosphere, such as nitrogen ( _N2 ) and argon (Ar) atmosphere, performed in a rapid thermal processing (RTP) chamber, such as a RADOX™ chamber available from Applied Materials, Inc., Santa Clara, Calif. The RTP chamber may be any of the process chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1. The post-deposition annealing process may thermally harden and densify the interfacial layer 304 and the high-k dielectric layer 306.

[0042] The post-deposition annealing process can be performed at a temperature between about 500°C and about 800°C, at a pressure between about 0.01 Torr and 10 Torr, and for a time between about 1 second and about 60 seconds.

[0043] In operation 250, instead of the post-deposition annealing process in operation 240, an optional re-oxidation process is performed to thermally oxidize the substrate 302. The re-oxidation process may include a thermal annealing process in an inert ambient, such as oxygen ( _O2 ), nitrous oxide ( _N2O ), and _H2 ambient, performed in a rapid thermal processing (RTP) chamber, such as a RADOX™ chamber available from Applied Materials, Inc., located in Santa Clara, Calif. The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. The reoxidation process in operation 250 can thermally oxidize the underlayer through the high-k dielectric layer 306, thus thickening the interfacial layer 304, if the interfacial layer 304 was formed in operation 220 to a thickness between about 3 Å and about 10 Å, or form an interfacial layer 304 in the substrate 302 near the interface with the high-k dielectric layer 306, if the interfacial layer 304 was not formed in operation 220.

[0044] The reoxidation process can be carried out at a temperature between about 400°C and about 900°C, at a pressure between about 0.01 Torr and 10 Torr, and for a time between about 1 second and about 30 seconds.

[0045] In operation 260, a plasma nitridation process is performed to insert nitrogen atoms into vacancies and defects in the high-k dielectric layer 306. The plasma nitridation process may be a decoupled plasma nitridation (DPN) process performed in a DPN chamber, such as a CENTURA® DPN chamber available from Applied Materials, Inc., Santa Clara, Calif. The DPN chamber may be any of the process chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1. The plasma nitridation process exposes the high-k dielectric layer 306 to a nitrogen plasma, which may allow nitrogen radicals or nitrogen atoms to be incorporated into the high-k dielectric layer 306 throughout the thickness of the high-k dielectric layer 306. During the plasma nitridation process, the nitrogen atoms may form metastable bonds with oxygen (O). Gases that may be used in the plasma process include nitrogen-containing gases such as nitrogen ( _N2 ), ammonia ( _NH3 ), or mixtures thereof. In one example, the nitrogen gas is ammonia ( _NH3 ) mixed with about 3% to about 8% nitrogen ( _N2 ). The plasma nitridation process may not change the thickness of the high-k dielectric layer 306 as a result of the incorporation of nitrogen into pores and defects in the as-deposited high-k dielectric layer 306.

[0046] The nitriding process can be carried out at a temperature between about 0°C and about 500°C for a period between about 10 seconds and about 300 seconds.

[0047] In operation 270, an optional thermal nitridation process is performed to further insert nitrogen atoms into vacancies and defects in the plasma nitrided high-k dielectric layer 306. The thermal nitridation process may include a thermal annealing process in an ammonia (NH3) ambient performed in a rapid thermal processing (RTP) chamber, such as a RADOX™ chamber available from Applied Materials, Inc., Santa Clara, Calif. The RTP chamber may be any of the process chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1.

[0048] The thermal nitridation process can be performed at a temperature between about 700°C and about 900°C, at a pressure between about 10 Torr and 740 Torr, and for a period between about 10 seconds and about 300 seconds.

[0049] In operation 280, a post-nitridation annealing process is performed to passivate remaining chemical bonds in the plasma-nitrided high-k dielectric layer 306. The post-nitridation annealing process may include a spike thermal annealing process in nitrogen ( _N2 ) and argon (Ar) ambient performed in a rapid thermal processing (RTP) chamber, such as a RADOX™ chamber available from Applied Materials, Inc., Santa Clara, Calif. The RTP chamber may be any of the process chambers 120, 122, 124, 126, 128, and 130 shown in Figure 1. The post-nitridation annealing process passivates metastable nitrogen bonds formed in the plasma nitridation process of operation 240, and may result in crystallization of the amorphous high-k dielectric layer 306.

[0050] The thermal spike annealing process can be performed at a temperature between about 700°C and about 850°C, at a pressure between about 10 Torr and 740 Torr, and for a time between about 1 second and about 30 seconds.

[0051] In operation 290, as an alternative to the post-nitridation annealing process in operation 280, a post-nitridation annealing and reoxidation process is performed to passivate the remaining chemical bonds in the high-k dielectric layer 306 as in operation 280, while simultaneously thermally oxidizing the substrate 302 as in operation 250. The post-nitridation annealing and reoxidation process in operation 290 is the same as the reoxidation process in operation 250. Therefore, details of the post-nitridation annealing and reoxidation process in operation 290 are omitted here.

[0052] In the embodiments described herein, systems and methods are provided for forming high quality thin high-k dielectric material layers. The properties of such high-k dielectric material layers can be well controlled. For example, the nitridation process in operations 260 and 270 can be controlled to introduce between about 3 atomic % and about 20 atomic % nitrogen into the high-k dielectric layer 306 to achieve higher dielectric constant values than higher amounts of nitrogen and better structural stabilization than lower amounts of nitrogen. The annealing process in operations 240, 270, 280, and 290 can also be controlled to provide grains having a size greater than about 20 Å in the high-k dielectric layer 306 to reduce leakage current through the high-k dielectric layer 306.

[0053] FIG. 4 is a process flow diagram of a method 400 for forming a semiconductor structure 500 in accordance with one or more embodiments of the present disclosure. In one or more embodiments, the operations of the method 400 may be performed in one or more chambers incorporated into a multi-chamber processing system 100, as previously described.

[0054] Method 400 may include one or more operations prior to the initiation of the described method operations, including front-end processing, deposition, etching, polishing, cleaning, or other operations performed prior to the described operations. The method may include numerous optional operations that may or may not be specifically associated with the method according to the present technology as illustrated in the figures. For example, many of the operations are described to provide a broader range of structure formation processes, but are not critical to the technology and may be performed by alternative methods as described further below. Method 400 describes the operations illustrated generally in Figures 5A-5F, which are described in conjunction with the operations of method 400. It should be understood that Figures 5A-5F show only partial schematic diagrams, and that the substrate may include any number of transistor sections and additional materials having aspects as illustrated in the figures.

[0055] Method 2400 may include optional operations to develop the semiconductor structure for a particular manufacturing operation. In some embodiments, method 400 may be performed on a basic structure, but in some embodiments, the method may be performed subsequent to the formation of other materials. As shown in FIG. 5A, the semiconductor structure may represent a device 500 after certain processing has been completed. For example, substrate 505 may be a planar material or a structured device, and it will be understood that materials that may include one or more materials configured as or defining posts, trenches, or other structures are also encompassed by the present technology. Substrate 505 may include any number of materials, including silicon or silicon-containing materials such as oxides, nitrides, carbides of silicon, as well as other materials that may be incorporated into the structure.

[0056] One or more layers of material may be formed over a portion or all of the substrate 505 or at least partially within the substrate to produce a structure, which may be a planarized material or a structured material, in embodiments. By way of non-limiting example, the substrate 505 may be or include silicon, or may include a surface amount of silicon formed over an additional material, such as silicon oxide, which may be a reduced portion of the silicon oxide leaving a silicon exposed surface. The substrate 505 may include a native oxide 510 as shown in FIG. 5A. In some embodiments, the exposed material on the surface of the substrate 505 may be etched, planarized, or otherwise processed to produce an intermittent pattern. Although shown as a single example, it should be understood that the apparatus 500 may include smaller sections of a larger process integration, which may include any number of additional sections similar or different to those shown. The substrate 505 may be contained or placed in a processing region of a semiconductor processing chamber, and the method 400 may be performed to produce a semiconductor material, such as a high-k dielectric material, on the substrate.

[0057] Method 400 may begin with an annealing process in operation 405. The annealing process may include spike annealing the substrate in a hydrogen (H ₂ ) ambient at a temperature ranging from 500° C. to 700° C. Annealing 405 may include a spike thermal annealing process carried out in a rapid thermal processing chamber, such as, for example, a RADOX™ chamber available from Applied Materials, Inc., Santa Clara, Calif. The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1. Without intending to be bound by theory, it is believed that spike annealing the surface of the substrate 505 in a hydrogen (H ₂ ) ambient smoothes the substrate surface 505 prior to film deposition, improving channel mobility. In one or more embodiments, annealing 405 serves a different purpose than the passivation annealing process. In one or more embodiments, to smooth the substrate surface 505, hydrogen (H ₂ ) is reacted with the substrate surface, e.g., silicon (Si), by annealing in an atmosphere of hydrogen (H ₂ ). In one or more embodiments, a subsequent high temperature annealing step breaks the hydrogen-silicon (H—Si) bonds and intentionally passivates the hydrogen after the film is deposited. In standard passivation processes, on the other hand, the hydrogen-silicon (H—Si) bonds are maintained at the end of the process.

[0058] In some embodiments, after annealing 405, method 400 may include removing native oxide 510 (as in FIG. 5A) from substrate 505 in operation 410. Removing native oxide 410 may be or include flowing a fluorine-containing precursor and a hydrogen-containing precursor. The fluorine-containing precursor may be or include nitrogen trifluoride and any other fluorine-containing precursor. The hydrogen-containing precursor may be characterized by an amine group [-NH ₂ ] or other nitrogen- or hydrogen-containing group. For example, the hydrogen-containing precursor may be or include a nitrogen- and hydrogen-containing precursor, such as, by way of non-limiting example, ammonia. Flowing may include flowing the fluorine-containing precursor and the hydrogen-containing precursor to a remote plasma region. The remote plasma region may be fluidly coupled to the substrate processing region. A plasma may be formed to generate a plasma effluent. The flow rate of the fluorine-containing precursor and the flow rate of the hydrogen-containing precursor may be characterized by an atomic flow ratio of hydrogen to fluorine of less than 1:2. The native oxide 410 is removed by flowing the plasma effluent through the substrate processing region while forming solid by-products on the surface of the substrate. Without being bound to a particular theory, the flow may leave a layer of fluorine on the substrate surface, which facilitates interface formation in operation 415, and the fluorine termination helps to increase reliability. The solid by-products are sublimated by increasing the temperature of the substrate above the sublimation temperature of the solid by-products. After sublimation, the substrate 505 is free or substantially free of native oxide. The removing may be or include removing the native oxide to a depth of up to or about 20 Å.

[0059] Method 400 may include a SiConi™ etch in operation 410, which may be a remote plasma-assisted dry etch process involving simultaneous exposure of a substrate, such as substrate 505 of FIG. 5A, to _H2 , _NF3 , and/or _NH3 plasma by-products. The removal of native oxide in operation 410 may be performed by an in-situ dry chemical process in which the substrate surface is not exposed to an atmosphere or an oxygen-containing environment. The removal of native oxide in operation 410 may be performed in a first processing chamber in some embodiments of method 400. Method 400 may include transferring the substrate from the first processing chamber to a second processing chamber prior to forming the high-k dielectric material, as in operation 420. Method 400 may include performing operations in one or more processing chambers without exposing the substrate surface to atmosphere or air. Method 400 may include maintaining a vacuum in system 100 during removal in operation 410. Maintaining an integrated vacuum can advantageously reduce surface contamination. Transfers may occur between one or more chambers on a single platform, or between chambers on multiple platforms. However, utilizing a single platform may better avoid exposing the substrate to oxygen and/or moisture environments.

[0060] In one or more embodiments, the method 400 can include, in operation 415, providing nitrous oxide and thermally annealing the substrate surface to form an oxide-containing interface. The nitrous oxide 515 provided to the substrate 505 as in FIG. 5B can help control how much of the substrate 505 having a surface without a native oxide is oxidized to form the oxide-containing interface 520 as in FIG. 5C. The operation 415 can include a thermal-based reaction using steam, such as an in-situ steam generation (ISSG) process, whereby oxidation occurs at a lower rate compared to conventional thermal techniques utilizing hydrogen and/or oxygen. The nitrogen can act as a carrier for oxygen and may not become part of the interface or the substrate. The oxide-containing interface formed is of high quality and highly ordered, meaning a crystallographic structure that is free or substantially free of defects. This can provide an interface 520 that can prevent nitrogen from approaching the channel region and prevent leakage during subsequent operation. The resulting oxide-containing interface can include silicon dioxide. The formed oxide-containing interface 520 may have a thickness of up to or about 5 Å. The method 400 may include, in operation 410, removal of the thicker native oxide, which may be replaced in a subsequent operation by the thinner oxide-containing interface 520.

[0061] The method 400 can include delivering a pretreatment precursor to the substrate. The pretreatment precursor can be or include a nitrogen-containing precursor or an oxygen-containing precursor. The precursor can contact the substrate and form or introduce reactive ligands on the exposed surface of the substrate, shown as ligands 520 in FIG. 5D. Unlike conventional techniques, the present technique can utilize a pretreatment configured to produce an ordered growth of a high-k dielectric material in a subsequent operation.

[0062] For example, in some embodiments, the substrate may be or include an exposed surface of silicon. The substrate 505 may itself be silicon or other silicon-containing material that has been reduced or modified to exhibit a silicon surface. As one non-limiting example in which the substrate 505 may include silicon oxide, an initial pretreatment may include removing oxygen from the surface of the structure, such as with a hydrogen-containing precursor. A thin surface layer of silicon may then be exposed. Without being bound to a particular theory, in some embodiments, silicon may provide improved base properties for receiving nitrogen-containing precursors compared to silicon oxide. This may enable superior formation of certain high-k dielectric materials.

[0063] The pretreatment precursor may be or include any nitrogen-containing or oxygen-containing precursor. Oxygen-containing precursors may be characterized by hydroxyl groups [-OH] that may be incorporated into the surface of the substrate 505. Nitrogen-containing precursors may be characterized by amine groups [ _-NH2 ] or other nitrogen-containing groups. For example, the nitrogen-containing precursor may be or include a nitrogen- and hydrogen-containing precursor, such as ammonia, as a non-limiting example, or a precursor that includes nitrogen and oxygen, or other precursor that includes nitrogen.

[0064] The surface termination in some embodiments may be or include a hydroxyl or amine group terminated surface. Method 400 may then include forming a high-k dielectric material on the substrate in operation 420. While the technique can encompass any formation or deposition of a high-k material, in some embodiments, formation operation 420 may be or include an atomic layer deposition or other atomic layer deposition chamber. Formation may be performed immediately after pre-treating the substrate surface, may be performed in the same chamber as the pre-treatment, or may be performed in an additional chamber, such as an additional chamber integrated into the same system, such as system 100. In some embodiments, vacuum conditions may be maintained while the substrate is transferred from the pre-treatment chamber to the deposition or formation chamber, thereby limiting exposure of the substrate to air.

[0065] When an atomic layer deposition process is performed to form a high-k dielectric material, a metal-containing precursor may be delivered to the substrate to react with the pretreated surface. For example, a transition metal-containing precursor, a base metal-containing precursor, or a lanthanide metal-containing precursor may be delivered to the process chamber to interact with reactive ligands exposed on the substrate by pretreatment. An oxygen-containing precursor may then be delivered in a second operation, such as a purge of the metal-containing precursor. This may result in an oxide layer, such as layer 530a as shown in FIG. 5E, being produced by atomic layer deposition. In one non-limiting example, a hafnium-containing precursor may be delivered in a first operation and an oxidizer may be delivered in a second operation to produce a hafnium oxide film. Additional metal-containing precursors may include zirconium-containing precursors to produce zirconium-containing materials, as well as any number of other metal-containing precursors to produce additional metal oxide structures. In the case of hafnium-containing precursors, and in the case of similar alternative metals, the precursor can be or include a halogen-containing precursor, an oxygen-containing precursor, a hydrogen-containing precursor, or a carbon-containing precursor in which hafnium is incorporated.

[0066] The oxidizing agent can be any oxygen-containing precursor that can react with the metal. For example, the oxygen-containing precursor can be or include water, diatomic oxygen, ozone, hydroxyl-containing precursors or alcohols, nitrogen- and oxygen-containing precursors, plasma-enhanced oxygen, including locally or remotely enhanced oxygen, or other materials that contain oxygen that can be incorporated into the metal, such as hafnium, to produce a metal oxide material layer on the substrate. Again, any of the above metal-containing materials can be used in embodiments of the present technology and can include any of the grouped metals, which can include, but are not limited to, hafnium, zirconium, silicon, lanthanum, aluminum, titanium, strontium, or combinations of these materials, such as, for example, hafnium silicate.

[0067] Once pretreatment according to embodiments of the present technology has been performed, the structure of the metal-containing material can be formed or deposited in an orderly manner to produce a more uniform grain structure. This can be produced by forming reactive ligands of the pretreatment precursor on a more structured surface material such as silicon. Furthermore, performing the pretreatment exposure under specific conditions can result in further improvements.

[0068] The pretreatment can be performed at a temperature configured to activate the precursor and/or the surface of the substrate. For example, in situations where nitrogen- and hydrogen-containing precursors can be used as pretreatment precursors, the substrate can be maintained at a temperature of about 300° C. or higher during the delivery of the precursor. Similarly, pretreatment with oxygen-containing precursors can also be performed while maintaining the substrate temperature at about 300° C. or higher. For any pretreatment operation, the substrate can also be maintained at a temperature of about 400° C. or higher, about 500° C. or higher, about 600° C. or higher, about 700° C. or higher, about 800° C. or higher, or higher. If the temperature of the pretreatment is reduced to about 500° C. or lower, it may be less effective. Similarly, if the temperature is increased to about 700° C. or higher, nucleation may not be improved and excess precursor may be incorporated at the surface, reducing device mobility. Thus, in some embodiments, the temperature can be maintained between about 500° C. and about 700° C. during pretreatment.

[0069] Similarly, exposure time may affect the amount of nitrogen-containing precursor incorporation, and therefore, to limit mobility loss in the fabricated device, exposure to the precursor may be less than about 3 minutes, and in some embodiments, exposure time may be about 2.5 minutes or less, about 2 minutes or less, about 1.5 minutes or less, about 1 minute or less, about 45 seconds or less, about 30 seconds or less, about 15 seconds or less, or less. Once an appropriate amount of amine groups is incorporated, formation may be performed. Although formation, including atomic layer formation, may be performed at any temperature, in some embodiments, atomic layer deposition may be performed at a temperature below or about the temperature at which pretreatment is performed, regardless of whether the operations are performed in the same chamber or a different chamber. For example, atomic layer deposition may be performed at a second temperature compared to the pretreatment temperature, and in embodiments, the formation temperature may be less than about 500°C, about 450°C or less, about 400°C or less, about 350°C or less, about 300°C or less, about 250°C or less, or less.

[0070] After the layer of high-k material is formed or deposited, one or more post-processing operations can be performed. In some embodiments, the substrate can be transferred from the deposition chamber to another chamber or series of chambers to post-process the material. As described above, the transfer can be performed on a single processing system having multiple chambers, and thus the transfer from or between any of these chambers can be performed while maintaining vacuum conditions. The method 400 can then include one or more additional post-processing operations. The post-processing operations can include one or more operations performed in one or more chambers, including multiple chambers on the same cluster tool. The post-processing operations can include oxidation, nitridation 430, and/or thermal annealing 425.

[0071] As mentioned above, a pretreatment operation can be performed to provide sufficient termination moieties to provide the aforementioned uniform growth while limiting the incorporation of excess precursor into the substrate. For example, incorporated nitrogen interfaces can reduce the mobility of the fabricated transistor or reduce the rate at which carriers can move through the structure. The pretreatments described above can further improve the scaling of the high-k film, but if not controlled, the pretreatments can actually reduce the mobility of the device. However, in some embodiments, one post-treatment can include oxidizing the formed high-k material with a second oxygen-containing precursor relative to the first oxygen-containing precursor that can be used in the pretreatment operation.

[0072] For example, an oxidation operation can be performed utilizing any of the oxygen-containing precursors described above to further oxidize the film after formation. The deposition or formation of a high-k film can produce a porous film, or a film that includes voids in its structure. By performing the oxidation operation, oxygen species can penetrate the film and fill the voids as shown by layer 530b, as well as potentially produce oxide material at the interface of the high-k material, such as any layer 520, if not formed in the previous step described above. This can improve the interface of the underlying layer with amine end groups, which can improve the mobile performance of the device. To limit excessive buildup of the underlying oxide layer, the oxidation operation can be performed for a limited time and can be performed within any of the time ranges described above.

[0073] The post-treatment operation 430 may further include contacting the substrate with a second nitrogen-containing precursor, if used, relative to the pre-treatment nitrogen-containing precursor. The second nitrogen-containing precursor may include any of the nitrogen-containing precursors described above, including nitrogen gas, as well as any nitrogen-containing precursors mentioned elsewhere. The second nitrogen-containing precursor may include a plasma-activated or enhanced nitrogen-containing precursor, thermally activated nitrogen, or other nitrogen precursor that allows nitrogen radicals or nitrogen atoms to incorporate into the high-k structure, thereby stabilizing the film or stabilizing it toward an equilibrium state. Unlike an oxidation operation, nitridation does not increase the thickness of an underlayer, such as silicon oxide, and may slightly increase the k-value of the resulting film.

[0074] Nitrogen incorporation can be controlled to limit incorporation into the film to maintain structural and electrical properties. In some embodiments, post-treatment nitridation can incorporate less than about 20 atomic % nitrogen in the surface region of the high-k film, and can incorporate about 15 atomic % or less nitrogen, about 10 atomic % or less nitrogen, about 8 atomic % or less nitrogen, about 6 atomic % or less nitrogen, about 4 atomic % or less nitrogen, about 2 atomic % or less nitrogen, or less. In some embodiments, incorporation between about 3 atomic % and about 7 atomic % can maintain a higher k value than more nitrogen incorporation and can better stabilize the film than lower nitrogen incorporation. By surface region, it is meant the exposed surface of the material, although nitrogen incorporation can extend any distance within the film and be consistent or form a decreasing gradient throughout the material.

[0075] While the post-treatment oxidation or nitridation can be performed at any of the temperatures previously mentioned, in some embodiments, the post-treatment oxidation and/or nitridation can be performed at a temperature range of about 500° C. or less, and may be performed at a temperature range of about 400° C. or less, about 300° C. or less, about 200° C. or less, about 100° C. or less, or less, depending on the operation being performed.

[0076] A post-processing anneal 425, 435 can be performed after any operation, including any of the post-processing operations described above. The post-processing anneal can be performed in any chamber in which the previous operation was performed, or can involve transfer to a different chamber, such as a chamber configured to perform a rapid thermal annealing process. Again, the chamber can be incorporated on the same platform as other chambers, allowing transfer between chambers while maintaining a vacuum. The post-processing anneal can further align the film bonds and further stabilize the film. In embodiments, the post-processing anneal can be performed at a third temperature relative to the first temperature, which may be greater than or near the first temperature. For example, the post-processing anneal can be performed at a temperature of about 400° C. or greater, and in embodiments, at a temperature of about 500° C. or greater, about 600° C. or greater, about 700° C. or greater, about 800° C. or greater, about 900° C. or greater, or greater.

[0077] Improved high-k materials can be produced by performing pre-processing and/or post-processing according to embodiments of the present technique. Layers of high-k materials can be produced to any thickness, including up to or about a few nanometers. However, due to the favorable grain structure produced by the present technique, thinner effective oxide thicknesses can be produced without compromising gate leakage performance. High-k materials produced according to the present technique can be characterized by k values of about 10 or greater, and can be characterized by k values of about 15 or greater, about 20 or greater, about 21 or greater, about 22 or greater, about 23 or greater, about 24 or greater, about 25 or greater, or greater.

[0078] As noted above, the present technique allows for further improvements in dielectric constants compared to conventional techniques. Additionally, due to the grain structure created, the gate leakage current associated with the film may be about 1/10 of that of a silicon oxide film of similar thickness, about 1/100 of that of a silicon oxide film of similar thickness, about 1/1000 of that of a silicon oxide film of similar thickness, about 1/5,000 of that of a silicon oxide film of similar thickness, about 1/10,000 of that of a silicon oxide film of similar thickness, about 1/20,000 of that of a silicon oxide film of similar thickness, about 1/50,000 of that of a silicon oxide film of similar thickness, about 1/100,000 of that of a silicon oxide film of similar thickness, or less. By producing films according to embodiments of the present technique, formed films having beneficial morphologies can be produced, which can improve the electrical properties of the film compared to conventional techniques.

[0079] FIG. 6 is a process flow diagram of a method 600 for forming a semiconductor structure 700 according to one or more embodiments of the present disclosure. FIGS. 7A and 7B are cross-sectional views of a portion of the semiconductor structure 700 corresponding to various states of the method 600. It should be understood that FIGS. 7A and 7B show only a partial schematic view of the semiconductor structure 700, and that the semiconductor structure 700 may include any number of transistor sections and additional materials having the aspects shown in the figures. It should also be noted that although the method steps shown in FIG. 6 are described in sequence, other processing sequences including one or more method steps omitted and/or added and/or rearranged in another desired order are within the scope of the embodiments of the disclosure provided herein.

[0080] Method 600 begins with an annealing process in operation 605. The annealing process may include spike annealing the substrate in a hydrogen (H ₂ ) ambient at a temperature ranging from 500° C. to 700° C. Annealing 605 may include a spike thermal annealing process carried out in a rapid thermal processing chamber, such as, for example, a RADOX™ chamber available from Applied Materials, Inc., Santa Clara, Calif. The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1. Without intending to be bound by theory, it is believed that spike annealing the surface of the substrate 702 in a hydrogen (H ₂ ) ambient smoothes the substrate surface 702 prior to film deposition, improving channel mobility. In one or more embodiments, annealing 605 serves a different purpose than the passivation annealing process. In one or more embodiments, to smooth the substrate surface 702, hydrogen (H ₂ ) is reacted with the substrate surface, e.g., silicon (Si), by annealing in an atmosphere of hydrogen (H ₂ ). In one or more embodiments, a subsequent high temperature annealing step breaks the hydrogen-silicon (H—Si) bonds and intentionally passivates the hydrogen after the film is deposited. In standard passivation processes, on the other hand, the hydrogen-silicon (H—Si) bonds are maintained at the end of the process.

[0081] In some embodiments, after annealing 605, a pre-cleaning process is performed in operation 610 to pre-clean the surface of the substrate 702. The pre-cleaning process can be a wet process using an ozone ( _O3 ) process or a solution such as a Standard Clean 1 (SC1) solution containing _NH4OH (ammonium hydroxide), _H2O2 (hydrogen _peroxide ), and _H2O (water) to oxidize the surface of the substrate 702, for example a SiConi™ remote plasma assisted dry etching process in which the surface of the substrate 702 is exposed to _N2 , _NF3 , and NH3 process by-products. The pre-cleaning process can be performed in a pre-cleaning chamber, such as process chamber 122 or 120 shown in FIG. 1.

[0082] Although not shown in FIG. 6, in some embodiments, a pre-cleaning process 610 can be performed prior to annealing 605.

[0083] In operation 620, a deposition process is performed to deposit a high-k dielectric layer 704 on the exposed surfaces of the semiconductor structure _700. The high-k dielectric layer 704 may be formed from a high-k dielectric material such as hafnium dioxide ( _HfO2 ), zirconium dioxide _{( ZrO2} ), ytterbium oxide ( _Y2O3 ), or aluminum oxide ( _Al2O3 ). The deposition process may include an atomic layer deposition (ALD) process in which a metal-containing precursor and an oxygen-containing precursor are alternately supplied to the exposed surfaces of the semiconductor structure 700. In some embodiments, the metal-containing precursor is purged before supplying the oxygen-containing precursor. The metal may be a transition metal such as hafnium (Hf), zirconium (Zr), titanium (Ti), a rare earth metal such as lanthanum (La), ytterbium (Yb), yttrium (Y), an alkaline earth metal such as strontium (Sr), or other metal such as aluminum (Al). The oxidizer can be any oxygen-containing precursor that can react with the metal. For example, the oxygen-containing precursor can be or include water, diatomic oxygen, ozone, hydroxyl-containing precursors or alcohols, nitrogen- and oxygen-containing precursors, plasma-enhanced oxygen, including locally or remotely enhanced oxygen, or any other material containing oxygen that can be incorporated into the metal to produce a layer of oxide of the metal on the substrate 702. In one example, the metal-containing precursor is hafnium tetrachloride (HfCl ₄ ) and the oxidizer is water (H ₂ O), forming a hafnium dioxide (HfO ₂ ) layer. The ALD process can be performed at a temperature between about 200° C. and about 400° C., for example, about 270° C. The high-k dielectric layer 704 deposited by the ALD process can be amorphous and have a thickness between about 10 Å and about 30 Å. The deposition process may be carried out in a processing chamber, such as processing chambers 120, 122, 124, 126, 128, or 130 shown in FIG.

[0084] In operation 630, a re-oxidation process is performed to thermally oxidize the substrate 702. The re-oxidation process may include a thermal annealing process in an inert ambient, such as oxygen ( _O2 ), nitrous oxide ( _N2O ), and _H2 ambient, performed in a rapid thermal processing (RTP) chamber, such as a RADOX™ chamber available from Applied Materials, Inc., Santa Clara, Calif. The RTP chamber may be any of the process chambers 120, 122, 124, 126, 128, and 130 shown in Figure 1. The re-oxidation process in operation 630 may thermally oxidize the underlying layer through the high-k dielectric layer 704 to form an interfacial layer 706 near the interface with the high-k dielectric layer 704 on the substrate 702.

[0085] The reoxidation process can be carried out at a temperature between about 400°C and about 900°C, at a pressure between about 0.01 Torr and 10 Torr, and for a period between about 1 second and about 30 seconds.

[0086] In operation 640, a plasma nitridation process is performed to insert nitrogen atoms into vacancies and defects in the high-k dielectric layer 704. The plasma nitridation process may be a decoupled plasma nitridation (DPN) process performed in a DPN chamber, such as a CENTURA® DPN chamber available from Applied Materials, Inc., Santa Clara, Calif. The DPN chamber may be any of the process chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1. The plasma nitridation process exposes the high-k dielectric layer 704 to a nitrogen plasma, which may allow nitrogen radicals or nitrogen atoms to be incorporated into the high-k dielectric layer 704 throughout the thickness of the high-k dielectric layer 704. During the plasma nitridation process, the nitrogen atoms may form metastable bonds with oxygen (O). Gases that may be used in the plasma process include nitrogen-containing gases such as nitrogen ( _N2 ), ammonia ( _NH3 ), or mixtures thereof. In one example, the nitrogen gas is ammonia ( _NH3 ) mixed with about 3% to about 8% nitrogen ( _N2 ). The plasma nitridation process may not change the thickness of the high-k dielectric layer 704 as a result of the incorporation of nitrogen into pores and defects in the as-deposited high-k dielectric layer 704.

[0087] The nitriding process can be carried out at a temperature between about 0°C and about 500°C for a period between about 10 seconds and about 300 seconds.

[0088] In operation 650, an optional thermal nitridation process is performed to further insert nitrogen atoms into vacancies and defects in the plasma nitrided high-k dielectric layer 704. The thermal nitridation process may include a thermal annealing process in an ammonia ( _NH3 ) ambient performed in a rapid thermal processing (RTP) chamber, such as a RADOX™ chamber available from Applied Materials, Inc., located in Santa Clara, Calif. The RTP chamber may be any of the process chambers 120, 122, 124, 126, 128, and 130 shown in FIG.

[0089] The thermal nitridation process can be performed at a temperature between about 700°C and about 900°C, at a pressure between about 10 Torr and 740 Torr, and for a period between about 10 seconds and about 300 seconds.

[0090] In operation 660, a post-nitridation annealing process is performed to passivate remaining chemical bonds in the plasma nitrided high-k dielectric layer 704. The post-nitridation annealing process may include a spike thermal annealing process in nitrogen ( _N2 ) and argon (Ar) ambient performed in a rapid thermal processing (RTP) chamber, such as a RADOX™ chamber available from Applied Materials, Inc., Santa Clara, Calif. The RTP chamber may be any of the process chambers 120, 122, 124, 126, 128, and 130 shown in Figure 1. The post-nitridation annealing process passivates metastable nitrogen bonds formed in the plasma nitridation process of operation 640, and may result in crystallization of the amorphous high-k dielectric layer 704.

[0091] The thermal spike annealing process can be performed at a temperature between about 700°C and about 850°C, at a pressure between about 10 Torr and 740 Torr, and for a time between about 1 second and about 30 seconds.

[0092] In the embodiments described herein, systems and methods are provided for forming high quality thin high-k dielectric material layers. The properties of such high-k dielectric material layers can be well controlled. For example, the nitridation process in operation 640 can be controlled to introduce between about 3 atomic % and about 20 atomic % nitrogen into the high-k dielectric layer 704 to achieve higher dielectric constant values than higher amounts of nitrogen and better structural stabilization than lower amounts of nitrogen. The annealing process in operation 660 can also be controlled to provide particles in the high-k dielectric layer 704 having a size greater than about 20 Å to reduce leakage current through the high-k dielectric layer 704.

[0093] References throughout this specification to "one embodiment," "a particular embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of phrases such as "in one or more embodiments," "a particular embodiment," "in an embodiment," or "in an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0094] Although the disclosure herein has been described with reference to particular embodiments, those skilled in the art will recognize that the described embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Thus, the disclosure is intended to include modifications and variations that come within the scope of the appended claims and their equivalents.

Claims (17)

1. A method of forming a semiconductor structure, comprising:
annealing the surface of the substrate in a hydrogen ( H 2 ) atmosphere at a temperature in the range of 500° C. to 600° C. , such that the hydrogen (H ₂ ) reacts with the silicon surface to form a smooth surface having hydrogen-silicon _(H—Si ) bonds ;
Then, in a processing system, without breaking vacuum, depositing a high-k dielectric layer directly over the smooth surface , the high-k dielectric layer having voids and defects as deposited ;
performing a re-oxidation process through the high-k dielectric layer at a temperature ranging from 400° C. to 900° C. in an oxygen (O 2 ), nitrous oxide (N 2 O), and hydrogen (H 2 ) atmosphere to thermally oxidize the smooth surface to form an oxide-containing interfacial layer on the silicon surface of the substrate at an interface with _the high _- k _dielectric layer ;
performing a plasma nitridation process to insert nitrogen atoms into the high-k dielectric layer to form a plasma nitrided high-k dielectric layer;
performing a post-nitridation annealing process to passivate chemical bonds in the plasma nitrided high-k dielectric layer and to break hydrogen-silicon (H—Si) bonds on the silicon surface of the substrate ;
The method , wherein depositing the high-k dielectric layer, performing the re-oxidation process, performing the plasma nitridation process, and performing the post-nitridation annealing process are performed in the processing system without breaking vacuum . 2. The method of claim 1, wherein the plasma nitridation process comprises exposing the high-k dielectric layer to a plasma comprising a mixture of nitrogen ( _N2 ) and ammonia ( _NH3 ). 2. The method of claim 1, wherein the post-nitridation annealing process comprises spike annealing the high-k dielectric layer at a temperature in the range of 700° C. to 850° C. in a nitrogen (N ₂ ) and argon (Ar) ambient. The method of claim 1, further comprising performing a post-deposition annealing process to harden and densify the high-k dielectric layer prior to the plasma nitridation process. 5. The method of claim 4 , wherein the post-deposition annealing process comprises annealing the high-k dielectric layer at a temperature in the range of 500° C. to 800° C. in a nitrogen (N ₂ ) and argon (Ar) ambient. The method of claim 1, wherein the high-k dielectric layer comprises hafnium oxide. 1. A method of forming a semiconductor structure, comprising:
annealing the surface of the substrate in a hydrogen (H ₂ ) atmosphere at a temperature in the range of 500° C. to 600° C. to form a smooth surface;
forming a high permittivity dielectric layer on said smooth surface;
performing a re-oxidation process to thermally oxidize the substrate;
performing a plasma nitridation process to insert nitrogen atoms into the high-k dielectric layer to form a plasma nitrided high-k dielectric layer;
performing a post-nitridation annealing process to passivate chemical bonds in the plasma nitrided high-k dielectric layer. The method of claim 7 , wherein forming the semiconductor structure is performed in a processing system without breaking vacuum. The method of claim 7 , wherein annealing the surface of the substrate comprises spike annealing the substrate . The method of claim 7 , wherein the high-k dielectric layer comprises hafnium oxide. 8. The method of claim 7 , wherein the plasma nitridation process comprises exposing the high-k dielectric layer to a plasma comprising a mixture of nitrogen ( _N2 ) and ammonia ( _NH3 ). 8. The method of claim 7 , further comprising pre-cleaning the smooth surface prior to forming the high-k dielectric layer on the smooth surface. The method of claim 7 , further comprising pre-cleaning the surface of the substrate prior to annealing the surface of the substrate. 8. The method of claim 7 , wherein the post-nitridation annealing process comprises spike annealing the high-k dielectric layer at a temperature in the range of 700° C. to 850° C. in a nitrogen (N ₂ ) and argon (Ar) ambient. 8. The method of claim 7 , further comprising performing a post-deposition annealing process to harden and densify the high-k dielectric layer prior to the plasma nitridation process. 16. The method of claim 15 , wherein the post-deposition annealing process comprises annealing the high-k dielectric layer at a temperature in the range of 500° C. to 800° C. in a nitrogen (N ₂ ) and argon (Ar) ambient. a first processing chamber;
a second processing chamber;
a third processing chamber;
a fourth processing chamber; and
a fifth processing chamber; and
a system controller ; and
The system controller,
annealing the surface of the substrate in the first processing chamber at a temperature in the range of 500° C. to 600° C. in a hydrogen (H ₂ ) atmosphere to form a smooth surface ;
depositing a high-k dielectric layer on the surface of the substrate in the second processing chamber;
exposing the deposited high-k dielectric layer to a nitrogen plasma in the third processing chamber to form a plasma nitrided high-k dielectric layer;
performing a re-oxidation process to thermally oxidize the surface of the substrate in the fourth process chamber; and annealing the plasma nitrided high-k dielectric layer in the fifth process chamber ;
A processing system, wherein the substrate is transferred between the first, second, third, fourth, and fifth processing chambers without breaking a vacuum environment within the processing system.

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