JP7589665B2 - Switch actuator - Google Patents

Description

The present invention relates to a switch drive device.

One known example of this type of drive device is one that alternately switches the upper arm switch and the lower arm switch to the on state with a dead time in between.

Here, of the upper and lower arm switches, the switch that is about to be switched to the on state is the own arm switch, and the remaining switch is the opposing arm switch. To shorten the dead time, it is necessary to quickly determine that the opposing arm switch has been switched to the off state and to switch the own arm switch to the on state. Patent Document 1 describes a technology in which a signal that notifies the switching state of the opposing arm switch in advance is input to the gate drive circuit of the own arm switch. If the gate drive circuit determines that the opposing arm switch is in the off state based on the input information, it switches the own arm switch to the on state.

JP 2020-96444 A

A drive device is also known that alternately turns on a number of upper arm switches connected in parallel and a number of lower arm switches connected in parallel with dead times in between. Here, variations in the characteristic values of the switches can cause variations in the timing of switching each of the opposing arm switches connected in parallel from the on state to the off state. In this case, if the opposing arm switch that can be switched off the earliest among the opposing arm switches is switched off and each arm switch is switched on, a short circuit between the upper and lower arms can occur.

The main objective of the present invention is to provide a switch drive device that can reduce dead time while suppressing the occurrence of short circuits between the upper and lower arms.

The present invention relates to a switch drive device that alternately turns on a plurality of upper arm switches connected in parallel and a plurality of lower arm switches connected in parallel with a dead time therebetween,
When one of the upper arm switch and the lower arm switch is a self-arm switch and the other is an opposing arm switch, an off determination unit determines whether a most delayed switch, which is a switch that switches from an on state to an off state the slowest, among the opposing arm switches is switched to an off state;
an ON operation unit that switches the respective arm switches that are in the OFF state to the ON state when it is determined that the most-delay switch is switched to the OFF state;
Equipped with.

In the present invention, the determination result that the most delayed switch among the opposing arm switches connected in parallel has been switched to the off state is used to switch each of the parallel-connected own arm switches to the on state. This makes it possible to accurately suppress the occurrence of short circuits between the upper and lower arms.

FIG. 1 is an overall configuration diagram of a control system according to a first embodiment. FIG. 2 is a diagram showing a drive IC and a circuit around the drive IC. 4 is a time chart showing changes in a drive signal and a gate voltage. FIG. 4 is a diagram showing the relationship between the characteristic value and the switching speed of each switch. 4 is a time chart showing the transition of upper and lower arm drive signals, etc. 10 is a time chart showing changes in a drive signal and a gate voltage according to a second embodiment. 10 is a time chart showing changes in a drive signal and a gate voltage according to a modified example of the second embodiment. 10 is a time chart showing changes in a drive signal and a gate voltage according to a modified example of the second embodiment. 10 is a time chart showing changes in a drive signal and a gate voltage according to a modified example of the second embodiment. FIG. 13 is a diagram showing a drive IC and a circuit around the drive IC according to a third embodiment. 4 is a time chart showing changes in a drive signal and a sense voltage; 13 is a time chart showing changes in a drive signal and a sense voltage according to a modification of the third embodiment. FIG. 13 is a diagram showing a drive IC and a circuit around the drive IC according to a fourth embodiment. 4A and 4B are diagrams showing a manner in which a semiconductor module is attached to a control board. FIG. FIG. 13 is a diagram showing a drive IC and a circuit around the drive IC according to a fifth embodiment. A diagram showing the effect of the presence or absence of a capacitor on switching speed. FIG. 13 is a diagram showing a drive IC and a circuit around the drive IC according to a sixth embodiment. 4 is a time chart showing the transition of the driving states of the first and second discharge switches;

First Embodiment
A first embodiment of a drive device according to the present invention will be described below with reference to the drawings. A control system equipped with the drive device of this embodiment can be applied to a moving body, a robot (e.g., an industrial robot), a generator, an elevator, etc. The moving body is, for example, an automobile, an aircraft, a ship, or a railroad car.

As shown in FIG. 1, the control system includes a rotating electric machine 10, an inverter 20, and a DC power supply 21. In this embodiment, the rotating electric machine 10 includes a three-phase winding 11 that is star-connected. The rotating electric machine 10 is, for example, a synchronous machine. When the control system is applied to an automobile, the rotating electric machine 10 may be an in-wheel motor that is integrally provided on the driving wheels of the automobile, or an on-board motor that is provided on the body of the automobile, or may be integrated with the inverter 20 and a transmission (not shown).

The rotating electric machine 10 is connected to a DC power source 21 via an inverter 20. The DC power source 21 is, for example, a secondary battery. The inverter 20 includes a smoothing capacitor 22. The smoothing capacitor 22 may be provided outside the inverter 20.

The inverter 20 has upper and lower arm switches for three phases. Each of the upper and lower arms is composed of two semiconductor power elements connected in parallel. The switches on the upper arm side are the first upper arm switch SWAH and the second upper arm switch SWBH. The switches on the lower arm side are the first lower arm switch SWAL and the second lower arm switch SWBL.

In this embodiment, each switch SWAH, SWBH, SWAL, SWBL is a voltage-controlled semiconductor switching element, specifically an Si IGBT. Therefore, in each switch SWAH, SWBH, SWAL, SWBL, the high-potential terminal is the collector, and the low-potential terminal is the emitter. A freewheel diode is connected in inverse parallel to each switch SWAH, SWBH, SWAL, SWBL. In this embodiment, each switch SWAH, SWBH, SWAL, SWBL has the same specifications. Therefore, each switch SWAH, SWBH, SWAL, SWBL has the same design value for threshold voltage Vth and the same design value for gate charge capacitance Qg.

Each of the switches SWAH, SWBH, SWAL, and SWBL may be, for example, an N-channel MOSFET having a body diode. In this case, the high-potential terminal of each of the switches SWAH, SWBH, SWAL, and SWBL is the drain, and the low-potential terminal is the source.

In each phase, the first end of the smoothing capacitor 22 is connected to the high potential terminals of the first and second upper arm switches SWAH and SWBH. In each phase, the low potential terminals of the first and second upper arm switches SWAH and SWBH are connected to the high potential terminals of the first and second lower arm switches SWAL and SWBL. In each phase, the second end of the smoothing capacitor 22 is connected to the low potential terminals of the first and second lower arm switches SWAL and SWBL. In each phase, the first end of the winding 11 of the rotating electric machine 10 is connected to the low potential terminals of the first and second upper arm switches SWAH and SWBH and the high potential terminals of the first and second lower arm switches SWAL and SWBL. The second end of the winding 11 of each phase is connected at the neutral point.

The control system includes a control board 25, a microcomputer 30, and upper and lower arm drive ICs 40 and 70. The microcomputer 30 controls the switching of the switches SWAH, SWBH, SWAL, and SWBL of the inverter 20 to control the control amount of the rotating electric machine 10 to a command value. The control amount is, for example, torque. The microcomputer 30 generates an upper arm main drive signal GH* corresponding to each upper arm switch SWAH, SWBH and a lower arm main drive signal GL* corresponding to each lower arm switch SWAL, SWBL in each phase to alternately turn on each upper arm switch SWAH, SWBH and each lower arm switch SWAL, SWBL. In this embodiment, each main drive signal GH*, GL* indicates an ON command with a logical H and indicates an OFF command with a logical L.

The microcomputer 30 is provided in the low-voltage region. On the other hand, the rotating electric machine 10, the switches SWAH, SWBH, SWAL, SWBL, the upper and lower arm drive ICs 40, 70, the DC power supply 21, and the smoothing capacitor 22 are provided in the high-voltage region.

Next, we will use Figure 2 to explain the microcontroller 30 and the upper and lower arm drive ICs 40 and 70.

The control system includes an upper arm isolator 31H and a lower arm isolator 31L. The upper and lower arm isolators 31H and 31L are provided so as to straddle the boundary between the low voltage region and the high voltage region. The upper and lower arm isolators 31H and 31L transmit the upper and lower arm main drive signals GH* and GL* output from the microcomputer 30 to the high voltage region while electrically insulating the low voltage region and the high voltage region. In this embodiment, the upper and lower arm isolators 31H and 31L are digital isolators, for example, magnetic insulation type isolators with a coil or capacitive insulation type isolators with a capacitor. For example, a magnetic insulation type digital isolator includes an encoder that converts an input signal into a pulse signal, a transformer that transmits the converted pulse signal from the low voltage region to the high voltage region, and a decoder that converts the pulse signal output from the transformer. The upper and lower arm isolators 31H and 31L may be, for example, optically isolated photocouplers instead of digital isolators.

The upper arm drive IC 40 includes an upper arm signal generator 41 and an upper arm driver 42. The upper arm main drive signal GH* is input to the upper arm signal generator 41 from the upper arm isolator 31H. The upper arm signal generator 41 generates an upper arm drive signal GHr of an ON command or an OFF command and outputs it to the upper arm driver 42.

The gate of the first upper arm switch SWAH is connected to the upper arm driver 42 via the first upper arm gate resistor 32AH, and the gate of the second upper arm switch SWBH is connected to the upper arm driver 42 via the second upper arm gate resistor 32BH.

When the upper arm driver 42 determines that the input upper arm drive signal GHr is an ON command, it performs an ON operation of the first and second upper arm switches SWAH and SWBH. In this embodiment, the ON operation is an operation of supplying a charging current to the gate of the first upper arm switch SWAH via the first upper arm gate resistor 32AH and supplying a charging current to the gate of the second upper arm switch SWBH via the second upper arm gate resistor 32BH. As a result, the gate voltages of the first and second upper arm switches SWAH and SWBH become equal to or higher than the threshold voltages VthA and VthB, and the first and second upper arm switches SWAH and SWBH are switched to the ON state.

On the other hand, when the upper arm driver 42 determines that the input upper arm drive signal GHr is an OFF command, it performs an OFF operation of the first and second upper arm switches SWAH and SWBH. In this embodiment, the OFF operation is an operation of discharging the gate charge of the first upper arm switch SWAH via the first upper arm gate resistor 32AH and discharging the gate charge of the second upper arm switch SWBH via the second upper arm gate resistor 32BH. As a result, the gate voltages of the first and second upper arm switches SWAH and SWBH become less than the threshold voltages VthA and VthB, and the first and second upper arm switches SWAH and SWBH are switched to the OFF state.

The upper arm drive IC 40 includes an upper arm determination unit 43 and an upper arm memory unit 44. The charge/discharge path connecting the upper arm driver 42 and the gate of the first upper arm switch SWAH is connected to the upper arm determination unit 43 via a first upper arm path LAH. The upper arm determination unit 43 detects the gate voltage VgAH of the first upper arm switch SWAH via the first upper arm path LAH. The charge/discharge path connecting the upper arm driver 42 and the gate of the second upper arm switch SWBH is connected to the upper arm determination unit 43 via a second upper arm path LBH. The upper arm determination unit 43 detects the gate voltage VgBH of the second upper arm switch SWBH via the second upper arm path LBH.

The upper arm memory unit 44 is a non-transient physical recording medium other than ROM (e.g., a non-volatile memory other than ROM). The upper arm determination unit 43 can read the stored information of the upper arm memory unit 44.

The lower arm drive IC 70 includes a lower arm signal generator 71 and a lower arm driver 72. The lower arm main drive signal GL* from the lower arm isolator 31L is input to the lower arm signal generator 71. The lower arm signal generator 71 generates a lower arm drive signal GLr of an ON command or an OFF command and outputs it to the lower arm driver 72.

The gate of the first lower arm switch SWAL is connected to the lower arm driver 72 via the first lower arm gate resistor 32AL, and the gate of the second lower arm switch SWBL is connected to the lower arm driver 72 via the second lower arm gate resistor 32BL.

When the lower arm driver 72 determines that the input lower arm drive signal GLr is an ON command, it performs an ON operation to supply a charging current to the gate of the first lower arm switch SWAL via the first lower arm gate resistor 32AL and to supply a charging current to the gate of the second lower arm switch SWBL via the second lower arm gate resistor 32BL. As a result, the gate voltages of the first and second lower arm switches SWAL, SWBL become equal to or higher than the threshold voltages VthA, VthB, and the first and second lower arm switches SWAL, SWBL are switched to the ON state.

On the other hand, when the lower arm driver 72 determines that the input lower arm drive signal GLr is an OFF command, it performs an OFF operation to discharge the gate charge of the first lower arm switch SWAL via the first lower arm gate resistor 32AL and the gate charge of the second lower arm switch SWBL via the second lower arm gate resistor 32BL. As a result, the gate voltages of the first and second lower arm switches SWAL and SWBL become less than the threshold voltages VthA and VthB, and the first and second lower arm switches SWAL and SWBL are switched to the OFF state.

The lower arm drive IC 70 includes a lower arm determination unit 73 and a lower arm memory unit 74. The charge/discharge path connecting the lower arm driver 72 and the gate of the first lower arm switch SWAL is connected to the lower arm determination unit 73 via a first lower arm path LAL. The lower arm determination unit 73 detects the gate voltage VgAL of the first lower arm switch SWAL via the first lower arm path LAL. The charge/discharge path connecting the lower arm driver 72 and the gate of the second lower arm switch SWBL is connected to the lower arm determination unit 73 via a second lower arm path LBL. The lower arm determination unit 73 detects the gate voltage VgBL of the second lower arm switch SWBL via the second lower arm path LBL.

The lower arm determination unit 73 and the upper arm determination unit 43 may be configured, for example, with a comparator circuit, a logic circuit, or a diode-OR (DiOR) circuit. In this embodiment, the lower arm determination unit 73 and the upper arm determination unit 43 correspond to the "off determination unit."

The lower arm memory unit 74 is a non-transient tangible recording medium other than ROM (e.g., a non-volatile memory other than ROM). The lower arm determination unit 73 can read the stored information in the lower arm memory unit 74.

The control system includes a first isolator 33 and a second isolator 34. The first isolator 33 and the second isolator 34 are provided in a high-voltage region. The first isolator 33 transmits the lower arm signal PL output from the lower arm determination unit 73 to the upper arm signal generation unit 41 while electrically insulating between the upper arm drive IC 40 and the lower arm drive IC 70. The second isolator 34 transmits the upper arm signal PH output from the upper arm determination unit 43 to the lower arm signal generation unit 71 while electrically insulating between the upper arm drive IC 40 and the lower arm drive IC 70. In this embodiment, the first and second isolators 33 and 34 are digital isolators similar to the upper and lower arm isolators 31H and 31L.

Although the switches SWAH, SWBH, SWAL, and SWBL have the same specifications, there are variations in characteristic values such as threshold voltage and gate charge capacity due to individual differences. For this reason, taking the upper arm side as an example, even if the first and second upper arm switches SWAH and SWBH are simultaneously switched to the off state, the rate at which the gate voltages of the first and second upper arm switches SWAH and SWBH decrease is different. As a result, one of the first and second upper arm switches SWAH and SWBH is switched to the off state first, followed by the other switch.

In this embodiment, the threshold voltage VthB of the second upper arm switch SWBH is higher than the threshold voltage VthA of the first upper arm switch SWAH. In addition, the gate charge capacitance QgB of the second upper arm switch SWBH is larger than the gate charge capacitance QgA of the first upper arm switch SWAH. As a result, the switching speed of the second upper arm switch SWBH is lower than the switching speed of the first upper arm switch SWAH. Therefore, the second upper arm switch SWBH corresponds to the "most delayed switch."

For the same reason, the switching speed of the second lower arm switch SWBL is slower than the switching speed of the first lower arm switch SWAL. Therefore, the second lower arm switch SWBL corresponds to the "most delayed switch."

Using Figure 3, we will explain the switching speed of the upper arm side as an example. Figure 3 (a) shows the transition of the upper arm drive signal GHr, and Figure 3 (b) shows the transition of the gate voltages VgAH and VgBH of the first and second upper arm switches SWAH and SWBH.

When the upper arm drive signal GHr is switched to an ON command at time t1, the upper arm driver 42 begins to charge the gates of the first and second upper arm switches SWAH and SWBH.

After that, at time t2, the gate voltage VgAH of the first upper arm switch SWAH reaches the threshold voltage VthA, and at time t3, the gate voltage VgBH of the second upper arm switch SWBH reaches the threshold voltage VthB. Therefore, the first upper arm switch SWAH is switched to the on state before the second upper arm switch SWBH. Note that in the example shown in FIG. 3, the timing at which the gate voltage VgAH of the first upper arm switch SWAH reaches the power supply voltage Vom occurs before the timing at which the gate voltage VgBH of the second upper arm switch SWBH reaches the threshold voltage VthB.

When the upper arm drive signal GHr is switched to an OFF command at time t4, the upper arm driver 42 begins to discharge the gate charges of the first and second upper arm switches SWAH and SWBH.

After that, at time t5, the gate voltage VgAH of the first upper arm switch SWAH falls below the threshold voltage VthA, and at time t6, the gate voltage VgBH of the second upper arm switch SWBH falls below the threshold voltage VthB. Therefore, the first upper arm switch SWAH is switched to the off state before the second upper arm switch SWBH. Note that in the example shown in FIG. 3, the gate voltage VgAH of the first upper arm switch SWAH reaches 0 before the gate voltage VgBH of the second upper arm switch SWBH falls below the threshold voltage VthB.

In consideration of the fact that the switching speeds of the switches connected in parallel are different in each arm, an upper arm determination unit 43 and a lower arm determination unit 73 are provided. When the first and second upper arm switches SWAH and SWBH are switched from an on operation to an off operation, the upper arm determination unit 43 outputs an upper arm signal PH indicating that the switch with the lower switching speed of the first and second upper arm switches SWAH and SWBH has been switched to the off state. In this embodiment, when the upper arm signal PH is H, it indicates that the second upper arm switch SWBH with the lower switching speed has been switched to the off state, that is, that both the first and second upper arm switches SWAH and SWBH have been switched to the off state. On the other hand, when the upper arm signal PH is L, it indicates that the second upper arm switch SWBH has not been switched to the off state.

When the first and second lower arm switches SWAL, SWBL are switched from an on operation to an off operation, the lower arm determination unit 73 outputs a lower arm signal PL indicating that of the first and second lower arm switches SWAL, SWBL, the switch with the slower switching speed has been switched to the off state. In this embodiment, when the lower arm signal PL is H, this indicates that the first and second lower arm switches SWAL, SWBL have been switched to the off state. On the other hand, when the lower arm signal PL is L, this indicates that the second lower arm switch SWBL, which has the slower switching speed, has not been switched to the off state.

As shown in FIG. 4, the upper arm memory unit 44 stores information on the threshold voltage and gate charge capacity of the first and second upper arm switches SWAH and SWBH. The upper arm determination unit 43 functions as an "identification unit" that identifies the switch with the higher threshold voltage and gate charge capacity of the first and second upper arm switches SWAH and SWBH as the most delayed switch. Incidentally, the upper arm memory unit 44 may store information on either the threshold voltage or the gate charge capacity. In this case, the upper arm determination unit 43 may identify the switch with the higher threshold voltage or the switch with the higher gate charge capacity of the first and second upper arm switches SWAH and SWBH as the most delayed switch.

The processing of the upper arm determination unit 43 will be described using FIG. 5. FIG. 5(a) and (b) show the transitions of the upper and lower arm main drive signals GH* and GL*, FIG. 5(c) shows the transition of the lower arm signal PL, and FIG. 5(d) shows the transition of the upper arm drive signal GHr. FIG. 5(e) shows the transition of the upper arm signal PH, and FIG. 5(f) shows the transition of the lower arm drive signal GLr. In FIG. 5, Tsw indicates the switching period of each switch SWAH, SWBH, SWAL, and SWBL. In each switching period Tsw, each main drive signal GH* and GL* becomes an ON command once. In the example shown in FIG. 5, the timing of switching the upper arm main drive signal GH* to an ON command is delayed by a specified period DT* with respect to the timing of switching the lower arm main drive signal GL* to an OFF command. Furthermore, the timing at which the lower arm main drive signal GL* switches to an ON command is delayed by a specified period DT* relative to the timing at which the upper arm main drive signal GH* switches to an OFF command. The specified period DT* is a period that is very short relative to the switching cycle Tsw. Note that the timing at which the upper arm main drive signal GH* switches to an ON command and the timing at which the lower arm main drive signal GL* switches to an OFF command may be set to the same timing, and the timing at which the upper arm main drive signal GH* switches to an OFF command and the timing at which the lower arm main drive signal GL* switches to an ON command may be set to the same timing.

The upper arm determination unit 43 determines whether the second upper arm switch SWBH is in the OFF state based on the detection value of the gate voltage VgBH of the second upper arm switch SWBH, which is the most delayed switch. In this embodiment, if the upper arm determination unit 43 determines that the detected gate voltage VgBH is less than the threshold voltage VthB stored in the upper arm memory unit 44, it determines that the second upper arm switch SWBH is in the OFF state and sets the upper arm signal PH to H. On the other hand, if the upper arm determination unit 43 determines that the detected gate voltage VgBH is equal to or greater than the threshold voltage VthB, it determines that the second upper arm switch SWBH is in the ON state and sets the upper arm signal PH to L.

When the lower arm signal generating unit 71 determines that the upper arm signal PH input via the second isolator 34 is L, it maintains the lower arm drive signal GLr at L (OFF command) regardless of the logic of the input lower arm main drive signal GL*. In other words, when it is determined that the upper arm signal PH on the opposing arm side is L, the first and second lower arm switches SWAL and SWBL, which are the own arm switches, are prohibited from being switched to the ON state. At time ta in FIG. 5, even though the lower arm main drive signal GL* has been switched to an ON command, the upper arm signal PH is L, so the lower arm drive signal GLr cannot be switched to an ON command.

On the other hand, if the lower arm signal generating unit 71 determines that the upper arm signal PH is H and the lower arm main drive signal GL* is an ON command (H) at time tb, it switches the lower arm drive signal GLr to an ON command (H). In other words, if it is determined that the upper arm signal PH is H, the first and second lower arm switches SWAL and SWBL are permitted to be switched to the ON state.

At time tc, the lower arm signal generating unit 71 determines that the lower arm main drive signal GL* has been switched off, and switches the lower arm drive signal GLr to an OFF command. At time td, the upper arm signal PH is switched to L. In this embodiment, the lower arm signal generating unit 71 and the lower arm driver 72 correspond to the "ON operation unit" on the lower arm side.

Next, the lower arm determination unit 73 and the lower arm memory unit 74 will be described. Note that the configuration of the lower arm side is similar to that of the upper arm side, so the description will be omitted as appropriate.

The lower arm memory unit 74 stores information on the threshold voltage and gate charge capacity of the first and second lower arm switches SWAL and SWBL. The lower arm determination unit 73 functions as an "identification unit" that identifies the switch with the higher threshold voltage and gate charge capacity of the first and second lower arm switches SWAL and SWBL as the most delayed switch.

The lower arm determination unit 73 detects the gate voltage VgBL of the second lower arm switch SWBL, which is the most delayed switch, and if it determines that the detected gate voltage VgBL is less than the threshold voltage VthB stored in the lower arm memory unit 74, it determines that the second lower arm switch SWBL is in the OFF state and sets the lower arm signal PL to H. On the other hand, if the lower arm determination unit 73 determines that the detected gate voltage VgBL is equal to or greater than the threshold voltage VthB, it determines that the second lower arm switch SWBL is in the ON state and sets the lower arm signal PL to L.

When the upper arm signal generating unit 41 determines that the lower arm signal PL on the opposing arm side input via the first isolator 33 is L, it maintains the upper arm drive signal GHr on its own arm side at L (OFF command) regardless of the logic of the input upper arm main drive signal GH*. At time t1 in FIG. 5, even though the upper arm main drive signal GH* has been switched to an ON command, the lower arm signal PL is L, so the upper arm drive signal GHr cannot be switched to an ON command.

On the other hand, if the upper arm signal generator 41 determines that the lower arm signal PL is H and the upper arm main drive signal GH* is an ON command (H) at time t2, it switches the upper arm drive signal GHr to an ON command (H).

At time t3, the upper arm signal generating unit 41 determines that the upper arm main drive signal GH* has been switched off, and switches the upper arm drive signal GHr to an off command. At time t4, the lower arm signal PL is switched to L. In this embodiment, the upper arm signal generating unit 41 and the upper arm driver 42 correspond to the "on operation unit" on the upper arm side.

Incidentally, information on the threshold voltage and gate charge capacity can be written to the upper arm memory unit 44 and the lower arm memory unit 74 by a data writing device, for example, during the manufacturing process of the switch drive device.

In addition, information on the threshold voltage and gate charge capacity may be written to the memory of the microcontroller 30. In this case, the information on the threshold voltage and gate charge capacity may be transmitted from the microcontroller 30 to each memory unit 44, 74.

According to the present embodiment described above, it is possible to effectively prevent short circuits between the upper and lower arms.

Second Embodiment
Hereinafter, the second embodiment will be described with reference to the drawings, focusing on the differences from the first embodiment. In this embodiment, each of the determination units 43 and 73 determines which switch is the most delayed switch based on the detection value of the gate voltage.

First, the processing of the upper arm determination unit 43 will be explained using FIG. 6.

At time t1, the upper arm drive signal GHr is switched to an OFF command, and the gate voltages VgAH, VgBH of the first and second upper arm switches SWAH, SWBH start to decrease from the power supply voltage Vom. The upper arm determination unit 43 detects the gate voltage VoffA of the first upper arm switch SWAH and the gate voltage VoffB of the second upper arm switch SWBH during the period from time t1 until the gate voltages VgAH, VgBH become 0 (t2). The upper arm determination unit 43 identifies the second upper arm switch SWBH corresponding to the higher of the detected gate voltages VoffA, VoffB as the most delayed switch.

The upper arm determination unit 43 may store information about the identified most delayed switch in the upper arm memory unit 44. In this case, the upper arm determination unit 43 may select, based on the information about the most delayed switch stored in the upper arm memory unit 44, which of the gate voltages VgAH, VgBH of the first and second upper arm switches SWAH, SWBH is to be used to generate the upper arm signal PH. In this embodiment, the first upper arm path LAH, the second upper arm path LBH, and the upper arm determination unit 43 correspond to the "detection unit" on the upper arm side.

Next, we will explain the processing of the lower arm determination unit 73.

The lower arm drive signal GLr is switched to an OFF command, and the gate voltages VgAL, VgBL of the first and second lower arm switches SWAL, SWBL start to decrease from the power supply voltage Vom. The lower arm determination unit 73 detects the gate voltage VoffA of the first lower arm switch SWAL and the gate voltage VoffB of the second lower arm switch SWBL during the period from when the lower arm drive signal GLr is switched to an OFF command until the gate voltages VgAL, VgBL become 0. The lower arm determination unit 73 identifies the second lower arm switch SWBL corresponding to the higher VoffB of the detected gate voltages VoffA, VoffB as the most delayed switch.

The lower arm determination unit 73 may store information about the identified most delayed switch in the lower arm storage unit 74, similar to the upper arm determination unit 43. In this embodiment, the first lower arm path LAL, the second lower arm path LBL, and the lower arm determination unit 73 correspond to the "detection unit" on the lower arm side.

Incidentally, the process of identifying the most delayed switch by the upper and lower arm determination units 43 and 73 may be performed, for example, when the control system is started up during one trip from when the control system is started up to when it is stopped.

According to the present embodiment described above, it is possible to eliminate the process of writing information on the most delayed switch to each memory unit 44, 74 during the manufacturing process. Furthermore, according to this embodiment, even if the magnitudes of the characteristic values (Vth, Qg) of the two switches connected in parallel are reversed due to aging, the determination process of the most delayed switch by each determination unit 43, 73 can accurately prevent the occurrence of a short circuit between the upper and lower arms.

<Modification of the second embodiment>
The method of identifying the most delayed switch may be any of the methods (A) to (C) described below. The following describes the process of the upper arm determination unit 43 as an example.

(A) At time t1 in FIG. 7, the upper arm drive signal GHr is switched to an ON command, and the gate voltages VgAH, VgBH of the first and second upper arm switches SWAH, SWBH start to rise from 0 toward the power supply voltage Vom. The upper arm determination unit 43 detects the gate voltage VonA of the first upper arm switch SWAH and the gate voltage VonB of the second upper arm switch SWBH during the period from time t1 until the gate voltages VgAH, VgBH reach the power supply voltage Vom (t2). The upper arm determination unit 43 identifies the second upper arm switch SWBH corresponding to the lower of the detected gate voltages VonA, VonB as the most delayed switch.

(B) At time t1 in FIG. 8, the upper arm drive signal GHr is switched to an OFF command, and the gate voltages VgAH, VgBH of the first and second upper arm switches SWAH, SWBH start to decrease from the power supply voltage Vom. The upper arm determination unit 43 calculates the decrease rate of the gate voltage VgAH of the first upper arm switch SWAH and the decrease rate of the gate voltage VgBH of the second upper arm switch SWBH during a predetermined period Δt from time t1 until the gate voltages VgAH, VgBH become 0. The upper arm determination unit 43 identifies the second upper arm switch SWBH corresponding to the lower decrease rate of the calculated decrease rates as the most delayed switch.

(C) At time t1 in FIG. 9, the upper arm drive signal GHr is switched to an ON command, and the gate voltages VgAH, VgBH of the first and second upper arm switches SWAH, SWBH start to rise from 0 toward the power supply voltage Vom. The upper arm determination unit 43 calculates the rate of rise of the gate voltage VgAH of the first upper arm switch SWAH and the rate of rise of the gate voltage VgBH of the second upper arm switch SWBH during a predetermined period Δt from time t1 until the gate voltages VgAH, VgBH reach the power supply voltage Vom. The upper arm determination unit 43 identifies the second upper arm switch SWBH corresponding to the lower of the calculated rates of rise as the most delayed switch.

Third Embodiment
Hereinafter, the third embodiment will be described with reference to the drawings, focusing on the differences from the second embodiment. In this embodiment, the most delayed switch is identified based on a sense voltage instead of a gate voltage.

Figure 10 shows the drive ICs 40 and 70 and their peripheral circuits in this embodiment. For convenience, the same reference numerals are used in Figure 10 for the same configuration as in Figure 2.

The first and second upper arm switches SWAH, SWBH are provided with first and second upper arm sense terminals StAH, StBH. A minute current that is correlated with the collector current of the first and second upper arm switches SWAH, SWBH flows through the first and second upper arm sense terminals StAH, StBH. The first ends of the first and second upper arm sense resistors 35AH, 35BH are connected to the first and second upper arm sense terminals StAH, StBH, and the emitters of the first and second upper arm switches SWAH, SWBH are connected to the second ends of the first and second upper arm sense resistors 35AH, 35BH.

The first end of the first upper arm sense resistor 35AH is connected to the upper arm determination unit 43 via a first upper arm detection path. The upper arm determination unit 43 detects the potential difference of the first upper arm sense resistor 35AH as a first upper arm sense voltage VsAH via the first upper arm detection path. The first end of the second upper arm sense resistor 35BH is connected to the upper arm determination unit 43 via a second upper arm detection path. The upper arm determination unit 43 detects the potential difference of the second upper arm sense resistor 35BH as a second upper arm sense voltage VsBH via the second upper arm detection path. In this embodiment, the first and second upper arm detection paths and the upper arm determination unit 43 correspond to the "detection unit" on the upper arm side.

The first and second lower arm switches SWAL, SWBL have first and second lower arm sense terminals StAL, StBL. The first and second lower arm sense terminals StAL, StBL are connected to first ends of the first and second lower arm sense resistors 35AL, 35BL, and the second ends of the first and second lower arm sense resistors 35AL, 35BL are connected to the emitters of the first and second lower arm switches SWAL, SWBL.

The first end of the first lower arm sense resistor 35AL is connected to the lower arm determination unit 73 via a first lower arm detection path. The lower arm determination unit 73 detects the potential difference of the first lower arm sense resistor 35AL as a first lower arm sense voltage VsAL via the first lower arm detection path. The first end of the second lower arm sense resistor 35BL is connected to the lower arm determination unit 73 via a second lower arm detection path. The lower arm determination unit 73 detects the potential difference of the second lower arm sense resistor 35BL as a second lower arm sense voltage VsBL via the second lower arm detection path. In this embodiment, the first and second lower arm detection paths and the lower arm determination unit 73 correspond to the "detection unit" on the lower arm side.

The processing of the upper arm determination unit 43 will be explained using Figure 11.

At time t1, the upper arm drive signal GHr is switched to an OFF command, and the first and second upper arm sense voltages VsAH and VsBH begin to decrease from their steady values. The steady value of the sense voltage is, for example, the sense voltage when the gate voltage of the switch is the power supply voltage Vom. The upper arm determination unit 43 detects the first upper arm sense voltage SoffA and the second upper arm sense voltage SoffB during the period from time t1 to when the sense voltages VsAH and VsBH become 0 (t2). When the gate voltage of the switch becomes 0, the collector current stops flowing, and the sense voltage becomes 0. The upper arm determination unit 43 identifies the second upper arm switch SWBH corresponding to the higher SoffB of the detected sense voltages SoffA and SoffB as the most delayed switch.

Next, we will explain the processing of the lower arm determination unit 73.

The lower arm drive signal GLr is switched to an OFF command, and the first and second lower arm sense voltages VsAL and VsBL begin to decrease from their steady values. The lower arm determination unit 73 detects the first lower arm sense voltage SoffA and the second lower arm sense voltage SoffB during the period from when the lower arm drive signal GLr is switched to an OFF command until the sense voltages VsAL and VsBL become 0. The lower arm determination unit 73 identifies the second lower arm switch SWBL corresponding to the higher of the detected sense voltages SoffA and SoffB as the most delayed switch.

According to the present embodiment described above, the same effects as those of the second embodiment can be obtained.

<Modification of the third embodiment>
The method of identifying the most delayed switch may be any of the methods (D) to (E) described below. The following describes the process of the upper arm determination unit 43 as an example.

(D) At time t1 in FIG. 12, the upper arm drive signal GHr is switched to an OFF command, and the first and second upper arm sense voltages VsAH, VsBH start to decrease from their steady-state values. The upper arm determination unit 43 calculates the rate of decrease of the first and second upper arm sense voltages VsAH, VsBH during a predetermined period Δt from time t1 until the sense voltages VsAH, VsBH become 0. The upper arm determination unit 43 identifies the second upper arm switch SWBH corresponding to the lower of the calculated decrease rates as the most delayed switch.

(E) The upper arm drive signal GHr is switched to an ON command, and the first and second upper arm sense voltages VsAH, VsBH start to rise from 0. The upper arm determination unit 43 calculates the rising speeds of the first and second upper arm sense voltages VsAH, VsBH during a predetermined period Δt from when the upper arm drive signal GHr is switched to an ON command until the sense voltages VsAH, VsBH reach steady-state values. The upper arm determination unit 43 identifies the second upper arm switch SWBH corresponding to the lower rising speed of the calculated rising speeds as the most delayed switch.

(F) The upper arm drive signal GHr is switched to an ON command, and the first and second upper arm sense voltages VsAH, VsBH start to rise from 0. The upper arm determination unit 43 detects the first and second upper arm sense voltages during the period from when the upper arm drive signal GHr is switched to an ON command until the sense voltages VsAH, VsBH reach steady-state values. The upper arm determination unit 43 identifies the second upper arm switch SWBH corresponding to the lower of the detected first and second upper arm sense voltages as the most delayed switch.

Fourth Embodiment
Hereinafter, the fourth embodiment will be described with reference to the drawings, focusing on the differences from the first embodiment. In this embodiment, the first upper arm switch SWAH is the most delayed switch among the first and second upper arm switches SWAH and SWBH. As shown in FIG. 13, a second upper arm path LBH for detecting the gate voltage of the second upper arm switch SWBH is not provided. In this embodiment, the first lower arm switch SWAL is the most delayed switch among the first and second lower arm switches SWAL and SWBL. As shown in FIG. 13, a second lower arm path LBL for detecting the gate voltage of the second lower arm switch SWBL is not provided. In FIG. 13, the same reference numerals are used for the same components as those shown in FIG. 2 for convenience.

The first and second upper arm switches SWAH, SWBH are housed in the upper arm semiconductor module MdH, as shown in Figures 14 and 15. The upper arm semiconductor module MdH has a flat rectangular parallelepiped shape. The upper arm semiconductor module MdH has a first upper arm gate terminal CAH connected to the gate of the first upper arm switch SWAH and a second upper arm gate terminal CBH connected to the gate of the second upper arm switch SWBH. The upper arm semiconductor module MdH of each phase is attached to the control board 25 via each upper arm gate terminal CAH, CBH so that the first upper arm gate terminal CAH is electrically connected to the first upper arm path LAH.

The first and second lower arm switches SWAL, SWBL are housed in the lower arm semiconductor module MdL. The lower arm semiconductor module MdL has a flat rectangular parallelepiped shape. The lower arm semiconductor module MdL has a first lower arm gate terminal CAL connected to the gate of the first lower arm switch SWAL and a second lower arm gate terminal CBL connected to the gate of the second lower arm switch SWBL. The lower arm semiconductor module MdL of each phase is attached to the control board 25 via each lower arm gate terminal CAL, CBL so that the first lower arm gate terminal CAL is electrically connected to the first lower arm path LAL.

According to the present embodiment described above, a configuration can be realized in which a voltage detection path connecting the gate charge/discharge path and the determination unit is provided only on the most delayed switch side. As a result, the configuration of the control system can be simplified.

Fifth Embodiment
The fifth embodiment will be described below with reference to the drawings, focusing on the differences from the fourth embodiment. In this embodiment, as shown in Fig. 16, the gate and emitter of the first upper arm switch SWAH are connected by an upper arm capacitor 36H, which is a passive element. Also, the gate and emitter of the first lower arm switch SWAL are connected by a lower arm capacitor 36L. In Fig. 16, the same reference numerals are used for the same components as those shown in Fig. 13 for convenience.

Taking the upper arm side as an example, as shown in FIG. 17, the rate of increase and decrease of the gate voltage VgAH indicated by the dashed line when a capacitor is provided is slower than the rate of increase and decrease of the gate voltage VgAH indicated by the solid line when a capacitor is not provided. Therefore, of the first and second upper arm switches SWAH and SWBH, the first upper arm switch SWAH, which is provided with the upper arm capacitor 36H, can be made the most delayed switch.

<Modification of the Fifth Embodiment>
In addition to the gate and emitter of the first upper arm switch SWAH, the gate and emitter of the second upper arm switch SWBH may also be connected by a capacitor. In this case, the capacitance of the capacitor provided in the first and second upper arm switches SWAH and SWBH that is to be the most delayed switch may be made larger. The same applies to the lower arm side.

Sixth Embodiment
The sixth embodiment will be described below with reference to the drawings, focusing on the differences from the first embodiment. In this embodiment, the drive IC and its peripheral circuits are changed. The upper arm side will be described below as an example.

Figure 18 shows the upper arm drive IC 40 and its peripheral circuits of this embodiment. Note that in Figure 18, the same components as those shown in Figure 2 above are denoted by the same reference numerals for convenience.

The upper arm drive IC 40 includes a power supply 37, a charging switch SC, a charging resistor 38, first and second discharging resistors 39A and 39B, and first and second discharging switches SD1 and SD2. The charging switch SC, the first discharging switch SD1, the second discharging switch SD2, and the drive control unit Dr correspond to the upper arm driver 42 in FIG. 2.

The power supply 37 is a constant voltage power supply that outputs the power supply voltage Vom described in each of the above embodiments. The gates of the first and second upper arm switches SWAH and SWBH are connected to the power supply 37 via the charging switch SC and the charging resistor 38.

The emitter of the first upper arm switch SWAH is connected to the gate of the first upper arm switch SWAH via the first discharge resistor 39A and the first discharge switch SD1. The emitter of the second upper arm switch SWBH is connected to the gate of the second upper arm switch SWBH via the second discharge resistor 39B and the second discharge switch SD2. In this embodiment, the resistance value RA of the first discharge resistor 39A is the same as the resistance value RB of the second discharge resistor 39B. Incidentally, the charging resistor 38 and each discharge resistor 39A, 39B may be provided outside the upper arm drive IC 40.

The upper arm drive IC 40 is equipped with a drive control unit Dr. The upper arm drive signal GHr generated by the upper arm signal generation unit 41 is input to the drive control unit Dr. When the drive control unit Dr determines that the upper arm drive signal GHr is an ON command, it performs an ON operation of the first and second upper arm switches SWAH and SWBH. In this embodiment, the ON operation is an operation of turning the charge switch SC to the ON state and turning each of the discharge switches SD1 and SD2 to the OFF state.

On the other hand, when the drive control unit Dr determines that the upper arm drive signal GHr is an OFF command, it performs an OFF operation of the first and second upper arm switches SWAH and SWBH. In this embodiment, the OFF operation is an operation of turning the charge switch SC to the OFF state and turning each discharge switch SD1, SD2 to the ON state. In detail, as shown in FIG. 19, the drive control unit Dr switches the first discharge switch SD1 to the ON state at time t1. After that, the drive control unit Dr switches the second discharge switch SD2 to the ON state at time t2, and then switches the first and second discharge switches SD1, SD2 to the OFF state at time t3. As a result, the timing of switching the second upper arm switch SWBH to the OFF state is later than the timing of switching the first upper arm switch SWAH to the OFF state. As a result, the second upper arm switch SWBH can be made the most delayed switch.

The upper arm determination unit 43 generates the upper arm signal PH based on the gate voltage VgAH detected via the first upper arm path LAH. In this embodiment, the drive control unit Dr corresponds to the "delay drive unit."

<Modification of the Sixth Embodiment>
The timing of switching the discharge switches SD1 and SD2 to the ON state may be simultaneous. In this case, the following configurations (G) and (H) may be adopted.

(G) The resistance value RB of the second discharge resistor 39B is made larger than the resistance value RA of the first discharge resistor 39A. This allows the second upper arm switch SWBH to be the most delayed switch.

(H) The opposite end of the first discharge switch SD1 to the first discharge resistor 39A is connected to a configuration (e.g., a negative power supply having a negative voltage) that has a lower potential than the potential of the emitter of the first upper arm switch SWAH. This makes it possible to make the discharge speed of the gate charge of the first upper arm switch SWAH higher than that of the second upper arm switch SWBH, and to make the second upper arm switch SWBH the most delayed switch.

<Other embodiments>
Each of the above embodiments may be modified as follows.

- The parameter used by the judgment unit 43, 73 to judge whether the switch is in the off state may be, for example, the collector-emitter voltage Vce of the switch.

-Each of the upper and lower arms of the inverter 20 may be composed of three or more switches connected in parallel.

- The determination unit 43, 73 may be provided outside the drive IC 40, 70.

- A power converter equipped with upper and lower arm switches is not limited to an inverter, and may be, for example, a DC-DC converter.

20... inverter, 40... upper arm drive IC, 70... lower arm drive IC, SWAH, SWBH... upper arm switches, SWAL, SWBL... lower arm switches.

Claims (7)

A switch drive device that alternately turns on a plurality of upper arm switches (SWAH, SWBH) connected in parallel and a plurality of lower arm switches (SWAL, SWBL) connected in parallel with a dead time therebetween,
an off determination unit (43, 73) that determines whether a most delayed switch, which is a switch that switches from an on state to an off state the slowest, among the opposing arm switches when one of the upper arm switch and the lower arm switch is a self-arm switch and the other is an opposing arm switch, is switched to an off state;
an ON operation unit (41, 42, 71, 72, SC, SD1, SD2, Dr) for switching each of the arm switches from the OFF state to the ON state when it is determined that the most-delay switch has been switched to the OFF state;
detection units (LAH, LBH, 43, LAL, LBL, 73) for detecting voltages of charge/discharge paths of the gates of the opposing arm switches at the same timing during a period from when the opposing arm switches are switched to an OFF operation until the gate voltages of the opposing arm switches fall to 0;
a determination unit (43, 73) that determines, among the opposing arm switches, an opposing arm switch corresponding to a highest detected voltage as the most delayed switch;
Equipped with
The off determination unit determines whether the identified most-delay switch is switched to an off state . A switch drive device that alternately turns on a plurality of upper arm switches (SWAH, SWBH) connected in parallel and a plurality of lower arm switches (SWAL, SWBL) connected in parallel with a dead time therebetween,
an off determination unit (43, 73) that determines whether a most delayed switch, which is a switch that switches from an on state to an off state the slowest, among the opposing arm switches when one of the upper arm switch and the lower arm switch is a self-arm switch and the other is an opposing arm switch, is switched to an off state;
an ON operation unit (41, 42, 71, 72, SC, SD1, SD2, Dr) for switching each of the arm switches from the OFF state to the ON state when it is determined that the most-delay switch has been switched to the OFF state;
detection units (LAH, LBH, 43, LAL, LBL, 73) for detecting voltages of charge/discharge paths of the gates of the opposing arm switches at the same timing during a period from when the opposing arm switches are switched to an on operation until the gate voltages of the opposing arm switches rise to a power supply voltage ;
a determination unit (43, 73) that determines , among the opposing arm switches, an opposing arm switch corresponding to a voltage with the lowest detected voltage as the most delayed switch;
Equipped with
The off determination unit determines whether the identified most-delay switch is switched to an off state. A switch drive device that alternately turns on a plurality of upper arm switches (SWAH, SWBH) connected in parallel and a plurality of lower arm switches (SWAL, SWBL) connected in parallel with a dead time therebetween,
an off determination unit (43, 73) that determines whether a most delayed switch, which is a switch that switches from an on state to an off state the slowest, among the opposing arm switches when one of the upper arm switch and the lower arm switch is a self-arm switch and the other is an opposing arm switch, is switched to an off state;
an ON operation unit (41, 42, 71, 72, SC, SD1, SD2, Dr) for switching each of the arm switches from the OFF state to the ON state when it is determined that the most-delay switch has been switched to the OFF state;
detection units (LAH, LBH, 43, LAL, LBL, 73) that detect a voltage change rate of a charge/discharge path of the gate of each of the opposing arm switches during a period from when each of the opposing arm switches is switched to an OFF operation until the gate voltage of each of the opposing arm switches drops to 0, or during a period from when each of the opposing arm switches is switched to an ON operation until the gate voltage of each of the opposing arm switches rises to a power supply voltage;
a determination unit (43, 73) for determining , among the opposing arm switches, an opposing arm switch corresponding to a lowest detected change rate as the most delayed switch;
Equipped with
The off determination unit determines whether the identified most-delay switch is switched to an off state. A switch drive device that alternately turns on a plurality of upper arm switches (SWAH, SWBH) connected in parallel and a plurality of lower arm switches (SWAL, SWBL) connected in parallel with a dead time therebetween,
The upper arm switch and the lower arm switch each have a sense terminal (StAH, StBH, StAL, StBL) through which a minute current that is correlated with a current flowing through the upper arm switch and the lower arm switch flows,
Sense resistors (35AH, 35BH, 35AL, 35BL) connected to the sense terminals;
an off determination unit (43, 73) that determines whether a most delayed switch, which is a switch that switches from an on state to an off state the slowest, among the opposing arm switches when one of the upper arm switch and the lower arm switch is a self-arm switch and the other is an opposing arm switch, is switched to an off state;
an ON operation unit (41, 42, 71, 72, SC, SD1, SD2, Dr) for switching each of the arm switches from the OFF state to the ON state when it is determined that the most-delay switch has been switched to the OFF state;
a detection unit (43, 73) for detecting a sense voltage, which is a potential difference between both ends of the sense resistor corresponding to each of the opposing arm switches, at the same timing during a period from when each of the opposing arm switches is switched to an OFF operation until the gate voltage of each of the opposing arm switches drops to 0 ;
a determination unit (43, 73) that determines , among the opposing arm switches, an opposing arm switch corresponding to a highest detected sense voltage as the most delayed switch;
Equipped with
The off determination unit determines whether the identified most-delay switch is switched to an off state. A switch drive device that alternately turns on a plurality of upper arm switches (SWAH, SWBH) connected in parallel and a plurality of lower arm switches (SWAL, SWBL) connected in parallel with a dead time therebetween,
The upper arm switch and the lower arm switch each have a sense terminal (StAH, StBH, StAL, StBL) through which a minute current that is correlated with a current flowing through the upper arm switch and the lower arm switch flows,
Sense resistors (35AH, 35BH, 35AL, 35BL) connected to the sense terminals;
an off determination unit (43, 73) that determines whether a most delayed switch, which is a switch that switches from an on state to an off state the slowest, among the opposing arm switches when one of the upper arm switch and the lower arm switch is a self-arm switch and the other is an opposing arm switch, is switched to an off state;
an ON operation unit (41, 42, 71, 72, SC, SD1, SD2, Dr) for switching each of the arm switches from the OFF state to the ON state when it is determined that the most-delay switch has been switched to the OFF state;
a detection unit (43, 73) for detecting a sense voltage, which is a potential difference between both ends of the sense resistor corresponding to each of the opposing arm switches, at the same timing during a period from when each of the opposing arm switches is switched to an on operation until a gate voltage of each of the opposing arm switches rises to a power supply voltage ;
a determination unit (43, 73) that determines , among the opposing arm switches, an opposing arm switch corresponding to a lowest sense voltage detected as the most delayed switch;
Equipped with
The off determination unit determines whether the identified most-delay switch is switched to an off state. A switch drive device that alternately turns on a plurality of upper arm switches (SWAH, SWBH) connected in parallel and a plurality of lower arm switches (SWAL, SWBL) connected in parallel with a dead time therebetween,
The upper arm switch and the lower arm switch each have a sense terminal (StAH, StBH, StAL, StBL) through which a minute current that is correlated with a current flowing through the upper arm switch and the lower arm switch flows,
Sense resistors (35AH, 35BH, 35AL, 35BL) connected to the sense terminals;
an off determination unit (43, 73) that determines whether a most delayed switch, which is a switch that switches from an on state to an off state the slowest, among the opposing arm switches when one of the upper arm switch and the lower arm switch is a self-arm switch and the other is an opposing arm switch, is switched to an off state;
an ON operation unit (41, 42, 71, 72, SC, SD1, SD2, Dr) for switching each of the arm switches from the OFF state to the ON state when it is determined that the most-delay switch has been switched to the OFF state;
a detection unit (43, 73) that detects a rate of change in a sense voltage, which is a potential difference between both ends of the sense resistor corresponding to each of the opposing arm switches, during a period from when each of the opposing arm switches is switched to an OFF operation until a gate voltage of each of the opposing arm switches falls to 0, or during a period from when each of the opposing arm switches is switched to an ON operation until a gate voltage of each of the opposing arm switches rises to a power supply voltage ;
a determination unit (43, 73) that determines, among the opposing arm switches, an opposing arm switch corresponding to a voltage whose detected rate of change is the lowest as the most delayed switch;
Equipped with
The off determination unit determines whether the identified most-delay switch is switched to an off state. 7. The switch drive device according to claim 1 , wherein the detection section is provided corresponding only to the most delayed switch among the opposing arm switches.

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