JP7592402B2 - Method for manufacturing semiconductor module, method for manufacturing electronic device, semiconductor module, and electronic device - Google Patents

Description

The present invention relates to technology for semiconductor modules having semiconductor devices.

Electronic devices such as mobile devices are equipped with a semiconductor module that includes a semiconductor device that communicates with another semiconductor device such as a memory, and a printed wiring board on which the semiconductor device is mounted. The semiconductor device is a semiconductor package that has a semiconductor element and a package substrate. The arrangement structure of the terminals included in the semiconductor device is, for example, a BGA (Ball Grid Array). In electronic devices, the communication speed of semiconductor devices is increasing and the voltage is decreasing, and there is a demand for reducing the noise generated in the semiconductor device. In addition, as electronic devices become smaller and thinner, there is a demand for a narrower pitch between adjacent terminals in semiconductor devices.

One method for reducing noise is to connect a bypass capacitor between the power supply terminal and the ground terminal of a semiconductor device. The bypass capacitor is generally mounted on a printed wiring board by SMT (Surface Mount Technology) next to the semiconductor device or on the side of the printed wiring board opposite to the side on which the semiconductor device is mounted. However, this method requires that wiring that electrically connects the semiconductor device and the capacitor be formed on the printed wiring board, and the inductance of this wiring is one of the factors that generates noise that inhibits faster communication speeds in the semiconductor device. In response to this, Patent Document 1 discloses a technology in which a bypass capacitor is directly soldered to the power supply pad and ground pad of a BGA package.

JP 2006-173407 A

However, in the technology of Patent Document 1, solder balls must be formed on each of a pair of electrodes of the capacitor before the semiconductor device is mounted on a printed wiring board. A capacitor is a small electronic component. For this reason, it is difficult to form solder balls on the electrodes of a capacitor in advance in manufacturing. In addition, the process of forming solder balls on the electrodes of the capacitor is required, which increases the number of manufacturing processes. Therefore, there is a need to improve the productivity of semiconductor modules compared to the past. Such problems also occur when connecting small electronic components other than capacitors, such as inductors or resistors, to a semiconductor device. Furthermore, these electronic components require a strong connection when connected to a semiconductor device.

Therefore, there was a need for technology that would improve the productivity of semiconductor modules. There was also a need to increase the bonding strength of electronic components connected to semiconductor modules.

According to a first aspect of the present invention , a chip component including a first electrode and a second electrode arranged at an interval in a predetermined direction, a semiconductor device including a first land and a second land, and a printed wiring board are prepared, a first solder paste and a second solder paste are supplied at an interval to the printed wiring board, the chip component is placed on the printed wiring board so that the first electrode contacts the first solder paste and the second electrode contacts the second solder paste, the semiconductor device is placed on the printed wiring board so that the first land faces the first electrode and the second land faces the second electrode, and the first solder paste and the second solder paste are applied to the printed wiring board. This is a method for manufacturing a semiconductor module, characterized in that the first land and the first electrode are joined by solder and the second land and the second electrode are joined by solder by heating and melting the molten solder, and the first solder paste is melted and solidified into a fillet shape that spreads continuously outward in the predetermined direction from the position where the first electrode contacts the printed wiring board toward the first land, and the second solder paste is melted and solidified into a fillet shape that spreads continuously outward in the predetermined direction from the position where the second electrode contacts the printed wiring board toward the second land .

According to a second aspect of the present invention , there is provided a semiconductor device including a printed wiring board, a semiconductor device mounted on the printed wiring board, the semiconductor device including a first electrode and a second electrode spaced apart in a predetermined direction, the chip component being arranged between the printed wiring board and the semiconductor device, a first solder joint portion joining the first electrode and the first land, and a second solder joint portion joining the second electrode and the second land, the printed wiring board having an insulating substrate and a solder resist arranged on a main surface of the insulating substrate, the chip component facing the solder resist and having a thickness of about 100 .mu.m when viewed from above. each of the first land and the second land overlaps with at least a portion of the first electrode and the second electrode and protrudes outward in the predetermined direction from the chip component, the first solder joint has a fillet shape that continuously expands outward in the predetermined direction from the first electrode as it moves from the solder resist to the first land, and the second solder joint has a fillet shape that continuously expands outward in the predetermined direction from the second electrode as it moves from the solder resist to the second land.

According to a third aspect of the present invention , there is provided a semiconductor device including a printed wiring board, a semiconductor device mounted on the printed wiring board and including a first land and a second land, a chip component including a first electrode and a second electrode spaced apart in a predetermined direction and disposed between the printed wiring board and the semiconductor device, a first solder joint portion joining the first electrode and the first land, and a second solder joint portion joining the second electrode and the second land, wherein the printed wiring board includes an insulating substrate, a third land disposed on a main surface of the insulating substrate and electrically connected to the first land by the first solder joint portion, and a fourth land disposed on the main surface of the insulating substrate and electrically connected to the second land by the second solder joint portion. and, in a planar view, each of the first land and the second land overlaps with at least a portion of each of the first electrode and the second electrode, and overlaps with at least a portion of each of the third land and the fourth land, and protrudes outward from the chip component in the predetermined direction, the first solder joint has a fillet shape that continuously spreads outward from the first electrode in the predetermined direction as it moves from the third land to the first land, and the second solder joint has a fillet shape that continuously spreads outward from the second electrode in the predetermined direction as it moves from the fourth land to the second land.

According to a fourth aspect of the present invention , there is provided a semiconductor device including a first land and a second land and mounted on the printed wiring board, a chip component including a first electrode and a second electrode spaced apart in a predetermined direction and arranged between the printed wiring board and the semiconductor device, a first solder joint portion joining the first electrode and the first land, and a second solder joint portion joining the second electrode and the second land, wherein the printed wiring board has an insulating substrate and a solder resist arranged on a main surface of the insulating substrate, the solder resist has an opening into which a portion of the chip component is inserted, and when viewed in a plan view, each of the first land and the second land is disposed between the first electrode and the second land. and the first solder joint overlaps at least a portion of each of the first and second electrodes and protrudes outward in the predetermined direction from the chip component, the first solder joint having a fillet shape that continuously spreads outward in the predetermined direction from the first electrode from a portion of the main surface of the insulating substrate that is exposed by the opening in the solder resist toward the first land, and the second solder joint has a fillet shape that continuously spreads outward in the predetermined direction from the second electrode from a portion of the main surface of the insulating substrate that is exposed by the opening in the solder resist toward the second land.

This invention improves the productivity of semiconductor modules.

FIG. 1 is an explanatory diagram of an example of an electronic device according to a first embodiment. 1A is a perspective view of a processing module according to a first embodiment, and FIG. 1B is a schematic cross-sectional view of the processing module. FIG. 2 is an enlarged schematic cross-sectional view of a portion of a processing module according to the first embodiment. 1A is a partial exploded perspective view of a processing module according to a first embodiment, and FIG. 1B is a schematic diagram for explaining the positional relationship of a semiconductor device, a capacitor, and a printed wiring board according to the first embodiment. 5A to 5F are explanatory views of a manufacturing method for a processing module according to the first embodiment. FIG. 11 is an enlarged schematic cross-sectional view of a portion of a processing module according to a second embodiment. 1A is a partial exploded perspective view of a processing module according to a second embodiment, and FIG. 1B is a schematic diagram for explaining the positional relationship of a semiconductor device, a capacitor, and a printed wiring board according to the second embodiment. 13A to 13F are explanatory views of a manufacturing method for a processing module according to a second embodiment. FIG. 11 is an enlarged schematic cross-sectional view of a portion of a processing module according to a third embodiment. 10A is a partial exploded perspective view of a processing module according to a third embodiment, and FIG. 10B is a schematic diagram for explaining the positional relationship of a semiconductor device, a capacitor, and a printed wiring board according to the third embodiment. 13A to 13F are explanatory views of a manufacturing method for a processing module according to a third embodiment. 1A is a schematic cross-sectional view of a processing module of Example 1, FIG. 1B is a schematic cross-sectional view of a processing module of Example 2, and FIG. 1C is a schematic cross-sectional view of a processing module of Comparative Example 1. 1 is a graph showing calculation results of inductance for Example 1, Example 2, and Comparative Example 1.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
[First embodiment]
1 is an explanatory diagram of a digital camera 600, which is an imaging device as an example of an electronic device according to the first embodiment. The digital camera 600, which is an imaging device, is a lens-interchangeable digital camera and includes a camera body 601. A lens unit (lens barrel) 602 including a lens is detachably attached to the camera body 601. The camera body 601 includes a housing 611, and a processing module 300, which is a printed circuit board, and a sensor module 900, which are disposed inside the housing 611. The processing module 300 is an example of a semiconductor module. The processing module 300 and the sensor module 900 are electrically connected by a cable 950.

The sensor module 900 has an image sensor 700, which is an imaging element, and a printed wiring board 800. The image sensor 700 is mounted on the printed wiring board 800. The image sensor 700 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge Coupled Device) image sensor. The image sensor 700 has a function of converting light incident through the lens unit 602 into an electrical signal.

The processing module 300 has a semiconductor device 100 and a printed wiring board 200, which is a first wiring board. The semiconductor device 100 is mounted on the printed wiring board 200. The printed wiring board 200 is a rigid substrate. The semiconductor device 100 is, for example, a digital signal processor, and has the function of acquiring an electrical signal from the image sensor 700, performing processing to correct the acquired electrical signal, and generating image data.

Figure 2(a) is a perspective view of the processing module 300 according to the first embodiment. Figure 2(b) is a schematic cross-sectional view of the processing module 300 taken along line IIB-IIB in Figure 2(a). Figure 3 is a schematic cross-sectional view of an enlarged portion of the processing module 300 shown in Figure 2(b). The following description will be given with reference to Figures 2(a), 2(b) and 3.

The semiconductor device 100 is an area array semiconductor package, and in the first embodiment, is a BGA semiconductor package. The semiconductor device 100 has a semiconductor element 101 and a package substrate 102, which is a second wiring board. The package substrate 102 is a rigid substrate.

The semiconductor element 101 is mounted on a package substrate 102. The package substrate 102 has an insulating substrate 120. The insulating substrate 120 has a main surface 121 and a main surface 122 opposite to the main surface 121. The material of the insulating substrate 120 is, for example, an epoxy resin containing ceramic such as alumina or glass. The semiconductor element 101 is, for example, a semiconductor chip, and is mounted on the main surface 121 of the insulating substrate 120 face-up or face-down, and in the first embodiment, face-down. The main surface 121 of the insulating substrate 120 is provided with a sealing resin 106 that seals the semiconductor element 101. The package substrate 102 has a plurality of lands 130 arranged on the main surface 122 of the insulating substrate 120. The arrangement pattern of the plurality of lands 130 may be a lattice pattern, i.e., a matrix pattern, or may be a staggered pattern. The land 130 is a terminal formed of a conductive metal material, for example, copper or gold, and is, for example, a signal terminal, a power terminal, a ground terminal, or a dummy terminal. A solder resist 108 is provided on the main surface 122. The solder resist 108 is a film made of a solder resist material. Each of the multiple lands 130 is exposed through an opening formed in the solder resist 108. The lands 130 may be either solder mask defined (SMD) or non-solder mask defined (NSMD) lands, but in the first embodiment, they are SMD lands. Although not shown, a heat sink may be disposed on the upper surface of the semiconductor element 101.

The semiconductor element 101 has multiple power supply terminals, multiple ground terminals, and multiple signal terminals, and each terminal is joined to the package substrate 102 by wire bonding or flip chip bonding (not shown). 2(b) and 3 show power supply terminal 111E, which is one of the multiple power supply terminals, and ground terminal 111G, which is one of the multiple ground terminals. That is, the semiconductor element 101 has power supply terminal 111E and ground terminal 111G.

The printed wiring board 200 has an insulating substrate 220. The insulating substrate 220 has a main surface 221 and a main surface 222 opposite the main surface 221. The printed wiring board 200 has a plurality of lands 230 arranged on the main surface 221 of the insulating substrate 220. The lands 230 are terminals formed of a conductive metal material, such as copper or gold, and are, for example, a signal terminal, a power terminal, a ground terminal, or a dummy terminal. The material of the insulating substrate 220 is an insulating material such as epoxy resin.

The printed wiring board 200 has a solder resist 208. The solder resist 208 is a film made of a solder resist material. The solder resist 208 is provided on the main surface 221. Each of the multiple lands 230 is exposed through an opening formed in the solder resist 208. The lands 230 may be either SMD or NSMD lands, but are SMD lands in the first embodiment.

The multiple lands 130 include land 130E, which serves as a power terminal, and land 130G, which serves as a ground terminal. The multiple lands 130 are arranged with a pitch of 0.4 mm or less between each land. Land 130E is the first land, and land 130G is the second land. Land 130E is electrically connected to power terminal 111E of semiconductor element 101 through via conductor 112E formed on insulating substrate 120. Land 130G is electrically connected to ground terminal 111G of semiconductor element 101 through via conductor 112G formed on insulating substrate 120.

The multiple lands 130 include a land 130S other than lands 130E and 130G. The land 130S is a land that serves as a signal terminal, a power terminal, a ground terminal, or a dummy terminal. In the first embodiment, each of the multiple lands 130S is a fifth land, and each of the multiple lands 230 is a sixth land. The land 130S and the land 230 are joined by a solder joint 193, which is a third solder joint formed with solder. The height of the solder joint 193 is higher than the height of the capacitor 400 described below. Specifically, the height is 1.3 times or less the height of the capacitor. This is because warping occurs from the center of the semiconductor element 101 toward the outer periphery during the heat bonding process.

The processing module 300 includes a capacitor 400, which is an example of a chip component. The capacitor 400 is a passive component and a chip component. The size of the chip component in a plan view is preferably 0402 size or smaller, such as 0402 size, which is 0.4 mm x 0.2 mm, or 0201 size, which is 0.25 mm x 0.125 mm. The notation of 0402 size, 0201 size, etc. conforms to the size notation method (mm standard) for electronic components in the Japanese Industrial Standards.
The capacitor 400 has an element body 401 having a substantially rectangular parallelepiped shape extending in a longitudinal direction, which is an example of a predetermined direction, and a pair of electrodes 410, 420 provided on both sides of the element body 401 in the longitudinal direction. The pair of electrodes 410, 420 are fixed to the element body 401 with a gap therebetween in the longitudinal direction. In FIG. 2B and FIG. 3, the longitudinal direction of the capacitor 400, i.e., the element body 401, is the X direction. The short side direction of the capacitor 400, i.e., the element body 401, is the Y direction. The Y direction is the width direction perpendicular to the X direction. The up-down direction of the capacitor 400, i.e., the element body 401, is the Z direction. The Z direction is the direction perpendicular to the X direction and the Y direction. The Z direction is also perpendicular to the main surfaces 121, 122, 221, and 222.

Of the pair of electrodes 410, 420, one electrode 410 is a first electrode, and the other electrode 420 is a second electrode. Each electrode 410, 420 includes a base and an outer coating film that covers the base. The material of the outer coating film of the electrodes 410, 420 is a conductive metal material such as tin.

Capacitor 400 is a bypass capacitor. Electrode 410 of capacitor 400 is electrically connected to land 130E, and electrode 420 of capacitor 400 is electrically connected to land 130G.

Power supply noise occurs due to the inductance of the wiring between the electrode 410 of the capacitor 400 and the power supply terminal 111E, and the inductance of the wiring between the electrode 420 of the capacitor 400 and the ground terminal 111G. Power supply noise refers to voltage fluctuations in the power supply line caused by the operation of the semiconductor device 100. This voltage fluctuation occurs when the power supply current changes due to inductance and resistance parasitic to the power supply line. In order to reduce the inductance of the wiring and reduce the power supply noise, it is preferable that the capacitor 400 is placed directly under the semiconductor element 101 so that the wiring between the power supply terminal 111E and the ground terminal 111G of the semiconductor device 100 is the shortest. In other words, when the processing module 300 is viewed in plan from the semiconductor device 100 side, it is preferable that the semiconductor element 101 and the capacitor 400 overlap.

Therefore, in the first embodiment, the capacitor 400 is disposed on the main surface 221 side of the insulating substrate 220 of the printed wiring board 200, that is, between the semiconductor device 100 and the printed wiring board 200. The electrode 410 of the capacitor 400 is joined to the land 130E at the solder joint 191, which is a first solder joint formed with solder. The electrode 420 of the capacitor 400 is joined to the land 130G at the solder joint 192, which is a second solder joint formed with solder. As a result, the electrode 410 of the capacitor 400 is electrically connected to the land 130E of the semiconductor device 100 directly at the solder joint 191 without passing through the printed wiring board 200. Therefore, the inductance of the wiring between the electrode 410 of the capacitor 400 and the land 130E can be reduced. In addition, the electrode 420 of the capacitor 400 is electrically connected to the land 130G of the semiconductor device 100 directly at the solder joint 192 without passing through the printed wiring board 200. This reduces the inductance of the wiring between the electrode 420 of the capacitor 400 and the land 130G. Because the inductance of the wiring is reduced, the power supply noise generated is reduced, and the communication speed in the semiconductor device 100 can be increased.

In the first embodiment, the solder joints 191, 192 are in contact with the solder resist 208 but are not in contact with the land 230 of the printed wiring board 200.

Figure 4(a) is a partial perspective view of an exploded processing module 300 according to the first embodiment. Figure 4(b) is a schematic diagram for explaining the relative positions of the semiconductor device 100, the capacitor 400, and the printed wiring board 200 when viewed in the Z direction. Note that in Figures 4(a) and 4(b), the solder joints 191 and 192 are omitted. In Figure 4(b), the lands 130E and 130G of the semiconductor device are shown by dashed lines.

As shown in FIG. 4(a), the electrode 410 has three side surfaces 411, 412, 413, an upper surface 414, and a lower surface 415, which are electrode surfaces. The side surfaces 411, 412, 413, the upper surface 414, and the lower surface 415 are rectangular when viewed from a direction perpendicular to each surface. Of the three side surfaces 411, 412, 413, two side surfaces 412 and 413 face each other with a gap in the Y direction. The upper surface 414 and the lower surface 415 face each other with a gap in the Z direction. The side surface 411 is adjacent to the side surfaces 412 and 413, the upper surface 414, and the lower surface 415, and is perpendicular to them. The electrode 420 has three side surfaces 421, 422, 423, an upper surface 424, and a lower surface 425, which are electrode surfaces. The side surfaces 421, 422, 423, the upper surface 424, and the lower surface 425 are rectangular when viewed from a direction perpendicular to each surface. Of the three side surfaces 421, 422, 423, the two side surfaces 422, 423 face each other with a gap in the Y direction. The upper surface 424 and the lower surface 425 face each other with a gap in the Z direction. The side surface 421 is adjacent to the side surfaces 422, 423, the upper surface 424, and the lower surface 425, and is perpendicular to them. The side surface 411 of the electrode 410 and the side surface 421 of the electrode 420 are disposed facing each other with a gap in the X direction. The upper surface 414 of the electrode 410 faces the land 130E of the semiconductor device 100, and the lower surface 415 of the electrode 410 faces the solder resist 208 of the printed wiring board 200. The upper surface 424 of the electrode 420 faces the land 130G of the semiconductor device 100, and the lower surface 425 of the electrode 420 faces the solder resist 208 of the printed wiring board 200.

As shown in FIG. 4B, the land 130E and the land 130G are arranged with an interval in the X direction. The land 130E overlaps at least a part of the electrode 410 of the capacitor 400 in a plan view, that is, in the Z direction, and in the first embodiment, the entirety of the electrode 410. The land 130G overlaps at least a part of the electrode 420 of the capacitor 400 in the Z direction, and in the first embodiment, the entirety of the electrode 420. In the first embodiment, the area S _130E of the land 130E is larger than the area S ₄₁₀ of the electrode 410 when viewed in the Z direction. Also, the area S _130G of the land 130G is larger than the area S ₄₂₀ of the electrode 420 when viewed in the Z direction. The lands 130E and 130G protrude outward in the X direction from the capacitor 400 when viewed in the Z direction.

As shown in FIG. 3, each of the solder joints 191 and 192 has a fillet shape in which the outer surface spreads away from the capacitor 400 as it moves from the solder resist 208 to each of the lands 130E and 130G. Specifically, the solder joint 191 has a fillet shape that spreads outward in the X direction from the electrode 410, that is, in the X1 direction, as it moves from the solder resist 208 to the land 130E. The solder joint 192 has a fillet shape that spreads outward in the X direction from the electrode 420, that is, in the X2 direction, as it moves from the solder resist 208 to the land 130G. The X1 direction is the direction in which the solder joint 192 moves away from the electrode 410 in the X direction. The X2 direction is the opposite direction to the X1 direction in the X direction, and is the direction in which the solder joint 192 moves away from the electrode 420. This increases the bonding strength between each of the lands 130E and 130G and each of the electrodes 410 and 420. In addition, as shown in FIG. 2(b), each solder joint 191, 192 is prevented from expanding in the X direction, and each solder joint 191, 192 is prevented from shorting out with the adjacent solder joint 193.

As shown in FIG. 4B, the lands 130E and 130G are rectangular when viewed in the Z direction, but this is not limited to this. For example, the lands 130E and 130G may be any shape, such as a polygon, a circle, or an ellipse, when viewed in the Z direction.

Next, a method for manufacturing the processing module 300 will be described. Figures 5(a) to 5(f) are explanatory diagrams of the method for manufacturing the processing module 300 according to the first embodiment. As shown in Figure 5(a), the printed wiring board 200 is prepared (step S1). In step S1, the semiconductor device 100 and the capacitor 400 are also prepared. Next, as shown in Figure 5(b), the first solder paste P1, the second solder paste P2, and the third solder paste P3 are supplied on the printed wiring board 200 with a gap between them (step S2). In the first embodiment, in step S2, the solder paste P1 and the solder paste P2 are supplied on the solder resist 208. In addition, in step S2, the solder paste P3 is supplied on the land 230 of the printed wiring board 200.

The solder pastes P1, P2, and P3 contain solder powder. The solder pastes P1, P2, and P3 may further contain flux components necessary for soldering. In this embodiment, the solder pastes P1, P2, and P3 are all made of the same material, but are not limited to being made of the same material as long as they have similar melting points. In step S2, the solder pastes P1, P2, and P3 are supplied to the printed wiring board 200 by screen printing using a metal mask 23. Note that the method of supplying the solder pastes P1, P2, and P3 is not limited to this. For example, the solder pastes P1, P2, and P3 may be supplied to the printed wiring board 200 by a dispenser.

Next, as shown in FIG. 5(c), the capacitor 400 prepared in step S1 is placed on the printed wiring board 200 so that the electrode 410 contacts the solder paste P1 and the electrode 420 contacts the solder paste P2 (step S3). As a result, the lower surface 415 of the electrode 410 contacts the solder paste P1 and the lower surface 425 of the electrode 420 contacts the solder paste P2. There is no need to attach solder balls to the electrodes 410 and 420 of the capacitor 400 in advance. In step S3, the capacitor 400 is placed on the printed wiring board 200 using a mounter (not shown). At this time, the capacitor 400 is aligned and placed on the printed wiring board so that the electrode 410 faces the solder paste P1 and the electrode 420 faces the solder paste P2.

5(d), the semiconductor device 100 prepared in step S1 is placed on the printed wiring board 200 so that the land 130E faces the electrode 410 and the land 130G faces the electrode 420 (step S4). In step S4, the semiconductor device 100 is placed on the printed wiring board 200 using a mounter (not shown). At this time, the semiconductor device 100 is aligned and placed on the printed wiring board so that the land 130E faces the electrode 410, the land 130G faces the electrode 420, and the land 130S faces the land 230. Here, no solder balls are provided on the lands 130E and 130G of the semiconductor device 100 prepared in step S1, and the land 130S is provided with a solder ball B, which is a ball terminal. Therefore, the semiconductor device 100 is placed on the printed wiring board 200 so that the center of the solder ball B and the center of the land 230 coincide with each other. In step S4, the semiconductor device 100 is placed on the printed wiring board 200, so that the solder balls B formed on the lands 130S come into contact with the solder paste P3. In FIG. 5(d), the upper surface 414 of the electrode 410 and the land 130E, and the upper surface 424 of the electrode 420 and the land 130G are not in contact, but they may be in contact.

In this step S4, the positional relationship between the printed wiring board 200, the capacitor 400, and the semiconductor device 100 when viewed from the Z direction is as shown in FIG. 4(b). When the capacitor 400 is placed on the printed wiring board 200, each of the lands 130E and 130G of the semiconductor device 100 overlaps at least a portion of each of the electrodes 410 and 420 when viewed in the Z direction, and protrudes outward from the capacitor 400 in the X direction.

Next, the semiconductor device 100 and the capacitor 400 are placed on the printed wiring board 200 and are transported to a reflow furnace (not shown). Then, in step S5-1 shown in FIG. 5(e), the temperature of the atmosphere in the reflow furnace is adjusted to a temperature equal to or higher than the melting point of the solder, and the solder pastes P1, P2, P3 and the solder balls B in FIG. 5(d) are melted as shown in FIG. 5(e). When the solder paste P1 is melted, it becomes a fluid molten solder M1, and when the solder paste P2 is melted, it becomes a fluid molten solder M2. When the solder paste P3 and the solder balls B are melted, they become a fluid molten solder M3.

Following step S5-1, in step S5-2 shown in FIG. 5(f), heating is continued to flow the molten solder M1, M2. Because the electrodes 410, 420 have better wettability than the solder resist 208, the molten solder M1, M2 creeps upward as indicated by the arrow Z1 on the side surfaces 411, 421 as shown in FIG. 5(e). Thereafter, due to their tendency to spread, the molten solder M1, M2 moves to the upper surfaces 414, 424 as shown in FIG. 5(f). Although not shown in FIG. 5(e), the molten solder M1, M2 also creeps upward as indicated by the arrow Z1 on the side surfaces 412, 413 of the electrode 410 and the side surfaces 422, 423 of the electrode 420.

The capacitor 400 is also pushed upward by the molten solder M1, M2 toward the semiconductor device 100, narrowing the distance between the upper surface 414 of the electrode 410 and the land 130E, and narrowing the distance between the upper surface 424 of the electrode 420 and the land 130G. The molten solder M1, M2 that has reached the upper surfaces 414, 424 comes into contact with the lands 130E, 130G, wetting and spreading over the lands 130E, 130G, forming a fillet shape with a wider base as it moves from the solder resist 208 toward the lands 130E, 130G.

Then, the molten solders M1 and M2 that have spread to every corner of the lands 130E and 130G are cooled and solidified. As a result, the molten solder M1 is cooled and solidified in a fillet shape on the land 130E. The molten solder M2 is cooled and solidified in a fillet shape on the land 130G. At the same time, the molten solder M3 is also cooled and solidified. As a result, as shown in FIG. 3, a solder joint 191 is formed by joining the land 130E and the electrode 410 with solder, and a solder joint 192 is formed by joining the land 130G and the electrode 420 with solder. Also, a solder joint 193 is formed by joining the land 130S and the land 230 with solder. In this way, the processing module 300 shown in FIG. 3 is manufactured.

Then, the processing module 300 shown in FIG. 3 is stored in the housing 611 shown in FIG. 1 to manufacture the camera body 601, i.e., the digital camera 600.

As described above, by melting the solder pastes P1 and P2 supplied to the printed wiring board 200, the solder can be supplied to the lands 130E and 130G of the semiconductor device 100 via the electrodes 410 and 420 of the capacitor 400. This eliminates the need to form solder balls on the electrodes 410 and 420 of the capacitor 400 in advance, and reduces the process of manufacturing the processing module 300. Therefore, the processing module 300 can be manufactured easily, improving the productivity of the processing module 300.

Here, when the wettability of the solder in the lands 130E and 130G of the semiconductor device 100 is F1 and the wettability of the solder in the electrodes 410 and 420 of the capacitor 400 is F2, it is preferable that the relationship F1 ≧ F2 is satisfied. For example, by using gold as the material of the surface of the land 130, i.e., the material of the surfaces of the lands 130E and 130G, the relationship F1 ≧ F2 is satisfied, and the molten solder M1 and M2 are more likely to wet and spread on the lands 130E and 130G. This makes it easier for the solder joints 191 and 192 to have a fillet shape on the lands 130E and 130G. Therefore, even if the amount of solder in the solder joints 191 and 192 is reduced, the lands 130E and 130G of the semiconductor device 100 can be reliably connected to the electrodes 410 and 420 of the capacitor 400. This makes it possible to prevent poor connection even if the lands 130 of the semiconductor device 100 are arranged at high density.

[Second embodiment]
A second embodiment will be described. Fig. 6 is a schematic cross-sectional view of an enlarged portion of a processing module according to the second embodiment. Fig. 6 shows a schematic cross-section of a processing module 300A according to the second embodiment. In the following description, the same reference numerals are used for configurations similar to those of the first embodiment, and detailed description thereof will be omitted.

The processing module 300A according to the second embodiment has a semiconductor device 100 having a configuration similar to that of the first embodiment, and a printed wiring board 200A. As in the first embodiment, the insulating substrate 120 included in the semiconductor device 100 has a main surface 122 on which a first land, a land 130E, a second land, and a fifth land, a land 130G, and a fifth land, respectively, arranged.

The printed wiring board 200A has an insulating substrate 220 similar to that of the first embodiment. The insulating substrate 220 has a main surface 221 and a main surface 222 opposite the main surface 221. The printed wiring board 200A has a third land, land 230E, a fourth land, land 230G, and a sixth land, land 230S, which are arranged on the main surface 221 of the insulating substrate 220.

Lands 230E, 230G, and 230S are terminals formed of a conductive metal material, such as copper or gold. Land 230E is a power terminal, and land 230G is a ground terminal. Land 230S is a signal terminal, power terminal, ground terminal, or dummy terminal. A via conductor 212E formed on the insulating substrate 220 is connected to land 230E. A via conductor 212G formed on the insulating substrate 220 is connected to land 230G.

The printed wiring board 200A has a solder resist 208A. The solder resist 208A is a film made of a solder resist material. The solder resist 208A is provided on the main surface 221. The land 230S is exposed through an opening formed in the solder resist 208A. The land 230E and the land 230G are exposed through one opening HA formed in the solder resist 208A. Note that the land 230E and the land 230G may each be exposed through two openings formed independently.

Land 130E and land 230E are joined at solder joint 191A, which is a first solder joint formed with solder. Land 130G and land 230G are joined at solder joint 192A, which is a second solder joint formed with solder. Land 130S and land 230S are joined at solder joint 193A, which is a third solder joint formed with solder.

The processing module 300A includes a capacitor 400 used as a bypass capacitor, as in the first embodiment. The capacitor 400 is disposed on the main surface 221 side of the insulating substrate 220 of the printed wiring board 200A, that is, between the semiconductor device 100 and the printed wiring board 200A. The electrode 410 of the capacitor 400 is joined to the land 130E at the solder joint 191A. The electrode 420 of the capacitor 400 is joined to the land 130G at the solder joint 192A. As a result, the electrode 410 of the capacitor 400 is electrically connected directly to the land 130E of the semiconductor device 100 at the solder joint 191A. Therefore, the inductance of the wiring between the electrode 410 of the capacitor 400 and the land 130E can be reduced. In addition, the electrode 420 of the capacitor 400 is electrically connected directly to the land 130G of the semiconductor device 100 at the solder joint 192A. This reduces the inductance of the wiring between the electrode 420 of the capacitor 400 and the land 130G. Because the inductance of the wiring is reduced, the power supply noise generated is reduced, and the communication speed in the semiconductor device 100 can be increased.

In the second embodiment, land 230E is electrically connected to land 130E at solder joint 191A. Land 230G is electrically connected to land 130E at solder joint 192A. A power supply IC (not shown) is mounted on printed wiring board 200A and is electrically connected to via conductors 212E and 212G shown in FIG. 6. The power supply IC is capable of supplying power to semiconductor element 101 of semiconductor device 100 via solder joint 191A and solder joint 192A.

Figure 7(a) is a partial perspective view of an exploded processing module 300A according to the second embodiment. Figure 7(b) is a schematic diagram for explaining the relative positions of the semiconductor device 100, the capacitor 400, and the printed wiring board 200A when viewed in the Z direction. Note that in Figures 7(a) and 7(b), the solder joints 191A and 192A are omitted. In Figure 7(b), the lands 130E and 130G of the semiconductor device are shown by dashed lines.

As shown in FIG. 7(a), the upper surface 414 of the electrode 410 faces the land 130E of the semiconductor device 100, and the lower surface 415 of the electrode 410 faces the land 230E of the printed wiring board 200A. The upper surface 424 of the electrode 420 faces the land 130G of the semiconductor device 100, and the lower surface 425 of the electrode 420 faces the land 230G of the printed wiring board 200A.

As shown in FIG. 7B, the land 130E and the land 130G are arranged with a gap in the X direction. The land 130E overlaps at least a part of the electrode 410 of the capacitor 400, and in the second embodiment, the whole of the electrode 420 of the capacitor 400, when viewed in the Z direction. The land 130G overlaps at least a part of the electrode 420 of the capacitor 400, and in the second embodiment, the whole of the electrode 420. The land 230E and the land 230G are arranged with a gap in the X direction. The land 230E overlaps at least a part of the electrode 410 of the capacitor 400, and in the second embodiment, the whole of the electrode 420 of the capacitor 400, when viewed in the Z direction. Moreover, the land 130E overlaps at least a part of the land 230E, and in the second embodiment, the whole of the land 230G, when viewed in the Z direction. Moreover, the land 130G overlaps at least a part of the land 230G, and in the second embodiment, the whole of the land 230G, when viewed in the Z direction. In the second embodiment, when viewed in the Z direction, the area _S130E of the land 130E is larger than the area _S410 of the electrode 410. Also, when viewed in the Z direction, the area _S130G of the land 130G is larger than the area _S420 of the electrode 420. When viewed in the Z direction, the land 130E and the land 130G protrude outward in the X direction from the capacitor 400.

7B, in the second embodiment, the area _S130E of the land 130E is larger than the area _S230E of the land 230E when viewed in the Z direction. The area _S130G of the land 130G is larger than the area S230G of the land _230G when viewed in the Z direction. Furthermore, the area _SHA of the opening HA is larger than the area _S400 of the capacitor 400 when viewed in the Z direction.

As shown in FIG. 6, each solder joint 191A, 192A has a fillet shape in which the outer surface spreads away from the capacitor 400 as it moves from each land 230E, 230G to each land 130E, 130G. Specifically, the solder joint 191A has a fillet shape that spreads outward in the X direction from the electrode 410, that is, in the X1 direction, as it moves from the land 230E to the land 130E. The solder joint 192A has a fillet shape that spreads outward in the X direction from the electrode 410, that is, in the X2 direction, as it moves from the land 230G to the land 130G. The X1 direction is the direction in which the solder joint 192A moves away from the electrode 410 in the X direction. The X2 direction is the opposite direction to the X1 direction in the X direction, and is the direction in which the solder joint 192A moves away from the electrode 420. This increases the bonding strength between each land 130E, 130G and each electrode 410, 420. In addition, each solder joint 191A, 192A is prevented from expanding in the X direction, and each solder joint 191A, 192A is prevented from shorting out with the adjacent solder joint 193A.

As shown in FIG. 7(b), the lands 230E and 230G are rectangular when viewed in the Z direction, but this is not limited to this. For example, the lands 230E and 230G may be any shape, such as a polygon, a circle, or an ellipse, when viewed in the Z direction.

Next, a method for manufacturing the processing module 300A will be described. FIGS. 8(a) to 8(f) are explanatory diagrams of a method for manufacturing the processing module 300A according to the second embodiment. As shown in FIG. 8(a), a printed wiring board 200A is prepared (step S11). In step S11, a semiconductor device 100 and a capacitor 400 are also prepared. Next, as shown in FIG. 8(b), a solder paste P1, which is a first solder paste, a solder paste P2, which is a second solder paste, and a solder paste P3, which is a third solder paste, are supplied on the printed wiring board 200A at intervals from each other (step S12). In the second embodiment, in step S12, the solder paste P1 is supplied on the land 230E exposed by the opening HA formed in the solder resist 208A. Also, the solder paste P2 is supplied on the land 230G exposed by the opening HA formed in the solder resist 208A. Also, in step S12, solder paste P3 is supplied onto land 230S of printed wiring board 200A.

In step S12, the solder pastes P1, P2, and P3 are supplied to the printed wiring board 200A by screen printing using a metal mask 23. Note that the method of supplying the solder pastes P1, P2, and P3 is not limited to this. For example, the solder pastes P1, P2, and P3 may be supplied to the printed wiring board 200A by a dispenser.

Next, as shown in FIG. 8(c), the capacitor 400 prepared in step S11 is placed on the printed wiring board 200A so that the electrode 410 contacts the solder paste P1 and the electrode 420 contacts the solder paste P2 (step S13). This brings the lower surface 415 of the electrode 410 into contact with the solder paste P1 and the lower surface 425 of the electrode 420 into contact with the solder paste P2. There is no need to attach solder balls to the electrodes 410 and 420 of the capacitor 400 in advance.

Next, as shown in FIG. 8(d), the semiconductor device 100 prepared in step S11 is placed on the printed wiring board 200A so that the land 130E faces the electrode 410 and the land 130G faces the electrode 420 (step S14). In step S14, the semiconductor device 100 is placed on the printed wiring board 200A, so that the solder ball B, which is a ball terminal provided on the land 130S, is brought into contact with the solder paste P3. In FIG. 8(d), the upper surface 414 of the electrode 410 and the land 130E and the upper surface 424 of the electrode 420 and the land 130G are not in contact, but they may be in contact.

In this step S14, the positional relationship between the printed wiring board 200A, the capacitor 400, and the semiconductor device 100 when viewed from the Z direction is as shown in FIG. 7(b). When the capacitor 400 is placed on the printed wiring board 200A, each of the lands 130E and 130G of the semiconductor device 100 overlaps at least a portion of each of the electrodes 410 and 420 when viewed in the Z direction, and protrudes outward from the capacitor 400 in the X direction.

Next, the semiconductor device 100 and the capacitor 400 are placed on the printed wiring board 200A and are transported to a reflow furnace (not shown). Then, in step S15-1 shown in FIG. 8(e), the temperature of the atmosphere in the reflow furnace is adjusted to a temperature equal to or higher than the melting point of the solder, and the solder pastes P1, P2, P3 and the solder balls B in FIG. 8(d) are melted as shown in FIG. 8(e). When the solder paste P1 is melted, it becomes a fluid molten solder M1, and when the solder paste P2 is melted, it becomes a fluid molten solder M2. When the solder paste P3 and the solder balls B are melted, they become a fluid molten solder M3.

Following step S15-1, in step S15-2 shown in FIG. 8(f), heating is continued to flow the molten solder M1, M2. The molten solder M1, M2 creeps upward as indicated by the arrow Z1 on the side surfaces 411, 421 as shown in FIG. 8(e). The molten solder M1, M2 then moves to the upper surfaces 414, 424 as shown in FIG. 8(f). Although not shown in FIG. 8(e), the molten solder M1, M2 also creeps upward as indicated by the arrow Z1 on the side surfaces 412, 413 of the electrode 410 and the side surfaces 422, 423 of the electrode 420.

The capacitor 400 is also pushed upward by the molten solders M1 and M2 toward the semiconductor device 100, narrowing the distance between the upper surface 414 of the electrode 410 and the land 130E, and narrowing the distance between the upper surface 424 of the electrode 420 and the land 130G. The molten solders M1 and M2 that reach the upper surfaces 414 and 424 come into contact with the lands 130E and 130G, wetting and spreading over the lands 130E and 130G, forming a fillet shape with a wider base as it moves from the solder resist 208A toward the lands 130E and 130G.

Then, the molten solder M1, M2 that has wetted and spread to every corner of the lands 130E, 130G is cooled and solidified. As a result, the molten solder M1 is cooled and solidified in a fillet shape on the land 130E. The molten solder M2 is cooled and solidified in a fillet shape on the land 130G. At the same time, the molten solder M3 is also cooled and solidified. As a result, the solder joints 191A, 192A, 193A are formed as shown in FIG. 6. In this manner, the processing module 300A shown in FIG. 6 is manufactured.

Then, the processing module 300A shown in FIG. 6 is stored in the housing 611 shown in FIG. 1 to manufacture the camera body of a digital camera, which is an example of an electronic device.

As described above, by melting the solder pastes P1 and P2 supplied to the printed wiring board 200A, the solder can be supplied to the lands 130E and 130G of the semiconductor device 100 via the electrodes 410 and 420 of the capacitor 400. This eliminates the need to form solder balls on the electrodes 410 and 420 of the capacitor 400 in advance, and reduces the process of manufacturing the processing module 300A. Therefore, the processing module 300A can be manufactured easily, improving the productivity of the processing module 300A.

Furthermore, land 130E and land 230E are electrically connected by solder joint 191A, and land 130G and land 230G are electrically connected by solder joint 192A. This allows the solder joints 191A and 192A for joining the capacitor 400 to the semiconductor device 100 to be used as a power supply line for supplying power to the semiconductor element 101 of the semiconductor device 100. This increases the degree of freedom in circuit design in the processing module 300A.

In the second embodiment, as shown in FIG. 7B, the areas _{S130E and S130G of the lands 130E} and _130G are larger than the areas S230E and S230G of the lands _230E and _230G when viewed in the Z direction. The molten solder M1 and M2 are easily wetted and spread on the lands 130E and 130G, and by utilizing this property, it is possible to promote the movement of more of the molten solder M1 and M2 to the lands 130E and 130G. As a result, even if there is variation in the supply amount of the solder paste P1 and P2, the allowable amount for the variation of the solder paste P1 and P2 increases because the areas of the lands 130E and 130G are larger. Therefore, it is possible to prevent side balls and the like from occurring in the solder joints 191A and 192A, and as a result, it is possible to prevent short-circuit defects in the solder joints 191A and 192A.

[Third embodiment]
A third embodiment will be described. Fig. 9 is a schematic cross-sectional view of an enlarged portion of a processing module according to the third embodiment. Fig. 9 shows a schematic cross-section of a processing module 300B according to the third embodiment. In the following description, the same reference numerals are used for configurations similar to those of the first embodiment, and detailed description thereof will be omitted.

The processing module 300B according to the third embodiment has a semiconductor device 100 having a configuration similar to that of the first embodiment, and a printed wiring board 200B. As in the first embodiment, the insulating substrate 120 included in the semiconductor device 100 has a main surface 122 on which a first land, a land 130E, a second land, and a fifth land, a land 130G, are arranged.

The printed wiring board 200B has an insulating substrate 220 similar to that of the first embodiment. The insulating substrate 220 has a main surface 221 and a main surface 222 opposite to the main surface 221. As in the first embodiment, a land 230 is disposed on the main surface 221 of the insulating substrate 220.

The printed wiring board 200B has a solder resist 208B. The solder resist 208B is a film made of a solder resist material. The solder resist 208B is provided on the main surface 221. The land 230 is exposed through an opening formed in the solder resist 208B.

The processing module 300B includes a capacitor 400 used as a bypass capacitor, as in the first embodiment. The capacitor 400 is disposed on the main surface 221 side of the insulating substrate 220 of the printed wiring board 200B, that is, between the semiconductor device 100 and the printed wiring board 200B. The electrode 410 of the capacitor 400 is joined to the land 130E at the solder joint 191B, which is a first solder joint formed with solder. The electrode 420 of the capacitor 400 is joined to the land 130G at the solder joint 192B, which is a second solder joint formed with solder. As a result, the electrode 410 of the capacitor 400 is electrically connected directly to the land 130E of the semiconductor device 100 at the solder joint 191B. This makes it possible to reduce the inductance of the wiring between the electrode 410 of the capacitor 400 and the land 130E. In addition, the electrode 420 of the capacitor 400 is electrically connected directly to the land 130G of the semiconductor device 100 at the solder joint 192B. This reduces the inductance of the wiring between the electrode 420 of the capacitor 400 and the land 130G. Since the inductance of the wiring is reduced, the generated power supply noise is reduced, and the communication speed in the semiconductor device 100 can be increased.

The land 130S and the land 230 are joined at a solder joint 193B, which is a third solder joint formed with solder. In the third embodiment, the solder resist 208B has an opening HB that exposes a portion 221B of the main surface 221.

Figure 10(a) is a partial perspective view of an exploded processing module 300B according to the third embodiment. Figure 10(b) is a schematic diagram for explaining the relative positions of the semiconductor device 100, the capacitor 400, and the printed wiring board 200B when viewed in the Z direction. Note that in Figures 10(a) and 10(b), the solder joints 191B and 192B are omitted. In Figure 10(b), the lands 130E and 130G of the semiconductor device are shown by dashed lines.

As shown in FIG. 10(a), the upper surface 414 of the electrode 410 faces the land 130E of the semiconductor device 100, and the lower surface 415 of the electrode 410 faces the portion 221B of the main surface 221 of the printed wiring board 200B. The upper surface 424 of the electrode 420 faces the land 130G of the semiconductor device 100, and the lower surface 425 of the electrode 420 faces the portion 221B of the printed wiring board 200B.

As shown in Fig. 10B, the land 130E and the land 130G are arranged with an interval in the X direction. The land 130E overlaps at least a part of the electrode 410 of the capacitor 400 in a plan view, i.e., in the Z direction, and in the third embodiment, the entire electrode 410 of the capacitor 400. The land 130G overlaps at least a part of the electrode 420 of the capacitor 400 in the Z direction, and in the third embodiment, the entire electrode 420 of the capacitor 400. In the third embodiment, the area _S130E of the land 130E is larger than the area _S410 of the electrode 410 when viewed in the Z direction. Also, the area _S130G of the land 130G is larger than the area _S420 of the electrode 420 when viewed in the Z direction. The lands 130E and 130G protrude outward in the X direction from the capacitor 400 when viewed in the Z direction.

As shown in FIG. 9, each solder joint 191B, 192B has a fillet shape in which the outer surface spreads away from the capacitor 400 as it moves from the portion 221B exposed by the opening HB toward each land 130E, 130G. Specifically, the solder joint 191B has a fillet shape that spreads outward in the X direction from the electrode 410, that is, in the X1 direction, as it moves from the portion 221B exposed by the opening HB toward the land 130E. The solder joint 192B has a fillet shape that spreads outward in the X direction from the electrode 420, that is, in the X2 direction, as it moves from the portion 221B exposed by the opening HB toward the land 130G. The X1 direction is the direction away from the electrode 410 in the X direction. The X2 direction is the opposite direction to the X1 direction in the X direction, and is the direction away from the electrode 420. This increases the bonding strength between the lands 130E, 130G and the electrodes 410, 420. In addition, the solder joints 191B, 192B are prevented from bulging in the X direction, and each solder joint 191B, 192B is prevented from shorting out with the adjacent solder joint 193B.

10B, in the third embodiment, when viewed in the Z direction, the area S _HB of the opening HB, i.e., the area S _221B of the portion 221B exposed by the opening HB, is larger than the area S ₄₀₀ of the capacitor 400. Therefore, as shown in FIG 9, a part of the capacitor 400 in the Z direction is inserted into the opening HB, and the gap between the semiconductor device 100 and the printed wiring board 200B is narrowed.

Next, a method for manufacturing the processing module 300B will be described. Figures 11(a) to 11(f) are explanatory diagrams of a method for manufacturing the processing module 300B according to the third embodiment. As shown in Figure 11(a), a printed wiring board 200B is prepared (step S21). In step S21, a semiconductor device 100 and a capacitor 400 are also prepared. Next, as shown in Figure 11(b), a solder paste P1, which is a first solder paste, a solder paste P2, which is a second solder paste, and a solder paste P3, which is a third solder paste, are supplied on the printed wiring board 200B with a gap therebetween (step S22). In the third embodiment, in step S22, the solder pastes P1 and P2 are supplied on the portion 221B exposed by the opening HB formed in the solder resist 208B with a gap therebetween. In addition, in step S22, the solder paste P3 is supplied on the land 230 of the printed wiring board 200B.

In step S22, the solder pastes P1, P2, and P3 are supplied to the printed wiring board 200B by screen printing using a metal mask 23. Note that the method of supplying the solder pastes P1, P2, and P3 is not limited to this. For example, the solder pastes P1, P2, and P3 may be supplied to the printed wiring board 200B by a dispenser.

Next, as shown in FIG. 11(c), the capacitor 400 prepared in step S21 is placed on the printed wiring board 200B so that the electrode 410 contacts the solder paste P1 and the electrode 420 contacts the solder paste P2 (step S23). This brings the lower surface 415 of the electrode 410 into contact with the solder paste P1 and the lower surface 425 of the electrode 420 into contact with the solder paste P2. There is no need to attach solder balls to the electrodes 410 and 420 of the capacitor 400 in advance.

Next, as shown in FIG. 11(d), the semiconductor device 100 prepared in step S21 is placed on the printed wiring board 200B so that the land 130E faces the electrode 410 and the land 130G faces the electrode 420 (step S24). In step S24, the semiconductor device 100 is placed on the printed wiring board 200B, so that the solder ball B, which is a ball terminal provided on the land 130S, is brought into contact with the solder paste P3. In FIG. 11(d), the upper surface 414 of the electrode 410 and the land 130E and the upper surface 424 of the electrode 420 and the land 130G are not in contact, but they may be in contact.

In this step S24, the positional relationship between the printed wiring board 200B, the capacitor 400, and the semiconductor device 100 when viewed from the Z direction is as shown in FIG. 10(b). When the capacitor 400 is placed on the printed wiring board 200B, each of the lands 130E and 130G of the semiconductor device 100 overlaps at least a portion of each of the electrodes 410 and 420 when viewed in the Z direction, and protrudes outward from the capacitor 400 in the X direction.

Next, the semiconductor device 100 and the capacitor 400 are placed on the printed wiring board 200B and are transported to a reflow furnace (not shown). Then, in step S25-1 shown in FIG. 11(e), the temperature of the atmosphere in the reflow furnace is adjusted to a temperature equal to or higher than the melting point of the solder, and the solder pastes P1, P2, P3 and the solder balls B in FIG. 11(d) are melted as shown in FIG. 11(e). When the solder paste P1 is melted, it becomes a fluid molten solder M1, and when the solder paste P2 is melted, it becomes a fluid molten solder M2. When the solder paste P3 and the solder balls B are melted, they become a fluid molten solder M3.

Following step S25-1, in step S25-2 shown in FIG. 11(f), heating is continued to cause the molten solder M1, M2 to flow. The molten solder M1, M2 creeps up the sides 411, 421 in the upward direction indicated by the arrow Z1 as shown in FIG. 11(e). The molten solder M1, M2 then moves to the upper surfaces 414, 424 as shown in FIG. 11(f). Although not shown in FIG. 11, the molten solder M1, M2 also creeps up the sides 412, 413 of the electrode 410 and the sides 422, 423 of the electrode 420 in the upward direction indicated by the arrow Z1.

The capacitor 400 is also pushed upward by the molten solders M1 and M2 toward the semiconductor device 100, narrowing the distance between the upper surface 414 of the electrode 410 and the land 130E, and narrowing the distance between the upper surface 424 of the electrode 420 and the land 130G. The molten solders M1 and M2 that reach the upper surfaces 414 and 424 come into contact with the lands 130E and 130G, wetting and spreading over the lands 130E and 130G, forming a fillet shape with a wider base as it moves from the solder resist 208B toward the lands 130E and 130G.

Then, the molten solder M1, M2 that has spread to the lands 130E, 130G is cooled and solidified. As a result, the molten solder M1 is cooled and solidified in a fillet shape on the land 130E. The molten solder M2 is cooled and solidified in a fillet shape on the land 130G. At the same time, the molten solder M3 is also cooled and solidified. As a result, the solder joints 191B, 192B, 193B are formed as shown in FIG. 9. In this manner, the processing module 300B shown in FIG. 9 is manufactured.

Then, the processing module 300B shown in FIG. 9 is stored in the housing 611 shown in FIG. 1 to manufacture the camera body of a digital camera, which is an example of an electronic device.

As described above, by melting the solder pastes P1 and P2 supplied to the printed wiring board 200B, the solder can be supplied to the lands 130E and 130G of the semiconductor device 100 via the electrodes 410 and 420 of the capacitor 400. This eliminates the need to form solder balls on the electrodes 410 and 420 of the capacitor 400 in advance, and reduces the process of manufacturing the processing module 300B. Therefore, the processing module 300B can be manufactured easily, improving the productivity of the processing module 300B.

In addition, in the third embodiment, a portion of the capacitor 400 is inserted into the opening HB, so that the height in the Z direction of the solder joints 191B, 192B, and 193B, i.e., the distance in the Z direction between the semiconductor device 100 and the printed wiring board 200B, can be narrowed. Therefore, the amount of solder in the solder joints 191B, 192B, and 193B can be reduced, and the manufacturing cost of the processing module 300B can be reduced.

Example 1
Example 1 corresponding to the first embodiment will be described. In the semiconductor device 100 shown in FIG. 3, the minimum pitch between the two adjacent solder balls B (FIG. 5(d)), which are ball terminals before bonding, was 0.4 [mm]. The material of the land 130 was Cu. The material of the solder bonding parts 191, 192, and 193 was Sn-3.0% Ag 0.5% Cu. The area S ₄₀₀ of the capacitor 400 as viewed from the Z direction shown in FIG. 4(b) was 0.4 [mm] x 0.2 [mm]. That is, the capacitor 400 was a 0402 chip component.

The thickness of the metal mask 23 shown in FIG. 5(b) used in the manufacturing process of the processing module 300 was set to 0.08 mm based on the minimum pitch of the solder balls B, which are adjacent ball terminals before bonding in the semiconductor device 100, and the size of the capacitor 400.

In steps S5-1 and S5-2 shown in FIG. 5(e) and FIG. 5(f), the peak temperature of the atmosphere in the reflow furnace was set to 230° C. or higher to melt the solder pastes P1, P2, and P3. The molten solders M1, M2, and M3 were then cooled and solidified. It was confirmed that the capacitor 400 was joined to the semiconductor device 100 by the solder joints 191 and 192. In addition, the solder joints 191 and 192 had a fillet shape on the lands 130E and 130G.

The following was confirmed by observation of the movement of the molten solders M1, M2, and M3 in steps S5-1 and S5-2. First, the solder paste P3 and the solder ball B melt together. At this time, the semiconductor device 100 moves toward the printed wiring board 200 due to the molten solder M3 that is trying to become round. On the other hand, the molten solders M1 and M2 are not in contact with the lands of the printed wiring board 200, so they move to the electrodes 410 and 420 of the capacitor 400, and reach the upper surfaces 414 and 424 by running along the side surfaces 411 and 412. The molten solders M1 and M2 raise the capacitor 400 above the surface of the solder resist 208. The amount of the rise depends on the amount of the solder pastes P1 and P2, but in Example 1, it was about 0.01 to 0.015 mm. This brings the upper surfaces 414, 424 of the capacitor 400 closer to the lands 130E, 130G. The molten solder M1, M2 that reaches the upper surfaces 414, 424 comes into contact with the lands 130E, 130G, and spreads over the lands 130E, 130G. The above movement of the molten solder M1, M2, M3 forms fillet-shaped solder joints 191, 192 on the lands 130E, 130G.

Example 2
Example 2 corresponding to the second embodiment will be described. In the semiconductor device 100 shown in FIG. 6, the minimum pitch between the two adjacent solder balls B (FIG. 8(d)), which are ball terminals before bonding, was 0.4 [mm]. The material of the land 130 was Cu. The material of the solder bonding parts 191A, 192A, and 193A was Sn-3.0% Ag 0.5% Cu. The area S ₄₀₀ of the capacitor 400 as viewed from the Z direction shown in FIG. 7(b) was 0.4 [mm] x 0.2 [mm]. That is, the capacitor 400 was a 0402 chip component.

The size of the lands 130E, 130G in the semiconductor device 100 as viewed from the Z direction was 0.6 mm × 0.22 mm. The size of the lands 230E, 230G in the printed wiring board 200A as viewed from the Z direction was 0.5 mm × 0.2 mm. The areas S _130E , S 130G of the lands _130E , _130G were 0.132 mm ^2. The areas S 230E , S 230G of the lands _230E , _230G were 0.1 mm ^2. In this way, the relationship between the areas S 130E , S 130G of the lands 130E, _130G and the areas S 230E , S _230G of the lands _230E , 230G was S _230E , S _230G <S _130E , S _130G .

The amount of solder paste P1 and P2 was increased compared to Example 1, and the thickness of the metal mask 23 used in step S12 shown in FIG. 8(b) was set to 0.10 mm, which is thicker than 0.08 mm, in order to confirm the fillet shape.

Since the areas S 130E , S 130G of the lands _130E , _130G are larger than the areas S _230E , S 230G of the lands 230E, _230G , the molten solders M1, M2 spread to the larger lands 130E, 130G in steps S15-1, S15-2. For this reason, in the second embodiment, it was confirmed that the occurrence of side balls and the expansion of fillets are prevented in the solder joints 191A, 192A, and short circuit defects are prevented.

Example 3
Next, a description will be given of Example 3. Example 3 corresponds to the first embodiment, but is different from Example 1 in the material of the lands 130E and 130G.

The wettability of the molten solder on the lands 130E, 130G of the semiconductor device 100 is F1, and the wettability of the molten solder on the electrodes 410, 420 of the capacitor 400 is F2. In the third embodiment, the materials of the lands 130E, 130G of the semiconductor device 100 and the electrodes 410, 420 of the capacitor 400 were selected so that the relationship F1 ≧ F2 was satisfied. The wettability of the molten solder refers to the ease with which the molten solder blends.

In order for the molten solder to wet and spread over the surfaces of the electrodes 410, 420 of the capacitor 400 and the surfaces of the lands 130E, 130G of the semiconductor device 100, it is important that the molten solder and the surface of the target metal are not contaminated. The cleaner the molten solder and the metal surface are, the closer the interatomic distance between them becomes, and the molten solder wets and spreads over the metal surface so as to adhere to the metal surface. For this reason, the lands 130E, 130G of the semiconductor device 100 are plated with Au, which is resistant to oxidation. In addition, the electrodes 410, 420 of the capacitor 400 are plated with Sn, which is easily oxidized and has a low reduction rate.

The thickness of the metal mask 23 shown in FIG. 5(b) was set to 0.05 mm. The supply amounts of the solder pastes P1, P2, and P3 were set to be smaller than those in Example 1. The sizes of the semiconductor device 100 and the capacitor 400 were the same as those in Example 1.

In steps S5-1 and S5-2 in FIG. 5(e) and FIG. 5(f), it was confirmed that the molten solder M1 and M2 migrate from the Sn-plated electrodes 410 and 420 to the lands 130E and 130G, which are plated with Au, which has high wettability. This confirmed that the capacitor 400 was well joined to the semiconductor device 100 by the solder joints 191 and 192.

(Inductance calculation)
Next, the inductance of the wiring between the semiconductor element and the capacitor was calculated for Example 1, Example 2, and Comparative Example 1. Fig. 12(a) is a schematic cross-sectional view of the processing module 300 of Example 1. Fig. 12(b) is a schematic cross-sectional view of the processing module 300A of Example 2. Fig. 12(c) is a schematic cross-sectional view of the processing module 300X of Comparative Example 1.

The processing module 300X of Comparative Example 1 shown in FIG. 12(c) has a semiconductor device 100, a capacitor 400, and a printed wiring board 200X. The semiconductor device 100 has a semiconductor element 101 and a package substrate 102. The semiconductor element 101 is mounted on the package substrate 102. The package substrate 102 includes a land 130E and a land 130G.

The printed wiring board 200 has an insulating substrate 220X. The insulating substrate 220X has one main surface and another main surface opposite the one main surface. Lands 230EX and 230GX are arranged on one main surface of the insulating substrate 220X. Lands 130E and 230EX are joined by solder joints 191X. Lands 130G and 230GX are joined by solder joints 192X.

The capacitor 400 is disposed on the other main surface of the insulating substrate 220X of the printed wiring board 200X. On the other main surface of the insulating substrate 220X, a land 240EX soldered to the electrode 410 of the capacitor 400 and a land 240GX soldered to the electrode 420 of the capacitor 400 are disposed. The land 230EX and the land 240EX are electrically connected by a via conductor 291X formed in the insulating substrate 220X. The land 230GX and the land 240GX are electrically connected by a via conductor 292X formed in the insulating substrate 220X.

The calculation conditions are as follows. The pitch between two adjacent ball terminals in the semiconductor device 100, which is a BGA semiconductor package, was set to 0.4 mm. The thickness of the package substrate 102 was set to 0.4 mm. The height and width of the solder joints 193, 193A, 191X, and 192X were set to 0.220 mm and 0.250 mm, respectively. The capacitor 400 was a 0402 size chip capacitor. The thickness of the printed wiring boards 200, 200A, and 200X was set to 0.8 mm. The inductance was calculated using the formula for inductance in a parallel conductor.

Calculation results of Example 1 shown in FIG. 12(a) will be described. The inductance value of each of the via conductors 112E and 112G in the package substrate 102 was 266 pH. The inductance value between the electrode 410 and the land 130E in the capacitor 400, and the inductance value between the electrode 420 and the land 130G in the capacitor 400 were each 180 pH. Therefore, the inductance value between the power terminal 111E of the semiconductor element 101 and the electrode 410 of the capacitor 400, and the inductance value between the ground terminal 111G of the semiconductor element 101 and the electrode 420 of the capacitor 400 were each 466 pH. The calculation results of Example 2 shown in FIG. 12(b) were similar to those of Example 1.

The calculation results of Comparative Example 1 shown in FIG. 12(c) will be described. The inductance value of each of the via conductors 112E and 112G in the package substrate 102 was 266 pH. The inductance value of each of the solder joints 191X and 192X was 42 pH. The inductance value of each of the via conductors 291X and 292X in the printed wiring board 200X was 545 pH. The inductance value between the electrode 410 and the land 240EX in the capacitor 400, and the inductance value between the electrode 420 and the land 240GX in the capacitor 400 were each 180 pH. Therefore, the inductance value between the power terminal 111E of the semiconductor element 101 and the electrode 410 of the capacitor 400, and the inductance value between the ground terminal 111G of the semiconductor element 101 and the electrode 420 of the capacitor 400 were each 1033 pH.

Figure 13 shows the calculation results of the inductance in Example 1, Example 2, and Comparative Example 1. As shown in Figure 13, in Examples 1 and 2, the inductance value is smaller than that in Comparative Example 1. This reduces the generated power supply noise, and enables the semiconductor device 100 to achieve high-speed communication. In Example 2, as shown in Figure 12 (b), the semiconductor device 100 and the printed wiring board 200A are connected by the solder joints 191A and 192A via the capacitor 400. This allows power to be supplied to the semiconductor element 101 via the solder joints 191A and 192A. Therefore, the land 130S can be used for purposes other than the power supply line, increasing the freedom of circuit design.

As a result, it is possible to manufacture a processing module that achieves faster communication speeds without adding any manufacturing processes.

The present invention is not limited to the embodiments described above, and many variations are possible within the technical concept of the present invention. Furthermore, the effects described in the embodiments are merely a list of the most favorable effects resulting from the present invention, and the effects of the present invention are not limited to those described in the embodiments.

In the above embodiment, the electronic component is a capacitor 400, but this is not limited to the above. The electronic component may be a passive component such as a resistor or an inductor.

In the above embodiment, the semiconductor device 100 is prepared with the solder balls B provided on the lands 230S in advance, but this is not limited to the above. In other words, the solder balls S may be provided on the lands 230S in the process of preparing the semiconductor device 100.

100...semiconductor device, 130E...land (first land), 130G...land (second land), 200...printed wiring board, 300...processing module (semiconductor module), 400...capacitor (electronic component), 410...electrode (first electrode), 420...electrode (second electrode)

Claims (18)

A chip component including a first electrode and a second electrode arranged at an interval in a predetermined direction, a semiconductor device including a first land and a second land, and a printed wiring board are provided;
Supplying a first solder paste and a second solder paste to the printed wiring board at an interval;
placing the chip component on the printed wiring board such that the first electrode contacts the first solder paste and the second electrode contacts the second solder paste;
placing the semiconductor device on the printed wiring board such that the first land faces the first electrode and the second land faces the second electrode;
heating the first solder paste and the second solder paste to melt them;
The molten solder that has spread is solidified , thereby joining the first land and the first electrode with solder, and joining the second land and the second electrode with solder,
the first solder paste is melted and solidified, and the solder has a fillet shape that continuously expands outward in the predetermined direction from a position of the first electrode in contact with the printed wiring board toward the first land,
the second solder paste is melted and solidified, and the solder has a fillet shape that continuously expands outward in the predetermined direction from a position of the second electrode in contact with the printed wiring board toward the second land;
A method for manufacturing a semiconductor module comprising the steps of: The printed wiring board includes an insulating substrate and a solder resist disposed on a main surface of the insulating substrate,
the first solder paste and the second solder paste are provided on the solder resist;
2. The method for manufacturing a semiconductor module according to claim 1 . the printed wiring board has an insulating substrate and a third land and a fourth land arranged on a main surface of the insulating substrate,
the first solder paste is provided on the third land, and the second solder paste is provided on the fourth land ;
When the molten solder is solidified, the first land is joined to the first electrode and the first land by soldering, and the second land is joined to the second electrode and the second land by soldering .
3. The method for manufacturing a semiconductor module according to claim 1 or 2 . In a plan view, an area of the first land is larger than an area of the third land, and an area of the second land is larger than an area of the fourth land.
4. The method for manufacturing a semiconductor module according to claim 3 . The printed wiring board includes an insulating substrate and a solder resist disposed on a main surface of the insulating substrate,
the solder resist has an opening that exposes a portion of a main surface of the insulating substrate;
the first solder paste and the second solder paste are supplied to a portion of the main surface of the insulating substrate that is exposed by the opening;
2. The method for manufacturing a semiconductor module according to claim 1 . the semiconductor device has a fifth land on which a solder ball is provided, and the printed wiring board has a sixth land;
supplying a third solder paste onto the sixth land when supplying the first solder paste and the second solder paste to the printed wiring board;
placing the semiconductor device on the printed wiring board to bring the solder balls into contact with the third solder paste;
heating and melting the third solder paste and the solder balls together with the first solder paste and the second solder paste;
When the molten solder is solidified , the first land and the first electrode are joined by solder, the second land and the second electrode are joined by solder, and the fifth land and the sixth land are joined by solder.
6. The method for manufacturing a semiconductor module according to claim 1, The semiconductor device is a BGA semiconductor package.
7. The method for manufacturing a semiconductor module according to claim 1, A method for manufacturing an electronic device, comprising:
The semiconductor module is manufactured by the manufacturing method according to any one of claims 1 to 7 ,
disposing the semiconductor module inside a housing;
2. A method for manufacturing an electronic device comprising the steps of: A printed wiring board;
a semiconductor device including a first land and a second land and mounted on the printed wiring board;
a chip component including a first electrode and a second electrode spaced apart in a predetermined direction, the chip component being disposed between the printed wiring board and the semiconductor device;
a first solder joint portion that joins the first electrode and the first land;
a second solder joint portion that joins the second electrode and the second land,
The printed wiring board includes an insulating substrate and a solder resist disposed on a main surface of the insulating substrate,
the chip component faces the solder resist,
In a plan view, each of the first land and the second land overlaps with at least a portion of the first electrode and the second electrode, and protrudes outward from the chip component in the predetermined direction,
the first solder joint portion has a fillet shape that continuously expands outward from the first electrode in the predetermined direction as the first solder joint portion extends from the solder resist toward the first land,
the second solder joint portion has a fillet shape that continuously expands outward from the second electrode in the predetermined direction as it moves from the solder resist toward the second land;
A semiconductor module comprising: A printed wiring board;
a semiconductor device including a first land and a second land and mounted on the printed wiring board;
a chip component including a first electrode and a second electrode spaced apart in a predetermined direction, the chip component being disposed between the printed wiring board and the semiconductor device;
a first solder joint portion that joins the first electrode and the first land;
a second solder joint portion that joins the second electrode and the second land,
the printed wiring board has an insulating substrate, a third land arranged on a main surface of the insulating substrate and electrically connected to the first land at the first solder joint, and a fourth land arranged on the main surface of the insulating substrate and electrically connected to the second land at the second solder joint,
In a plan view, each of the first land and the second land overlaps with at least a portion of each of the first electrode and the second electrode, and also overlaps with at least a portion of each of the third land and the fourth land, and protrudes outward from the chip component in the predetermined direction, and the first solder joint portion has a fillet shape that continuously expands outward from the first electrode in the predetermined direction as it moves from the third land to the first land,
the second solder joint portion has a fillet shape that continuously expands outward from the second electrode in the predetermined direction as it moves from the fourth land to the second land;
A semiconductor module comprising: A printed wiring board;
a semiconductor device including a first land and a second land and mounted on the printed wiring board;
a chip component including a first electrode and a second electrode spaced apart in a predetermined direction, the chip component being disposed between the printed wiring board and the semiconductor device;
a first solder joint portion that joins the first electrode and the first land;
a second solder joint portion that joins the second electrode and the second land,
The printed wiring board includes an insulating substrate and a solder resist disposed on a main surface of the insulating substrate,
the solder resist has an opening into which a part of the chip component is inserted,
In a plan view, each of the first land and the second land overlaps with at least a portion of the first electrode and the second electrode, and protrudes outward from the chip component in the predetermined direction,
the first solder joint portion has a fillet shape that continuously expands outward from the first electrode in the predetermined direction from a portion of the main surface of the insulating substrate that is exposed by the opening of the solder resist toward the first land,
the second solder joint portion has a fillet shape that continuously expands outward from the second electrode in the predetermined direction from a portion of the main surface of the insulating substrate that is exposed by the opening of the solder resist toward the second land,
A semiconductor module comprising: The first land is a power terminal, and the second land is a ground terminal.
12. The semiconductor module according to claim 9 , wherein the semiconductor module is a semiconductor device. The chip components are chip components having a size of 0402 or less.
13. The semiconductor module according to claim 9 , wherein the semiconductor module is a semiconductor device. 14. The semiconductor module according to claim 9 , wherein the chip component is a capacitor. The semiconductor device is a BGA semiconductor package in which the spacing between lands is 0.4 mm or less.
15. The semiconductor module according to claim 9 , wherein the semiconductor module is a semiconductor device. The semiconductor device includes a semiconductor element,
When the semiconductor module is viewed in a plan view, the semiconductor element and the chip component overlap each other.
16. The semiconductor module according to claim 9 , wherein the semiconductor module is a semiconductor device. the semiconductor device includes a fifth land,
the printed wiring board has a sixth land on a main surface of the insulating substrate,
a third solder joint portion that joins the fifth land and the sixth land,
The height of the third solder joint is greater than the height of the chip component.
17. The semiconductor module according to claim 9 , wherein the semiconductor module is a semiconductor device. A housing and
and the semiconductor module according to any one of claims 9 to 17 , disposed inside the housing.
1. An electronic device comprising:

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