JP7593239B2 - Inverter output voltage detection device - Google Patents

Description

The present invention relates to a method for detecting the output voltage of an inverter, particularly a high-voltage inverter.

In a multi-cell high-voltage inverter, the output voltage may be detected to improve control performance, as described in Patent Document 1, for example. A voltage transformer is generally used as a means for detecting the inverter output voltage, which is a high voltage, and inputting it into the control device.

In addition, there is a technique that can detect the inverter output voltage over a wide band from DC to the carrier frequency, such as the method described in FIG. 2 of Patent Document 2 and Patent Document 3, which uses an isolated A/D converter.

Patent No. 3892804 JP 2015-049104 A JP 2017-225210 A

However, the method described in Patent Document 1 has the problem that when the inverter output frequency significantly exceeds the rated frequency of the transformer, the characteristics of the transformer increase the error in the fundamental wave component of the voltage detection value.

In addition, in the methods of Patent Documents 2 and 3, the voltage detection section is insulated on a printed circuit board, so the withstand voltage is low and the method has not been applied to high-voltage inverters.

The present invention aims to solve the above problems, and its purpose is to improve the control performance and protection function of the device by making it possible to detect the inverter output voltage over a wide frequency range.

In order to solve the above problem, the inverter output voltage detection device according to claim 1 is
An apparatus for detecting an output voltage of an inverter, comprising:
A voltage divider circuit that converts the output voltage of the inverter into a low voltage and detects it;
a ΔΣ modulator that operates based on a clock signal sent from a control unit of the inverter and converts the analog voltage value detected by the voltage divider circuit into a digital bit string;
an optical transmitter that transmits the digital signal converted by the ΔΣ modulator to a control unit of the inverter by optical communication; an optical receiver that receives a clock signal sent from the control unit of the inverter by optical communication; and an optical communication unit having an optical cable connecting the optical transmitter and the optical receiver to the control unit of the inverter;
a decimation filter provided in the control unit of the inverter, receiving as input the digital bit string transmitted from the ΔΣ modulator via the optical communication unit, and simultaneously removing the quantization noise and switching frequency components of the ΔΣ modulator contained in the digital bit string in synchronization with a switching period of the inverter;
The inverter is characterized by comprising a phase selection unit that selects whether the clock signal sent from the inverter control unit to the ΔΣ modulator is in phase or inverted in phase with respect to the clock used in the decimation filter.

The output voltage detection device for an inverter according to claim 2 is the same as the output voltage detection device according to claim 1,
The phase selection unit is characterized by comprising a time difference measurement circuit that measures the time difference between the rising time of a digital bit string transmitted from the ΔΣ modulator via an optical communication unit and the rising time of a clock used in the decimation filter, and a phase selection circuit that selects the phase based on the time difference measured by the time difference measurement circuit.

(1) According to the invention described in claims 1 and 2, the inverter output voltage value can be obtained over a wide frequency range from DC to the carrier frequency, and a higher voltage resistance can be achieved than the conventional method using an isolated A/D converter. In addition, since the phase of the clock signal sent to the ΔΣ modulator can be selected, stable operation is possible even when there is a communication delay.

(2) According to the invention described in claim 2, the phase of the clock signal sent to the ΔΣ modulator can be automatically selected to an appropriate clock phase depending on the amount of communication delay, eliminating the need for adjustment.

1 is a configuration diagram of an output voltage detection device according to a first embodiment of the present invention. FIG. 4 is a configuration diagram of a decimation filter used in the first embodiment of the present invention. FIG. 3 is a diagram illustrating the time response of the decimation filter of FIG. 2 . FIG. 11 is a circuit diagram of a clock phase selection circuit mounted in a second embodiment of the present invention. 5 is a timing chart of the clock phase selection circuit of FIG. 4 .

The following describes an embodiment of the present invention with reference to the drawings, but the present invention is not limited to the following embodiment.

Figure 1 shows the hardware configuration of the first embodiment. In Figure 1, 1 is an inverter that drives a motor (three-phase motor M) 2 as a load. This inverter 1 is composed of, for example, a cell-multiplexed high-voltage inverter, and the semiconductor elements that make up the main circuit of the inverter are switched and controlled by a PWM signal created by a control unit (not shown), and three-phase output voltages Vu, Vv, and Vw are applied to the motor 2. The control unit in the inverter 1 is provided with a decimation filter, which will be described later.

A voltage divider circuit 3 equipped with resistors 3a to 3i is connected between the three-phase circuit connecting the inverter 1 and the motor 2 and the ground. In the voltage divider circuit 3, resistors 3a to 3c convert the U-phase output voltage Vu of the inverter 1 to a low voltage for detection, resistors 3d to 3f convert the V-phase output voltage Vv of the inverter 1 to a low voltage for detection, and resistors 3g to 3i convert the W-phase output voltage Vw of the inverter 1 to a low voltage for detection.

The voltage detected by the voltage divider circuit 3 is input to the ΔΣ modulators (1-bit ADC) 12u, 12v, and 12w via the differential amplifiers 11u, 11v, and 11w in the voltage detection circuit 4.

The ΔΣ modulators 12u, 12v, and 12w convert the analog voltage values of each of the three phases, which are the outputs of the differential amplifiers 11u, 11v, and 11w, into digital values (bit strings) based on the clock signal CLK sent from the control unit in the inverter 1 via the optical cable 13c and received by the optical receiver 14 (optical RX).

The digital signals converted by the ΔΣ modulators 12u, 12v, and 12w are transmitted to the control unit in the inverter 1 via the optical transmitters 15u, 15v, and 15w (optical TX) and the optical cables 13u, 13v, and 13w.

The optical cables 13c, 13u, 13v, and 13w, the optical receiver 14, and the optical transmitters 15u, 15v, and 15w constitute the optical communication section.

As shown in FIG. 1, in the voltage detection circuit 4, the ΔΣ modulators 12u, 12v, and 12w are operated based on the clock signal CLK sent from the inverter 1, and each phase voltage is converted into a digital value (bit string) and transmitted to the control unit of the inverter 1.

By using optical cables 13c, 13u, 13v, and 13w for communication between the voltage detection circuit 4 and the inverter 1, insulation between the circuits has been achieved with a higher voltage resistance than in the prior art. Since a common clock is used with the decimation filter implemented on the inverter 1 side, it is necessary to send a clock signal CLK from the inverter 1 to the voltage detection circuit 4.

2 shows the configuration of the decimation filter used on the inverter side of Example 1. This filter is called a sinc filter, and is configured by cascading an integrator 20 that operates at a common clock frequency (F _ADC ) with the ΔΣ modulators (1-bit ADCs) 12u, 12v, and 12w, and a differentiator 30 that operates at twice the equivalent switching frequency (F _PWM ) of the inverter.

The accumulator 20 adds the previous value delayed by the delay unit 21 to the bit strings of the ΔΣ modulators 12u, 12v, and 12w sent via the optical transmitters 15u, 15v, and 15w and optical cables 13u, 13v, and 13w in FIG. 1 in the adder 22.

The differentiator 30 subtracts the value, which is the output of the integrator 20 delayed by delay units 31 and 32, from the output of the integrator 20 in a subtractor 33. The output of the differentiator 30 (Output To CPU) is input to the CPU circuit (not shown) of the control unit, and the CPU circuit controls the inverter 1 based on this input value.

The integrator 20 and differentiator 30 configuration allows the sum (moving average x interval width) of the bit strings sent from the ΔΣ modulators 12u, 12v, and 12w over the equivalent switching period to be obtained for each half period of the equivalent switching period. This filter simultaneously removes the quantization noise contained in the bit strings and the switching components of the inverter 1.

Due to delays in optical communication between the ΔΣ modulators 12u, 12v, and 12w and the inverter 1, the phase of the transmitted bit string may lag significantly behind the clock of the decimation filter. As a result, if the edge of the bit string transmitted from the ΔΣ modulators 12u, 12v, and 12w overlaps with the rising edge of the clock, the integrator 20 will not operate normally and voltage detection will become impossible.

As a countermeasure to this problem, in this embodiment 1, it is made possible to select whether the clock (Clock To ADC) sent from the inverter 1 to the ΔΣ modulators 12u, 12v, and 12w of the voltage detection circuit 4 in Figure 1 is in phase with the clock (F _ADC ) input to the integrator 20 or is delayed by 180 degrees.

That is, an XOR gate (exclusive OR) 40 is provided which takes the exclusive OR of a Select signal which is input to one input terminal and selects in-phase or 180 degree delay, and a clock signal F _ADC (which has a common clock frequency with the ΔΣ modulator) used in the decimation filter which is input to the other input terminal, and the output of the XOR gate 40 is used as the clock (Clock To ADC) which is sent to the ΔΣ modulators 12u, 12v, and 12w in Figure 1. The XOR gate 40 constitutes the phase selection unit of the present invention.

With the configuration in Figure 2, when the Select signal is 0, a clock with the same phase is sent to the ΔΣ modulators 12u, 12v, and 12w in Figure 1, and when the Select signal is 1, a clock with a 180 degree delay is sent. By selecting a clock with an appropriate phase depending on the amount of communication delay between the inverter 1 and the voltage detection circuit 4, stable operation is possible even when there is a delay. In a high-voltage inverter, the wiring is not changed except in the event of a unit failure, and the amount of delay is constant, so the value of the Select signal can be adjusted manually when the product is shipped.

Figure 3 shows the waveforms of inverter 1's phase voltage command (L1), phase voltage output (L2), and phase voltage detection (L3) (voltage conversion of the theoretical filter output value in Figure 2 above) superimposed on the time axis. V_dc is the DC voltage for one cell stage in the multi-cell high-voltage inverter. As can be seen from Figure 3, the phase voltage detection value (L3) does not contain a switching component, and its phase lags behind the phase voltage command value (L1) by half a switching cycle.

As described above, according to the first embodiment, the output voltage of the high-voltage inverter can be detected without using a transformer or the like, and therefore the output voltage value can be obtained over a wide frequency range from DC to the carrier frequency. In addition, since the insulation is performed by the optical cable, a higher voltage resistance can be achieved than the conventional method using an isolated A/D converter. Furthermore, by synchronizing the operation of the decimation filter with the switching period of the inverter, the switching frequency component can be removed from the detection value. Furthermore, since the phase of the clock sent to the ΔΣ modulator (A/D converter) can be selected, stable operation is possible even when there is a large communication delay.

In the first embodiment, the clock phase was selected by a manually adjusted (set) Select signal, but in the second embodiment, the clock phase is configured to be selected automatically.

Figure 4 shows the clock phase selection circuit constituting the phase selection unit in the second embodiment. The clock phase selection circuit in Figure 4 has an element (time difference measurement circuit) that measures the time difference between the edge (rising time) of the bit string signal (DATA) sent from the ΔΣ modulators 12u, 12v, and 12w and the rising time of the clock CLK used in the decimation filter, and an element (phase selection circuit) that switches the clock phase selection signal (SELECT) depending on the magnitude of the edge (rising time).

In Figure 4, 51 is an edge detector that detects the rising edge of the clock CLK (F _ADC ) used in the decimation filter of Figure 2, and 52 is an edge detector that detects the rising edge of the bit string signal DATA sent from the ΔΣ modulators 12u, 12v, and 12w of Figure 1 and obtains a pulse (2) corresponding to the rising edge.

The logical product of the output of edge detector 51 and the clock CLK is taken by AND gate 53, and a pulse (1) corresponding to the rising edge of CLK is obtained at the output side.

The obtained pulses (1) and (2) are input to an SR latch circuit 55 to obtain a pulse (3) whose width is proportional to the time difference between the edges of the CLK and DATA. However, since it is prohibited for both inputs of the SR latch circuit 55 to be 1 at the same time, a circuit (54) is inserted so that when the input terminal "R" is 1, "S" is always 0.

That is, a pulse (1) is input to the inverting input terminal of AND gate 54 with inverting input terminal, and a pulse (2) is input to the non-inverting input terminal, and the output of AND gate 54 with inverting input terminal is input to set terminal S of SR latch circuit 55. The edge detector 51 to SR latch circuit 55 constitute the time difference measurement circuit of the present invention.

The pulse (3) obtained at the Q output of the SR latch circuit 55 is integrated by the integrator 56 to obtain a signal (4) that converts the time difference (3) between the edges into a voltage.

The signal (4) obtained by converting the time difference between these edges into a voltage is compared in comparator 57 with a reference value (0.5clk-Th) set by subtracting the integrator hold time Th from half the clock period.

When the comparison output signal (5) of the comparator 57 is 0 at the rising edge of the clock CLK, the bit string signal DATA sent to the decimation filter overlaps with the rising edge of the clock CLK, so the phase of the clock sent to the ΔΣ modulators 12u, 12v, and 12w of the voltage detection circuit 4 is shifted by 180 degrees from the one currently selected by the subsequent circuits. However, in order to prevent the phase from switching at undesirable times, such as when the inverter is operating, the selected phase is fixed when the HOLD signal is 1.

That is, for example, a HOLD signal that becomes 1 at undesirable times such as when the inverter is operating is input to one input terminal of a NOR gate (negative OR circuit) 58, the comparison output signal (5) of the comparator 57 is input to the other input terminal of the NOR gate 58, the clock CLK is input to the clock terminal of a D-type flip-flop 59, and the output of the NOR gate 58 is input to the D input terminal of the D-type flip-flop 59. When the HOLD signal becomes 0 and the phase inversion condition is met (the output of the comparator 57 becomes 0), the Q output signal (6) of the D-type flip-flop 59 becomes 1.

Then, the following circuit obtains a signal (7) that becomes 1 for only one clock when the output signal (6) becomes 1. That is, a D-type flip-flop 60 having the signal (6) input to its D input terminal and the clock CLK input to its clock terminal, and an AND gate 61 with an inverting input terminal having the output signal (6) input to its non-inverting input terminal and the Q output of the D-type flip-flop 60 input to its inverting input terminal are provided, and the signal (7) is obtained at the output terminal side of the AND gate 61 with an inverting input terminal.

When the signal (6) becomes 1, a signal (7) that becomes 1 for only one clock is input to the T input terminal of a T-type flip-flop 62, whose clock terminal receives the clock CLK.

As a result, when the phase inversion condition is met, signal (7) becomes 1, switching the SELECT signal, which is the Q output of T-type flip-flop 62, and completing the clock phase selection operation.

When the SELECT signal switches, the clock sent to the ΔΣ modulators 12u, 12v, and 12w is delayed by 180 degrees, so the edge of the bit string signal DATA from the ΔΣ modulators 12u, 12v, and 12w is also delayed by 180 degrees. Therefore, the phase inversion condition is no longer satisfied, and the Q output signal (6) of the D-type flip-flop 59 becomes 0.

The phase selection circuit of the second embodiment (Figure 4) may not be able to select an appropriate phase if the quality of the signals sent from the ΔΣ modulators 12u, 12v, and 12w is poor and the jitter is large. In this case, manual adjustment is preferable as in the first embodiment.

Next, a timing chart showing waveforms at each part in the circuit of Fig. 4 will be described with reference to Fig. 5. In Fig. 5, the same parts as in Fig. 4 are designated by the same reference numerals. Note that CLK in the figure is the clock (F _ADC ) used in the decimation filter, and (CLK_ADC) is the clock sent from the control unit of the inverter 1 to the ΔΣ modulators 12u, 12v, and 12w.

In FIG. 5, when the clock CLK rises, for example at time t1, the edge detector 51 and AND gate 53 generate a pulse (1) corresponding to the rising edge of the CLK.

A pulse (3) with a width proportional to the time difference between the edges is generated between, for example, time t2 when the output pulse (2) of the edge detector 52 rises and time t3 when the pulse (1) detected by the clock CLK rises.

At these times t2 and t3, the HOLD signal is 1, so the Q output signal (6) of the D-type flip-flop 59 and the output (7) of the AND gate 61 with inverting input terminal are both 0, the SELECT signal does not switch, and the clock CLK and the clock (CLK_ADC) are in phase.

In this embodiment, for example, at time t4, the HOLD signal switches to 0. At time t5, one clock CLK away from time t4, the HOLD signal is 0, the comparison output signal (5) of comparator 57 is 0, and the clock CLK input to the clock terminal of D-type flip-flop 59 is 1, so the Q output signal (6) of D-type flip-flop 59 becomes 1, and the signal (7) at the T input terminal of T-type flip-flop 62 also becomes 1.

At time t6, one clock CLK after time t5, the signal (7) at the T input terminal of T-type flip-flop 62 becomes 0, and the SELECT signal at the Q output switches to 1.

As a result, after time t6, the clock (CLK_ADC) sent to the ΔΣ modulators 12u, 12v, and 12w is delayed by 180 degrees relative to the clock CLK, and the edges of the bit string signal DATA from the ΔΣ modulators 12u, 12v, and 12w are also delayed by 180 degrees after time t7.

At time t8, when the output signal (4) of the integrator 56 exceeds the reference value (0.5clk-Th) of the comparator 57 after time t7, the output signal (5) of the comparator 57 becomes 1, and at time t9, when the clock CLK input to the D-type flip-flop 59 next rises, the Q output signal (6) of the D-type flip-flop 59 becomes 0.

At time t10 after time t9, when the output signal (4) becomes equal to or lower than the reference value of comparator 57, the output signal (5) of comparator 57 becomes 0.

In this embodiment, for example, the HOLD signal is switched to 1 at time t11.

As described above, according to the second embodiment, in addition to the effect of the first embodiment, the phase of the clock signal sent to the ΔΣ modulators 12u, 12v, and 12w can be automatically selected to an appropriate phase clock depending on the amount of communication delay, thereby eliminating the need for adjustment.

1... inverter 2... motor 3... voltage divider circuit 4... voltage detection circuit 11u, 11v, 11w... differential amplifier 12u, 12v, 12w... delta-sigma modulator 13c, 13u, 13v, 13w... optical cable 14... optical receiver 15u, 15v, 15w... optical transmitter 20... integrator 21, 31, 32... delay section 22... adder 30... differentiator 33... subtractor 40... XOR gate 51, 52... edge detector 53... AND gate 54, 61... AND gate with inverted input terminal 55... SR latch circuit 56... integrator 57... comparator 58... NOR gate 59, 60... D-type flip-flop 62... T-type flip-flop

Claims (2)

An apparatus for detecting an output voltage of an inverter, comprising:
A voltage divider circuit that converts the output voltage of the inverter into a low voltage and detects it;
a ΔΣ modulator that operates based on a clock signal sent from a control unit of the inverter and converts the analog voltage value detected by the voltage divider circuit into a digital bit string;
an optical transmitter that transmits the digital signal converted by the ΔΣ modulator to a control unit of the inverter by optical communication; an optical receiver that receives a clock signal sent from the control unit of the inverter by optical communication; and an optical communication unit having an optical cable connecting the optical transmitter and the optical receiver to the control unit of the inverter;
a decimation filter provided in the control unit of the inverter, receiving as input the digital bit string transmitted from the ΔΣ modulator via the optical communication unit, and simultaneously removing the quantization noise and switching frequency components of the ΔΣ modulator contained in the digital bit string in synchronization with a switching period of the inverter;
a phase selection unit that selects whether a clock signal sent from the inverter control unit to the ΔΣ modulator is in phase with or inverted from a clock used in the decimation filter;
An inverter output voltage detection device comprising: The inverter output voltage detection device according to claim 1, characterized in that the phase selection unit includes a time difference measurement circuit that measures the time difference between the rising edge of the digital bit string transmitted from the ΔΣ modulator via the optical communication unit and the rising edge of the clock used in the decimation filter, and a phase selection circuit that selects the phase according to the time difference measured by the time difference measurement circuit.

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