JP7595166B2 - POWER CONVERSION APPARATUS AND METHOD FOR CONTROLLING POWER CONVERSION APPARATUS - Google Patents

Description

The present invention relates to a power conversion device that converts DC power to AC power or AC power to DC power using semiconductor switching elements, and a control method thereof.

So-called power conversion devices, which use semiconductor switching elements to convert DC power to AC power or AC power to DC power, often form a bridge circuit in which two semiconductor switching elements, one above and one below, are connected in series to a DC power source, and the number of circuits connected in parallel corresponds to the number of load phases, with the junction point between the upper and lower semiconductor switching elements connected to the load.

As an example of a typical bridge circuit, a two-level circuit will be taken. There are two output potentials for each phase: DC power supply voltage Ed and 0. When the upper semiconductor switching element is on and the lower semiconductor switching element is off, the output potential is Ed, and when the lower semiconductor switching element is on and the upper semiconductor switching element is off, the output potential is 0.

At this time, if the upper and lower semiconductor switching elements are turned on at the same time, the internal impedance of the semiconductor switching elements is extremely small compared to the load, so almost no current flows in the load and a huge short-circuit current flows through the upper and lower semiconductor switching elements, resulting in the destruction of the semiconductor switching elements.

To avoid such short circuit breakdown, a period is provided during which both the upper and lower semiconductor switching elements are off while one of the upper and lower semiconductor switching elements transitions from its on state to its on state. This off period is called the "non-overlapping period" because the on states of the upper and lower semiconductor switching elements do not "overlap."

The operation of the power conversion device during the non-overlap period is explained using the figures. Figures 5 to 8 show the operating waveforms during the non-overlap period, taking only one phase (U-phase) of the power conversion device.

Both Figures 5 and 6 show the waveforms of the gate signals Gpu and Gnu, the applied voltages Epu and Enu to each element, and the output potential vu from when the U-phase upper semiconductor switching element Spu is on, through the non-overlapping period when both the upper and lower semiconductor switching elements are off, until the U-phase lower semiconductor switching element Snu is on. In Figure 5, the load current iu>0, and the output potential vu=0 during the non-overlapping period. In Figure 6, the load current iu<0, and the output potential vu=Ed during the non-overlapping period.

On the other hand, both Figures 7 and 8 show the waveforms of the gate signals Gpu and Gnu, the applied voltages Epu and Enu to each element, and the output potential vu from when the U-phase lower semiconductor switching element Snu is on, through the non-overlapping period when both the upper and lower semiconductor switching elements are off, until the U-phase upper semiconductor switching element Spu is on. In Figure 7, the load current iu>0, and the output potential during the non-overlapping period is vu=0. In Figure 8, the load current iu<0, and the output potential during the non-overlapping period is vu=Ed.

From the above, it can be seen that the output potential vu during the non-overlap period is determined by the polarity of the load current iu, and the output potential of the power conversion device during the non-overlap period is unstable. Therefore, in order to increase the output voltage accuracy of the power conversion device, it is preferable to make the period during which the output potential is unstable, i.e., the non-overlap period, as short as possible.

However, semiconductor switching elements operate with a slight delay after the gate signal is applied, and the turn-on delay and turn-off delay are generally different. In addition, these delay times fluctuate and vary depending on the applied voltage, current flow, operating temperature, and individual differences in the semiconductor switching elements. Therefore, it is necessary to set the non-overlap period by ensuring a sufficient margin for these fluctuations and variations.

Technologies for ensuring an appropriate non-overlapping period depending on the situation are known, such as those described in Patent Document 1 or Patent Document 2.

In addition, the technology described in Patent Document 3 or Patent Document 4 is known as a technology for predicting the polarity of the load current during the non-overlap period to predict the output potential and perform voltage compensation based on this predicted value of the output potential (generally referred to as "non-overlap compensation").

JP 2010-142074 A JP 2017-93073 A Japanese Patent Application Publication No. 64-60264 Japanese Patent Application Publication No. 6-62580

The technologies described in Patent Documents 1 and 2 improve the output voltage accuracy by shortening the period during which the output potential is unstable by keeping the non-overlapping period as short as possible depending on the operating conditions of the semiconductor switching element, the applied voltage, the flow current, the operating temperature, etc. However, it is not possible to eliminate the non-overlapping period itself, and there is a limit to how much the output voltage accuracy can be improved.

The technology described in Patent Document 3 and Patent Document 4 estimates the output potential during the non-overlap period according to the current polarity and compensates for this to improve the output voltage accuracy. However, semiconductor switching elements operate with a slight delay from the application of the gate signal, and the turn-on delay and turn-off delay are generally different. In addition, these delay times fluctuate and vary depending on the applied voltage, current flow, operating temperature, and individual differences in semiconductor switching elements, so the amount of compensation may be insufficient or excessive.

Therefore, the present invention aims to provide a technology that improves the accuracy of the output voltage of a power conversion device against fluctuations in delay time due to the magnitude of the current flowing through it, which is the most dominant factor in delays when turning on and off a semiconductor switching element.

In order to solve the above-mentioned problems, one representative power conversion device according to the present invention includes a power conversion unit constituted by semiconductor elements and converts DC power to AC power or converts AC power to DC power, a current control unit that controls the AC current of the power conversion unit based on a DC current detection value obtained by converting a current detection value of the power conversion unit using a fundamental wave phase of the power conversion unit obtained based on a DC current command value for the power conversion unit and a drive frequency of the power conversion unit, and a drive control unit that corrects the voltage command value generated based on an output of the current control unit and generates a gate signal for driving the semiconductor element using the corrected voltage command value, wherein the drive control unit generates a fundamental wave phase of the next cycle of the power conversion unit by adding an increment of the fundamental wave phase obtained from the product of the drive frequency and a sampling period when PWM controlling the power conversion unit to the fundamental wave phase , calculates an AC current command value based on the DC current command value and the fundamental wave phase of the next cycle, calculates a correction amount for the voltage command value based on the AC current command value and a DC stage detection voltage of the power conversion unit, and adds the correction amount to the voltage command value to obtain a corrected voltage command value.

According to the present invention, the accuracy of the output voltage of a power conversion device can be improved by performing optimal voltage compensation according to the turn-on delay and turn-off delay caused by the current flowing through a semiconductor switching element.
Problems, configurations and effects other than those described above will become apparent from the description of the following embodiments.

1 is a diagram showing a configuration of a power conversion device according to a first embodiment of the present invention and blocks of a drive control system included therein; FIG. 4 is a diagram showing a current waveform in the first embodiment, taking a U-phase current as an example. FIG. 4 is a diagram showing a first mode of voltage compensation by the voltage compensation means of the first embodiment. FIG. 11 is a diagram showing a second mode of voltage compensation by the voltage compensation means of the first embodiment. FIG. 2 is a diagram showing an operation waveform at one point of time for one phase of the two-level inverter circuit targeted in the first embodiment. 6 is a diagram showing operational waveforms for the same phase as in FIG. 5 at the same time point when the U-phase current iu is negative. FIG. 6 is a diagram showing the operational waveforms at a different point in time for the same one phase as in FIG. 5 . 8 is a diagram showing operational waveforms for the same phase as in FIG. 7 at the same time point when the U-phase current iu is negative. FIG. 11 is a diagram showing the configuration of a power conversion device according to a second embodiment of the present invention and blocks of a drive control system included therein. FIG. 11 is a diagram showing a current waveform in the second embodiment, taking a secondary current is as a U-phase current as an example. FIG. 11 is a diagram showing a first mode of voltage compensation by a voltage compensation means of the second embodiment. FIG. 11 is a diagram showing a second mode of voltage compensation by the voltage compensation means of the second embodiment. FIG. 11 is a diagram showing operational waveforms at one point in time for one phase of a three-level converter circuit targeted in Example 2. FIG. 14 is a diagram showing operational waveforms for the same phase as in FIG. 13 at the same time point when the secondary current is negative. FIG. 11 is a diagram for explaining the definition of a turn-on operation delay time of a switching element. FIG. 11 is a diagram for explaining the definition of a turn-off operation delay time of a switching element.

Hereinafter, with reference to the drawings, examples 1 and 2 will be described as a form for carrying out the present invention. Note that the present invention is not limited to these examples. In addition, in the description of the drawings, the same parts are denoted by the same reference numerals.

FIG. 1 is a diagram showing the configuration of a power conversion device according to a first embodiment of the present invention and blocks of a drive control system included therein.
As a power conversion device, a series connection of U-phase upper semiconductor switching element 11 and U-phase lower semiconductor switching element 12, a series connection of V-phase upper semiconductor switching element 13 and V-phase lower semiconductor switching element 14, and a series connection of W-phase upper semiconductor switching element 15 and W-phase lower semiconductor switching element 16 are each connected between the lines of the DC stage via a smoothing capacitor 10 connected in parallel to a DC voltage source not shown.

In addition, the connection point between the U-phase upper semiconductor switching element 11 and the U-phase lower semiconductor switching element 12, the connection point between the V-phase upper semiconductor switching element 13 and the V-phase lower semiconductor switching element 14, and the connection point between the W-phase upper semiconductor switching element 15 and the W-phase lower semiconductor switching element 16 are connected to the U-phase terminal, V-phase terminal and W-phase terminal of the AC motor 17, respectively.

The detector is equipped with a voltage sensor (PT) 18 that detects the voltage of the smoothing capacitor 10 and a current sensor (CT) 19 that detects the output current to the AC motor 17.

The drive control system block consists of the following components:
An A/D converter 20 that quantizes the U/V/W phase currents (detected values) iu, iv, and iw detected by the current sensor (CT) 19
An A/D converter 36 that quantizes the DC stage voltage (detected value) Ed detected by the voltage sensor (PT) 18
An integrator 23 that integrates the fundamental wave angular frequency ω that drives the AC motor 17 to obtain the fundamental wave phase θ
Rotating coordinate conversion means 21 for determining d-axis and q-axis currents (detected values) Id and Iq using the fundamental wave phase θ from the output of the A/D converter 20
Subtractors 25 and 26 that calculate the difference between the given d/q axis current commands Id* and Iq* and the d/q axis currents (detected values) Id and Iq
A current control means (ACR) 27 that uses the outputs (deviations) of the subtractors 25 and 26 to output a manipulated variable that makes the deviation zero
A voltage vector generating means 28 that determines d-axis/q-axis voltage command values Vd* and Vq* using the output of the current control means (ACR) 27.
A multiplier 22 that obtains the increment Δθ of the fundamental wave phase from the product of the fundamental wave angular frequency ω and the sampling period Tc.
An adder 24 for calculating the fundamental wave phase θ' of the next cycle from the sum of the increment Δθ of the fundamental wave phase and the fundamental wave phase θ
A stationary coordinate conversion means 29 for determining U/V/W phase voltage command values vu*, vv* and vw* using the fundamental wave phase θ' of the next cycle from the d/q axis voltage command values Vd* and Vq*
A stationary coordinate conversion means 40 for determining U/V/W phase current command values iu*, iv* and iw* using the fundamental wave phase θ' of the next cycle from the given d/q axis current commands Id* and Iq*
Voltage compensation means 41, 42 and 43 for determining U/V/W phase voltage compensation amounts Δvu, Δvv and Δvw using U/V/W phase current command values iu*, iv* and iw* and the output of the A/D converter 26
Adders 30, 31 and 32 that add U/V/W phase voltage compensation amounts Δvu, Δvv and Δvw to the U/V/W phase voltage command values vu*, vv* and vw*.
PWM generation means 33, 34 and 35 for outputting gate signals Gpu, Gnu, Gpv, Gnv, Gpw and Gnw for driving the semiconductor switching elements 11 to 16 using the U/V/W phase voltage compensated command values vu**, vv** and vw** which are the outputs of the adders 30, 31 and 32 and the output of the A/D converter 36.

FIG. 2 is a diagram showing a current waveform in the first embodiment, taking a U-phase current as an example.
2, it can be seen that the U-phase current command value iu* is read ahead by the increment Δθ of the fundamental wave phase with respect to the U-phase current iu. This is because the operation delay time of the semiconductor switching element has current dependency, and the voltage compensation amount to compensate for this naturally also has current dependency, so if the current detection value is used, a current error occurs by the product of the current change rate di/dt and the sampling period Tc, Tc×di/dt.

In Example 1, the phase θ rather than time t is taken as the reference axis, and by utilizing the fact that the frequency of the U-phase current (fundamental wave angular frequency ω) is known, Δθ = ω · Tc is set, and the phase delay of the sampling period Tc is compensated for.

As a result, in Example 1, the U/V/W phase current command values iu*, iv* and iw* at the fundamental wave phase θ' of the next cycle are predicted, and the predicted values are used to determine the voltage compensation amounts Δvu, Δvv and Δvw.

Next, the operating principle of the first embodiment will be described with reference to the drawings.
5 is a diagram showing the operation waveforms at one point in time for one phase of the two-level inverter circuit targeted in the first embodiment. Here, the U-phase portion is taken as an example, and the operation waveforms are shown when the U-phase upper semiconductor switching element Spu is turned off, and after the non-lap period Tlap has elapsed, the U-phase lower semiconductor switching element Snu is turned on. In FIG. 5, the U-phase current iu is positive. The current polarity is positive in the direction going out of the circuit.

Here, the non-overlap period Tlap is defined as the period from the falling edge of the gate signal Gpu that drives the U-phase upper semiconductor switching element Spu to the rising edge of the gate signal Gnu that drives the U-phase lower semiconductor switching element Snu.

At this time, the U-phase upper semiconductor switching element Spu transitions to a cutoff state with a delay of the turn-off delay time Tdoff from the falling edge of the gate signal Gpu, and the DC power supply voltage Ed is applied. At the same time, the applied voltage of the U-phase lower semiconductor switching element Snu becomes 0, and current flows to the diode side of the U-phase lower semiconductor switching element Snu (upper center diagram in Figure 5).

On the other hand, when the gate signal Gnu rises, there is no change from the state before the rise and nothing happens (a transition from the center to the right in the upper diagram of Figure 5). The U-phase potential vu is equal to the applied voltage Enu of the U-phase lower semiconductor switching element Snu.

Here, we calculate the output voltage error during the non-overlapping period. The output potential during the non-overlapping period is determined by the polarity of the output current and is either the DC power supply voltage Ed or 0. However, as an expected value, we consider half of the non-overlapping period to be the DC power supply voltage Ed and the other half to be 0.

The expected value of the U-phase potential vu is considered to fall half the non-lap period from the falling edge of the gate signal Gpu, that is, (Tlap + Tdon + Tdoff)/2, which is the sum of Tlap/2 and the average value of the turn-on delay time and the turn-off delay time.

However, the actual U-phase potential vu falls with a delay of the turn-off delay time Tdoff from the falling edge of the gate signal Gpu, so that the difference between the two means that it falls earlier by (Tlap + Tdon - Tdoff)/2. In other words, the output voltage is insufficient for this time.

6 is a diagram showing operational waveforms in the case where the U-phase current iu is negative at the same time point for the same phase as in FIG. 5. The definition of the non-overlap period Tlap is also the same as in FIG.
At this time, when the gate signal Gpu of the U-phase upper semiconductor switching element Spu falls, there is no change from the state before the fall and nothing happens (a transition from the left side to the center in the upper diagram of FIG. 6).

On the other hand, the U-phase lower semiconductor switching element Snu transitions to a conductive state with a delay of turn-on delay time Tdon from the rising edge of the gate signal Gnu, the applied voltage becomes 0, and a current flows through the U-phase lower switching element Snu (the diagram on the upper right side of FIG. 6). At the same time, the applied voltage to the U-phase upper semiconductor switching element Spu becomes the DC power supply voltage Ed.
The U-phase potential vu is equal to the applied voltage Enu to the U-phase lower semiconductor switching element Snu.

Here, we calculate the output voltage error during the non-overlap period. As in the case of Figure 5, the expected value of the output potential during the non-overlap period is considered to be the DC power supply voltage Ed for half of the non-overlap period and 0 for the other half.

The expected value of the U-phase potential vu is thought to fall with a delay of (Tlap + Tdon + Tdoff)/2, as in the case of Figure 5, but the actual U-phase potential vu falls with a delay of the turn-on delay time Tdon from the rising edge of the gate signal Gnu, so the net result is that it falls with a delay of (Tlap + Tdon - Tdoff)/2. In other words, the output voltage is excessive for this period of time.

Figure 7 shows the operating waveforms at a different point in time for the same phase as in Figure 5. That is, it shows the operating waveforms when the U-phase lower semiconductor switching element Snu is turned off, and after the non-lap period Tlap has elapsed, the U-phase upper semiconductor switching element Spu is turned on. In Figure 7, the U-phase current iu is positive. Note that the current polarity is positive in the direction out of the circuit.

Here, the non-overlap period Tlap is defined as the period from the falling edge of the gate signal Gnu that drives the U-phase lower semiconductor switching element Snu to the rising edge of the gate signal Gpu that drives the U-phase upper semiconductor switching element Spu.

At this time, when the gate signal Gnu of the U-phase lower semiconductor switching element Snu falls, there is no change from the state before the fall and nothing happens (transition from the left side to the center in the upper diagram of Figure 7).

On the other hand, the U-phase upper semiconductor switching element Spu transitions to a conductive state with a delay of turn-on delay time Tdon from the rising edge of the gate signal Gpu, the applied voltage becomes 0, and a current flows through the U-phase upper switching element Spu (the diagram on the upper right side of FIG. 7). At the same time, the applied voltage to the U-phase lower semiconductor switching element Snu becomes the DC power supply voltage Ed.
The U-phase potential vu is equal to the applied voltage Enu to the U-phase lower semiconductor switching element Snu.

Here, we calculate the output voltage error during the non-overlap period. As in the cases of Figures 5 and 6, the expected value of the output potential during the non-overlap period is considered to be the DC power supply voltage Ed for half of the non-overlap period and 0 for the other half.

The expected value of the U-phase potential vu is considered to rise half the non-lap period from the falling edge of the gate signal Gnu, that is, (Tlap + Tdon + Tdoff)/2, which is the sum of Tlap/2 and the average value of the turn-on delay time and the turn-off delay time.

However, the actual U-phase potential vu rises with a delay of the turn-on delay time Tdon from the rising edge of the gate signal Gpu, so the net result is that it rises with a delay of (Tlap + Tdon - Tdoff)/2. In other words, the output voltage is insufficient for this time.

8 is a diagram showing operational waveforms when the U-phase current iu is negative at the same time point for the same phase as in FIG. 7. The definition of the non-overlap period Tlap is also the same as in FIG.
At this time, the U-phase lower semiconductor switching element Snu transitions to a cutoff state with a delay of the turn-off delay time Tdoff from the falling edge of the gate signal Gnu, and the DC power supply voltage Ed is applied to it. At the same time, the applied voltage to the U-phase upper semiconductor switching element Spu becomes 0, and a current flows to the diode side of the U-phase upper semiconductor switching element Spu (the diagram in the upper center of FIG. 8).

On the other hand, when the gate signal Gpu rises, there is no change from the state before the rise and nothing happens (a transition from the center to the right in the upper diagram of Figure 5). The U-phase potential vu is equal to the applied voltage Enu of the U-phase lower semiconductor switching element Snu.

Here, we calculate the output voltage error during the non-overlap period. As in the cases of Figures 5 to 7, the expected value of the output potential during the non-overlap period is considered to be the DC power supply voltage Ed for half of the non-overlap period and 0 for the other half.

The expected value of the U-phase potential vu is thought to rise with a delay of (Tlap + Tdon + Tdoff)/2, as in the case of Figure 7, but the actual U-phase potential vu falls with a delay of the turn-off delay time Tdoff from the falling edge of the gate signal Gnu, so the net result is that it rises earlier by (Tlap + Tdon - Tdoff)/2. In other words, the output voltage is excessive for this period of time.

The output voltage error obtained from Figs. 5 to 8 can be summarized as follows. That is, in terms of the U phase,
When the U-phase current iu is positive, the output voltage is insufficient by ΔT=(Tlap+Tdon-Tdoff)/2.
When the U-phase current iu is negative, the output voltage becomes excessive by ΔT=(Tlap+Tdon-Tdoff)/2.

Therefore, the pulse width may be directly corrected by ΔT in the PWM generating means 33 to 35 shown in Figure 1. However, in the first embodiment, the voltage compensation means 41 to 43 calculate the voltage correction amount ΔV for each phase as ΔV = ±ΔT/Tc × Ed, where Ed is the DC power supply voltage and Tc is the sampling period.

Furthermore, since it is known that the turn-on delay time Tdon and turn-off delay time Tdoff of the semiconductor switching elements have a current dependency (see the lower graphs of Figures 3 and 4 described below), it is sufficient to prepare a table of ΔT corresponding to the magnitude and polarity of the current flowing through each phase in the voltage compensation means 41 to 43.

FIG. 3 is a diagram showing a first mode of voltage compensation by the voltage compensation means 41 to 43 of the first embodiment.
The lower graph in FIG. 3 shows an example of the current dependency of the turn-on delay time Tdon and the turn-off delay time Tdoff in a bipolar element such as an IGBT.

In bipolar elements such as IGBTs, the turn-on delay time Tdon tends to increase as the flow current increases, while the turn-off delay time Tdoff tends to increase rapidly as the interruption current decreases.

The upper graph in Figure 3 shows the characteristics of the voltage compensation means 41, 42, and 43 for semiconductor switching elements with such a tendency. In this characteristic, a non-lap compensation current lower limit Imin is set, and when the absolute values of the current command values iu*, iv*, and iw* are equal to or less than Imin, linear interpolation is performed so that the compensation amount becomes 0 when the current command value is 0.

Here, the reason for performing linear interpolation will be explained. The voltage compensation means 41, 42, and 43 of the first embodiment use a current command value without using a current detection value, but as shown in FIG. 2, the difference is that the current command value is only a fundamental wave component and no harmonic components (switching ripple) are superimposed. Normally, switching ripple, which is a harmonic component, is considered to appear symmetrically in positive and negative with respect to the fundamental wave component, so the error in the compensation amount is considered to be 0 on average. However, in the vicinity of the zero crossing of the current value, if the polarity discrimination is incorrect due to the influence of the switching ripple, the error becomes large, so it is preferable to reduce the compensation amount in the vicinity of the zero crossing of the current value, and therefore the linear interpolation described above is performed.

FIG. 4 is a diagram showing a second mode of voltage compensation by the voltage compensation means 41 to 43 of the first embodiment.
The lower graph in FIG. 4 shows an example of the current dependency of the turn-on delay time Tdon and the turn-off delay time Tdoff in a unipolar element such as a MOS-FET.

In unipolar elements such as MOS-FETs, the turn-on delay time Tdon tends to remain almost constant or decrease slowly as the flow current increases, while the turn-off delay time Tdoff tends to increase slowly as the blocking current increases.

The upper graph in Figure 4 shows the characteristics of the voltage compensation means 41, 42, and 43 for semiconductor switching elements having such a tendency. In this characteristic, as in the characteristic shown in Figure 3, a non-lap compensation current lower limit Imin is set, and when the absolute values of the current command values iu*, iv*, and iw* are equal to or less than Imin, linear interpolation is performed so that the compensation amount becomes 0 when the current command value is 0.

Here, the definitions of the turn-on delay time Tdon and the turn-off delay time Tdoff in the present invention will be explained.
FIG. 15 is a diagram for explaining the definition of the turn-on delay time Tdon of a switching element.

With respect to the rising edge of the gate signal Gpu of the U-phase upper semiconductor switching element Spu (upper part of FIG. 15), the dv/dt of the applied voltage Epu of the U-phase upper semiconductor switching element Spu until it transitions from the DC power supply voltage Ed to 0 is not constant (middle part of FIG. 15). For this reason, considering Epu' which approximates the applied voltage Epu to a square wave (lower part of FIG. 15), the time from the falling edge of Gpu until Epu converges to a steady state is defined as T1, and the time T0 at which the area S of Epu up to time T1 is equal to the area of the square wave Epu' is defined as the turn-on delay time Tdon (see equation 1).

FIG. 16 is a diagram for explaining the definition of the turn-off delay time Tdoff of a switching element.
With respect to the falling edge of the gate signal Gpu of the U-phase upper semiconductor switching element Spu (upper part of FIG. 16), the dv/dt of the applied voltage Epu of the U-phase upper semiconductor switching element Spu is not constant until it transitions from 0 to the DC power supply voltage Ed, and it may overshoot beyond the DC power supply voltage Ed (middle part of FIG. 16). For this reason, considering Epu' which approximates the applied voltage Epu to a square wave (lower part of FIG. 16), the time from the falling edge of Gpu until Epu converges to a steady state is defined as T1, and the time T0 at which the area S of Epu up to time T1 and the area of the square wave Epu' become equal is defined as the turn-off delay time Tdoff (see equation 2).

By defining the turn-on delay time Tdon and the turn-off delay time Tdoff as shown in Figures 15 and 16, the exact delay time can be grasped and an accurate voltage compensation amount can be obtained even if the dv/dt at the rise and fall times is not constant.

This is because the AC motor driven by the power converter is a so-called inductive load (inductance load), and the current value is the magnetic flux integrated from the output voltage of the power converter divided by the inductance, so even if the voltage waveform has an inconstant dv/dt when rising and falling, it can be approximated by a square wave that can be integrated to have an equal area.

FIG. 9 is a diagram showing the configuration of a power conversion device according to a second embodiment of the present invention and blocks of a drive control system included therein.
As a power conversion device, the main body portion is configured as follows.
Smoothing capacitors 62 and 63 connected in series are connected in parallel to a DC load (not shown).
The first and second semiconductor switching elements 50 and 51 of the U-phase are connected in series and connected in parallel to a smoothing capacitor 62, and the third and fourth semiconductor switching elements 52 and 53 of the U-phase are connected in series and connected in parallel to a smoothing capacitor 63.
The first and second clamp diodes 54 and 55 of the U-phase are connected in series to connect the connection point of the first and second semiconductor switching elements 50 and 51 of the U-phase to the connection point of the third and fourth semiconductor switching elements 52 and 53 of the U-phase, and the connection point of the first and second clamp diodes 54 and 55 of the U-phase is connected to the connection point of the smoothing capacitors 62 and 63.
The first and second semiconductor switching elements 56 and 57 of the V phase are connected in series and connected in parallel to a smoothing capacitor 62, and the third and fourth semiconductor switching elements 58 and 59 of the V phase are connected in series and connected in parallel to a smoothing capacitor 63.
The first and second clamp diodes 60 and 61 of the V phase are connected in series to connect the connection point of the first and second semiconductor switching elements 56 and 57 of the V phase to the connection point of the third and fourth semiconductor switching elements 58 and 59 of the V phase, and the connection point of the first and second clamp diodes 60 and 61 of the V phase is connected to the connection point of the smoothing capacitors 62 and 63.

The input voltage is supplied from an AC voltage source 64 via a transformer 65 having a primary terminal connected to the AC voltage source 64 and a secondary terminal connected to the connection point of the second and third semiconductor switching elements 51 and 52 of the U phase and the connection point of the second and third semiconductor switching elements 57 and 58 of the V phase.

The detectors include a voltage sensor (PT) 66 that detects the voltage es of the AC voltage source 64, a current sensor (CT) 67 that detects the secondary current is flowing from the secondary terminal of the transformer 65 to the connection point of the second and third semiconductor switching elements 51 and 52 of the U phase, and voltage sensors (PT) 68 and 69 that detect the voltages Edp and Edn of the smoothing capacitors 62 and 63.

The drive control system block consists of the following components:
An A/D converter 70 that quantizes the AC power supply voltage detection value es detected by the voltage sensor (PT) 66
An A/D converter 71 that quantizes the secondary current is detected by the current sensor (CT) 67.
An A/D converter 72 that quantizes the detection value Edp of the DC stage voltage (upper) and the detection value Edn of the DC stage voltage (lower) detected by the voltage sensors (PT) 68 and 69.
An integrator 73 that integrates the angular frequency ω of the AC voltage source 64 to obtain the fundamental wave phase θ
A sine function table 74 that generates a reference sine wave sin θ from a fundamental wave phase θ
A multiplier 75 that obtains a first secondary current instantaneous value command is1* from the product of a given secondary current effective value command Isp and a reference sine wave sin θ.
A subtractor 76 that calculates the deviation between the secondary current instantaneous value command is1* and the output of the A/D converter 71
Current control means (ACR) 77 that outputs a manipulated variable that makes the output (deviation) of the subtractor 76 zero
A subtractor 78 that obtains a converter output voltage command value ec* from the difference between the output of the A/D converter 70 and the output of the current control means (ACR) 77
A multiplier 80 that obtains an increment Δθ of the fundamental wave phase from the product of the angular frequency ω of the AC voltage source 64 and the sampling period Tc.
An adder 81 that calculates the fundamental wave phase θ' of the next cycle from the sum of the increment Δθ of the fundamental wave phase and the fundamental wave phase θ
A sine function table 82 for generating a reference sine wave sin θ' for the next cycle from the fundamental wave phase θ' for the next cycle
A multiplier 83 for obtaining a second secondary current instantaneous value command is2* by multiplying a given secondary current effective value command Isp and the reference sine wave sin θ' of the next cycle.
Voltage compensation means 84 for determining the converter output voltage compensation amount Δec using the second secondary current instantaneous value command is2* and the output of the A/D converter 72
An adder 85 that adds the converter output voltage compensation amount Δec to the converter output voltage command value ec*.
A PWM generating means 79 that uses the output of the adder 85 and the output of the A/D converter 72 to output gate signals Gu1 to 4 and Gv1 to 4 that drive the semiconductor switching elements 50 to 53 and 56 to 59.

FIG. 10 is a diagram showing a current waveform in the second embodiment, taking as an example a secondary current is that is a U-phase current.
10, it can be seen that the second secondary current instantaneous value command is2* reads ahead by the increment Δθ of the fundamental wave phase with respect to the secondary current is. This is because the operation delay time of the semiconductor switching element has current dependency, and the voltage compensation amount to compensate for this naturally also has current dependency, so if the current detection value is used, a current error occurs by the product Tc×di/dt of the current change rate di/dt and the sampling period Tc.

In Example 2, the phase θ rather than time t is taken as the reference axis, and by utilizing the fact that the frequency of the secondary current is (fundamental wave angular frequency ω) is known, Δθ = ω · Tc is set, and the phase delay of the sampling period Tc is compensated for.

As a result, in Example 2, the second secondary current command value is2* at the fundamental wave phase θ' of the next cycle is predicted, and this predicted value is used to calculate the voltage compensation amount Δec.

Next, the operating principle of the second embodiment will be described with reference to the drawings.
13 is a diagram showing the operation waveforms at one point in time for one phase of the three-level converter circuit targeted in the second embodiment. Here, the U-phase portion is taken out, and the operation waveforms are shown when the U-phase first semiconductor switching element Su1 is turned off, and after the non-lap period Tlap has elapsed, the U-phase third semiconductor switching element Su3 is turned on. In FIG. 13, the secondary current is is positive. The current polarity is positive in the direction entering the circuit.

Here, the non-overlap period Tlap is defined as the period from the falling edge of the gate signal Gu1 that drives the U-phase first semiconductor switching element Su1 to the rising edge of the gate signal Gu3 that drives the U-phase third semiconductor switching element Su3.

At this time, when the gate signal Gu1 of the U-phase first semiconductor switching element Su1 falls, there is no change from the state before the fall and nothing happens (a transition from the left side to the center in the upper diagram of FIG. 13). Meanwhile, the U-phase third semiconductor switching element Su3 transitions to a conductive state with a delay of turn-on delay time Tdon from the rising edge of the gate signal Gu3, the applied voltage becomes 0, and a current flows through the U-phase third switching element Su3 and the U-phase second clamp diode Du2 (the diagram on the upper right side of FIG. 13). At the same time, the applied voltage of the U-phase first semiconductor switching element Su1 becomes the DC power supply voltage (upper) Edp.
The U-phase potential ecu is equal to the applied voltage Eu3 to the U-phase third semiconductor switching element Su3.

Here, we calculate the output voltage error during the non-overlapping period. The output potential during the non-overlapping period is determined by the polarity of the input current and is either the DC power supply voltage (upper) Edp or 0. However, as an expected value, we consider half of the non-overlapping period to be the DC power supply voltage (upper) Edp, and the other half to be 0.

The expected value of the U-phase potential ecu is considered to fall half the non-lap period from the falling edge of the gate signal Gpu, that is, (Tlap + Tdon + Tdoff)/2, which is the sum of Tlap/2 and the average value of the turn-on delay time and the turn-off delay time.

However, the actual U-phase potential ecu falls with a delay of the turn-on delay time Tdon from the rising edge of the gate signal Gu3, so that the difference between the two is (Tlap + Tdon - Tdoff)/2. In other words, the output voltage is excessive for this period.

Fig. 14 is a diagram showing operational waveforms when the secondary current is negative at the same time point for the same phase as in Fig. 13. The definition of the non-overlap period Tlap is also the same as in Fig. 13.
At this time, the U-phase first semiconductor switching element Su1 transitions to a cutoff state with a delay of the turn-off delay time Tdoff from the falling edge of the gate signal Gu1, and the DC power supply voltage (upper) Edp is applied to it. At the same time, the voltage applied to the U-phase third semiconductor switching element Su3 becomes 0, and a current flows through the U-phase first clamp diode Du1 and the semiconductor switching element Su2 (the diagram in the upper center of FIG. 14).

On the other hand, when the gate signal Gu3 rises, there is no change from the state before the rise and nothing happens (a transition from the center to the right in the upper diagram of Figure 14). The U-phase potential ecu is equal to the applied voltage Eu3 of the U-phase third semiconductor switching element Su3.

Here, we calculate the output voltage error during the non-overlapping period. The output potential during the non-overlapping period is determined by the polarity of the input current and is either the DC power supply voltage (upper) Edp or 0. However, as an expected value, we consider half of the non-overlapping period to be the DC power supply voltage (upper) Edp, and the other half to be 0.

The expected value of the U-phase potential ecu is considered to fall half the non-lap period from the falling edge of the gate signal Gu1, that is, (Tlap + Tdon + Tdoff)/2, which is the sum of Tlap/2 and the average value of the turn-on delay time and the turn-off delay time.

However, the actual U-phase potential ecu falls with a delay of the turn-off delay time Tdoff from the falling edge of the gate signal Gu1, so that the net result is that it falls (Tlap + Tdon - Tdoff)/2 earlier than the falling edge of the gate signal Gu1. In other words, the output voltage is insufficient for this period of time.

The output voltage error obtained from FIGS. 13 and 14 can be summarized as follows. That is,
When the secondary current is positive, the output voltage becomes excessive by ΔT=(Tlap+Tdon-Tdoff)/2.
When the secondary current is negative, the output voltage is insufficient by ΔT=(Tlap+Tdon-Tdoff)/2.

Therefore, the pulse width may be directly corrected by ΔT in the PWM generating means 79 shown in Fig. 9. However, in the second embodiment, the voltage compensation amount Δec is calculated by the voltage compensation means 84 as Δec = ±ΔT/Tc × (Edp + Edn)/2, where Edp is the DC power supply voltage (upper), Edn is the DC power supply voltage (lower), and Tc is the sampling period.

Furthermore, since it is known that the turn-on delay time Tdon and turn-off delay time Tdoff of the semiconductor switching element have a current dependency (see the lower graphs of Figures 11 and 12 described below), it is sufficient to prepare a table of ΔT according to the magnitude and polarity of the current flowing in the voltage compensation means 84.

FIG. 11 is a diagram showing a first mode of voltage compensation by the voltage compensation means 84 of the second embodiment.
The lower graph of FIG. 11, like the lower graph of FIG. 3, shows an example of the current dependency of the turn-on delay time Tdon and the turn-off delay time Tdoff in a bipolar element such as an IGBT.

In bipolar elements such as IGBTs, the turn-on delay time Tdon tends to increase as the flow current increases, while the turn-off delay time Tdoff tends to increase rapidly as the interruption current decreases.

The upper graph in Figure 11 shows the characteristics of the voltage compensation means 84 for a semiconductor switching element having such a tendency. In this characteristic, a non-lap compensation current lower limit Imin is set, and when the absolute values of the current command values iu*, iv* and iw* are equal to or less than Imin, linear interpolation is performed so that the compensation amount is 0 when the current command value is 0. The reason for linear interpolation here is the same as that given in the explanation of the characteristics of the voltage compensation means 41, 42 and 43 in Example 1 using Figure 3 (paragraph [0056]).

FIG. 12 is a diagram showing a second mode of voltage compensation by the voltage compensation means 84 of the second embodiment.
The lower graph of FIG. 12, like the lower graph of FIG. 4, shows an example of the current dependency of the turn-on delay time Tdon and the turn-off delay time Tdoff in a unipolar element such as a MOS-FET.

In unipolar elements such as MOS-FETs, the turn-on delay time Tdon tends to remain almost constant or decrease slowly as the flow current increases, while the turn-off delay time Tdoff tends to increase slowly as the blocking current increases.

The upper graph in Figure 12 shows the characteristics of the voltage compensation means 84 for a semiconductor switching element having such a tendency. In this characteristic, as in the characteristic shown in Figure 11, a non-lap compensation current lower limit Imin is set, and when the absolute values of the current command values iu*, iv*, and iw* are equal to or less than Imin, linear interpolation is performed so that the compensation amount becomes 0 when the current command value is 0.

In the above, in the first embodiment of the present invention, a three-phase inverter circuit using a two-level circuit is given as an example of a configuration, and in the second embodiment, a single-phase converter circuit using a three-level circuit is given as an example of a configuration, but with these configurations, a three-phase inverter circuit using a three-level circuit and a single-phase converter circuit using a two-level circuit can be similarly realized. In this way, the present invention is not limited to the above two embodiments, and various modifications are possible within the scope of the gist of the present invention.

10, 62, 63 Smoothing capacitor 11 to 16, 50 to 53, 56 to 59 Semiconductor switching element 17 AC motor 18, 66, 68, 69 Voltage sensor (PT)
19, 67 Current sensor (CT)
20, 36, 70, 71, 72 A/D converter 21 Rotation coordinate conversion means 22, 75, 80, 83 Multiplier 23, 73 Integrator 24, 30 to 32, 81 Adder 25, 26, 76, 78 Subtractor 27, 77 Current control means (ACR)
28 Voltage vector generating means 29, 40 Stationary coordinate conversion means 33 to 35, 79 PWM generating means 41 to 43, 84 Voltage compensation means 54, 55, 60, 61 Clamp diode 64 AC voltage source 65 Transformer 74, 82 Sine function table Du1, 2, Dv1, 2 U/V phase 1st and 2nd clamp diodes Ed DC stage voltage detection value Edp DC stage voltage (upper) (detection value)
Edn DC stage voltage (lower) (detected value)
Epu, Enu U-phase upper/lower element applied voltage Epu' U-phase upper element applied voltage (approximately square wave)
Eu1-4 U phase 1st to 4th element applied voltage es AC power supply voltage detection value ec Converter output voltage (UV line voltage)
ecu, ecv U/V phase voltage ec* Converter output voltage command value ec** Compensated converter output voltage command value Δec Converter output voltage compensation amount Gpu, Gpv, Gpw U/V/W phase upper switching element gate signal Gnu, Gnv, Gnw U/V/W phase lower switching element gate signal Gu1 to 4, Gv1 to 4 U/V phase 1st to 4th switching element gate signals iu*, iv*, iw* U/V/W phase current command value iu, iv, iw U/V/W phase current detection value Id*, Iq* d/q-axis current command value Id, Iq d/q-axis current detection value Imin Non-lap compensation current lower limit Isp Secondary current effective value command is Secondary current detection value is1* First secondary current instantaneous value command is2* Second secondary current instantaneous value command Spu, Spv, Spw U/V/W phase upper switching element Snu, Snv, Snw U/V/W phase lower switching element Su1 to 4 U phase 1st to 4 elements Sv1 to 4 U phase 1st to 4 elements Tc Sampling period Tdon Turn-on delay time Tdoff Turn-off delay time Tlap Non-lap period Vd*, Vq* d/q-axis voltage command value vu, vv, vw U/V/W phase voltage vu*, vv*, vw* U/V/W phase voltage command value vu**, vv**, vw** U/V/W phase voltage compensated command value Δvu, Δvv, Δvw U/V/W phase voltage compensation amount ω Fundamental wave angular frequency θ Fundamental wave phase θ' Fundamental wave phase of next cycle Δθ Fundamental wave phase increment

Claims (8)

a power conversion unit that is configured by semiconductor elements and that converts DC power into AC power or converts AC power into DC power;
a current control unit that controls the AC current of the power conversion unit based on a DC current detection value obtained by converting a current detection value of the power conversion unit using a DC current command value for the power conversion unit and a fundamental wave phase of the power conversion unit obtained based on a drive frequency of the power conversion unit; and
a drive control unit that corrects a voltage command value generated based on an output of the current control unit, and generates a gate signal for driving the semiconductor element using the corrected voltage command value,
The drive control unit is
generating a fundamental wave phase of the next cycle of the power conversion unit by adding an increment of the fundamental wave phase, the increment being calculated from the product of the drive frequency and a sampling period when PWM controlling the power conversion unit, to the fundamental wave phase;
determining an AC current command value based on the DC current command value and the fundamental wave phase of the next cycle;
calculating a correction amount for the voltage command value based on the AC current command value and a DC stage detection voltage of the power conversion unit;
a power conversion device that adds the correction amount to the voltage command value to obtain the corrected voltage command value. The power conversion device according to claim 1,
When the power conversion unit converts DC power into AC power,
The power conversion device, wherein the current detection value is a detection value of an AC output current of the power conversion unit. The power conversion device according to claim 1,
When the power conversion unit converts AC power into DC power,
the current detection value is a detection value of an input AC current of the power conversion unit,
The power conversion device according to claim 1, wherein the drive control unit generates the voltage command value based on a difference between an output of the current control unit and a detected AC power supply voltage value. The power conversion device according to any one of claims 1 to 3,
the drive control unit calculates the correction amount based on a value obtained by subtracting a turn-on delay time of the semiconductor element corresponding to the AC current command value from a turn-off delay time of the semiconductor element corresponding to the AC current command value, and adding the result to a non-overlap period fixed for the power conversion unit, and the DC stage detection voltage. The power conversion device according to claim 4,
The power conversion device, wherein the drive control unit determines the correction amount by linear interpolation such that the correction amount becomes zero when the AC current command value is zero when the AC current command value is equal to or lower than a predetermined threshold value. A method for controlling a power conversion device that is configured with semiconductor elements and converts DC power to AC power or AC power to DC power, comprising the steps of:
integrating a drive frequency of the power conversion device to obtain a fundamental wave phase of the power conversion device;
converting a current detection value of the power conversion device using the fundamental wave phase to obtain a DC current detection value;
Calculating a fundamental wave phase of the next cycle of the power conversion device by adding an increment of the fundamental wave phase obtained from the product of the drive frequency and a sampling period when PWM controlling the power conversion device to the fundamental wave phase;
generating a voltage command value for controlling an AC current of the power conversion device based on a DC current command value for the power conversion device and the DC current detection value;
determining an AC current command value based on the DC current command value and the fundamental wave phase of the next cycle;
calculating a correction amount for the voltage command value based on the AC current command value and a DC stage detection voltage of the power conversion device ;
A control method for a power conversion device, comprising: generating a gate signal for driving the semiconductor element based on a corrected voltage command value obtained by adding the correction amount to the voltage command value. A method for controlling a power conversion device according to claim 6, comprising:
a turn-on delay time of the semiconductor element corresponding to the AC current command value minus a turn-off delay time of the semiconductor element corresponding to the AC current command value, and a value obtained by adding the result to a non-overlap period fixed for the power conversion device, and the DC stage detection voltage, the correction amount being calculated based on the DC stage detection voltage and the turn-on delay time of the semiconductor element corresponding to the AC current command value. A method for controlling a power conversion device according to claim 7,
a control method for a power conversion device, characterized in that the correction amount is determined by linear interpolation such that the correction amount becomes zero when the AC current command value is zero when the AC current command value is equal to or lower than a predetermined threshold value.

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