JP7596638B2 - Processor and error detection method - Patents.com - Google Patents

Description

The present invention relates to a processor and an error detection method.

In processors equipped with memory, as disclosed in Patent Document 1, error checking and correcting (ECC) is widely used to detect memory anomalies.

For example, Patent Document 1 discloses an electronic control device that includes an arithmetic unit having a CPU and a memory, and a memory anomaly detection unit that is an ECC that detects memory anomalies. This memory and the memory anomaly detection unit exchange data via a bus, and the CPU reads and writes data to the memory via the memory anomaly detection unit 11E.

JP 2018-10362 A

Here, FIG. 6 shows a processor 100 in which a pipeline control circuit 114 performs processing according to instructions from a memory 112. Conventionally, as shown in FIG. 6, an ECC circuit 116 is disposed between the memory 112 and the pipeline control circuit 114, and the ECC circuit 116 detects faults (ECC errors) present in the memory 112. Meanwhile, faults in the pipeline control circuit 114 are detected by comparing the outputs from the duplicated pipeline control circuits 114 with a comparator 120.

However, in such a conventional configuration, the pipeline control circuit 114 is duplicated, which increases the circuit size. In addition, in the conventional configuration, the ECC circuit 116 detects errors in the memory 112 before performing error detection processing on the pipeline control circuit 114, which may result in poor processing timing in the pipeline control circuit 114. Furthermore, if error detection is performed on a process that requires a high processing speed, the required processing speed may not be met.

In view of the above background, the present invention aims to provide a processor and an error detection method that can more appropriately detect errors that occur in a processor with a simpler configuration.

The present invention employs the following technical means to solve the above problems. The symbols in parentheses in the claims and in this section are examples showing the corresponding relationship with the specific means described in the embodiments described below as one aspect, and do not limit the technical scope of the present invention.

The processor (10) of one aspect of the present invention comprises a processing means (14) that performs processing according to an input command, and an error detection means (16) that detects errors in the processing means, and the error detection means switches between performing and not performing error detection for the processing means according to the processing executed by the processing means, and the switching between performing and not performing error detection by the error detection means is defined for each command indicating the processing to be executed by the processing means.

The present invention makes it possible to more appropriately detect errors that occur in a processor with a simpler configuration.

FIG. 2 is a schematic configuration diagram of a processor according to the first embodiment. 4 is a schematic diagram showing an instruction code of a pipeline control circuit according to the first embodiment; FIG. 4 is a flowchart showing a flow of instruction processing executed by the processor of the first embodiment. FIG. 11 is a schematic configuration diagram of a processor according to a second embodiment. 10 is a flowchart showing a flow of instruction processing executed by a processor according to a second embodiment; FIG. 1 is a schematic diagram of a processor including a conventional ECC circuit.

Below, an embodiment of the present invention will be described with reference to the drawings. Note that the embodiment described below is an example of how the present invention can be implemented, and the present invention is not limited to the specific configuration described below. When implementing the present invention, a specific configuration according to the embodiment may be appropriately adopted.

First Embodiment
1 is a schematic diagram of a processor 10 according to the present embodiment. The processor 10 according to the present embodiment includes a memory 12, a pipeline control circuit 14, an ECC circuit 16, and a register 18. In addition, the processor 10 according to the present embodiment applies RISC-V as an example of an instruction set architecture.

Data, ECC codes, etc. are stored in the memory 12, which are read out and used in processing by the pipeline control circuit 14, and the results of that processing are stored in the register 18.

The pipeline control circuit 14 is an example of a processing means that performs processing (tasks) according to input instructions (hereinafter also referred to as "instruction codes"). In this embodiment, the pipeline control circuit 14 has instruction execution units, which are processing elements, connected in series, and the output of the previous instruction execution unit is used as the input of the next instruction execution unit, so that multiple instruction execution units perform parallel processing.

In FIG. 1, the instruction execution units include an instruction fetch 14A, an instruction decoder 14B, and an ALU (Arithmetic Logic Unit) 14C, but this is just one example, and the pipeline control circuit 14 also includes other instruction execution units for performing addition, subtraction, multiplication, etc.

The ECC circuit 16 is hardware provided downstream of the pipeline control circuit 14, and detects errors that occur in either the pipeline control circuit 14 or the memory 12. In this embodiment, the ECC circuit 16 switches between performing and not performing error detection on the pipeline control circuit 14 depending on the processing executed by the pipeline control circuit 14.

In this embodiment, the switching between execution and non-execution of error detection by the ECC circuit 16 is defined for each instruction code that indicates the process to be executed by the pipeline control circuit 14. FIG. 2 is a schematic diagram showing an example of an instruction code in this embodiment.

The instruction code shown in FIG. 2 is an instruction (Memrory[rs1+imm] → rd) for loading the contents (data) of the address “rs1+imm” in memory 12 into register 18, and shows a normal instruction code and an instruction code with ECC.

As shown in FIG. 2, the normal instruction code and the ECC-added instruction code differ in the underlined portion, for example. This difference defines whether or not to perform error detection for the pipeline control circuit 14, and in this embodiment is defined by the extended field (Custom-0 Field) of the instruction set in RISC-V. In other words, the ECC-added instruction code includes a processing instruction for the pipeline control circuit 14 as well as an instruction to execute error detection by the ECC circuit 16. This further simplifies the instruction to switch between executing and not executing error detection.

In this way, the ECC circuit 16 of this embodiment is enabled when the instruction code is an ECC instruction code, but is disabled when the instruction code is a normal instruction code, switching between performing and not performing error detection for the pipeline control circuit 14.

Note that instruction codes that require error detection are used to perform processes that require functional safety, whereas instruction codes that do not require error detection are used to perform processes that require, for example, processing speed rather than functional safety. In this way, whether the instruction code is ECC-enabled or normal depends on the processing content executed by the pipeline control circuit 14. Therefore, the processor 10 of this embodiment can perform appropriate error detection according to the processing content.

In addition, since the ECC circuit 16 is provided after the pipeline control circuit 14, it is possible to detect an error whether it occurs in the memory 12 or in the pipeline control circuit 14. As a result, the circuit scale of the processor 10 can be reduced compared to a case in which the ECC circuit 16 is provided between the memory 12 and the pipeline control circuit 14 and the pipeline control circuit 14 is duplicated.

Figure 3 is a flowchart showing the flow of instruction processing executed by the processor 10 of this embodiment.

First, in step S100, an instruction code is output from memory 12 to the pipeline control circuit 14.

In the next step S102, the pipeline control circuit 14 executes processing based on the instruction code. When the processing by the pipeline control circuit 14 is completed, the instruction code and the processing result by the pipeline control circuit 14 are input to the ECC circuit 16 via the pipeline control circuit 14.

Then, in the next step S106, the ECC circuit 16 determines whether the input instruction code is an instruction code with ECC, and if the determination is positive, the process proceeds to step S106. On the other hand, if the determination is negative, the ECC circuit 16 does not perform error detection, the processing result by the pipeline control circuit 14 is stored in the register 18, and the instruction processing ends.

In step S106, the ECC circuit 16 performs error detection based on the processing result of the pipeline control circuit 14, outputs the error detection result, and ends this instruction processing. Note that the ECC circuit 16 outputs an error signal only when an error is detected, but does not have to output any signal if no error is detected.

As described above, in the processor 10 of this embodiment, when an instruction to the pipeline control circuit 14 includes an instruction to execute error detection by the ECC circuit 16, the ECC circuit 16 executes error detection for the pipeline control circuit 14 after processing by the pipeline control circuit 14 is completed.

In other words, depending on the processing content executed by the pipeline control circuit 14, error detection for the pipeline control circuit 14 may be unnecessary or may not be desirable. In anticipation of such a situation, the processor 10 of this embodiment switches between enabling and disabling the ECC circuit 16 depending on the processing executed by the pipeline control circuit 14, allowing for more appropriate operation with a simpler configuration.

Second Embodiment
A second embodiment of the present invention will now be described.

Figure 4 shows the configuration of the processor 10 according to the second embodiment. Note that components in Figure 4 that are the same as those in Figure 1 are given the same reference numerals as in Figure 1, and their description will be omitted.

The processor 10 of this embodiment includes a comparison unit 20 that compares the results of multiple identical processes performed by the pipeline control circuit 14. In other words, the comparison unit 20 functions as an error detection means that detects errors that occur in the pipeline control circuit 14. Note that the comparison unit 20 of this embodiment is executed by software processing, as an example.

In the processor 10 of this embodiment, when the instruction code is an instruction code with ECC, the pipeline control circuit 14 performs the same process multiple times based on the instruction code, and the comparison unit 20 compares the process results. If the multiple process results are the same, no error has occurred, and if the multiple process results are different, an error signal is output indicating that an error has occurred.

Figure 5 is a flowchart showing the flow of instruction processing executed by the processor 10 of this embodiment.

First, in step 200, the instruction code is output from the memory 12 to the pipeline control circuit 14.

In the next step 202, it is determined whether the instruction code is an instruction code with ECC, and if the determination is positive, the process proceeds to step 208, and if the determination is negative, the process proceeds to step 206.

In step 206, the pipeline control circuit 14 executes processing based on the instruction code, the processing result is stored in the register 18, and the instruction processing ends. In other words, if the determination in step 202 is negative, no error detection is performed.

On the other hand, in step 208, which is reached if the determination in step 202 is positive, the pipeline control circuit 14 performs a first processing based on the instruction code. The result of this first processing is output to the comparison unit 20.

In the next step 210, the pipeline control circuit 14 performs a second processing based on the instruction code, and the result of the second processing is also output to the comparison unit 20.

In the next step 212, the comparison unit 20 compares the first processing result with the second processing result, and this instruction processing ends. If the comparison results by the comparison unit 20 are different, the comparison unit 20 outputs an error signal, assuming that an error has occurred in the pipeline control circuit 14. On the other hand, if the comparison results by the comparison unit 20 are the same, no error has occurred in the pipeline control circuit 14, and the comparison unit 20 does not output a signal, or outputs a signal indicating that no error has occurred.

Note that in this embodiment, the presence or absence of an error is detected by comparing the results of performing the same process twice in the pipeline control circuit 14, but this embodiment is not limited to this.

For example, processing based on the ECC-added instruction code may also be executed by other instruction execution units included in the pipeline control circuit 14, and the comparison unit 20 may compare the execution results to detect errors. For example, the pipeline control circuit 14 may include multiple adders, subtractors, multipliers, etc. as instruction execution units. In such a case, the same arithmetic instruction is executed multiple times using different adders, subtractors, multipliers, etc., and the comparison unit 20 compares the results of the multiple arithmetic operations. As a result, if an error (fault) has occurred in any of the instruction execution units that performed the operation, the comparison results will be different, and an error signal will be output from the comparison unit 20.

In addition, the input contents to the pipeline control circuit 14 based on the ECC-added instruction code and the inverted data of the processing result may be stored in a buffer, and the pipeline control circuit 14 may again execute processing based on the data stored in the buffer, and the comparison unit 20 may compare this processing result with the data stored in the buffer to detect errors.

The present invention has been described above using the above embodiment, but the technical scope of the present invention is not limited to the scope described in the above embodiment. Various modifications or improvements can be made to the above embodiment without departing from the gist of the invention, and forms with such modifications or improvements are also included in the technical scope of the present invention. In addition, the above first and second embodiments may be combined.

In the above embodiment, RISC-V is applied as the architecture of the processor 10, and an embodiment is described in which the execution or non-execution of error detection is defined by an extension field of the instruction set in RISC-V, but the present invention is not limited to this. Other architectures may be used as long as the execution or non-execution of error detection can be defined by the instruction set.

In the above embodiment, the switching between execution and non-execution of error detection is described as being defined for each instruction code to the pipeline control circuit 14, but the present invention is not limited to this. For example, the switching between execution and non-execution of error detection may be performed according to the processing mode of the processor 10. In other words, the processing mode of the processor 10 can be set to a mode in which error detection is performed and a mode in which error detection is not performed.

In addition, in the above embodiment, a form in which a processor 10 that performs pipeline processing has been described, but the present invention is not limited to this, and the processor 10 does not necessarily have to perform pipeline processing. For example, the processor 10 may have a form including multiple CPUs (Central Processing Units). In this case, when the same process is performed multiple times as in the second embodiment and the comparison unit 20 compares the processing results, the comparison unit 20 compares the processing results of the processes executed by the multiple CPUs.

10: processor; 14: pipeline control circuit; 16: ECC circuit;
20...Comparison section

Claims (5)

A processing means (14) for performing processing according to instructions input from a memory;
an ECC circuit (16) provided downstream of the processing means for detecting an error in the processing means and switching between execution and non-execution of error detection;
Equipped with
The switching between execution and non-execution of error detection by the ECC circuit is defined for each instruction indicating a process to be executed by the processing means,
There is no detection means between the memory and the processing means for performing error detection on data output from the memory.
Processor (10). a processing means for performing processing in response to an instruction input from a memory;
an error detection means (20) for detecting an error by comparing the results of a plurality of identical processes performed by the processing means, and for switching between execution and non-execution of error detection;
Equipped with
switching between execution and non-execution of error detection by said error detection means is defined for each instruction indicating a process to be executed by said processing means;
There is no detection means between the memory and the processing means for performing error detection on data output from the memory.
Processor. 3. The processor according to claim 2, wherein execution or non-execution of error detection by said error detection means is defined in an extension field of an instruction set in RISC-V. An error detection method for a processor comprising: a processing means for performing processing in accordance with an instruction input from a memory; and an ECC circuit provided downstream of the processing means for detecting an error in the processing means and for switching between execution and non-execution of error detection; and no detection means provided between the memory and the processing means for performing error detection on data output from the memory, comprising:
a first step in which the processing means performs processing in accordance with an input command;
a second step in which the ECC circuit performs error detection after the first step is completed in response to a process performed by the processing means;
having
The execution or non-execution of the error detection by the second step is defined for each command indicating a process to be executed by the processing means.
Error detection methods. 1. An error detection method for a processor comprising a processing means for performing processing in accordance with an instruction input from a memory, and an error detection means for detecting an error by comparing results of a plurality of identical processes performed by the processing means, and no detection means for detecting an error in data output from the memory between the memory and the processing means, comprising:
a first step in which the processing means performs processing in accordance with an input command;
a second step in which the error detection means performs error detection after the first step is completed in accordance with the processing performed by the processing means;
having
The execution or non-execution of the error detection by the second step is defined for each command indicating a process to be executed by the processing means.
Error detection methods.

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