JP7596951B2 - Electronic Control Unit - Google Patents

Description

The present invention relates to an electronic control device.

In recent years, for example in electronic control devices for automobiles, efforts are being made to improve the processing power of microcomputers due to the increasing complexity of control. One example is a microcomputer equipped with multiple cores and a parallel processor, where the core requests the parallel processor to process a set of arithmetic instructions, which is a collection of arithmetic instructions, and the parallel processor processes the arithmetic instructions in parallel, thereby speeding up arithmetic processing.

The parallel arithmetic processor extracts arithmetic instructions from a set of arithmetic instructions requested by the core, and uses the hardware functions to automatically allocate optimal resources to multiple arithmetic units, enabling high-speed parallel calculations.

JP 2016-126426 A

Incidentally, the parallel processor is configured to receive a group of operation instructions requested for processing from a core, and to process the received group of operation instructions in order.
However, a parallel processor may be configured to accept requests for processing a set of operation instructions different from the set of operation instructions currently being processed, but not for the same set of operation instructions. In such a configuration, there is a problem that the parallel processor cannot process the same set of operation instructions when multiple cores make duplicate requests to process the same set of operation instructions.

The present invention was made in consideration of the above circumstances, and its purpose is to provide an electronic control device that can process the same set of calculation instructions using a parallel calculation processor even when processing is requested in duplicate.

According to the invention of claim 1, the control functions (A to C) of the control function unit (X) request the processing of an arithmetic instruction group. When a processing request is received from the control function of the control function unit, the holding unit (Y1) puts the processing request into a standby state. The management function unit (Y2) manages the standby state of the processing request by the holding unit and the processing state of the arithmetic instruction group by the parallel arithmetic processor (13), so that when the control function of the control function unit requests processing of the same arithmetic instruction group in duplicate, the management function unit puts the processing request from the control function unit into a standby state in the holding unit until the parallel arithmetic processor completes processing of the arithmetic instruction group, and as soon as the parallel arithmetic processor completes processing of the arithmetic instruction group, it acquires the processing request waiting in the holding unit and mediates so that the parallel arithmetic processor can execute it. This makes it possible to avoid a request for processing the same arithmetic instruction group to the parallel arithmetic processor, and even if a processing request is received for the same arithmetic instruction group as the arithmetic instruction group being processed in the parallel arithmetic processor, the request can be accepted.

The management function unit manages the control functions related to the process from when the control function of the control function unit makes a processing request to when the parallel arithmetic processor returns the processing result, in association with the operation instruction group and the execution/completion of the processing. This allows the processing result by the parallel arithmetic processor to be passed to the control function of the control function unit that is the processing request source. When making a processing request, the control function of the control function unit provides request information for the operation instruction group corresponding to the processing request to the holding unit. When a processing request is received from the control function of the control function unit, the holding unit enqueues the request information for the given operation instruction group in a queuing mechanism (Y1). The management function unit has a management function corresponding to each operation instruction group processed by the parallel arithmetic processor, and obtains request information corresponding to the operation instruction group that the parallel arithmetic processor can accept from the queuing mechanism and provides it to the parallel arithmetic processor. The parallel arithmetic processor processes the operation instruction group based on the request information provided from the management function unit. The queuing mechanism has a queue corresponding to each operation instruction group processed by the parallel arithmetic processor, and when request information for the operation instruction group is provided from the control function of the control function unit, the queuing mechanism enqueues the request information in the queue for the corresponding operation instruction group. The management function acquires request information corresponding to an operation instruction group that the parallel processor can accept from the queue of the corresponding operation instruction group, and provides the request information to the parallel processor.

FIG. 1 is a functional block diagram showing a configuration of a microcomputer according to an embodiment. A block diagram showing the connections between the engine ECU and each ECU. A block diagram showing the schematic configuration of a parallel arithmetic processor. Diagram showing graph structure A schematic diagram showing the functions of the graph manager Diagram showing the operation of each function

Hereinafter, an embodiment will be described with reference to the drawings.
As shown in Fig. 2, the vehicle is equipped with an engine ECU (Electronic Control Unit) 1. The engine ECU 1 corresponds to an electronic control device. The engine ECU 1 is communicably connected to other ECUs, such as an automatic transmission ECU 3, a meter ECU 4, and an air conditioning ECU 5, via an in-vehicle LAN 2. The protocol of the in-vehicle LAN 2 is, for example, CAN (Controller Area Network). CAN is a registered trademark.

The engine ECU 1 is mainly composed of a microcomputer 11. As shown in FIG. 1, the microcomputer 11 is composed of a core group 12 consisting of multiple cores 12a to 12c and a parallel calculation processor 13, and these cores 12a to 12c and the parallel calculation processor 13 process multiple calculations in parallel to achieve high-speed processing.

The cores 12a to 12c and the parallel processor 13 are connected to each other via an internal bus 14, and are also connected to memories such as ROM 15 and RAM 16, and to I/O 17 such as a CAN interface. The microcomputer 11 is also connected to other microcomputers 18 and peripheral circuits 19 such as an AD converter.

The cores 12a to 12c receive detection signals from various sensors for detecting the operating state of the engine via the input circuit 20, and process the detection values indicated by the detection signals to control actuators for controlling the engine via the output circuit 21, and send and receive communication signals with other ECUs via the communication circuit 22. When specific calculation processing is required to control the engine, the cores 12a to 12c request the parallel calculation processor 13 to perform the processing.

As shown in FIG. 3, the parallel arithmetic processor 13 is composed of a memory 23, a control circuit 24, and multiple arithmetic units 25. The memory 23 sequentially stores information for processing groups of arithmetic instructions provided by the multiple cores 12a to 12c.

The control circuit 24 performs calculations on the set of calculation instructions stored in the memory 23 in cooperation with the arithmetic unit 25. In other words, the control circuit 24 has a scheduler function and automatically assigns the calculation instructions constituting the set of calculation instructions stored in the memory 23 to the corresponding arithmetic unit 25.

The calculator 25 sequentially processes the calculation instructions assigned by the control circuit 24. The calculators 25 may be of the same type or different types, and parallel processing is possible by assigning the same type or different types of calculation instructions to the calculators 25. The calculator 25 stores the calculation processing results in the memory 23.

When multiple cores 12a to 12c request the parallel arithmetic processor 13 to process a group of arithmetic instructions, they obtain the arithmetic results via memory 23 and execute subsequent processing based on those arithmetic results.

The processing order of the calculation instructions requested by the cores 12a to 12c is specified. For example, the calculation instruction group shown in FIG. 4 specifies that the next calculation instructions B to D are processed after the calculation processing of calculation instruction A is completed, and the next calculation instruction E is processed after the calculation processing of all calculation instructions B to D is completed. Hereinafter, the calculation instruction group is referred to as a graph.

In this embodiment, the parallel processor 13 is configured to accept a processing request for a graph different from the graph being processed, but not to accept a processing request for the same graph. This causes a problem in that if the cores 12a to 12c make duplicate processing requests for the same graph, the parallel processor 13 cannot process it.

For these reasons, in this embodiment, an arbitration function is provided between the cores 12a to 12c and the parallel processor 13. This arbitration function puts graph processing requests from the cores 12a to 12c into a standby state, monitors the standby state and the processing state of the parallel processor 13, and provides the parallel processor 13 with graph processing requests that the parallel processor 13 can accept.

The arbitration function will now be described. As shown in FIG. 5, the electronic control device 1 is configured with a parallel arithmetic processor 13, as well as a control function unit X and a graph management unit Y. The control function unit X is configured to have multiple control functions. The graph management unit Y is configured to have a queuing mechanism Y1 and a graph management function Y2. The queuing mechanism Y1 corresponds to the holding unit, and the graph management function Y2 corresponds to the management function unit.

The queuing mechanism Y1 has multiple graph request queues corresponding to the graphs, and enqueues the graph request information in the corresponding graph request queue in response to a graph processing request from each control function of the control function unit X.

Graph management function Y2 has multiple graph request information management functions corresponding to the graphs and a graph state management function. The graph request information management function manages the control functions and graphs related to the process from when each control function of control function unit X requests processing to when parallel processing unit 13 returns the processing result, as well as identification information that identifies the execution/completion of the processing. The graph state management function monitors the processing state of the graph in parallel processing unit 13, and when parallel processing unit 13 is able to accept processing of the graph, it dequeues and acquires the graph request information enqueued in the graph request queue and sends it to parallel processing unit 13.

In this embodiment, cores 12a to 12c have the control functions of one or more control function units X. Core 12c also has the functions of graph management unit Y in addition to the control functions of control function unit X.

An example of processing a graph requested by each control function of control function unit X using each control function of control function unit X possessed by cores 12a to 12c and the function of graph management unit Y possessed by core 12c will be described with reference to FIG. 6.

In the example shown in FIG. 6, the control function unit X has control functions A to C, the queuing mechanism Y1 has a graph 0 request queue and a graph 1 request queue, and the graph management function Y2 has a graph 0 management function and a graph 1 management function.

The parallel computing processor 13 is capable of accepting graph 0 and graph 1, but is configured not to accept a processing request for the same graph as the graph currently being processed. When neither graph 0 nor graph 1 is being processed, it is capable of accepting graph 0 and graph 1, and is configured to process, for example, the previously accepted graph 0 before processing the next accepted graph 1.

6 shows a case where control function A requests the processing of graph 0, then control function B requests the processing of graph 1, and then control function C requests the processing of graph 0. In this case, control function A and control function C are making overlapping requests to process graph 0.
First, control function A requests graph 0 to graph management unit Y for processing. This request to process graph 0 is made by simultaneously transmitting request information of control function A to graph management unit Y. The request information includes information on the control function that originated the request, control information required for processing the graph, and result storage address information.

When there is a processing request for graph 0, the queuing mechanism Y1 enqueues the request information of the control function A in the corresponding request queue for graph 0. In other words, the processing request for graph 0 is put into a waiting state.
The graph management function Y2 manages the states of graph 0 and graph 1 processed by the parallel processor 13. That is, when a graph processing trigger is sent to the parallel processor 13, the corresponding graph is determined to be in a BUSY state, and when a graph completion trigger is received from the parallel processor 13, the corresponding graph is determined to be in an IDLE state. However, in the initial state, graph 0 and graph 1 are determined to be in an IDLE state.

The graph management function Y2 determines the request information required for the parallel processing unit 13 to process the graph, and obtains the request information by dequeuing it from the corresponding graph request queue. In other words, the parallel processing unit 13 determines which graphs are in the IDLE state, and obtains the request information by dequeuing the control function from the graph request queue in the IDLE state according to a predetermined rule, for example, FIFO (First In First Out).

In the example shown in FIG. 6, the graph 0 management function of the graph management function Y2 determines that the graph 0 of the parallel processing unit 13 is in the IDLE state. In this case, since the request information of the control function A is enqueued in the graph 0 request queue of the queuing mechanism Y1, the graph 0 management function dequeues and acquires the request information of the control function A, and transmits the request information of the control function A and a graph 0 processing trigger to the parallel processing unit 13.

When the parallel computing device 13 receives the graph 0 processing trigger, it is not processing graph 0, so it accepts the graph 0 processing trigger and starts processing graph 0 based on the request information.

Next, if control function B requests the processing of graph 1 while the parallel computing processor 13 is processing graph 0 of control function A, the queuing mechanism Y1 enqueues the request information of control function B in the graph 1 request queue. In this case, since the parallel computing processor 13 determines that graph 1 is in the IDLE state, it dequeues and acquires the request information of control function B from the graph 1 request queue and transmits the request information of control function B and a graph 1 processing trigger to the parallel computing processor 13. At this time, since the parallel computing processor 13 is processing graph 0 but not graph 1, it accepts the request information of control function B in response to receiving the graph 1 processing trigger.

Next, if control function C requests the processing of graph 0 while the parallel processor 13 is processing graph 0, the request information of control function C is enqueued in the graph 0 request queue. In other words, the processing request of control function C goes into a waiting state. At this time, the graph 0 management function of graph management function Y2 determines that graph 0 of the parallel processor 13 is in a BUSY state, and therefore maintains the enqueued state of the request information of control function C. In other words, the waiting state of the processing request of graph 0 of control function C continues.
When the parallel processor 13 finishes processing of graph 0, it transmits a graph 0 completion trigger and then starts processing the request information of graph 1 which is in a waiting state.

When the graph 0 management function of graph management function Y2 receives a graph 0 completion trigger from the parallel computing processor 13, it sends a graph 0 processing completion notification to control function A. This allows control function A to recognize that the processing of graph 0 by the parallel computing processor 13 has ended, and to carry out subsequent processing based on the processing results of graph 0. In this case, graph management function Y2 will exclude the graph 0 processing request from control function A from its management targets.

On the other hand, when the graph 0 management function of the graph management function Y2 receives a graph 0 completion trigger from the parallel processing unit 13, it determines that graph 0 is in the IDLE state, dequeues and acquires the request information of control function C enqueued in the graph 0 request queue, and transmits the request information of control function C and the graph 0 processing trigger to the parallel processing unit 13. As a result, the parallel processing unit 13 accepts the request information, and starts processing of graph 0 when processing of graph 1 is completed.
In this manner, the arbitration function of the graph management function Y2 makes it possible for the parallel processor 13 to accept processing requests for the same graph from the control functions A to C even when the parallel processor 13 is processing graph 0 or graph 1.

Here, the graph management function Y2 manages the above-mentioned control functions, graphs, graph processing, and graph completion triggers by IDs. In other words, it assigns an ID that identifies control functions A to C of the control function unit X, a graph ID that identifies the graph, and an ID that identifies the graph processing trigger and graph completion trigger, and manages them by linking them with IDs related to the process from when control functions A to C of the control function unit X make a processing request to when the parallel processing unit 13 returns the processing result. This allows the processing result by the parallel processing unit 13 to be passed to the cores 12a to 12c that are the source of the processing request. The ID corresponds to the identification information. In this case, the graph management function Y2 excludes the processing request for graph 1 from control function C from its management targets.

According to this embodiment, the following effects can be obtained.
When graph request information is transmitted from the control functions A to C of the control function unit X, the graph management unit Y enqueues the request information in the queuing mechanism Y1, and when the parallel processing unit 13 is capable of accepting processing of the graph and request information for the same graph as the graph in question has been enqueued, the graph management unit Y transmits the processing request to the parallel processing unit 13. In this way, by using the queuing mechanism Y1, a processing request for the same graph as the graph being processed by the parallel processing unit 13 can be accepted and processed.

In addition, the control functions and graphs related to the process from when the control functions A to C of the control function unit X that originated the processing request make a processing request until the parallel arithmetic processor 13 returns the processing result are linked and managed, as well as identification information that identifies the execution/completion of the processing. This makes it possible to pass the processing result by the parallel arithmetic processor 13 to the control functions A to C of the control function unit X that originated the processing request.

When control functions A to C of control function unit X make a processing request, they provide graph request information corresponding to the processing request to the queuing mechanism Y1, and when graph request information is provided from control functions A to C of control function unit X, the queuing mechanism Y1 enqueues the request information in the corresponding graph request queue, and the graph management function Y2 obtains request information corresponding to a graph that the parallel computing processor 13 can accept from the corresponding graph request queue of the queuing mechanism Y1 and provides it to the parallel computing processor 13, and the parallel computing processor 13 processes the graph based on the request information provided from the graph management function Y2. In this way, by providing a graph request queue as the queuing mechanism Y1, processing requests can be processed via the graph request queue.

When the graph management unit Y requests the parallel processing unit 13 to process a graph, it sends a processing trigger corresponding to the graph to the parallel processing unit 13, and the parallel processing unit 13 processes the graph based on the request information in response to the received processing trigger. This allows the graph to be processed in the parallel processing unit 13 based on the request information from the graph management unit Y in synchronization with the graph processing trigger.

When the parallel arithmetic processor 13 completes the processing of a graph, it sends a completion trigger corresponding to that graph, and when the graph management unit Y receives a completion trigger from the parallel arithmetic processor 13, it notifies the control functions A to C of the control function unit X that sent the completion of processing, and the control functions A to C of the control function unit X obtain the processing results in response to the received processing completion notification and execute subsequent processing based on the processing results. This makes it possible to notify the control functions A to C of the control function unit X that the processing by the parallel arithmetic processor 13 has been completed in synchronization with the completion trigger.

When a processing trigger is sent, the graph management unit Y determines that the graph corresponding to the processing trigger is in a BUSY state, and when a graph completion trigger is received, the graph corresponding to the graph processing trigger is in an IDLE state, thereby managing the processing state of the parallel processing unit 13, and dequeues and obtains request information from the graph request queue corresponding to the graph determined to be in an IDLE state. This makes it possible to manage the processing state of the parallel processing unit 13 in synchronization with the graph processing trigger and the graph completion trigger.

The graph management unit Y links and manages IDs related to the process from when the control functions A to C of the control function unit X that originated the processing request make a processing request until the parallel processing unit 13 returns the processing result, by adding IDs to the control functions A to C of the control function unit X, which originated the processing request. This makes it possible to manage the graph that is requested to be processed by the parallel processing unit 13 based on the request information from the control functions A to C of the control function unit X and the control functions A to C of the control function unit X that originated the processing request, and to notify the control functions A to C of the control function unit X that originated the processing request of the processing completion based on the completion trigger sent when the graph processing is completed.

Other Embodiments
When request information is not enqueued in the graph request queue corresponding to the graph determined to be in the IDLE state, the graph management unit Y may determine request information in response to a processing request received from the control functions A to C of the control function unit X, and transmit the request information and a graph processing trigger to the parallel processing unit 13, which may process the graph based on the request information in response to receiving the graph processing trigger. In this case, the parallel processing unit 13 can obtain the request information even if the request information is not enqueued in the graph request queue.
The electronic control device is not limited to the engine ECU, and may be any device that controls a controlled object.

Although the present disclosure has been described with reference to an embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

In the drawing, 1 is an engine ECU (electronic control unit), 11 is a microcomputer, 12a to 12c are cores, 13 is a parallel processing unit, 25 is a calculator, X is a control function unit, A to C are control functions, Y is a management unit, Y1 is a queuing mechanism (holding unit), and Y2 is a graph management function.

Claims (7)

An electronic control device including a microcomputer (11) equipped with a parallel arithmetic processor (13) capable of parallel processing a plurality of arithmetic instructions constituting an arithmetic instruction group by a plurality of arithmetic units (25),
control functions (A to C) of a control function unit (X) for requesting processing of a group of arithmetic instructions;
a holding unit (Y1) that holds a processing request in a standby state when the processing request is received from a control function of the control function unit;
a management function unit (Y2) that arbitrates processing requests for each of the operation instruction groups to the parallel processor by managing a standby state of a processing request by the holding unit and a processing state of the operation instruction groups by the parallel processor, and that manages a control function related to a process from when a control function of the control function unit makes a processing request to when the parallel processor returns a processing result, the operation instruction groups, and the execution and completion of the process in association with each other;
Equipped with
When a control function of the control function unit requests processing, the control function unit provides request information of a set of operation instructions corresponding to the processing request to the holding unit;
the holding unit, when a processing request is received from a control function of the control function unit, enqueues request information of a given set of operation instructions in a queuing mechanism (Y1);
the management function unit has a management function corresponding to each operation instruction group processed by the parallel processing unit, acquires request information corresponding to an operation instruction group that can be accepted by the parallel processing unit from the queuing mechanism, and provides the request information to the parallel processing unit;
the parallel arithmetic processor processes a group of arithmetic instructions based on request information provided by the management function unit;
the queuing mechanism includes a queue corresponding to each operation instruction group processed by the parallel operation processor, and when request information of an operation instruction group is given from a control function of the control function unit, enqueues the request information in the queue of the corresponding operation instruction group;
The management function is an electronic control device that obtains request information corresponding to a group of operation instructions that the parallel processor can accept from a queue of the corresponding group of operation instructions and provides the request information to the parallel processor . The electronic control device according to claim 1, wherein the management function unit arbitrates by providing a processing request for an arithmetic instruction group to the parallel arithmetic processor when the parallel arithmetic processor is capable of accepting the processing request for the arithmetic instruction group and when a processing request for the same arithmetic instruction group as the arithmetic instruction group is in a waiting state. when providing a processing request for a group of operation instructions to the parallel processor, the management function unit transmits a processing trigger corresponding to the group of operation instructions;
3. The electronic control device according to claim 1, wherein the parallel operation processor processes a group of operation instructions based on request information in response to receiving a processing trigger . the parallel operation processor transmits a completion trigger corresponding to a group of operation instructions when the processing of the group of operation instructions is completed;
The management function unit notifies the control function of the control function unit, which is a transmission source, of the completion of the process in response to receiving the completion trigger;
The electronic control device according to claim 1 , wherein the control function of the control function unit acquires a processing result in response to receiving a processing completion notification, and executes a subsequent process based on the processing result . 5. The electronic control device according to claim 3 or 4, wherein the management function unit manages the processing state of the parallel arithmetic processor by determining that a processing trigger corresponding to the processing trigger is in a BUSY state when a processing trigger is sent, and determining that a processing instruction group corresponding to the processing trigger is in an IDLE state when a completion trigger is received, and dequeues and acquires request information from a queue of an arithmetic instruction group corresponding to the arithmetic instruction group determined to be in an IDLE state. 6. The electronic control device according to claim 5, wherein the management function unit, when no request information is enqueued in a queue of an arithmetic instruction group corresponding to an arithmetic instruction group determined to be in an IDLE state, acquires request information corresponding to a processing request provided from a control function of the control function unit . 7. The electronic control device according to claim 5 or 6, wherein the management function unit identifies the control function of the control function unit, the calculation instruction group, the processing trigger, and the completion trigger by IDs, and manages the control function related to the process from when the control function of the control function unit makes a processing request to when the parallel calculation processor returns the processing result, in association with the calculation instruction group, and identification information that identifies the execution and completion of the processing .

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