JP7599588B2 - Oscillator Circuit - Google Patents

Description

The present disclosure relates to an oscillator circuit.

In recent years, there has been an increasing need for on-chip oscillator circuits that can reduce the board area compared to crystal oscillators, in order to reduce costs. Generally, RC oscillator circuits are well known as on-chip oscillator circuits, as they have low phase noise and excellent frequency tunability.

For example, Non-Patent Document 1 describes a typical circuit configuration of an RC type oscillator circuit. Specifically, it discloses a circuit configuration that forms a circulation loop with a feedback path provided by a feedback resistor and a feedback capacitance for providing a signal delay to multiple stages of inverters. In this circuit configuration, an oscillation signal can be generated by providing a time difference due to the above-mentioned signal delay in the inversion timing of the output signal between the first stage inverter and the last stage inverter.

In an RC type oscillator circuit, the oscillation frequency can be designed by the product of the resistance value (R) of the feedback resistor and the capacitance value (C) of the feedback capacitance, so it is relatively easy to adjust the frequency of the oscillation signal. For example, JP 2019-12944 A (Patent Document 1) describes a technique for adjusting the oscillation frequency by trimming a resistive element based on the results of monitoring the output signal.

JP 2019-12944 A

Junsoo Ko and Minjae, "A 1.8 V 18.13 MHz Inverter-Based On-Chip RC Oscillator with Flicker Noise Suppression Using Logic Transition Voltage Feedback", November 15, 2019, MDPI (Multidisciplinary Digital Publishing Institute), Electronics 2019, 8, 1353.

Typically, an oscillation signal is designed to have a duty ratio, which is the ratio between the logical high level (hereinafter simply referred to as "H level") period and the logical low level (hereinafter simply referred to as "L level") period, of 50(%):50(%). In particular, when an oscillation signal is used as a reference clock for a system, there are many applications in which both the rising edge and the falling edge of the oscillation signal are used to trigger the operation of internal circuits, so a duty ratio close to 50(%):50(%) is required.

On the other hand, in an RC type oscillator circuit, if the characteristics of the first stage inverter, typically the inversion threshold voltage, fluctuate due to manufacturing variations (process variations), there is a concern that the duty ratio of the oscillation signal will deviate from 50(%):50(%).

However, while the trimming of the resistive element described in Patent Document 1 allows the oscillation frequency to be adjusted with a simple configuration, it does not allow the duty ratio to be adjusted.

In addition, Non-Patent Document 1 describes a circuit configuration that automatically feedback controls the back-gate potential of the N-type transistor that constitutes the first-stage inverter in order to control the inversion threshold voltage of the inverter to a constant value. However, there are concerns that the introduction of such feedback control will lead to an increase in the scale of the circuit configuration and an increase in power consumption.

This disclosure has been made to solve these problems, and the purpose of this disclosure is to provide an RC-type oscillator circuit that is capable of adjusting the duty ratio of an oscillation signal with a simple configuration.

According to an aspect of the present disclosure, an oscillator circuit is provided. The oscillator circuit includes a plurality of signal paths each configured to pass through a first logic inversion circuit, a selection unit, at least one second logic inversion circuit, a feedback resistor, and a feedback capacitance. The first logic inversion circuits are configured to pass through a first logic inversion circuit that generates an output signal that is set to a first logic level or a second logic level according to a comparison result between a voltage of an input node and an inversion threshold voltage. The selection unit selects one of the plurality of signal paths and transmits the output signal to a first node. At least one second logic inversion circuit is connected in series between the second node and the first node. The feedback resistor is connected between a third node, which is either an input side or an output side of the second logic inversion circuit, and the input node. The feedback capacitance is connected between a fourth node and the input node. The fourth node is either an input side or an output side of the second logic inversion circuit, and is different from the third node. The signal paths are formed such that at least one of an inversion threshold voltage and an edge propagation delay difference of the output signal is different from each other, the edge propagation delay difference being equivalent to a difference between a first delay time occurring during a first transition from a first logic level to a second logic level and a second delay time occurring during a second transition from the second logic level to the first logic level.

According to the present disclosure, even if the characteristics of the first logic inversion circuit vary due to manufacturing variations, the duty ratio of the oscillation signal output from the second logic inversion circuit can be set to a desired value by selecting multiple signal paths, thereby providing an RC-type oscillation circuit that can adjust the duty ratio of the oscillation signal with a simple configuration.

1 is a block diagram illustrating a basic configuration of an oscillator circuit according to an embodiment of the present invention. 1 is a circuit diagram illustrating a configuration example of an oscillator circuit according to a first embodiment; FIG. 2 is a circuit diagram illustrating the configuration of each inverter. FIG. 1 is a circuit diagram of an oscillator circuit according to a comparative example. 5 is an operational waveform diagram of the oscillator circuit shown in FIG. 4. 5 is a table illustrating the operation of a resistance control unit in the oscillator circuit according to the first embodiment. 5 is an operational waveform diagram illustrating the relationship between the inversion threshold voltage of the first-stage inverter and the duty ratio of the oscillation signal. FIG. 4 is a table explaining the operation of a selection unit in the oscillation circuit according to the first embodiment; 4 is a flowchart of a control process for adjusting a duty ratio in the oscillator circuit according to the first embodiment. FIG. 11 is a circuit diagram illustrating a configuration example of an oscillator circuit according to a second embodiment. 11 is a conceptual diagram for explaining the operation of a dummy switch. FIG. FIG. 13 is a circuit diagram illustrating a configuration example of an oscillator circuit according to a first modification of the second embodiment. 13 is an operational waveform diagram illustrating duty adjustment in an oscillator circuit according to a first modification of the second embodiment. FIG. FIG. 13 is a circuit diagram illustrating a configuration example of an oscillator circuit according to a second modification of the second embodiment. FIG. 11 is a circuit diagram illustrating a configuration example of an oscillator circuit according to a third embodiment. 16 is a circuit diagram illustrating the configuration of each clocked inverter shown in FIG. 15. FIG. 13 is a circuit diagram illustrating a configuration example of an oscillator circuit according to a modified example of the third embodiment. 18 is a circuit diagram illustrating a configuration of a clocked inverter shown in FIG. 17. 13 is a table for explaining an example of setting a control signal for adjusting a duty ratio in an oscillator circuit according to a modification of the third embodiment. FIG. 13 is a circuit diagram illustrating a configuration example of an oscillator circuit according to a fourth embodiment. 21 is an operational waveform diagram of the oscillator circuit shown in FIG. 20. FIG. 13 is a circuit diagram illustrating a configuration example of an oscillator circuit according to a first modification of the fourth embodiment. FIG. 13 is a circuit diagram illustrating a configuration example of an oscillator circuit according to a second modification of the fourth embodiment.

Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings will be given the same reference numerals, and in principle, their description will not be repeated.

Embodiment 1.
FIG. 1 is a block diagram illustrating a basic configuration of an oscillator circuit 100 according to the present embodiment.

Referring to FIG. 1, the oscillator circuit 100 includes a first logic circuit 10, a selection unit 20, a second logic circuit 30, a feedback resistor 40, a resistance control unit 45, a feedback capacitance 50, and a control circuit 90.

The first logic circuit 10 is composed of one logic inversion circuit (typically, an inverter) and generates an output voltage corresponding to the inverted logic of the voltage of the input node Na. The second logic circuit 30 is composed of at least one logic inversion circuit (typically, an inverter) connected in series between the nodes Nb and Nd. As a result, the second logic circuit 30 generates a pulse signal of a logic level in phase or opposite phase to the voltage of the node Nb as the oscillation signal Vosc.

In addition, in this embodiment, an example is described in which each logic inversion circuit is composed of an inverter, so the logic inversion circuit is also simply referred to as an inverter, and in particular, the inverter that constitutes the first logic circuit 10 is also referred to as the first-stage inverter.

In this embodiment, a plurality of signal paths IPT including a first logic circuit 10 are provided in parallel between the input node Na and the node Nb. Hereinafter, the signal path is also referred to as the "first-stage inverter path IPT." In FIG. 1, M (M: integer equal to or greater than 2) first-stage inverter paths IPT1 to IPTM are provided in parallel.

As will become clear from the following explanation, the first-stage inverter paths IPT1 to IPTM may be constructed by arranging in parallel signal paths including first-stage inverters each having a different inversion threshold voltage, or may be constructed by branching the output of a common first-stage inverter.

As described later, the multiple first-stage inverter paths IPT are configured such that at least one of the inversion threshold voltages of the first-stage inverters included in the paths and the edge propagation delay characteristics of the output signals of the first-stage inverters are different from each other. The edge propagation delay characteristics will be described in detail in a modified example of the second embodiment.

The selection unit 20 selects one of the first-stage inverter paths IPT1 to IPTM in accordance with the control signal CNT1 and transmits the output signal of the first-stage inverter to the node Nb. This results in a series connection of multiple inverter stages consisting of one inverter included in the selected first-stage inverter path and at least one inverter included in the second logic circuit 30.

The feedback resistor 40 and the feedback capacitor 50 are connected between the second logic circuit 30 and the input node Na so as to form signal feedback paths from the multiple inverter stages. This forms a circulation loop of a pulse signal from the multiple inverter stages, accompanied by a signal delay due to the feedback resistor 40 (resistance value Roc) and the feedback capacitor 50 (capacity value Coc), thereby forming an RC type oscillator circuit.

Since the frequency (oscillation frequency) of the oscillation signal Vosc changes depending on the product (RC time constant) of the capacitance value Coc of the feedback capacitance 50 and the resistance value Roc of the feedback resistor 40, in the oscillation circuit 100, the oscillation frequency can be adjusted by variably controlling the resistance value Roc based on the control signal CNT2.

Furthermore, as will be described in detail later, the oscillation circuit 100 can adjust the duty ratio of the oscillation signal by selecting and controlling the first-stage inverter paths IPT1 to IPTM based on the control signal CNT1. The control circuit 90 generates the control signals CNT1 and CNT2 according to instructions from outside the oscillation circuit 100 or according to the actual values of the frequency and duty ratio of the oscillation signal Vosc. Note that the actual values of the frequency and duty ratio of the oscillation signal Vosc may be provided by measurement results from outside the oscillation circuit 100. The function of the control circuit 90 may also be provided outside the oscillation circuit 100. That is, the control signals CNT1 and CNT2 may be generated outside the oscillation circuit 100 and input to the selection unit 20 and the resistance control unit 45.

Next, a specific configuration example of the oscillator circuit according to the first embodiment will be described.
FIG. 2 shows a circuit diagram illustrating a configuration example of an oscillator circuit 100a according to the first embodiment.

As shown in Figure 2, in the oscillator circuit 100a, M = 3 in Figure 1, and the first logic circuit 10 has inverters INV11 to INV13 connected in parallel to the input node Na. Also, the second logic circuit 30 has two inverters INV2 and INV3 connected in series. Each of the inverters INV11 to INV13 corresponds to an embodiment of the "first logic inversion circuit", and each of the inverters INV2 and INV3 corresponds to an embodiment of the "second logic inversion circuit". Also, the first stage inverter paths IPT1 to IPT3 correspond to an embodiment of the "multiple signal paths".

Figure 3 is a circuit diagram explaining the configuration of each inverter. Figure 3 shows the circuit configuration of inverter INV, which collectively refers to inverters INV11 to INV13, INV2, and INV3, which are shown as representative examples of logic inversion circuits that make up the first logic circuit 10 and the second logic circuit 30.

As shown in Figure 3, the inverter INV has a P-type transistor MP0 and an N-type transistor MN0 connected in series between a power supply line PL and a ground line NL. The power supply line PL supplies a power supply voltage VDD corresponding to an H level, and the ground line NL supplies a ground voltage GND corresponding to an L level. In this embodiment, each transistor can be configured by a field effect transistor, for example, a MOS (Metal Oxide Semiconductor) transistor.

The P-type transistor MP0 has a gate width Wp and a gate length Lp, and the N-type transistor MN0 has a gate width Wn and a gate length Ln. The gates of the P-type transistor MP0 and the N-type transistor MN0 have parasitic capacitances Cpp and Cpn, which include gate capacitance and wiring capacitance, respectively, so the gate voltage changes with the charging and discharging of the parasitic capacitances Cpp and Cpn.

A common input voltage Vin is input to the gates of the P-type transistor MP0 and the N-type transistor MN0. For example, in the first-stage inverter, the gates of the P-type transistor MP0 and the N-type transistor MN0 are commonly connected to the input node Na.

An output voltage Vout is generated at an output node No, which corresponds to the connection point between the drains of P-type transistor MP0 and N-type transistor MN0. The inverter INV inverts the logical level of the input voltage Vin based on the inversion threshold voltage Vinv to set the output voltage Vout. Specifically, when Vin<Vinv, the P-type transistor MP0 is turned on to set Vout=H level, while when Vin≧Vinv, the N-type transistor MN0 is turned on to set Vout=L level.

In this embodiment, the L level and ground voltage GND are an example of a "first logic level" and a "first voltage", and the H level and power supply voltage VDD are an example of a "second logic level" and a "second voltage". Thus, the ground line NL corresponds to an example of a "first wiring", and the power supply line PL corresponds to an example of a "second wiring". Also, in the inverter INV, the P-type transistor MP0 corresponds to a "P-type field effect transistor", and the N-type transistor MN0 corresponds to an "N-type field effect transistor".

Here, further using the threshold voltage Vtn and mobility μn of N-type transistor MN0 and the threshold voltage Vtp and mobility μp of P-type transistor MP0, it is known that the inversion threshold voltage Vinv of inverter INV is roughly represented by the following equations (1) and (2).

Vinv=(VDD-Vtp+Vtn・K)/(1+K)...(1)
K=√(Kn/Kp)…(2)
In the formula (2), Kn=μn·(Wn/Ln), Kp=μp·(Wp/Lp).

Therefore, it can be understood that the inversion threshold voltage Vinv of the inverter INV can be made to have different values by changing the ratio of the transistor size (Wp/Lp) of the P-type transistor MP0 and the transistor size (Wn/Ln) of the N-type transistor MN0. That is, the inverters INV11 to INV13 in FIG. 2 are designed to have different values for the ratio of the above-mentioned transistor sizes (Wn/Ln) and (Wp/Lp), and as a result, the parameter value K in equation (2) is different from one another. As a result, the inverters INV11 to INV13 are configured to have different inversion threshold voltages Vinv from one another.

In this specification, each logic inversion circuit constituting the first logic circuit 10 and the second logic circuit 30 is described as an inverter, but as long as a logic inversion operation between the input voltage Vin and the output voltage Vout can be realized in the same way as the inverter INV shown in FIG. 3, it is also possible to configure the first logic circuit 10 and the second logic circuit 30 using, for example, a NAND gate or a NOR gate in which the voltage of some input terminals is fixed, other than the inverter INV shown in FIG. 3. When a NAND gate or a NOR gate is used, it is also possible to input an enable signal to the above-mentioned part of the input terminal to which the input voltage Vin is not input. Here, the enable signal is a signal that controls the activation and deactivation of a certain function, and when the enable signal is off, the function is stopped. For the oscillation circuit 100a, when the enable signal is off, the output of the inverter is fixed to the L level or H level, so that the oscillation is stopped and the oscillation signal Vosc is also fixed to a certain logic level.

Referring again to Figure 2, the input voltage Vin (Figure 2) of the inverters INV11 to INV13 is common and is the voltage VA of the input node Na. The inverters INV11 to INV13 each have a different inversion threshold voltage Vinv, and their respective output voltages Vout (Figure 2) are represented by voltages V1 to V3.

2 again, the selection unit 20 has switch circuits ISW1 to ISW3 arranged in series with inverters INV11 to INV13, respectively, between the input node Na and a node Nb corresponding to the input node of the inverter INV2. Each of the switch circuits ISW1 to ISW3 can be configured by a transfer gate using at least one of a P-type transistor and an N-type transistor.

As a result, three (M=3) first-stage inverter paths IPT1 to IPT3 are connected in parallel between the input node Na and the node Nb. In FIG. 2, the first-stage inverter paths IPT1 to IPT3 are configured to include inverters INV11 to INV13, each of which has a different inversion threshold voltage.

For example, the switch circuit ISW1 can be configured by connecting in parallel an N-type transistor MN4, whose gate receives the control signal VISW1, and a P-type transistor MP4, whose gate receives the control signal VISW1B (the inverted signal of VISW1). Setting VISW1 = H level (VISW1B = L level) turns the switch circuit ISW1 on. Conversely, setting VISW1 = L level (VISW1B = H level) turns the switch circuit ISW1 off.

Similarly, the switch circuit ISW2 is configured by a parallel connection of an N-type transistor MN5, whose gate receives the control signal VISW2, and a P-type transistor MP5, whose gate receives the control signal VISW2B (the inverted signal of VISW2). The switch circuit ISW3 is configured by a parallel connection of an N-type transistor MN6, whose gate receives the control signal VISW3, and a P-type transistor MP6, whose gate receives the control signal VISW3B (the inverted signal of VISW3).

The on/off of the switch circuits ISW2 and ISW3 is also controlled by the control signals VISW2 (VISW2B) and VISW3 (VISW3B), respectively. The control signals VISW1 to VISW3 (VISW1B to VISW3B) shown in Figure 2 constitute the control signal CNT1 of the selection unit 20 shown in Figure 1.

The selection unit 20 is controlled by the control signal CNT1 to selectively turn on one of the switch circuits ISW1 to ISW3 while turning off the remaining two. As a result, one of the multiple first-stage inverter paths IPT1 to IPT3 is selected, and one of the output voltages V1 to V3 of the inverters INV11 to INV13, which have different inversion threshold voltages, is selectively transmitted to the node Nb with respect to the common input voltage VA. The voltage VB at the node Nb becomes the input voltage Vin (Figure 3) of the inverter INV2.

The inverters INV2 and INV3 are connected in series between the nodes Nb and Nd via the node Nc. The inverter INV2 generates a voltage VC at the node Nc that is the inversion of the logical level of the voltage VB at the node Nb, based on the inversion threshold voltage of the inverter INV2. The inverter INV3 generates a voltage at the node Nd that is the inversion of the logical level of the voltage VC at the node Nc, based on the inversion threshold voltage of the inverter INV3, as the oscillation signal Vosc.

The feedback capacitance 50 includes a capacitor C1 (capacitance value Coc) connected between the node Nc and the input node Na. The feedback resistor 40 includes I resistance elements (I: natural number) connected between the node Nd and the input node Na. In the example of FIG. 2, I=3, and the feedback resistor 40 has resistance elements R1 to R3 connected in series. Hereinafter, the resistance values of the resistance elements R1 to R3 will also be represented as R1 to R3, respectively. The resistance value Roc of the feedback resistor 40 is variably controlled by the resistance control unit 45.

The resistance control unit 45 has transistor switches MN1 to MN3 connected in parallel with I (I=3) resistance elements R1 to R3, respectively. The gates of the transistor switches MN1 to MN3 receive control signals VRSW1 to VRSW3, which constitute the control signal CNT2 in FIG. 1, respectively.

When the transistor switches MN1 to MN3 are on, they each form a bypass path for the parallel-connected resistor elements R1 to R3. Therefore, when all of the transistor switches MN1 to MN3 are turned off, the resistance value Roc of the feedback resistor 40 becomes R1 + R2 + R3, whereas when any of the transistor switches MN1 to MN3 is turned on, the resistance value Roc decreases from R1 + R2 + R3.

In this way, the control signals VRSW1 to VRSW3 control the on/off of the transistor switches MN1 to MN3, thereby variably controlling the resistance value Roc of the feedback resistor 40. For example, when R1=Ru, R2=2·Ru, and R3=4·Ru are set according to the factorials of 2, the resistance value Roc of the feedback resistor 40 can be variably controlled in 2 ³ =8 steps by the 3-bit control signals VRSW1 to VRSW3.

Next, the operation of the oscillator circuit will be described in detail.
FIG. 4 is a circuit diagram of an oscillator circuit 100# according to a comparative example.

The oscillator circuit 100# shown in Fig. 4 has a circuit configuration in which the selection unit 20 is omitted in the oscillator circuit 100a shown in Fig. 2, the first logic circuit 10 is composed of a single inverter INV1, and the inversion threshold voltage Vinv of the first-stage inverter is fixed. In other words, the oscillator circuit 100a according to the first embodiment has a configuration in which the inversion threshold voltage Vinv of the first-stage inverter INV1 in the oscillator circuit 100# can be switched between M stages.

In the oscillator circuit 100#, a feedback capacitance 50 is connected between the node Nc and the input node Na, and a feedback resistor 40 is connected between the node Nd and the input node Na, similar to the oscillator circuit 100a, for a multi-stage inverter consisting of a plurality of inverters INV1 to INV3 connected in series. That is, the feedback capacitance 50 is connected between two nodes between which an even number of inverters (logic inversion circuits) are connected in series, and the feedback resistor 40 is connected between two nodes between which an odd number of inverters (logic inversion circuits) are connected in series. In the oscillator circuit 100#, both the capacitance value Coc of the feedback capacitance 50 and the resistance value Roc of the feedback resistor 40 are fixed values.

Figure 5 is an operational waveform diagram of the oscillator circuit 100# shown in Figure 4. Figure 5 shows the waveforms of the voltage VA at the input node Na, i.e., the input voltage VA of the first stage inverter (INV1), and the oscillation signal Vosc generated at the node Nd, i.e., the output voltage of the final stage inverter (INV3).

As shown in Figure 5, at time ta, the oscillation signal Vosc, which is the output voltage, is at H level, so the input voltage VA rises toward the power supply voltage VDD with a delay due to the RC time constant (Roc·Coc), which is the product of the resistance value Roc of the feedback resistor 40 and the capacitance value Coc of the feedback capacitance 50.

At time tb, when the input voltage VA reaches the inversion threshold voltage Vinv of the inverter INV1, the output of the inverter INV1 (voltage VB) changes from H level to L level, and accordingly, the oscillation signal Vosc, which is the output of the inverter INV13, changes from H level (VDD) to L level (GND). At this time, the voltage VC of the node Nc to which the feedback capacitance 50 is connected changes from L level (GND) to H level (VDD), so that the input voltage VA rises from the inversion threshold voltage Vinv to VDD due to capacitive coupling. As a result, at time tb, VA = Vinv + VDD.

After time tb, the oscillation signal Vosc is at L level, so the voltage VA drops toward GND with a delay due to the RC time constant (Roc·Coc). Then, at time tc, when the input voltage VA drops to the inversion threshold voltage Vinv, the output of the inverter INV13, the oscillation signal Vosc, changes from L level (GND) to H level (VDD), in response to the output of the inverter INV1 (voltage VB) changing from L level to H level. At this time, the voltage VC changes from H level (VDD) to L level (GND), so the input voltage VA drops from the inversion threshold voltage Vinv by VDD due to capacitive coupling. As a result, at time tb, VA = Vinv - VDD.

After time tc, as at time ta, the input voltage VA rises with a delay due to the RC time constant (Roc·Coc), and at time td when the input voltage VA rises to the inversion threshold voltage Vinv, the input voltage VA and the oscillation signal Vosc experience a voltage change similar to that at time tb. The behavior of the input voltage VA and the oscillation signal Vosc between times td and te is the same as between times tb and tc, and the behavior of the input voltage VA and the oscillation signal Vosc after time te is the same as after time tc. Oscillation occurs due to periodic voltage changes in such multiple inverter stages, generating an oscillation signal Vosc that periodically transitions between H level and L level.

If the length of the H-level period of the oscillation signal Vosc is T1 and the length of the L-level period is T2, as shown in Non-Patent Document 1, the oscillation period Tosc, which is the period length of the oscillation signal Vosc, is expressed by the following formula (3). However, in formula (3), RC = Roc · Coc. Also, VX and VY in formula (3) are expressed by formulas (4) and (5), respectively.

Tosc=T1+T2=RC・(ln(VX)+ln(VY))...(3)
VX=(VDD+Vinv)/Vinv...(4)
VY=(Vinv-2・VDD)/(Vinv-VDD)...(5)
As can be seen from equations (3) to (5), the oscillation period Tosc, which is the reciprocal of the oscillation frequency fosc, depends on the power supply voltage VDD, the inversion threshold voltage Vinv of the first-stage inverter, and the time constant RC. Since the on-chip resistance and capacitance values include fluctuations due to process variations and temperature, there is a risk that the RC time constant will deviate from the design value, causing the oscillation frequency to deviate from the desired value.

2, the resistance value Roc of the feedback resistor 40 can be variably adjusted by the control signal CNT2 (VRSW1 to VRSW3) to the resistance control unit 45. This makes it possible to maintain the oscillation period Tosc at a desired value by changing RC = Roc · Coc in equation (3).

Figure 6 is a diagram explaining the operation of the resistance control unit 45 in the oscillator circuit 100a according to embodiment 1. Figure 6 shows the operation of the resistance control unit 45 when I = 3, as illustrated in Figure 2.

As shown in Figure 6, the resistance value Roc of the feedback resistor 40 can be adjusted in eight steps from 0 to 7·Ru in increments of Ru by combining the control signals VRSW1 to VRSW3 with "0" (L level) and "1" (H level).

For example, if Roc = 4·Ru is used as the reference value and each circuit constant is initially set so that the oscillation frequency is the desired value, the oscillation frequency can be adjusted by operating the oscillator circuit 100a in a state of (VRSW1, VRSW2, VRSW3) = (0, 0, 1) and setting the control signals VRSW1 to VRSW3 according to the results of monitoring the oscillation period Tosc.

Specifically, when the monitored oscillation period Tosc is longer than the design value, i.e., when the oscillation frequency f osc is lower than the desired value, the oscillation frequency f osc can be increased by determining the control signals VRSW1 to VRSW3 so that the resistance value Roc of the feedback resistor 40 decreases from 4·Ru.

Conversely, if the monitored oscillation period Tosc is shorter than the design value, i.e., if the oscillation frequency fosc is higher than the desired value, the oscillation frequency fosc can be lowered by determining the control signals VRSW1 to VRSW3 so that the resistance value Roc of the feedback resistor 40 increases from 4·Ru.

2, an example in which I=3 has been described, but the value of I is arbitrary. Similarly, by setting the resistance values of the I resistive elements constituting the feedback resistor 40 in accordance with a factorial of 2, the resistance value Roc can be variably controlled in ^2I steps by an I-bit control signal.

Next, we will explain the fluctuation in the duty ratio of the oscillation signal Vosc due to the influence of the inversion threshold voltage Vinv of the first stage inverter. As will be explained below, the fluctuation in the duty ratio cannot be accommodated by adjusting the resistance value Roc of the feedback resistor 40.

If the inversion threshold voltage of the first stage inverter is Vinv = VDD/2, then in the above equations (4) and (5), VX = (VDD + Vinv) / Vinv = 3, and VY = (Vinv-2 * VDD) * (Vinv-VDD) = 3. Therefore, in equation (3), between ln(VX), which corresponds to T1/RC, and ln(VY), which corresponds to T2/RC, ln(VX) = ln(VY). Also, Tosc = RC * 2ln(3) ≈ 2.2RC.

Therefore, if the inversion threshold voltage Vinv = VDD/2, as shown in Figure 5, T1 = T2, that is, the duty ratio of the oscillation signal Vosc is 50(%):50(%).

For example, when VDD=1.8 (V), Vtp=0.7 (V), and Vtn=0.7 (V), if K=1 in formula (1), then Vinv=VDD/2=0.9 (V). To achieve K=1, the ratios of (Wp/Lp) and (Wn/Ln) between the P-type and N-type transistors that make up the first-stage inverter should be set according to the inverse ratio of the mobilities μp and μn, as shown in formula (2). Assuming μn=2μp, then K=1 can be achieved by setting (Wp/Lp)=2·(Wn/Ln).

In this embodiment, (μn/μp) = 2 is fixed, and examples of transistor size design are explained below as appropriate, but the actual value of (μn/μp) may vary depending on the process parameters. Therefore, by replacing the ratio of μp and μn in the explanation of this embodiment with the values in the actual process, it is possible to configure the oscillator circuit of this embodiment to suit any process parameters.

If Vinv = VDD/2, the duty ratio of the oscillation signal Vosc can be set to an ideal state, that is, 50(%):50(%), as shown in Figure 5. If the inversion threshold voltage Vinv deviates from VDD/2 from this state, a time difference occurs between T1 and T2, and the duty ratio deviates from 50(%):50(%).

Figure 7 shows an operating waveform diagram of oscillator circuit 100# when Vinv = VDD/3, which explains the relationship between the inversion threshold voltage of the first stage inverter and the duty ratio of the oscillation signal.

When Vinv = VDD/3, in the above equations (4) and (5), VX = (VDD + Vinv)/Vinv = 4, VY = (Vinv-2 * VDD) * (Vinv-VDD) = 2.5. Therefore, in equation (3), ln(VX) corresponding to T1/RC and ln(VY) corresponding to T2/RC are ln(VX) = ln(4) and ln(VY) = ln(2.5). Also, Tosc = RC * (ln(4) + ln(2.5)) ≒ 2.302RC.

The ratio of T1 to T2 is ln(4):ln(2.5) ≈ 1.386:0.916. At this time, as shown in Figure 7, the duty ratio of the oscillation signal Vosc is approximately 60(%):40(%), which deviates from 50(%):50(%). For example, in a system that uses the oscillation signal Vosc as a clock signal, in an application in which circuits are operated using both the rising and falling edges of the clock signal as triggers, a breakdown in the duty ratio may cause malfunctions in the circuit operation.

In response to this, in the oscillator circuit 100a of embodiment 1, by selecting M first-stage inverter paths IPT, one of the inverters INV11 to INV13, which have different inversion threshold voltages Vinv, is made the first-stage inverter, thereby adjusting the duty ratio through the inversion threshold voltage Vinv.

For example, when M = 3, inverters INV11 to INV13 can be provided that are designed for parameter value K in equation (2) of 1, √8, and √(1/8), respectively. This makes it possible to adjust the inversion threshold voltage Vinv of the first-stage inverter to near VDD/2 even if the threshold voltages Vtp, Vtn of the P-type and M-type transistors that make up the first-stage inverter vary within a range of 0.6 (V) to 0.8 (V) due to process variations with respect to the above-mentioned design value of 0.7 (V).

First, if process variations of Vtp = 0.8 (V) and Vtn = 0.6 (V) occur, when K = 1 in the above formula (1), Vinv = 0.8 (V) ≒ 0.444 VDD. As a result, there is a concern that a deviation in the duty ratio will occur in a manner such that T1 is longer than T2, as in FIG. 7. Specifically, substituting Vinv = 0.444 VDD into formulas (3) to (5) gives T1:T2 = 53.4 (%):46.6 (%). In other words, the duty ratio during the L level period increases.

On the other hand, the ratios of (Wp/Lp) and (Wn/Ln) in the P-type and N-type transistors of the first-stage inverter can be designed so that K = √(1/8) in equation (2). This makes it possible to make Vinv ≒ 0.9 (V) = VDD/2 for VDD = 1.8 (V) even when Vtp = 0.8 (V) and Vtn = 0.6 (V) in equation (1).

Conversely, if process variations of Vtp = 0.6 (V) and Vtn = 0.8 (V) occur, when K = 1 in the above formula (1), Vinv = 1.0 (V) ≒ 0.556 VDD. This raises concerns that a deviation in the duty ratio will occur in a manner such that T2 is longer than T1, contrary to FIG. 7. Specifically, substituting Vinv = 0.556 VDD into formulas (3) to (5) gives T1:T2 = 46.6 (%):53.4 (%). In other words, the duty ratio during the L level period decreases.

In contrast, if the ratios of (Wp/Lp) and (Wn/Ln) in the P-type and N-type transistors of the first stage inverter are K = √8 in equation (2), then even when Vtp = 0.6 (V) and Vtn = 0.8 (V) in equation (1), Vinv ≒ 0.9 (V) = VDD/2 for VDD = 1.8 (V).

As an example, the inverters INV11 to INV13 of the first logic circuit 10 can be designed in a lower order so that K = 1, K = √8, and K = √(1/8).

For the reference inverter INV11, by setting Wn/Ln = Wmin/Lmin and Wp/Lp = 2 x Wmin/Lmin, a first-stage inverter can be constructed in which K = 1 in equation (2).

For inverter INV12, by setting Wn/Ln = Wmin/Lmin and Wp/Lp = 16 x Wmin/Lmin, a first-stage inverter with K = √(1/8) in equation (2) can be configured. For inverter INV13, by setting Wn/Ln = 4 x Wmin/Lmin and Wp/Lp = Wmin/Lmin, a first-stage inverter with K = √8 in equation (2) can be configured.

As shown in Fig. 8, the selection unit 20 selects patterns PT1 to PT3 in which the first-stage inverter paths IPT1 to IPT3 are different in accordance with the control signals VISW1 to VISW3 shown in Fig. 2. This makes it possible to selectively set inverters INV11 to INV13, each of which has a different inversion threshold voltage Vinv corresponding to the parameter values K = 1, √(1/8), and √8, as the first-stage inverters.

Specifically, in pattern PT1, (VISW1, VISW2, VISW3) = (1, 0, 0) allows inverter INV11 with K = 1 to be used as the first-stage inverter. In contrast, in pattern PT2, (VISW1, VISW2, VISW3) = (0, 1, 0) allows inverter INV12 with K = √(1/8) to be used as the first-stage inverter. By applying pattern PT2, it is possible to reduce the ratio of the H-level period compared to pattern PT1.

In pattern PT3, (VISW1, VISW2, VISW3) = (0, 0, 1), inverter INV13 with K = √8 is used as the first stage inverter. By applying pattern PT3, the ratio of the H level period can be increased compared to pattern PT1.

Figure 9 shows a flowchart of a control process for adjusting the duty ratio in an oscillator circuit of embodiment 1.

9, the control circuit 90 obtains the duty ratio DT1 of the oscillation signal Vosc when the oscillation circuit 100a is operated in the pattern PT1 of Fig. 8 in step (hereinafter simply referred to as "S") S110. The duty ratio DT1 indicates the ratio of the L level period to the oscillation period, that is, T1/(T1+T2).

As described above, the measurement of the duty ratio DT1 may be performed by the control circuit 90, or may be performed by monitoring the oscillation signal Vosc external to the oscillator circuit 100a. In this case, the measured value of the duty ratio DT1 obtained external to the oscillator circuit 100a is input to the control circuit 90.

In S120, the control circuit 90 determines whether the duty ratio DT1 obtained in S110 is within a reference range that includes 50(%). The reference range can be set to, for example, 50±DTr(%). In the above example assuming a fluctuation in the range of 46.6(%) to 53.4(%), DTr can be set to approximately 2(%).

When the duty ratio DT1 is within the reference range (NO in S120), the control circuit 90 advances processing to S140 and applies pattern PT1 to operate the oscillator circuit 100a.

On the other hand, when the duty ratio DT1 is outside the reference range (YES judgment in S120), the control circuit 90 judges in S130 whether the duty ratio DT1 is less than 50 (%).

When DT1>50(%) (YES in S130), the control circuit 90 advances the process to S150. In S150, in order to reduce the duty ratio, the oscillator circuit 100a operates by applying pattern PT2, in which the parameter value K of the first stage inverter is smaller than pattern PT1 (K=1).

Conversely, when DT1<50(%) (NO in S130), the control circuit 90 advances the process to S160. In S150, in order to increase the duty ratio, the oscillator circuit 100a operates by applying pattern PT3, in which the parameter value K of the first stage inverter is greater than that of pattern PT1 (K=1).

In this way, in the oscillator circuit 100a of embodiment 1, by configuring the first-stage inverter by selecting multiple inverters with different inversion threshold voltages Vinv, the duty ratio of the oscillation signal of the RC type oscillator circuit can be adjusted with a simple configuration.

In addition, in embodiment 1, the inversion threshold voltage Vinv is made different through the parameter value K by designing the transistor sizes (Wp/Lp), (Wn/Ln) of the P-type and N-type transistors that constitute the inverters INV11 to INV13.

For this reason, in Figure 2, it is preferable to design the transistor sizes of the N-type transistors MN4 to MN6 and the P-type transistors MP4 to MP6, which constitute the switch circuits ISW1 to ISW3 connected in series with the inverters INV11 to INV13, respectively, in coordination with the inverters INV11 to INV13.

Here, for each of the inverters INV11 to INV13, the inverse (Kp/Kn) of (Kn/Kp) shown in equation (2) is defined as the inverter size Kinv. The ratio of the inverter sizes Kinv between the inverters INV11, INV12, and INV13 is 1:8:(1/8).

In each of the switch circuits ISW1 to ISW3, the ratio of the transistor size (Wn/Ln) of the N-type transistors (MN4 to MN6) to the transistor size (Wp/Lp) of the P-type transistors (MP4 to MP6) is designed to be equal. For example, according to the inverse ratio of the mobilities μp and μn described in equation (2), it can be set to (Wp/Lp) = 2 × (Wn/Ln).

On the other hand, it is preferable that the transistor size ratio between the switch circuits ISW1 to ISW3 be 1:8:(1/8), which is equivalent to the inverter size Kinv of the inverters INV11 to INV13 connected in series.

For example, in the switch circuit ISW3 connected in series with the inverter INV13, the transistor size of MN6 can be set to Wmin/Lmin (=Wnmin/Lmin), while the transistor size of MP6 can be set to 2×Wmin/Lmin (=Wpmin/Lmin). In other words, Wpmin=2×Wmin.

On the other hand, in the switch circuit ISW1 connected in series with the inverter INV11, the transistor size of MN4 is set to 8 x Wmin/Lmin (= 8 x Wnmin/Lmin) while the transistor size of MP4 is set to 16 x Wmin/Lmin (= 8 x Wpmin/Lmin), thereby making it possible to align the transistor size ratio between the switch circuits ISW1 and ISW3 to 1:(1/8) = 8:1, which is the inverter size ratio between the inverters INV11 and INV13.

Furthermore, in the switch circuit ISW2 connected in series with the inverter INV12, the transistor size of MN5 is set to 64 x Wmin/Lmin (= 64 x Wnmin/Lmin) while the transistor size of MP5 is set to 128 x Wmin/Lmin (= 64 x Wpmin/Lmin), thereby making it possible to align the transistor size ratio between the switch circuits ISW1 and ISW2 with the inverter size ratio of 1:8 between the inverters INV11 and INV12.

For the inverters INV2 and INV3 constituting the second logic circuit 30, the ratio between the transistor size (Wp/Lp) of the P-type transistor MP0 (FIG. 3) and the transistor size (Wn/Ln) of the N-type transistor MN0 (FIG. 3) is set according to the inverse ratio of the mobilities μp and μn described above. For the inverter INV2, it is preferable to design the transistor sizes of the P-type transistor MP0 and the N-type transistor MN0 so that the inverter INV2 has a larger driving force than the inverters INV11 to INV13 constituting the first logic circuit 10.

Furthermore, since inverter INV3 needs to generate oscillation signal Vosc using feedback resistor 40, feedback capacitor 50, and the supply destination of oscillation signal Vosc as loads, it is necessary to design the transistor sizes of P-type transistor MP0 and N-type transistor MN0 so that it has even greater driving force than inverter INV2.

Embodiment 2.
FIG. 10 is a circuit diagram illustrating an example of the configuration of an oscillator circuit 100b according to the second embodiment.

As shown in FIG. 10, the oscillator circuit 100b differs from the oscillator circuit 100a (FIG. 2) of embodiment 1 in that it further includes a delay adjustment circuit 25.

The delay adjustment circuit 25 includes dummy switch circuits DSW1 to DSW3 connected in series with the switch circuits ISW1 to ISW3 constituting the selection unit 20 in each of the first-stage inverter paths IPT1 to IPT3. Each of the dummy switch circuits DSW11 to DSW13 has a P-type transistor and an N-type transistor connected in parallel. The source and drain of each of the P-type transistors and the N-type transistors are connected. The dummy switch circuits DSW11 to DSW13 are arranged to add adjustment capacitance for signal delay to each of the first-stage inverter paths IPT1 to IPT3.

The dummy switch circuit DSW1 has an N-type transistor MN4D and a P-type transistor MP4D connected in parallel. A control signal VISW1B common to the P-type transistor MP4 of the switch circuit ISW1 connected in series with the dummy switch circuit DSW1 is input to the gate of the N-type transistor MN4D. Similarly, a control signal VISW1 common to the N-type transistor MN4 of the switch circuit ISW1 is input to the gate of the P-type transistor MP4D. That is, in the dummy switch circuit DSW1, the control signals VISW1 and VISW1B common to the switch circuit ISW1 are input to the gate of a transistor of the opposite conductivity type to the switch circuit ISW1. As a result, the dummy switch circuit DSW1 performs on-off operations complementary to the switch circuit ISW1.

Similarly, the dummy switch circuit DSW2, which is connected in series with the switch circuit ISW2, has an N-type transistor MN5D and a P-type transistor MP5D connected in parallel. The control signals VISW2 and VISW2B, which are common to the switch circuit ISW2, are input to the gates of the N-type transistor MN5D and the P-type transistor MP5D, respectively, of the transistors of the opposite conductivity type to that of the switch circuit ISW2. In other words, the dummy switch circuit DSW2 performs on-off operations complementary to the switch circuit ISW2.

The dummy switch circuit DSW3, which is connected in series with the switch circuit ISW3, has an N-type transistor MN6D and a P-type transistor MP6D connected in parallel. The control signals VISW3 and VISW3B, which are common to the switch circuit ISW3, are input to the gates of the N-type transistor MN6D and the P-type transistor MP6D, respectively, of the transistors of the opposite conductivity type to that of the switch circuit ISW3. In other words, the dummy switch circuit DSW3 performs on-off operations complementary to the switch circuit ISW3.

Therefore, in each of the dummy switch circuits DSW1 to DSW3, when the series-connected switches (ISW1 to ISW3) are on, an L level (GND) is input to the gate of the N-type transistor MND (collectively referring to MN4D to MN6D), while an H level (VDD) is input to the gate of the P-type transistor MPD (collectively referring to MP4D to MP6D).

FIG. 11 is a conceptual diagram for explaining the operation of the dummy switch.
The dummy switch circuit DSW shown in FIG. 11 collectively denotes the dummy switch circuits DSW1 to DSW3 shown in FIG. 10, and has an N-type transistor MND and a P-type transistor MPD connected in parallel.

Now consider the operation of the dummy switch circuit DSW when an L level (GND) is input to the gate of the N-type transistor MND and an H level (VDD) is input to the gate of the P-type transistor MPD, and a pulse signal Spl is input to the left side of the figure, i.e., the drain of the N-type transistor MND and the source of the P-type transistor MPD.

At the rising edge of the pulse signal Spl, when it transitions from the L level to the H level, the gate capacitance Cgdn (parasitic capacitance between the gate and drain) of the N-type transistor MND is charged, and the source voltage of the N-type transistor MND rises. As a result, the rising edge of the pulse signal Spl is transmitted by the dummy switch circuit DSW.

On the other hand, at the falling edge of the pulse signal Spl when it transitions from H level to L level, when the gate capacitance Cgsp (parasitic capacitance between the gate and source) of the P-type transistor MPD is charged, the drain voltage of the P-type transistor MPD drops. As a result, the falling edge of the pulse signal Spl is transmitted by the dummy switch circuit DSW.

Therefore, when the pulse signal Spl passes through, the dummy switch circuit DSW can impart a first delay time that depends on the gate capacitance Cgdn to the rising edge and a second delay time that depends on the gate capacitance Cgsp to the falling edge. In this embodiment, the transition from L level to H level at the rising edge corresponds to the "first transition", and the transition from H level to L level at the falling edge corresponds to the "second transition".

In each of the dummy switch circuits DSW1 to DSW3 included in the delay adjustment circuit 25 (FIG. 10), the gate capacitances Cgsp and Cgdn are designed so that the first delay time and the second delay time are equivalent. In this case, the delay time provided by the dummy switch circuits DSW1 to DSW3 basically does not affect the duty ratio in the downstream inverters INV2 and INV3 (second logic circuit 30). In other words, the delay adjustment circuit 25 corresponds to one embodiment of the "first delay adjustment circuit."

On the other hand, the transistor sizes of the P-type transistors MPD and N-type transistors MND in the dummy switch circuits DSW1 to DSW3 are designed so that different delay times are imparted between the first-stage inverter paths IPT1 to IPT3. Specifically, the delay times imparted by the dummy switch circuits DSW1 to DSW3 are set so that the sum of the delay times imparted by the switch circuits ISW1 to ISW3 and the dummy switch circuits DSW1 to DSW3 is equal between the first-stage inverter paths IPT1 to IPT3.

For example, as described above, if a ratio of 1:8:(1/8) is set between the transistor sizes of the switch circuits ISW1 to ISW3 to correspond to the inverter size ratio of the inverters INV11 to INV13, then the inverse ratio of 1:(1/8):8 can be given between the transistor sizes of the dummy switch circuits DSW1 to DSW3.

In this case, the transistor sizes of the N-type transistor MN5D and the P-type transistor MP5D that constitute the dummy switch circuit DSW2 connected in series with the switch circuit ISW2 can be set to Wnmin/Lmin and Wpmin/Lmin as described in embodiment 1.

Furthermore, the transistor sizes of the N-type transistor MN4D and the P-type transistor MP4D that constitute the dummy switch circuit DSW1 connected in series with the switch circuit ISW1 can be set to 8×Wnmin/Lmin and 8×Wpmin/Lmin, respectively. This allows the transistor size ratio between the dummy switch circuits DSW1 and DSW2 to be the inverse ratio (1:(1/8) = 8:1) of the transistor size ratio (1:8) between the switch circuits ISW1 and ISW2.

Similarly, the transistor sizes of the N-type transistor MN6D and the P-type transistor MP6D constituting the dummy switch circuit DSW3 connected in series with the switch circuit ISW3 can be set to 64×Wnmin/Lmin and 64×Wpmin/Lmin, respectively. This allows the transistor size ratio between the dummy switch circuits DSW1 and DSW3 to be the inverse ratio (1:8) of the transistor size ratio (1:(1/8)) between the switch circuits ISW1 and ISW3.

This makes it possible to suppress the difference in delay capacitance provided to the output signal paths of the inverters INV11 to INV13 between the first-stage inverter paths IPT1 to IPT3 selected to adjust the duty ratio of the oscillation signal Vosc. In other words, if there is a large difference in the transistor sizes of the switch circuits ISW1 to ISW3, in the oscillator circuit 100a according to the first embodiment, the frequency of the oscillation signal Vosc may differ depending on which of the first-stage inverter paths IPT1 to IPT3 is selected.

In contrast, in the oscillator circuit 100b according to the second embodiment, the arrangement of the delay adjustment circuit 25 including the dummy switch circuits DSW1 to DSW3 makes it possible to suppress the fluctuation of the oscillation frequency that depends on the selection of the first-stage inverter paths IPT1 to IPT3 for adjusting the duty ratio of the oscillation signal Vosc. As a result, in addition to the same effect as in the first embodiment, the setting accuracy of the oscillation frequency can be improved.

It is also possible to adopt a configuration in which a switch and a capacitor connected in series are used for the first-stage inverter paths IPT1 to IPT3, and capacitance is added by turning the switch on and off. However, in such a configuration, the combined capacitance of the switch and the capacitor is applied to the selected first-stage inverter path, making it difficult to ensure linearity. In contrast, by using a dummy switch circuit DSW, it becomes easier to adjust the capacitance value of the delay capacitance added to the first-stage inverter paths IPT1 to IPT3.

Variation example 1 of embodiment 2.
In the second embodiment, an example has been described in which the first delay time (rising edge) and the second delay time (falling edge) of each dummy switch circuit DSW are made equal. However, by intentionally setting a difference between the two, it is also possible to use the dummy switch circuit DSW for duty ratio adjustment.

Referring again to Figure 11, by adjusting the gate capacitance of the P-type transistor MPD and the N-type transistor MND that constitute the dummy switch circuit DSW, a difference can be intentionally created between the first and second delay times.

For example, since the gate capacitance of a transistor has the characteristic of changing in proportion to the gate surface area, by designing the transistor sizes (Wp/Lp) and (Wn/Ln) of the P-type transistor MPD and the N-type transistor MND, the gate capacitances Cgsp and Cgdn can be adjusted so that an intentional difference is generated between the first delay time of the rising edge and the second delay time of the falling edge.

Figure 12 is a circuit diagram illustrating an example configuration of an oscillator circuit 100c relating to variant example 1 of embodiment 2.

Referring to FIG. 12, the oscillator circuit 100c differs from the oscillator circuit 100a (FIG. 2) of embodiment 1 in that the first logic circuit 10 is composed of one inverter INV1 and in that it further includes a delay adjustment circuit 26.

The output signal of inverter INV1 is branched into multiple (M=3) first-stage inverter paths IPT1 to IPT3. In oscillator circuit 100c, inverter INV1, which is the first-stage inverter, is common to first-stage inverter paths IPT1 to IPT3, and the duty ratio is adjusted by delay adjustment circuit 26. For example, the P-type transistor MP0 and N-type transistor MN0 of inverter INV1, which is the first-stage inverter, can be designed to have the minimum transistor size (Wpmin/Lmin and Wnmin/Lmin described above).

The selection unit 20 includes switch circuits ISW1 to ISW3 arranged in the first-stage inverter paths IPT1 to IPT3, respectively, as in Figure 2. The configuration of the switch circuits ISW1 to ISW3 is the same as in Figure 2, so it will not be repeated.

The delay adjustment circuit 26 includes, in each of the first-stage inverter paths IPT1 to IPT3, dummy switch circuits DDSW1 to DDSW3 that are connected in series with the switch circuits ISW1 to ISW3 that constitute the selection unit 20. The dummy switch circuits DDSW1 to DDSW3 are composed of N-type transistors MN4D to MN6D and P-type transistors MP4D to MP6D, similar to the dummy switch circuits DSW1 to DSW3 (FIG. 10) of the delay adjustment circuit 25, and have the circuit configuration shown in FIG.

In at least some of the dummy switch circuits DDSW1 to DDSW3 of the delay adjustment circuit 26, the gate capacitance Cgdn (MND) and the gate capacitance Cgsp (MPD) are designed so that a difference occurs between the first delay time (rising edge) and the second delay time (falling edge). In this respect, the delay adjustment circuit 26 (dummy switch circuits DDSW1 to DDSW3) differs from the delay adjustment circuit 25 (dummy switch circuits DSW1 to DSW3).

For example, in the dummy switch circuit DDSW1 arranged in the first-stage inverter path IPT1, the transistor sizes of the N-type transistor MND and the P-type transistor MPD are Wnmin/Lmin and Wpmin/Lmin, respectively. As a result, in the dummy switch circuit DDSW1, the delay capacitances (gate capacitances Cgdn, Cgsp) added to the first-stage inverter path IPT1 are adjusted so that the first delay time acting on the rising edge of the pulse signal Spl and the second delay time acting on the falling edge are equivalent.

In contrast, in the dummy switch circuit DDSW2 arranged in the first-stage inverter path IPT2, for example, the transistor sizes of the N-type transistor MND and the P-type transistor MPD are set to Wnmin/Lmin and 2×Wpmin/Lmin, respectively. As a result, in the dummy switch circuit DDSW2, the ratio of the gate capacitance Cgsp (MPD) to the gate capacitance Cgdn (MND) is increased compared to the dummy switch circuit DDSW1. As a result, in the dummy switch circuit DDSW2, the delay capacitances (gate capacitances Cgdn, Cgsp) added to the first-stage inverter path IPT2 are adjusted so that the second delay time acting on the falling edge is greater than the first delay time acting on the rising edge.

Furthermore, in the dummy switch circuit DDSW3 arranged in the first-stage inverter path IPT3, the transistor sizes of the N-type transistor MND and the P-type transistor MPD are Wnmin/Lmin and (1/2) × Wpmin/Lmin, respectively. As a result, in the dummy switch circuit DDSW2, the ratio of the gate capacitance Cgsp (MNP) to the gate capacitance Cgdn (MND) is reduced compared to the dummy switch circuit DDSW1. As a result, in the dummy switch circuit DDSW3, the delay capacitance (gate capacitances Cgdn, Cgsp) added to the first-stage inverter path IPT3 is adjusted so that the first delay time acting on the rising edge is greater than the second delay time acting on the falling edge.

In the oscillator circuit 100c, the P-type transistors MP0, MP4-MP6 and the N-type transistors MN0, MN4-MN6 constituting the inverter INV1 and the switch circuits ISW1-ISW3 can be designed with the minimum transistor sizes Wpmin/Lmin and Wnmin/Lmin. On the other hand, the gate dimensions (transistor sizes) of the P-type transistors MP4D-MP6D and the N-type transistors MN4D-MN6D constituting the dummy switch circuits DDSW1-DDSW3 constituting the delay adjustment circuit 26 are arbitrarily designed as described above. This allows the magnitude relationship (difference) between the first delay time and the second delay time to be arbitrarily set between the first-stage inverter paths IPT1-IPT3. In other words, the delay adjustment circuit 26 corresponds to one embodiment of the "second delay adjustment circuit".

Figure 13 shows an operating waveform diagram explaining duty adjustment in an oscillator circuit relating to variant example 1 of embodiment 2.

In the example of Figure 13, the output voltage V1 of the first-stage inverter INV1 has a ratio of L level period to H level period of 60(%):40(%) due to fluctuations in the inversion threshold voltage Vinv, and the duty ratio DT1 (Figure 9) has increased from 50(%).

Specifically, when the input voltage VA rises to the inversion threshold voltage Vinv of the inverter INV1 at time tb, a falling edge occurs in the output voltage V1 of the inverter INV1, transitioning from the H level (VDD) to the L level (GND). The input voltage VB to the second logic circuit 30 falls to the inversion threshold voltage Vinv of the inverter INV2 of the second logic circuit 30 at time tx, which is delayed from time tb by the second delay time Tdp provided by one of the first-stage inverter paths IPT1 to IPT3.

On the other hand, at time tc when the input voltage VA, which decreases after time tb, falls to the inversion threshold voltage Vinv of the inverter INV1, a rising edge occurs in the output voltage V1 of the inverter INV1, transitioning from the L level (GND) to the H level (VDD). The input voltage VB to the second logic circuit 30 rises to the inversion threshold voltage Vinv of the inverter INV2 of the second logic circuit 30 at time ty, which is delayed from time tc by the first delay time Tdn provided by the first-stage inverter path IPT2.

Therefore, in the example of Figure 13 where the duty ratio is greater than 50% (T1>T2), by selecting the first-stage inverter path IPT2 in which the second delay time Tdp is greater than the first delay time Tdn, the duty ratio of the input voltage VB to the second logic circuit 30 can be brought closer to 50%.

Conversely, in cases where the duty ratio is less than 50% (T1<T2), by selecting the first-stage inverter path IPT3 in which the first delay time Tdn is greater than the second delay time Tdp, it is possible to bring the duty ratio of the input voltage VB to the second logic circuit 30 closer to 50%. In this way, it can be understood that the duty ratio of the oscillation signal Vosc can be adjusted by selecting multiple (M) first-stage inverter paths having different (Tdn-Tdp) differences between the first delay time Tdn and the second delay time Tdp.

Therefore, in the oscillator circuit 100c according to the first modification of the second embodiment, the duty ratio of the oscillation signal Vosc can be adjusted by the same method as that shown in FIG. 8 and FIG. 9 described in the first embodiment. Specifically, when the control signals VISW1 to VISW3 are set in the same manner as in the pattern PT1 of FIG. 8, the duty ratio DT1 when the first-stage inverter path IPT1, in which the first delay time Tdn and the second delay time Tdp are equivalent, is selected can be obtained (S110 in FIG. 9). Then, by using the obtained duty ratio DT1 to execute the processes of S120 to S160 in FIG. 8, the duty ratio of the oscillation signal of the RC type oscillator circuit can be adjusted by a simple configuration, as in the first embodiment.

In addition, in variant example 1 of embodiment 2, the number of dummy switch circuits DDSW arranged, i.e., the number of first-stage inverter paths having different differences between the first and second delay times, is set to M = 3, but M can also be any number.

In variant example 1 of embodiment 2, by adding capacitance using the dummy switch circuit DDSW, it becomes easier to adjust the first delay time Tdn and the second delay time Tdp in each of the first stage inverter paths IPT1 to IPT3 compared to a configuration using switches and capacitors connected in series.

Variation 2 of embodiment 2.
FIG. 14 is a circuit diagram illustrating a configuration example of an oscillator circuit 100d according to a second modification of the second embodiment.

Referring to FIG. 14, compared to the oscillator circuit 100a (FIG. 2) of embodiment 1, the oscillator circuit 100d has a configuration in which a circuit block including the selection unit 20 and delay adjustment circuit 26 shown in FIG. 12 is arranged for each of the inverters INV11 to INV13 included in the first logic circuit 10.

Specifically, a circuit block 201 including a selection unit 20 and a delay adjustment circuit 26 is arranged between the inverter INV11 and a node Nb corresponding to the input node of the inverter INV2 of the second logic circuit 30. The configuration and operation of the selection unit 20 and the delay adjustment circuit 26 are similar to those of the first modification of the second embodiment, and therefore detailed description will not be repeated. As a result, the first-stage inverter path IPT1 (FIG. 2) including the inverter INV11 is subdivided into first-stage inverter paths IPT11-IPT13 which pass through the dummy switch circuits DDSW1-DDSW3, respectively.

The combination of delay times Tdn and Tdp given to each of the first-stage inverter paths IPT11 to IPT13 can be set in the same way as for each of the first-stage inverter paths IPT1 to IPT3 in Figure 12. That is, Figure 14 also shows an example in which the number of dummy switch circuits DDSW is three.

Similarly, a circuit block 202 is disposed between the inverter INV12 and the node Nb, and a circuit block 203 is disposed between the inverter INV13 and the node Nb. Although not shown in the figure, each of the circuit blocks 202 and 203 has a selection unit 20 and a delay adjustment circuit 26 similar to those of the circuit block 201.

Therefore, the first-stage inverter path IPT2 (FIG. 2) including the inverter INV12 is subdivided into first-stage inverter paths IPT21-IPT23 by the circuit block 202. Similarly, the first-stage inverter path IPT3 (FIG. 2) including the inverter INV13 is subdivided into first-stage inverter paths IPT31-IPT33 by the circuit block 203. Each of the first-stage inverter paths IPT21-IPT23 and the first-stage inverter paths IPT31-IPT33 can be given a combination of delay times Tdn and Tdp that are set in the same way as the first-stage inverter paths IPT1-IPT3, respectively.

In the oscillator circuit 100d, (M1×M2) first-stage inverter paths are provided between the input node Na and node Nb (the input node of inverter INV2) according to the multiplication value of the number M1 (M1: an integer of 2 or more) of first-stage inverters arranged in parallel and the number M2 (M2: an integer of 2 or more) of branches of the output signal of each first-stage inverter. Then, one of the (M1×M2) first-stage inverter paths (in FIG. 14, M1×M2=3×3=9) is selected.

That is, the control signals VISW1 to VISW3 for selectively turning on the switch circuits ISW1 to ISW3 of the selection unit 20 are set individually between the circuit blocks 201 to 203. As a result, one of the above-mentioned (M1 x M2) first-stage inverter paths is selected by turning on the switch circuit ISW in that path using (M1 x M2) control signals in total.

As an example, in the oscillator circuit 100d, the delay adjustment circuit 26 can be configured so that the duty ratio adjustment amount based on the difference between the delay times Tdp and Tdn is reduced in the delay adjustment circuit 26 relative to the duty ratio adjustment amount based on the selection of the inversion threshold voltage Vinv of the inverters INV11 to INV13.

As a result, according to the oscillator circuit 100d of variant example 2 of embodiment 2, in addition to the effect of the oscillator circuit 100a of embodiment 1, it is possible to adjust the duty ratio more precisely.

Embodiment 3.
In the third embodiment, an example of a circuit configuration using a clocked inverter will be described.

FIG. 15 is a circuit diagram illustrating a configuration example of an oscillator circuit 100e according to the third embodiment.
15, the oscillator circuit 100e differs from the oscillator circuit 100b (FIG. 10) according to the second embodiment in that the first logic circuit 10 is composed of M (in the example of FIG. 15, M=3) clocked inverters CINV11-CINV13 connected in parallel. That is, in the oscillator circuit 100e, first-stage inverter paths IPT1-IPT3 each including the clocked inverters CINV11-CINV13 are formed in parallel between the input node Na and node Nb (the input node of the second logic circuit 30).

Figure 16 is a circuit diagram explaining the configuration of a clocked inverter. Figure 16 shows the circuit configuration of a clocked inverter CINV1, which collectively refers to the clocked inverters CINV11 to CINV13 shown in Figure 15.

As shown in FIG. 16, the clocked inverter CINV1 further has a P-type switch transistor MPSW and an N-type switch transistor MNSW in addition to the circuit configuration of the inverter INV shown in FIG. 3. The switch transistor MPSW is connected in series with the P-type transistor MP0 between the output node No at which the output voltage Vout is generated and the power supply line PL. Similarly, the switch transistor MNSW is connected in series with the N-type transistor MN0 between the output node No and the ground line NL. The transistor sizes of the switch transistors MPSW and MNSW can be the same as those of the P-type transistor MP0 and the N-type transistor MN0, respectively.

A control signal VISW, which collectively refers to the control signals VISW1 to VISW3, is input to the gate of the switch transistor MPSW. On the other hand, a control signal VISWB, which collectively refers to the control signals VISW1B to VISW3B, is input to the gate of the switch transistor MNSW.

When the control signal VISW is set to H level (i.e., the control signal VISWB is set to L level), the switch transistors MNSW and MPSW are turned on, and the clocked inverter CINV operates in the same manner as the inverter INV1 shown in Figure 3. That is, when the input voltage Vin is lower than the inversion threshold voltage Vinv, the clocked inverter CINV sets Vout to H level (VDD), whereas when Vin ≥ Vinv, it sets Vout to L level (GND).

On the other hand, when the control signal VISW is set to the L level (i.e., the control signal VISWB is set to the H level), the switch transistors MNSW and MPSW are turned off, and the output node No is disconnected from both the power supply line PL and the ground line NL. Therefore, neither the power supply voltage VDD nor the ground voltage GND is output from the clocked inverter CINV.

Referring again to Figure 15, the clocked inverters CINV11 to CINV13 are configured to have the same inversion threshold voltage Vin as each of the inverters INV11 to INV13 by adjusting the transistor sizes of the P-type transistor MP0 and the N-type transistor MN0 described in embodiment 1.

As described above, by controlling the operation and stopping of the clocked inverters CINV1 to CINV3 using the control signals VISW1 to VISW3 (VISW1B to VISW3B), the oscillator circuit 100e can realize the function of the selection unit 20 without having to arrange switch circuits ISW1 to ISW3 as shown in Figure 2.

Furthermore, in the oscillator circuit 100e, a delay adjustment circuit 25 similar to that in FIG. 10 is arranged between the output sides of the clocked inverters CINV11 to CINV13 and node Nb. The delay adjustment circuit 25 has dummy switch circuits DSW1 to DSW3 similar to that in FIG. 10. The dummy switch circuits DSW1 to DSW3 are respectively connected between the output nodes of the clocked inverters CINV11 to CINV13 and node Nb corresponding to the input node of the second logic circuit 30. The configuration of the other parts of the oscillator circuit 100e is similar to that of the oscillator circuit 100b in FIG. 10, so detailed description will not be repeated.

Therefore, in the oscillator circuit 100e, a first stage inverter path IPT1 in which a clocked inverter CINV11 and a dummy switch circuit DSW1 are connected in series, a first stage inverter path IPT2 in which a clocked inverter CINV12 and a dummy switch circuit DSW2 are connected in series, and a first stage inverter path IPT3 in which a clocked inverter CINV13 and a dummy switch circuit DSW3 are connected in series are provided in parallel between the input node Na and the node Nb.

Then, one of the clocked inverters CINV11 to CINV13 is selectively operated in response to the control signals VISW1 to VISW3 (control signals VISW1B to VISW3B), and one of the first-stage inverter paths IPT1 to IPT3 is selectively formed between the input node Na and the node Nb. Furthermore, the inversion threshold voltage Vinv of the inverter in the first-stage inverter paths IPT1 to IPT3 and the adjustment capacitance added by the delay adjustment circuit 25 are the same as those in the oscillator circuit 100b according to the second embodiment.

Therefore, like the oscillator circuit 100b of embodiment 2, the oscillator circuit 100e of embodiment 3 also makes it possible to adjust the duty ratio of the oscillation signal Vosc and improve the accuracy of the oscillation frequency.

Furthermore, in the oscillator circuit 100e of embodiment 3, the circuit area and current consumption can be reduced by using a clocked inverter instead of an inverter.

First, the number of wiring connections is reduced in the clocked inverters CINV11 to CINV13 compared to the combination of the inverters INV11 to INV13 in Fig. 10 (embodiment 2) and the switch circuits ISW1 to ISW3, which are CMOS (Complementary MOS) switches. This makes it possible to reduce the circuit area in terms of layout.

Furthermore, when the input voltage VA at the input node Na is close to the inversion threshold voltage Vinv, a through current is generated in the P-type transistor MP0 and the N-type transistor MN0 in each of the inverters INV11 to INV13 in FIG. 2 and the like. On the other hand, as illustrated in FIG. 5 and the like, the change in the input voltage VA near the inversion threshold voltage Vinv is relatively gradual due to the time constant of the feedback resistor 40 (Roc) and the feedback capacitor 50 (Coc). As a result, in the circuit configurations of embodiments 1 and 2 and the like in which M inverters are arranged in parallel, there is a concern that the above-mentioned through current will increase the current consumption of the M inverters.

In contrast, in the oscillator circuit 100e according to the third embodiment, among the M clocked inverters connected in parallel, in the clocked inverter stopped by the control signal VISW (VISWB), the switch transistors MPSW and MNSW (FIG. 16) are turned off, so that no through current occurs. As a result, by applying the clocked inverter, it is possible to reduce the current consumption compared to the first and second embodiments.

In the first and second embodiments, it is possible to suppress the through current by placing an additional transistor switch between the input node Na and the input nodes of the inverters INV11 to INV13, the switch being turned on and off in conjunction with the selection of the first-stage inverter paths IPT1 to IPT3. However, there is a concern that adding such a transistor switch will increase the circuit area and degrade the frequency correction accuracy due to increased unnecessary parasitic capacitance and on-resistance. In the oscillator circuit 100e according to the third embodiment, the use of a clocked inverter makes it possible to reduce current consumption without causing such problems.

In addition, in the example of Figure 15, in the oscillator circuit 100e of embodiment 3, a configuration example in which a delay adjustment circuit 25 is arranged as in Figure 10 has been described, but when the fluctuation in oscillation frequency due to the selection of clocked inverters CINV11 to CINV13 is small, it is possible to omit the arrangement of the delay adjustment circuit 25 as in the oscillator circuit 100a of embodiment 1 (Figure 2).

Alternatively, in the oscillator circuit 100e according to the third embodiment, in the configuration example of FIG. 15, the delay adjustment circuit 25 can be replaced with the delay adjustment circuit 26 (FIG. 12). In this case, it is possible to finely adjust the duty ratio, as in the oscillator circuit 100d according to the second modification of the second embodiment described in FIG. 14.

A modified example of embodiment 3.
FIG. 17 is a circuit diagram illustrating a configuration example of an oscillator circuit 100f according to a modification of the third embodiment.

17, the oscillator circuit 100f differs from the oscillator circuit 100a according to the first embodiment in that a clocked inverter VCINV controlled by N-bit (N: an integer of 2 or more) control signals VISWN[N:1] and VISWP[N:1] is arranged instead of the multiple inverters INV11-INV13 and the selection unit 20. Compared to the oscillator circuit 100e according to the third embodiment (FIG. 15), the oscillator circuit 100f has a circuit configuration in which a clocked inverter VCINV is arranged instead of the multiple clocked inverters CINV11-CINV13, and the delay adjustment circuit 25 is omitted.

Figure 18 shows a circuit diagram explaining the configuration of the clocked inverter VCINV shown in Figure 17.

18, the clocked inverter VCINV has N clocked inverters CINV1 to CINVN connected in parallel. Each of the clocked inverters CINV1 to CINVN has a circuit configuration similar to that of the clocked inverter CINV1 shown in FIG.

Specifically, the clocked inverters CINV1 to CINVN respectively have P-type transistors MPC1 to MPCN, N-type transistors MNC1 to MNCN, P-type switch transistors MPCSW1 to MPCSWN, and N-type switch transistors MNCSW1 to MPCSWN.

Among the clocked inverters CINV1 to CINVN, the P-type transistors MPC1 to MPCN and the N-type transistors MNC1 to MNCN have different transistor sizes. For example, the gate length of each of the P-type transistors MPC1 to MPCN and the N-type transistors MNC1 to MNCN is common (Limn). On the other hand, the gate widths of the P-type transistors MPC1 to MPCN and the N-type transistors MNC1 to MNCN are each designed to have values that differ in stages according to a power of two.

Specifically, the gate width of N-type transistor MNC1 is set to a minimum value Wmin, the gate width of N-type transistor MNC2 is set to W2N=2·Wmin, and the gate width of the Nth N-type transistor MNCN is Wn2=2 ^(N-1) ·Wmin. The transistor sizes of N-type switch transistors MNCSW1 to MNCSWN are set to be equal to those of N-type transistors MNC1 to MNCN, respectively.

Similarly, the gate width of P-type transistor MPC1 is Wmin, the gate width of P-type transistor MPC2 is Wp2=2·Wmin, and the gate width of the Nth P-type transistor MPCN is WpN=2 ^(N-1) ·Wmin. The transistor sizes of the P-type switch transistors MPCSW1 to MPCSWN are equivalent to those of the P-type transistors MPC1 to MPCN, respectively.

Control signals VISWN[1] to VISWN[N] are input to the gates of the N-type switch transistors MNCSW1 to MNCSWN. As a result, in the clocked inverter VCINV, at least one N-type transistor selected by the control signal VISWN[1] to VISWN[N] from among the N-type transistors MNC1 to MNCN is connected in parallel between the ground line NL and the output node No of the clocked inverter VCINV (corresponding to node Nb in FIG. 17).

For example, when all of the control signals VISWN[1] to VISWN[N] are "1," all of the N-type transistors MNC1 to MNCN are connected between the ground line NL and the output node of the clocked inverter VCINV. This state is equivalent to the state in the inverter of FIG. 3 where the gate width of the N-type transistor MN0 is (2 ^N -1)·Wmin.

Similarly, inverted control signals VISWP[1] to VISWP[N] are input to the gates of the P-type switch transistors MPCSW1 to MPCSWN. As a result, in the clocked inverter VCINV, at least one P-type transistor among the P-type transistors MPC1 to MPCN selected by the control signal VISWP[1] to VISWP[N] is connected in parallel between the power supply line PL and the output node No of the clocked inverter VCINV.

For example, when all of the control signals VISWP[1] to VISWP[N] are "1," all of the P-type transistors MPC1 to MPCN are connected between the power supply line PL and the output node of the clocked inverter VCINV. This state is equivalent to the state in the inverter of FIG. 3 where the gate width of the N-type transistor MN0 is (2 ^N -1)·Wmin.

In this way, in the clocked inverter VCINV shown in Figure 18, the overall transistor size of at least one N-type transistor connected in parallel between the ground line NL and the output node No (corresponding to the transistor size of N-type transistor MN0 in inverter INV1 in Figure 3) can be changed in stages depending on the control signals VISWN[1] to VISWN[N].

Similarly, the overall transistor size of at least one P-type transistor connected in parallel between the power supply line PL and the output node No (corresponding to the transistor size of P-type transistor MP0 in inverter INV1 in Figure 3) can be changed in stages depending on the control signals VISWP[1] to VISWP[N].

As a result, in the clocked inverter VCINV, Kn and Kp in the above equation (2) can be changed by variably controlling the ratio between the transistor size (Wn/Ln) of the N-type transistor MN0 and the transistor size (Wp/Lp) of the P-type transistor MP0.

This allows the clocked inverter VCINV to selectively form one of multiple inverters (corresponding to the inverter INV in FIG. 3) with different inversion threshold voltages Vinv as a first-stage inverter between the input node Na and node Nb in response to the control signals VISWN[1] to VISWN[N] and VISWP[1] to VISWP[N]. This allows the selection of multiple inverter paths that pass through each of the multiple inverters to be equivalently performed.

Figure 19 shows an example of setting the control signal for the clocked inverter VCINV. Figure 19 shows an example when N=5.

19, by setting the control signal VISWP[1]="1" and the control signals VISWP[2] to VISWP[5]="0", the transistor size (Wp/Lp) of the P-type transistor becomes the minimum value (1). In this state, the transistor size (Wn/Ln) of the N-type transistor can be set in stages between the minimum value (1) and the maximum value (2 ^N -1=31) by a combination of the five bits of the control signals VISWN[1] to VISWn[5], "0" and "1". When (Wp/Lp) is fixed and (Wn/Ln) is increased in stages, the inversion threshold voltage Vinv of the clocked inverter VCINV can be decreased in stages in accordance with the increase in the parameter value K in the formula (2).

Similarly, by setting the control signal VISWN[1] to "1" and the control signals VISWN[2] to VISWN[5] to "0", the transistor size (Wn/Ln) of the N-type transistor becomes the minimum value (1). Under this condition, the transistor size (Wp/Lp) of the P-type transistor can be set stepwise between the minimum value (1) and the maximum value (for example, 2 ^N -1=31) by a combination of the five bits of "0" and "1" of the control signals VISWP[1] to VISWP[5]. When (Wn/Ln) is fixed and (Wp/Lp) is increased stepwise, the inversion threshold voltage Vinv of the clocked inverter VCINV can be increased stepwise in accordance with the decrease in the parameter value K in the formula (2).

For example, if VISWP[2] = "1", VISWP[1] = VISWP[3] to VISW[5] = "0", and VISWN[1] = "1", VISWN[2] to VISWN[5] = "0", then (Wp/Lp) = 2 and (Wn/Ln) = 1. Therefore, the clocked inverter VCINV is in a state where an inverter having an inversion threshold voltage Vinv equivalent to that of the inverter INV11 (K = 1) in embodiment 1 (Figure 2) is formed between the input node Na and the node Nb. In other words, a state equivalent to that in embodiment 1 (Figure 2) where the first-stage inverter path IPT1 including the inverter INV11 is selected is formed.

Similarly, if VISWP[5] = "1", VISWP[1] to VISWP[4] = "0", VISWN[1] = "1", VISWN[2] to VISWN[5] = "0", then (Wp/Lp) = 16 and (Wn/Ln) = 1. Therefore, the clocked inverter VCINV is in a state where an inverter having an inversion threshold voltage Vinv equivalent to that of inverter INV12 (K = √(1/8)) in embodiment 1 (Figure 2) is formed between input node Na and node Nb. In other words, a state equivalent to that in embodiment 1 (Figure 2) where the first-stage inverter path IPT2 including inverter INV12 is selected is formed.

Also, if VISWP[1] = "1", VISWP[2] to VISWP[5] = "0", and VISWN[3] = "1", VISWN[1] = VISWN[2] = VISWN[4] = VISWN[5] = "0", then (Wp/Lp) = 1 and (Wn/Ln) = 4. Therefore, the clocked inverter VCINV is in a state where an inverter having an inversion threshold voltage Vinv equivalent to the inverter INV13 (K = √8) in the first embodiment (FIG. 2) is formed between the input node Na and the node Nb. In other words, a state equivalent to the first stage inverter path IPT3 including the inverter INV13 in the first embodiment (FIG. 2) is selected is formed.

In this way, in the clocked inverter VCINV, the inversion threshold voltage Vinv can be variably set by changing the ratio between the transistor size of the P-type transistor and the transistor size of the N-type transistor in the first-stage inverter in accordance with the control signals VISWN[1] to VISWN[N] and VISWP[1] to VISWP[N].

As a result, the clocked inverter VCINV can select multiple first-stage inverter paths with different inversion threshold voltages Vinv, similar to the inverters INV11 to INV13 and the selection unit 20 in embodiment 1. Specifically, it is equivalently possible to select multiple first-stage inverter paths in which multiple inverters with different inversion threshold voltages Vinv formed by combinations of the control signals VISWN[N:1] and VISWP[N:1] serve as first-stage inverters. In particular, since the inversion threshold voltage Vinv differs for each combination of the N-bit control signals VISWN[N:1] and VISWP[N:1], the number of selectable first-stage inverter paths increases.

When all of the control signals VISWN[1] to VISWN[N] and VISWP[1] to VISWP[N] are set to "0", the paths between the output node of the clocked inverter VCINV and the power supply line PL (VDD) and ground line NL (GND) are cut off, and the clocked inverter VCINV is stopped. In this case, the occurrence of a through current is avoided.

Referring again to Figure 17, in the oscillator circuit 100f, the output voltage VB of the clocked inverter CINV is input to the second logic circuit 30, and an oscillation signal Vosc is generated having a frequency that depends on the resistance value Roc of the feedback resistor 40 and the capacitance value Coc of the feedback capacitance 50, similar to the oscillator circuit 100a (Figure 2) of embodiment 1.

Furthermore, in the oscillator circuit 100f, as in embodiment 1, the duty ratio DT1 (S110 in Figure 9) can be obtained when the oscillator circuit 100f is operated with the control signals VISWN[N:1] and VISWP[N:1] set so that the inversion threshold voltage Vinv corresponding to K = 1 is set.

Then, by changing the control signals VISWN[N:1] and VISWP[N:1] so that the parameter value K is decreased when the acquired duty ratio DT1 is greater than 50(%), and the parameter value K is increased when the duty ratio DT1 is less than 50(%), the duty ratio of the oscillation signal of the RC type oscillation circuit can be adjusted, as in embodiment 1.

In this way, according to the oscillator circuit of the modified example of the third embodiment, the application of the clocked inverter VCINV, which can variably control the transistor size, makes it possible to adjust the duty of the oscillation signal Vosc by selecting multiple first-stage inverter paths with different inversion threshold voltages. By using the clocked inverter VCINV, it is possible to reduce the circuit area and current consumption as in the third embodiment, and it becomes easier to finely adjust the duty ratio.

In addition, when the oscillation frequency varies due to the change in capacitance value of the path in response to the selection of multiple first-stage inverter paths in the clocked inverter CINV, it is possible to configure the delay adjustment circuit 25 described in the second embodiment to be connected to the output node of the clocked inverter VCINV. However, in this case, it is necessary to provide a mechanism for gradually changing the delay capacitance added to the output node in response to the control signals VISWN[N:1] and VISWP[N:1].

Embodiment 4.
In the fourth embodiment, a configuration example of the oscillator circuit to which the enable signal can be input will be described.

FIG. 20 is a circuit diagram illustrating a configuration example of an oscillator circuit 100g according to the fourth embodiment.
As shown in Fig. 20, the oscillator circuit 100g differs from the oscillator circuit 100a (Fig. 2) according to the first embodiment in that it includes a feedback capacitor 50g instead of the feedback capacitor 50. It also differs in that the first logic circuit 10 includes equivalent inverters INV11X-INV13X configured with NAND gates instead of the inverters INV11-INV13 (Fig. 2). Other configurations of the oscillator circuit 100g are similar to those of the oscillator circuit 100a (Fig. 2).

One of the inputs of the NAND gates that constitute each of the inverters INV11X to INV13X is the enable signal EN1, and the other input is a voltage VA (input node Na) that is the same as the input of the inverters INV11 to INV13.

During the L level period of the enable signal EN1 (also referred to as the "enable off period"), the function of the oscillator circuit 100g is stopped and the outputs of the inverters INV11X to INV13X and the oscillation signal Vosc are fixed to the H level. In contrast, when the enable off is released and the enable signal EN1 changes from the L level to the H level, the operation of the oscillator circuit 100g is started and the oscillation signal Vosc repeats the H level and the L level at a constant frequency. Each of the inverters INV11X to INV13X may be configured with a NOR gate instead of a NAND gate. When a NOR gate is used, an inverted signal of the enable signal EN1 (H level during the enable off period) is used as one of the inputs of the NOR gate instead of the enable signal EN1.

Normally, oscillator circuits are divided into applications for automatic startup by power on and rapid startup controlled by an enable signal, and embodiments 1 to 3 are suitable for the former power on application. In contrast, embodiment 4 is suitable for the latter application, which has become increasingly popular in recent years. As will be described later, by applying embodiment 4, it becomes possible to suppress the momentary voltage rise at input node Na when enable off is released, making it suitable for applications that start up rapidly by an enable signal.

Feedback capacitance 50g includes a capacitor C1 (capacitance value Coc) similar to feedback capacitance 50, and further includes a control switch ISWg1 that is turned on and off in response to enable signal EN1. The control switch ISWg is connected between one electrode of capacitor C1 connected to input node Na and ground (GND) corresponding to ground line NL (Figure 3, etc.).

The control switch ISWg can be configured by a transfer gate of at least one of a P-type transistor and an N-type transistor that is turned on and off in response to the enable signal EN1. In the example of FIG. 20, the control switch ISWg is configured by connecting in parallel a P-type transistor MPg1, whose gate receives the enable signal EN1, and an N-type transistor MNg1, whose gate receives the inverted signal EN1B of the enable signal EN1.

In the fourth embodiment and its modified example, the polarity of the capacitor C1 is configured such that the input node Na side is a top plate with a small parasitic capacitance and the opposite side (node Nc side) is a bottom plate with a large parasitic capacitance, but a similar configuration can be applied to the first to third embodiments and their modified examples. Alternatively, in each embodiment and its modified example, the polarity of the capacitor C1 may be arbitrary. In addition, the capacitor C1 can typically have a MIM (Metal Insulator Metal) structure, but it can also be configured using a PIP (Poly-Insulator Poly) structure, a MOM (Metal Oxide Metal) structure, or a gate oxide film capacitance of a field effect transistor.

Here, a comparative example of the voltage waveform of the input node Na in the case where the control switch ISWg1 is not arranged in the oscillator circuit 100g will be described with reference to Fig. 21. In Fig. 23, the voltage waveform (input voltage VA#) in the comparative example is shown by a dotted line, and the voltage waveform (input voltage VA) in the oscillator circuit 100g in which the control switch ISWg1 is arranged is shown by a solid line.

When the enable-off is released, if the initial voltage of the input node Na is VADE and the initial voltage of the node Nc is VCDE, then an amount of charge according to the product of the voltage difference (VADE-VCDE) and the capacitance value Coc is stored in the capacitor C1. Here, one inverter INV2 is connected between the output node of the inverters INV11X to INV13X and the node Nc, and one inverter INV is also connected between the node Nc and the input node Na. Therefore, during the enable-off period, the outputs of the inverters INV11X to INV13X are fixed to the H level, so the node Nc is fixed to the L level, and the node Nd and the input node Na are fixed to the H level.

As shown in Figure 21, at time tx, when the enable signal EN1 changes from L level to H level (VDD), the enable off is released. As described above, before time tx, which is the enable off period, VA# = VDD. In addition, a voltage difference of (VADE - VCDE) = VDD is maintained between both ends of capacitor C1.

At time tx, when enable off is released, the enable signal EN1 is set to H level, and the outputs of the inverters INV11X to INV13X change from H level to L level. In response to this, the voltage VC of the node Nc changes from L level to H level, and the voltage of the node Nd changes from H level to L level. However, due to the influence of the RC time constant (Roc·Coc) due to the resistance value Roc of the feedback resistor 40 and the capacitance value Coc of the feedback capacitance 50g, the input voltage VA# of the input node Na does not immediately change from H level to L level.

As a result, at time tx, the input voltage VA# rises by the voltage difference (VADE-VCDE) = VDD held in capacitor C1 due to capacitive coupling via capacitor C1. As a result, at time tx, the input voltage VA# momentarily rises to twice VDD. Thereafter, when the input voltage VA# falls to the inverter's inversion threshold voltage Vinv according to the above-mentioned RC time constant, a change similar to that at time tc in Figure 5 occurs in the input voltage VA#, and VA# = Vinv-VDD. Thereafter, the input voltage VA# of the comparative example changes in the same way as the input voltage VA after time tc in Figure 5.

In this way, in the oscillator circuit 100e having the function of operating in response to an enable signal, if the control switch ISWg1 is not configured, there is a concern that an overvoltage may momentarily occur at the input node Na when the enable off is released (time tx in Figure 21) if the enable off period (EN1 = L level) is longer than the delay time due to the above-mentioned RC time constant.

Non-Patent Document 1 describes a configuration in which the power supply voltage (corresponding to VDD) supplied to the inverter can be controlled by a regulator. If such a regulator is used to control VDD low during the enable-off period, it is possible to suppress the overvoltage at the above-mentioned time tx. However, this requires additional arrangement of a regulator, level shifter, etc. Also, it is possible to deal with the overvoltage by configuring the logic inversion circuit in the first logic circuit 10 with high-voltage elements, but there are concerns about a decrease in operating speed and an increase in circuit area.

In contrast, in the oscillator circuit 100g according to the fourth embodiment, during the enable-off period (EN1=L level), the control switch ISWg1 is turned on, and the input node Na is connected to ground. Therefore, as shown by the solid line in FIG. 21, the input voltage VA is fixed at 0. As a result, the voltage difference between the electrodes on both sides of the capacitor C1 becomes zero, so that the initial charge of the capacitor C1 is reset and VA is maintained at 0 even at time tx.

After time tx, the enable signal EN1 is set to H level and the control switch ISWg1 is turned off, so that the oscillator circuit 100e operates in the same manner as the oscillator circuit 100a (FIG. 2) according to the first embodiment. Therefore, the waveform of the input voltage VA after time tx is the same as the waveform of the input voltage VA after time ta in FIG. 5.

In this way, in the oscillator circuit of embodiment 4, in a configuration in which the first logic circuit 10 operates in response to the enable signal EN1, it is possible to prevent the occurrence of an overvoltage when the enable off is released due to the influence of the charge held in capacitor C1 during the enable off period.

Although Figure 20 illustrates an example of a configuration in which the first logic circuit 10 operates in response to the enable signal EN1, even if the second logic circuit 30, or both the first logic circuit 10 and the second logic circuit 30, operate in response to the enable signal EN1, it is possible to similarly suppress overvoltage by placing the control switch ISWg1 on the input node Na side of the capacitor C1.

A modified example of embodiment 4.
FIG. 22 is a circuit diagram illustrating a configuration example of an oscillator circuit 100h according to a first modification of the fourth embodiment.

As shown in FIG. 22, the oscillator circuit 100h differs from the oscillator circuit 100g of FIG. 20 in that, instead of the control switch ISWg1 provided on the input node Na side of the capacitor C1, it has control switches ISWh0 and ISWh1 provided on the node Nc side of the capacitor C1.

The control switch ISWh1 is connected between one electrode of the capacitor C1 on the node Nc side and the node Nb, and is turned on and off in response to the enable signal EN1. The control switch ISWh1 is turned on during the enable off period (EN1 = L level) and turned off during the enable off release period (EN1 = H level).

The control switch ISWh0 is connected between one electrode on the node Nc side of the capacitor C1 and the node Nc, and is turned on and off according to the enable signal EN0. The enable signal EN0, like the enable signal EN1, is set to L level during the enable-off period, but is set to H level during the enable-off release period. The control switch ISWh0 is turned off during the enable-off period (EN1 = L level), but is turned on during the enable-off release period (EN1 = H level). However, between the enable signals EN0 and EN1, timing adjustments (addition of dead time) are made so that there is no period during which both the control switches ISWh0 and ISWh1 are on.

Each of the control switches ISWh1 and ISWh0 can be configured by a transfer gate made of at least one of a P-type transistor and an N-type transistor that is turned on and off in response to the enable signal EN0 or EN1. In the example of FIG. 20, the control switch ISWh1 is configured by connecting in parallel a P-type transistor MPh1, whose gate receives the enable signal EN1, and an N-type transistor MNh1, whose gate receives the inverted signal EN1B of the enable signal EN1. The control switch ISWh0 is configured by connecting in parallel an N-type transistor MNh0, whose gate receives the enable signal EN0, and a P-type transistor MPh0, whose gate receives the inverted signal EN0B of the enable signal EN0.

Therefore, in the oscillator circuit 100h, during the enable-off period (EN1 = L level), the capacitor C1 is connected between the input node Na and the node Nb, both of which are fixed to the H level (VDD). As a result, the voltage difference between the electrodes on both sides of the capacitor C1 becomes zero, so that the charge (initial charge) held in the capacitor C1 during the enable-off period can be reset in the same way as the oscillator circuit 100e of the fourth embodiment. This makes it possible to prevent an overvoltage exceeding VDD from occurring at the input node Na when the enable-off is released, in the same way as in the fourth embodiment.

In the oscillator circuit 100h, when the enable signals EN0 and EN1 are set to the H level, the control switch ISWh1 is turned off and the control switch ISWh0 is turned on, so that the circuit state becomes the same as that of the oscillator circuit 100a (FIG. 2) according to the first embodiment. Therefore, after the enable-off period is released, the oscillator circuit 100h operates in the same manner as the oscillator circuit 100a, and can generate the oscillation signal Vosc.

In the oscillator circuit 100h according to the first modification of the fourth embodiment, the overvoltage of the input node Na when the enable-off is released can be suppressed, similar to the oscillator circuit 100e according to the fourth embodiment. Furthermore, in the oscillator circuit 100i, the control switch in the off state connected to the input node Na can be unconfigured when the oscillation signal Vosc is generated (EN1=H level period). As a result, compared to the oscillator circuit 100g (FIG. 20), the oscillator circuit 100i can improve the frequency accuracy of the oscillation signal Vosc by suppressing the parasitic capacitance added to the input node Na that determines the oscillation frequency.

22 shows an example in which the control switch ISWh1 is connected between the electrode on the node Nc side of the capacitor C1 (the electrode on the opposite side to the input node Na) and the node Nb, but instead of the node Nb, the control switch ISWh1 may be connected to another node that maintains a voltage at the same level (H/L level) as the input node Na during the enable-off period. Similarly, instead of the node Nc, the control switch ISWh0 may be connected between the electrode on the node Nc side of the capacitor C1 and another node that exhibits a voltage at the opposite level (H/L level) to the input node Na after the enable-off is released.

Variation 2 of embodiment 4.
FIG. 23 is a circuit diagram illustrating a configuration example of an oscillator circuit 100i according to a second modification of the fourth embodiment.

As shown in FIG. 22, the oscillator circuit 100i differs from the oscillator circuit 100g of FIG. 20 in that instead of the control switch ISWg1, it has control switches ISWi0, ISWi1, and control switches ISWi2, ISWi3 provided at both ends of the capacitor C1.

The control switch ISWi0 is connected between the electrode of the capacitor C1 on the input node Na side and the input node Na, and is turned on and off in response to the enable signal EN0. The control switch ISWi1 is connected between the electrode of the capacitor C1 on the input node Na side and ground (GND), and is turned on and off in response to the enable signal EN1.

The control switch ISWi0 is turned off during the enable-off period (EN0 = L level) and turned on during the enable-off release period (EN0 = H level). Conversely, the control switch ISWi1 is turned on during the enable-off period (EN1 = L level) and turned off during the enable-off release period (EN1 = H level).

The control switch ISWi2 is connected between one electrode on the node Nc side of the capacitor C1 and the node Nc, and is turned on and off in response to the enable signal EN2. The control switch ISWi3 is connected between one electrode on the node Nc side of the capacitor C1 and ground (GND), and is turned on and off in response to the enable signal EN3.

The control switch ISWi2 is turned off during the enable-off period (EN2 = L level) and turned on during the enable-off release period (EN2 = H level). Conversely, the control switch ISWi3 is turned on during the enable-off period (EN3 = L level) and turned off during the enable-off release period (EN3 = H level).

Furthermore, between the enable signals EN0 to EN3, timing adjustments (addition of dead time) are appropriately performed so that none of the following periods occur: a period when both control switches ISWi0 and ISWi1 are on, a period when both control switches ISWi2 and ISWi3 are on, a period when both control switches ISWi0 and ISWi3 are on, or a period when both control switches ISWi1 and ISWi2 are on.

Each of the control switches ISWi0 to ISWi3 can be configured as a transfer gate made of at least one of a P-type transistor and an N-type transistor that is turned on and off in response to the enable signals EN0 to EN3. In the example of FIG. 23, the control switch ISWi0 is configured by connecting in parallel an N-type transistor MNi10 whose gate receives the enable signal EN0, and a P-type transistor MPi10 whose gate receives the inverted signal EN0B of the enable signal EN0. The control switch ISWi1 is configured by connecting in parallel a P-type transistor MPi11 whose gate receives the enable signal EN1, and an N-type transistor MNi11 whose gate receives the inverted signal EN1B of the enable signal EN1.

23, the control switch ISWi3 is configured by connecting in parallel a P-type transistor MPhi13, whose gate receives the enable signal EN3, and an N-type transistor MNi13, whose gate receives the inverted signal EN3B of the enable signal EN3. The control switch ISWi2 is configured by connecting in parallel an N-type transistor MNi12, whose gate receives the enable signal EN2, and a P-type transistor MPi12, whose gate receives the inverted signal EN2B of the enable signal EN2.

Therefore, in the oscillator circuit 100i, during the enable-off period (EN0 to EN3 = L level), both ends of the capacitor C1 are connected to ground (GND), and the voltage difference between both electrodes of the capacitor C1 becomes zero. As a result, the charge (initial charge) held in the capacitor C1 during the enable-off period can be reset in the same way as the oscillator circuit 100e of the fourth embodiment. This makes it possible to prevent an overvoltage exceeding VDD from occurring at the input node Na when the enable-off is released, in the same way as in the fourth embodiment.

In the oscillator circuit 100i, when the enable signals EN0 to EN3 are set to the H level, the control switches ISWi1 and ISWi3 are turned off and the control switches ISWh0 and ISWi2 are turned on, so that the circuit state becomes the same as that of the oscillator circuit 100a (FIG. 2) according to the first embodiment. Therefore, after the enable-off period is released, the oscillator circuit 100i operates in the same manner as the oscillator circuit 100a, and can generate the oscillation signal Vosc.

In the oscillator circuit 100i according to variant example 2 of embodiment 4, the charge (initial charge) held in capacitor C1 when enable off is released can be reset more reliably than in the oscillator circuits 100g and 100h described above.

In the fourth embodiment and its modified examples, the number of control switches can be adjusted as desired. In the first to fourth embodiments and their modified examples, node Nb corresponds to the "first node", node Nd corresponds to the "second node", and node Nc corresponds to the "fourth node". In the present embodiment, an example has been shown in which the second logic circuit 30 is composed of two inverters (INV2, INV3), so node Nd also corresponds to the "third node" to which feedback resistor 40 is connected.

In the first to fourth embodiments and their modified examples, the second logic circuit 30 is shown to be composed of two inverters (logic inversion circuits), but the number is arbitrary. In this case, the feedback capacitance 50 can be connected between the input node Na and the output node of any logic inversion circuit (inverter) in which an even number of inverters (logic inversion circuits) are connected in series between the input node Na and the output node of any logic inversion circuit (inverter). Similarly, the feedback resistor 40 can be connected between the input node Na and the output node of any logic inversion circuit (inverter) in which an odd number of inverters (logic inversion circuits) are connected in series between the input node Na and the output node of any logic inversion circuit (inverter).

Furthermore, the oscillation signal Vosc does not need to be the output of the final stage inverter of the second logic circuit 30, and any output signal of at least one of the inverters that constitute the second logic circuit 30 can be used as the oscillation signal Vosc.

In addition, in the first to fourth embodiments and their modified examples, the transistors that control the connection of the resistors or inverters (the transistors that constitute the selection unit 20 and the resistance control unit 45) are illustrated as field effect transistors, but the transistors that control the switches can also be replaced with bipolar transistors. That is, the P-type switch transistor can also be configured with a pnp-type bipolar transistor, and the N-type switch transistor can also be configured with an npn-type bipolar transistor.

The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The technical scope of the present disclosure is indicated by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

10 first logic circuit, 20 selection unit, 25, 26 delay adjustment circuit, 30 second logic circuit, 40 feedback resistor, 45 resistance control unit, 50 feedback capacitance, 90 control circuit, 100a to 100i oscillation circuit, 201 to 203 circuit block, C1 capacitor, CINV, CINV1 to CINVN, CINV11 to CINV13, VCINV clocked inverter, CNT1, CNT2, VISW, VISW1 to VISW3, VISW1B, VISW1B to VISW3B, VISWN[N:1], VISWP[N:1], VRSW1 to VRSW3 control signal, EN0 to EN3 enable signal, EN0B to EN3B inverted signal (enable signal), Cgdn, Cgsp gate capacitance, Cpn, Cpp Parasitic capacitance, Coc capacitance value (feedback capacitance), DDSW, DDSW1 to DDSW3, DSW, DSW1 to DSW3, DSW11 to DSW13 dummy switch circuit, GND ground voltage, INV, INV1, INV2, INV3, INV11 to INV13, INV11X to INV13X inverter, ISWg1, ISWh0 to ISWh1, ISWi0 to ISWi2 control switch, IPT1 to IPT3, IPT11 to IPT13, IPT21 to IPT23, IPT31 to IPT33, IPTM first stage inverter path, ISW, ISW1 to ISW3, ISW11 to ISW13 switch circuit, NL ground line, Na input node, Nb to Nd nodes, No output node (inverter), PL power line, Spl Pulse signal, R1 to R3 resistive elements, Roc resistance value (feedback resistor), Tdn first delay time (rising edge), Tdp second delay time (falling edge), Tosc oscillation period, VDD power supply voltage, Vinv inversion threshold voltage, Vosc oscillation signal.

Claims (17)

a plurality of signal paths each configured to pass through a first logic inverter circuit that generates an output signal that is set to a first logic level or a second logic level according to a comparison result between a voltage at an input node and an inversion threshold voltage;
a selection unit that selects one of the plurality of signal paths and transmits the output signal to a first node;
at least one second logic inverter circuit connected in series between a second node and the first node;
a feedback resistor connected between a third node, which is either an input side or an output side of the second logic inversion circuit, and the input node;
a fourth node which is an input side or an output side of the second logic inversion circuit and is different from the third node, and a feedback capacitance connected between the input node and the fourth node;
the plurality of signal paths are formed such that at least one of the inversion threshold voltage of the first logic inversion circuit included in each signal path and an edge propagation delay difference of the output signal in each signal path is different from one another;
an oscillator circuit, wherein the edge propagation delay difference corresponds to the difference between a first delay time occurring during a first transition from the first logic level to the second logic level and a second delay time occurring during a second transition from the second logic level to the first logic level. the plurality of signal paths each include a plurality of the first logic inversion circuits, each of which has an input side commonly connected to the input node and has the inversion threshold voltage different from one another;
the selection unit includes, in each of the plurality of signal paths, a switch circuit connected in series with the first logic inversion circuit between the input node and the first node,
2. The oscillation circuit according to claim 1, wherein the selection section turns on the switch circuit in the selected one of the signal paths based on a control signal. The oscillator circuit includes:
a first delay adjustment circuit for providing an equal delay time to each of the first transition and the second transition of the output signal in the selected one of the signal paths;
3. The oscillator circuit according to claim 2, wherein the delay times provided by the first delay adjustment circuit differ among the plurality of signal paths. the first delay adjustment circuit includes a first dummy switch circuit connected in series with the switch circuit between the first logic inversion circuit and the first node in each of the plurality of signal paths;
the first dummy switch circuit is configured to perform an on/off operation in a complementary manner with the switch circuit connected in series, and to provide an equal delay time to each of the first transition and the second transition of the output signal;
4. The oscillation circuit according to claim 3, wherein the delay times provided by the first dummy switch circuits differ among the plurality of signal paths. the plurality of signal paths are configured to branch the output signal of the common first logic inversion circuit into a plurality of paths;
the selection unit includes a switch circuit connected in series with the first logic inversion circuit between the input node and the first node in each of the plurality of signal paths, and is configured to turn on the switch circuit in the one signal path selected based on a control signal;
The oscillator circuit includes:
a second delay adjustment circuit connected between an output side of the first logic inversion circuit and the first node;
the second delay adjustment circuit applies the first delay time and the second delay time to the first transition and the second transition of the output signal, respectively, in the one selected signal path;
2. The oscillation circuit according to claim 1, wherein a difference between the first delay time and the second delay time provided by the second delay adjustment circuit differs among the plurality of signal paths. the plurality of signal paths are configured by branching, into a second plurality of outputs, each of the first plurality of first logic inversion circuits having an input side commonly connected to the input node and having mutually different inversion threshold voltages,
the selection unit includes a switch circuit connected between an output side of one of the first plurality of first inversion logic circuits and the first node in each of the plurality of signal paths;
the selection unit turns on the switch circuit in the one selected signal path based on a control signal;
The oscillator circuit includes:
a second delay adjustment circuit for applying the first delay time and the second delay time to the first transition and the second transition of the output signal in the selected one signal path,
2. The oscillation circuit according to claim 1, wherein a difference between the first delay time and the second delay time provided by the second delay adjustment circuit differs among the plurality of signal paths. the second delay adjustment circuit includes, in each of the plurality of signal paths, a second dummy switch circuit connected in series with the switch circuit between the first logic inversion circuit and the first node,
the second dummy switch circuit is configured to perform an on/off operation complementary to the switch circuit connected in series with the second dummy switch circuit, and to provide the first delay time and the second delay time to the first transition and the second transition of the output signal, respectively;
6. The oscillation circuit according to claim 5 , wherein a difference between the first delay time and the second delay time provided by the second dummy switch circuit differs among the plurality of signal paths. the first logic inversion circuit includes a P-type field effect transistor and an N-type field effect transistor, the gates of which are commonly connected to the input node;
the N-type field effect transistor is connected between a first wiring that supplies a first voltage corresponding to the first logic level and an output node at which the output signal is generated;
the P-type field effect transistor is connected between a second wiring supplying a second voltage corresponding to the second logic level and the output node;
Between the first logic inversion circuits having different inversion threshold voltages,
2. The oscillator circuit according to claim 1 , wherein a ratio of a transistor size of said P-type field effect transistor to a transistor size of said N-type field effect transistor is different. the plurality of signal paths each include, as the first logic inversion circuit, a plurality of clocked inverters whose input sides are commonly connected to the input node and whose inversion threshold voltages are different from one another;
2. The oscillator circuit of claim 1, wherein the selection section controls operation and stopping of each of the plurality of clocked inverters based on a control signal, and selects the one signal path by operating one of the plurality of clocked inverters. The oscillator circuit includes:
a first delay adjustment circuit disposed between the plurality of clocked inverters and the first node;
the first delay adjustment circuit is configured to impart an equal delay time to each of the first transition and the second transition of the output signal in the selected one signal path;
10. The oscillator circuit according to claim 9, wherein the delay times provided by the first delay adjustment circuit differ among the plurality of signal paths. the first delay adjustment circuit includes a first dummy switch circuit connected between each of the clocked inverters and the first node in each of the plurality of signal paths;
the first dummy switch circuit is configured to provide an equal delay time to each of the first transition and the second transition of the output signal in the selected one signal path while being fixed to an off state;
The oscillation circuit according to claim 10 , wherein the delay times provided by the first dummy switch circuits differ among the plurality of signal paths. the first logic inversion circuit is configured to selectively form one inverter among a plurality of inverters having different inversion threshold voltages between the input node and the first node in response to a first control signal and a second control signal each having a plurality of bits;
each of the signal paths includes the inverters;
2. The oscillator circuit according to claim 1, wherein the selection section selects the one inverter from the plurality of inverters based on the first control signal and the second control signal, thereby selecting the one selected signal path. The first logic inversion circuit is
a plurality of clocked inverters connected in parallel between a first wiring that supplies a first voltage corresponding to the first logic level and a second wiring that supplies a second voltage corresponding to the second logic level;
Each of the plurality of clocked inverters
an N-type field effect transistor and a first switch transistor connected in series between the first wiring and an output node at which the output signal is generated;
a P-type field effect transistor and a second switch transistor connected in series between the second wiring and the output node;
the gates of the N-type field effect transistor and the P-type field effect transistor of each of the clocked inverters are commonly connected to the input node;
In the plurality of clocked inverters, each of the first switch transistors is turned on and off in response to a different bit of the first control signal, and each of the second switch transistors is turned on and off in response to a different bit of the second control signal,
in the first logic inversion circuit, a first transistor size of at least one N-type field effect transistor connected in parallel between the output node and the first wiring is changed stepwise as a whole by turning on the first switch transistor in response to the first control signal, and a second transistor size of at least one P-type field effect transistor connected in parallel between the output node and the second wiring is changed stepwise as a whole by turning on the second switch transistor in response to the second control signal,
The oscillator circuit according to claim 12 , wherein a ratio of the first transistor size to the second transistor size varies among the plurality of signal paths. the second delay adjustment circuit includes, in each of the plurality of signal paths, a second dummy switch circuit connected in series with the switch circuit between the first logic inversion circuit and the first node,
the second dummy switch circuit is configured to perform an on/off operation complementary to the series-connected switch circuit, and to provide the first delay time and the second delay time to the first transition and the second transition of the output signal, respectively;
7. The oscillation circuit according to claim 6, wherein a difference between the first delay time and the second delay time provided by the second dummy switch circuit differs among the plurality of signal paths. at least one of the first logic inversion circuit and the second logic inversion circuit is configured such that an output signal is fixed to either the first logic level or the second logic level during an enable-off period in response to an enable signal;
The oscillator circuit includes:
at least one control switch that is provided in correspondence with at least one of the electrodes on both sides of the feedback capacitance and that is turned on and off in response to the enable signal;
15. The oscillation circuit according to claim 1, wherein the at least one control switch operates such that the feedback capacitance is connected between the fourth node and the input node when the enable-off period is released, while changing a connection destination of the at least one electrode from when the enable-off period is released so that a voltage difference between the electrodes on both sides becomes zero during the enable-off period. 16. The oscillator circuit according to claim 15 , wherein the at least one control switch operates to connect one or both electrodes of the feedback capacitance to ground during the enable-off period. 16. The oscillator circuit according to claim 15 , wherein the at least one control switch operates such that the feedback capacitance is connected between the first node and the input node during the enable-off period.

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