JP7600518B2 - Multilayer structure, method for manufacturing multilayer structure, and method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a multilayer structure (SiC epitaxial growth substrate), which is a composite structure in which a silicon carbide (SiC) single crystal is epitaxially grown on a single crystal or the like that serves as a base substrate, a method for manufacturing the multilayer structure, and a method for manufacturing a semiconductor device.

It is known that a multilayer structure including an epitaxially grown layer of SiC contains many stacking faults, which adversely affect the characteristics of a semiconductor device. Commercially available SiC substrates contain threading screw dislocations and edge dislocations that propagate in the c-axis direction, and basal plane dislocations (BPDs) that propagate in the basal plane. There are also many mixed dislocations (dislocation loops) that are a mixture of screw dislocations and edge dislocations. These dislocations in the multilayer structure propagate into the epitaxial layer during epitaxial growth and are inherited. It is known that threading dislocations such as screw dislocations and edge dislocations increase the leakage current of semiconductor devices using SiC single crystals (hereinafter referred to as "SiC semiconductor devices"). Patent Document 1 describes that ions are implanted into the main surface of a substrate constituting a multilayer structure to reduce crystallinity, and then heat treatment is performed to restore crystallinity, thereby eliminating screw dislocations from the threading mixed dislocations in the surface layer of the substrate.

On the other hand, basal plane dislocations cause the deterioration of the characteristics of power semiconductor devices using SiC single crystals (hereinafter referred to as "SiC power devices"), especially the deterioration of forward characteristics. For example, it is known that the forward resistance increases when a forward current is passed through a pin diode using a SiC multilayer structure. The increase in the forward resistance of a pin diode occurs when stacking faults expand from basal plane dislocations present in the drift region of the n-type epitaxial layer. The basal plane dislocations continue from the substrate to the epitaxial layer, penetrating the epitaxial layer to the surface. The basal plane dislocations in the drift region can become the origin of stacking faults when minority carriers (holes in the n-type epitaxial layer) are injected from the p-type anode region into the drift region due to current flow.

It is known that dislocations are converted during the process in which dislocations in the substrate propagate to the epitaxial layer. Most of the basal plane dislocations in the substrate are converted to threading dislocations during epitaxial growth, and the remaining few propagate through the epitaxial layer as basal plane dislocations. Since threading dislocations do not expand into stacking faults, it is possible to suppress the occurrence of stacking faults by increasing the conversion rate of basal plane dislocations to threading dislocations in the drift region to close to 100% and further reducing the density of holes injected into the basal plane dislocations.

The conversion rate from basal plane dislocations to threading dislocations is about 95%, and about 5% of them remain in the epitaxial layer. Non-Patent Document 1 reports that the conversion rate from BPD to TED increases by implanting argon (Ar) ions near the top surface of the substrate. However, although they are converted into harmless threading dislocations, the basal plane dislocations at the root of the threading dislocations remain near the substrate interface in the epitaxial layer, making it difficult to completely prevent the defects that cause the expansion of stacking faults. Furthermore, even with regard to the method of reducing the hole density injected from the p-type anode region by using a buffer layer, the threshold hole density at which basal plane dislocations start to expand into stacking faults varies greatly depending on the stress in the substrate. Therefore, in order to prevent the expansion of basal plane dislocations with a small threshold into stacking faults, the current cannot be increased, making it difficult to use at the limit of device performance.

JP 2011-168453 A

C. Heidorn et al., "Basal Plane Dislocation Enhancement in 4H-SiC homo-epitaxial Layers by Ion Implantation into the Wafer Substrate," 12th European Conference on Silicon Carbide and Related Materials, 2018, Proceedings ID: 1228

In view of the above problems, the present invention aims to provide a multilayer structure capable of preventing the expansion of stacking faults and suppressing the deterioration of the forward characteristics of a semiconductor device using SiC, a method for manufacturing the multilayer structure, and a method for manufacturing a semiconductor device.

In order to achieve the above object, one aspect of the present invention comprises: (a) a silicon carbide substrate of a first conductivity type; (b) a buffer layer of the first conductivity type provided on the substrate and having a lower impurity density than the substrate; and (c) an epitaxial growth layer of the first conductivity type provided on the buffer layer and having a lower impurity density than the buffer layer, wherein the buffer layer further comprises a first passivation layer extending in a thickness direction of the buffer layer from an interface with the substrate to an interface with the epitaxial growth layer, the first passivation layer immobilizing basal plane dislocations that occur in the epitaxial growth layer continuously from basal plane dislocations present in the substrate; and The present invention relates to a multilayer structure having an off-angle greater than 0° and smaller than 8° in the [11-20] direction with respect to the [ 11-20] direction, the first passivation layer being a plurality of stripe-shaped second conductivity type semiconductor regions extending parallel to each other in a direction perpendicular to the [11-20] direction , and a spacing d between the plurality of second conductivity type semiconductor regions satisfies h/d>tan θ, where h is the film thickness of the buffer layer and θ is the off-angle of the substrate, and the substrate further comprises a second passivation layer on the surface side of the substrate below the interface between the buffer layer and the substrate , which immobilizes basal plane dislocations with crystal defects, the second passivation layer containing atoms that immobilize basal plane dislocations and being provided on the entire in-plane direction of the substrate.

Another aspect of the present invention includes the steps of: (a) epitaxially growing a buffer layer of a first conductivity type on a silicon carbide substrate of a first conductivity type with a lower impurity density than the substrate; (b) epitaxially growing an epitaxial growth layer of the first conductivity type on the buffer layer with a lower impurity density than the buffer layer ; ( c ) forming a first passivation layer inside the buffer layer, the first passivation layer extending in the thickness direction of the buffer layer from the interface with the substrate to the interface with the epitaxial growth layer, the first passivation layer immobilizing basal plane dislocations occurring in the epitaxial growth layer continuously from basal plane dislocations present in the substrate; and (d) forming a second passivation layer on a surface side of the substrate below the interface between the buffer layer and the substrate, the second passivation layer immobilizing basal plane dislocations by crystal defects , the surface of the substrate being a (0001) plane with an off angle of more than 0° and less than 8° in the [11-20] direction with respect to the [0001] axial direction,
The first passivation layer is a plurality of stripe-shaped second conductivity type semiconductor regions extending parallel to each other in a direction perpendicular to the [11-20] direction , a distance d between the plurality of second conductivity type semiconductor regions satisfies h/d>tan θ, where h is the film thickness of the buffer layer and θ is the off-angle of the substrate, and the second passivation layer contains atoms that immobilize basal plane dislocations and is formed over the entire in-plane direction of the substrate.

Another aspect of the present invention includes the steps of: (a) epitaxially growing a buffer layer of a first conductivity type on a silicon carbide substrate of a first conductivity type with an impurity density lower than that of the substrate; (b) forming a first passivation layer on the entire in-plane direction of the buffer layer, the first passivation layer having a peak in the concentration distribution of atoms that immobilize basal plane dislocations inside the buffer layer within 50 nm from the interface between the substrate and the buffer layer , and immobilizing basal plane dislocations that occur in the buffer layer continuously from basal plane dislocations present in the substrate with crystal defects; (c) epitaxially growing a traveling layer of the first conductivity type on the buffer layer with an impurity density lower than that of the buffer layer; and (d) forming a carrier injection region of a second conductivity type on a surface of the traveling layer for injecting carriers into the traveling layer. The method for epitaxially growing a buffer layer includes a step of epitaxially growing a defect conversion layer on a substrate, the defect conversion layer converting basal plane dislocations into threading dislocations, and a step of epitaxially growing a recombination promotion layer on the defect conversion layer, the recombination promotion layer having a higher impurity density than the defect conversion layer and reducing injected minority carriers through recombination, and further including a step of forming a third passivation layer on the entire in-plane direction of the recombination promotion layer, the third passivation layer having a peak in the concentration distribution of atoms that passivate basal plane dislocations within the recombination promotion layer and located within 50 nm from the interface between the defect conversion layer and the recombination promotion layer, the third passivation layer immobilizing basal plane dislocations present in the recombination promotion layer by crystal defects.

The present invention provides a multilayer structure capable of preventing the expansion of stacking faults and suppressing the deterioration of the forward characteristics of a semiconductor device using SiC, a method for manufacturing the multilayer structure, and a method for manufacturing a semiconductor device.

1 is a schematic cross-sectional view showing an example of a semiconductor device according to a first embodiment of the present invention; FIG. 2( a ) is a schematic top view illustrating an example of a basal plane defect in a SiC substrate, and FIG. 2( b ) is a corresponding schematic cross-sectional view. FIG. 3( a ) is a schematic top view showing an example of the behavior of dislocation defects in a SiC substrate and an epitaxial layer, and FIG. 3( b ) is a corresponding schematic cross-sectional view. FIG. 1 is a top schematic diagram illustrating the expansion of the spacing between partial dislocations in a SiC substrate. 1 is a schematic cross-sectional view showing an example of a position where secondary impurity atoms are introduced by ion implantation into an upper portion of a SiC substrate. FIG. 6( a ) is a schematic top view showing an example of the behavior of dislocation defects in the SiC substrate and growth layer shown in FIG. 5 , and FIG. 6( b ) is a corresponding schematic cross-sectional view. FIG. 7(a) is a schematic top view showing an example of a multilayer structure (epitaxial growth substrate) according to the first embodiment, and FIG. 7(b) is a corresponding schematic cross-sectional view. FIG. 8(a) is a schematic top view showing another example of the multilayer structure according to the first embodiment, and FIG. 8(b) is a corresponding schematic cross-sectional view. FIG. 9(a) is a schematic top view showing another example of the multilayer structure according to the first embodiment, and FIG. 9(b) is a corresponding schematic cross-sectional view. FIG. 10( a ) is a diagram showing an example of an n-type impurity distribution measured by SIMS for the multilayer structure according to the first embodiment, FIG. 10 ( b ) is a diagram showing an example of an impurity distribution of atoms that immobilize corresponding basal plane dislocations, and FIG. 10 ( c ) is a diagram showing another example of an impurity distribution of atoms that immobilize corresponding basal plane dislocations. 3A to 3C are schematic cross-sectional views illustrating an example of a process for manufacturing a semiconductor device using the multilayer structure according to the first embodiment. 12 is a schematic cross-sectional view illustrating an example of a process subsequent to FIG. 11 in the method for manufacturing a semiconductor device using the multilayer structure according to the first embodiment. FIG. 13 is a schematic cross-sectional view illustrating an example of a process subsequent to FIG. 12 in the method for manufacturing a semiconductor device using the multilayer structure according to the first embodiment. FIG. 14 is a schematic cross-sectional view illustrating an example of a process subsequent to FIG. 13 in the method for manufacturing a semiconductor device using the multilayer structure according to the first embodiment. FIG. 15 is a schematic cross-sectional view illustrating an example of a process subsequent to FIG. 14 in the method for manufacturing a semiconductor device using the multilayer structure according to the first embodiment. FIG. 13 is a schematic cross-sectional view illustrating another example of a process subsequent to FIG. 12 in the method for manufacturing a semiconductor device using a multilayer structure according to the first embodiment. FIG. 17 is a schematic cross-sectional view illustrating an example of a process subsequent to FIG. 16 in the method for manufacturing a semiconductor device using the multilayer structure according to the first embodiment. FIG. 5A to 5C are schematic cross-sectional views illustrating an example of a process for manufacturing a semiconductor device using a multilayer structure according to a modified example of the first embodiment. 20 is a schematic cross-sectional view illustrating an example of a step subsequent to FIG. 19 in a method for manufacturing a semiconductor device using a multilayer structure according to a modified example of the first embodiment. FIG. FIG. 1A is a diagram showing an example of an n-type impurity distribution measured by SIMS for a multilayer structure according to a modified example of the first embodiment, and FIG. 1B is a diagram showing an example of an impurity distribution of atoms that immobilize basal plane dislocations. FIG. 11 is a schematic cross-sectional view showing an example of a semiconductor device used to explain a second embodiment of the present invention. 5A to 5C are schematic cross-sectional views illustrating an example of a process for producing a multilayer structure according to a second embodiment. 23 is a schematic cross-sectional view illustrating an example of a process subsequent to that shown in FIG. 22 in the method for producing a multilayer structure according to the second embodiment. FIG. 24 is a schematic cross-sectional view illustrating an example of a process subsequent to FIG. 23 in the method for manufacturing a multilayer structure according to the second embodiment. FIG. 10A to 10C are schematic cross-sectional views illustrating another example of the steps of the method for producing a multilayer structure according to the second embodiment. 26 is a schematic cross-sectional view illustrating another example of a process subsequent to FIG. 25 in the method for manufacturing a multilayer structure according to the second embodiment. FIG. 13 is a schematic cross-sectional view showing an example of a semiconductor device used to explain a modified example of the second embodiment. FIG. 13 is a schematic cross-sectional view illustrating another example of the semiconductor device according to the modified example of the second embodiment. FIG. 13 is a schematic cross-sectional view illustrating another example of the semiconductor device according to the modified example of the second embodiment. FIG. 13 is a schematic cross-sectional view illustrating another example of the semiconductor device according to the modified example of the second embodiment. FIG. 11 is a schematic cross-sectional view illustrating an example of a process for producing a multilayer structure according to a modified example of the second embodiment. FIG. FIG. 33 is a schematic cross-sectional view illustrating an example of a step subsequent to that shown in FIG. 32 in a method for producing a multilayer structure according to a modified example of the second embodiment. FIG. 34 is a schematic cross-sectional view illustrating an example of a step subsequent to FIG. 33 in a method for producing a multilayer structure according to a modified example of the second embodiment. FIG. 35 is a schematic cross-sectional view illustrating an example of a step subsequent to FIG. 34 in a method for producing a multilayer structure according to a modified example of the second embodiment. FIG. 11 is a schematic cross-sectional view showing an example of a semiconductor device used to explain other embodiments. This is a plan view seen from the line AA in Figure 36. FIG. 37 is a schematic cross-sectional view showing an example of a dislocation immobilization layer provided in the semiconductor device shown in FIG. 36. 5A to 5C are schematic cross-sectional views illustrating an example of a process for producing a multilayer structure according to another embodiment. FIG. 40 is a schematic cross-sectional view illustrating an example of a step subsequent to FIG. 39 in a method for manufacturing a multilayer structure according to another embodiment. FIG. 11 is a schematic cross-sectional view showing another example of a multilayer structure used in a semiconductor device according to another embodiment. FIG. 11 is a schematic cross-sectional view showing another example of a multilayer structure used in a semiconductor device according to another embodiment.

Below, an embodiment of the present invention will be described with reference to the drawings. In the description of the drawings, identical or similar parts are given the same or similar reference numerals, and duplicate explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each layer, etc. may differ from the actual ones. Furthermore, there may be parts with different dimensional relationships and ratios between the drawings. Furthermore, the embodiments shown below are examples of devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

In addition, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical idea of the present invention. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and of course if it is rotated 180 degrees and observed, up and down are read inverted. In the following description, the first conductivity type is n-type and the second conductivity type is p-type as an example. However, the conductivity types may be selected in the opposite relationship, with the first conductivity type being p-type and the second conductivity type being n-type. In addition, + and - attached to n and p mean that the semiconductor region has a relatively high or low impurity density, respectively, compared to a semiconductor region without + and -. However, even if the same n and n are attached to semiconductor regions, it does not mean that the impurity density of each semiconductor region is strictly the same. In addition, in the notation of Miller indices in this specification, "-" means a bar attached to the index immediately after it, and adding "-" before the index represents a negative index.

In the following description, a pin diode is used as a representative example of a semiconductor device, but the semiconductor device of the present invention is not limited to a pin diode. For example, the semiconductor device may be a bipolar device such as an insulated gate bipolar transistor (IGBT) in which a forward current flows through a pn junction, a static induction thyristor (SI thyristor), or a gate turn-off (GTO) thyristor. It may also be a MOS field effect transistor (FET), MISFET, or static induction transistor (SIT) in which a body diode having a drain region epitaxially grown on a substrate is parasitic.

First Embodiment
As shown in FIG. 1, the semiconductor device according to the first embodiment of the present invention has a vertical structure including a carrier collection layer 1 made of a semiconductor region of a first conductivity type (n ⁺ type) that collects carriers traveling from above. The semiconductor device according to the first embodiment further includes an n ^- type transit layer 3 in which carriers collected by the carrier collection layer 1 travel vertically in a drift electric field, and a second conductivity type (p ⁺ type) carrier injection region 5 that injects carriers into the transit layer. The transit layer 3 is provided with a first passivation layer 21 near the interface between the carrier collection layer 1 and the transit layer 3. The p ⁺ type carrier injection region 5 is locally embedded in the upper part of the n type transit layer 3 to form a p ⁺ -n ^- junction that constitutes a potential barrier that controls the injection of carriers into the transit layer 3. In the vertical two-terminal structure shown in FIG. 1, the carrier collection layer 1 functions as a "cathode region" and the carrier injection region 5 functions as an "anode region". The multilayer structure shown in FIG. 1 has a substrate made of SiC crystal as the carrier collection layer 1, and an epitaxially grown layer formed by epitaxially growing SiC crystal vertically on the substrate as the travel layer 3. The travel layer 3 functions as a "drift region" in which carriers, which are the main current, drift and travel. To form a two-terminal structure, a cathode electrode 9 is provided as an ohmic electrode on the lower surface of the carrier collection layer 1, and an anode electrode 7 is provided as an ohmic electrode on the upper surface of the carrier injection region 5. A current from an external circuit is supplied to the carrier injection region 5 through the anode electrode 7, and the carriers supplied to the carrier collection layer 1 are supplied to the external circuit as a current through the cathode electrode 9. It is desirable that the impurity density of the travel layer 3 is a low impurity density close to that of an intrinsic semiconductor. When the impurity density of the travel layer 3 is close to that of an intrinsic semiconductor, it can be considered as an "i layer", and in this case, a "pin diode" can be formed by the p ⁺ type carrier injection region 5, the i type travel layer 3, and the n ⁺ type carrier collection layer 1.

The carrier injection region 5 is also a semiconductor region made of SiC crystal. The n-type (first conductivity type) impurity element of the carrier collection layer 1 is, for example, nitrogen (N), and the impurity density is in the range of about 5×10 ¹⁷ cm ^-3 to 1×10 ¹⁸ cm ^-3 , and the thickness of the carrier collection layer 1 is about 100 μm to 600 μm. The surface of the carrier collection layer 1 is a (0001) Si surface, and has an off angle of about 0° to 8° in the <11-20> direction with respect to the <0001> (c-axis) direction. The traveling layer 3 and the carrier injection region 5 epitaxially grown on the carrier collection layer 1 also have the same off angle as the carrier collection layer 1. The n-type impurity of the traveling layer 3 is, for example, N, and the impurity density is in the range of about 1×10 ¹⁴ cm ^-3 to 1×10 ¹⁷ cm ^-3 . The thickness of the travel layer 3 is in the range of about 10 μm to several hundreds of μm, and the optimal thickness and impurity density are selected according to the withstand voltage specifications of the pin diode. For example, about 10 μm is selected for a withstand voltage of 1000 V, and about 100 μm is selected for a withstand voltage of 10 kV. The carrier injection region 5 selectively adds p-type (second conductivity type) impurity elements, which are the opposite conductivity type to the impurities of the travel layer 3, to the upper part of the travel layer 3 to form a p ⁺ -n ^- junction. The anode electrode 7 may include a contact layer, a barrier metal layer, a surface electrode layer, and the like. For example, the contact layer may be a nickel silicide (NiSi _x ) film, the barrier metal layer may be a titanium nitride (TiN) film, and the surface electrode layer may be an aluminum (Al) film. The cathode electrode 9 may be, for example, a single layer film made of gold (Au) or a metal film laminated in the order of Al, nickel (Ni), and Au.

SiC crystals have crystal polymorphism, the main ones being cubic 3C, and hexagonal 4H and 6H. The band gap at room temperature has been reported to be 2.23 eV for 3C-SiC, 3.26 eV for 4H-SiC, and 3.02 eV for 6H-SiC. This invention will be explained using 4H-SiC.

The first passivation layer 21 provided at the interface between the carrier collection layer 1 and the running layer 3 that constitute the substrate is a region provided at a depth of about 50 nm from the interface in the lower part of the running layer 3. This first passivation layer 21 is formed by implanting impurity ions that become atoms that immobilize basal plane dislocations into the lower part of the running layer 3. Any one or more types of atoms among silicon (Si), carbon (C), hydrogen (H), helium (He), argon (Ar), magnesium (Mg), calcium (Ca), barium (Ba), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), and iron (Fe) that become atoms that immobilize basal plane dislocations can be used. The impurity density of the atoms that immobilize basal plane dislocations is preferably in the range of 1×10 ¹⁴ cm ⁻³ or more and 1×10 ¹⁸ cm ⁻³ or less in order to avoid an increase in resistance due to excessive defects caused by ion implantation. More preferably, the impurity density is in the range of 3×10 ¹⁵ cm ^-3 or more and 3×10 ¹⁶ cm ^-3 or less. In this way, it is possible to form a number of crystal defects equivalent to the impurity density. Atoms that immobilize basal plane dislocations other than Si and C, which are the constituent atoms of SiC crystal, can be detected by secondary ion mass spectrometry (SIMS).

As shown in Figures 2(a) and 2(b), a large number of basal plane dislocations (BPDs) exist in an n ⁺ -type 4H-SiC substrate 1s, which is a substrate used as the carrier collection layer 1. The two-dot chain line shown in Figure 2(a) is an intersection line Lb between the surface of the substrate 1s and the basal plane including the substrate-side basal plane dislocation 12 shown in Figure 2(b). The substrate-side basal plane dislocation 12 is decomposed into two partial dislocations, a silicon (Si) core 12s and a carbon (C) core 12c, within the basal plane, and reaches the intersection line Lb. The distance between the substrate-side Si core 12s and the substrate-side C core 12c is about 30 nm to 70 nm.

On the substrate 1s, an epitaxial growth layer (intermediate growth layer) 3e having a lower impurity density than the substrate 1s is grown, for example, to a thickness of about 1 μm. As shown in Figures 3(a) and (b), the substrate-side basal plane dislocation 12 of the substrate 1s extends into the intermediate growth layer 3e and continues to the growth layer-side basal plane dislocation 22. As shown in Figure 3(b), most of the growth layer-side basal plane dislocations 22 are converted to threading dislocations (TED) 14 near the interface between the substrate 1s and the intermediate growth layer 3e during film formation. In this case, as shown in Figure 3(a), the substrate-side Si core 12s and substrate-side C core 12c of the substrate-side basal plane dislocation 12 that was decomposed into two in the substrate 1s during the epitaxial growth process are inherited by the growth layer-side Si core 22s and growth layer-side C core 22c of the growth layer-side basal plane dislocation 22 in the intermediate growth layer 3e. Here, the substrate-side Si core 12s is a Si-Si bond, and the substrate-side C core 12c is a C-C bond. Since the energy of the Si-Si bond is smaller than that of the C-C bond, partial dislocations with Si cores are movable by energy provided by heating or current flow, but partial dislocations with C cores are not movable. Therefore, as shown in FIG. 3(a), the growth layer-side Si core 22s approaches the growth layer-side C core 22c and is converted into one threading dislocation 14. However, some of the growth layer-side basal plane dislocations 22 are not converted into threading dislocations 14 even inside the intermediate growth layer 3e, but are inherited as growth layer-side basal plane dislocations 22z, and reach the surface of the intermediate growth layer 3e at the intersection line Ls.

The increase in the forward resistance of the pin diode is caused by the expansion of stacking faults starting from the growth layer side basal plane dislocations 22z present in the intermediate growth layer 3e shown in Figures 3(a) and (b). More specifically, this occurs when minority carriers are injected from the p-type carrier injection region 5 shown in Figure 1 into the electronic level created by stacking faults in the n-type intermediate growth layer 3e. In the n-type travel layer 3 shown in Figure 1, holes are injected from the carrier injection region 5 as "minority carriers (minority carriers)". It is known that the electronic level of this stacking fault is 0.2 eV to 0.3 eV lower than the lower end of the conduction band of the 4H-SiC crystal. The expansion of stacking faults occurs when electrons in the conduction band generated by current flow or photoexcitation recombine with holes at the electronic level of the stacking faults. The substrate side basal plane dislocations 12 in the substrate 1s are generated to relieve stress inside the crystal caused by non-uniform temperature during the substrate manufacturing stage, and exist in the substrate 1s at a ^density of 1000/cm2. As shown in FIG. 3B, the growth layer side basal plane dislocation 22z is a portion extending from the substrate side basal plane dislocation 12 of the substrate 1s to the intermediate growth layer 3e, and the growth layer side basal plane dislocation 22z penetrates the intermediate growth layer 3e to reach the surface. When a pin diode is manufactured by growing a main growth layer (upper growth layer) thereon using such a multilayer structure (1s, 3e) as an intermediate product, the growth layer side basal plane dislocation 22z in the intermediate growth layer 3e can become the starting point of the expansion of stacking faults due to the passage of current. That is, holes are injected as minority carriers from the p-type carrier injection region constituting the anode region into the running layer constituting the main growth layer (upper growth layer) grown on the intermediate growth layer 3e, and the growth layer side basal plane dislocation 22z can become the starting point of the expansion of stacking faults.

On the other hand, as shown in FIG. 3B, the growth layer side basal plane dislocation 22 corresponds to the portion continuing from the substrate side basal plane dislocation 12 of the substrate 1s to the intermediate growth layer 3e, but is converted into a threading dislocation 14 parallel to the c-axis of the SiC crystal in the intermediate growth layer 3e. The threading dislocation 14 does not expand into a stacking fault. However, in the structure shown in FIG. 1, when the holes injected from the p-type carrier injection region 5 travel through the running layer 3 constituted by the main growth layer (upper growth layer) grown on the intermediate growth layer 3e and reach the vicinity of the interface between the carrier collection layer 1 and the running layer 3, the stacking fault may expand. As shown in FIG. 3B, when the injected holes reach the vicinity of the interface between the substrate 1s and the intermediate growth layer 3e, the holes are injected into the electron level of the stacking fault originating from the growth layer side basal plane dislocation 22. It is said that stacking faults originating from basal plane dislocations 22 on the growth layer side start to expand when the hole density in the vicinity of the interface between the substrate 1s and the intermediate growth layer 3e exceeds a threshold value of 1×10 ¹⁵ cm ^-3 .

It is known that when the intermediate growth layer 3e is epitaxially grown on the substrate 1s, the conversion rate of the growth layer side basal plane dislocations 22 in the peripheral part of the substrate 1s to threading dislocations 14 is lower than in other parts. It is presumed that the reason for this is the large temperature distribution around the substrate 1s. Figure 4 explains the mechanism of the cause of the low dislocation conversion rate in the peripheral part of the substrate 1s. As shown in Figure 4, the substrate side basal plane dislocations 12 in the substrate 1s are decomposed into partial dislocations consisting of the substrate side C core 12c and the substrate side Si core 12s. The temperature when forming the first intermediate growth layer and the upper growth layer on the substrate 1s is about 1600°C, but before increasing the temperature to 1600°C, the temperature is increased to 900°C to 1000°C and maintained for a certain period of time. If the temperature distribution in the substrate 1s during this period of time is large, the temperature difference applies shear stress to the substrate side basal plane dislocations 12. Therefore, as shown in FIG. 4, the gap between the substrate-side Si core 12s and the substrate-side C core 12c expands near the surface of the substrate 1s. FIG. 4 shows a state in which the substrate-side Si core 12s, which is more mobile than the substrate-side C core 12c, moves near the surface, and the gap Db between the partial dislocations formed by the substrate-side Si core 12b and the substrate-side C core 12c expands from the gap Ds between the partial dislocations formed by the original substrate-side Si core 12s and the substrate-side C core 12c. In this way, if the gap Db between the partial dislocations between the substrate-side Si core 12b and the substrate-side C core 12c expands significantly before the epitaxial growth of the first intermediate growth layer and the upper growth layer, the substrate-side basal plane dislocations 12 are less likely to be converted to threading dislocations 14 during epitaxial growth.

As shown in FIG. 5, by providing a second passivation layer 11 in which crystal defects are introduced by ion implantation on the surface of the substrate 1s, it is possible to prevent the spacing of partial dislocations from expanding during the temperature rise during epitaxial growth. That is, it is known that the introduction of crystal defects has the effect of suppressing the movement of partial dislocations. For example, Non-Patent Document 1 reports that the conversion rate of substrate-side basal plane dislocations to threading dislocations is increased by ion implanting argon (Ar) ions into the substrate surface. The second passivation layer 11 is provided by ion implantation on the surface of the substrate 1s before epitaxial growth to suppress the movement of partial dislocations. As a result, as shown in FIG. 6(a) and (b), the conversion rate of growth layer-side basal plane dislocations 22 to threading dislocations 14 is improved in the intermediate growth layer 3e during epitaxial growth on the substrate 1s.

Since the expansion of stacking faults due to forward current flow to the p-n junction does not originate from threading dislocations 14, converting the substrate-side basal plane dislocations 12 in the substrate 1s to threading dislocations 14 has a certain effect on preventing the expansion of stacking faults. However, if the current flow amount or current flow time is increased, the expansion of stacking faults originates near the interface between the intermediate growth layer 3e and the substrate 1s, and stacking faults cannot be completely prevented. This is because, as shown in Figure 6 (a), partial dislocations of the growth layer side Si core 22s remain in the part at the interface between the substrate 1s and the intermediate growth layer 3e where the growth layer side basal plane dislocations 22 are converted to threading dislocations 14. This partial dislocation of the growth layer side Si core 22s is not in the substrate 1s where the substrate side basal plane dislocations 12 are immobile due to ion implantation, but in the intermediate growth layer 3e. Therefore, the growth layer side Si core 22s is in a movable state, and when the energy required for movement is obtained by current flow, it moves and becomes the origin of stacking faults. By providing a second passivation layer 11 on the surface of the substrate 1s, the conversion rate of the substrate-side basal plane dislocations 12 in the substrate 1s to threading dislocations 14 can be increased to approximately 99%. However, since no measures are taken for the growth layer-side Si cores 22s at the interface between the substrate 1s and the intermediate growth layer 3e, where the growth layer-side basal plane dislocations 22 are converted to threading dislocations 14, the expansion of stacking faults cannot be completely prevented.

As shown in FIG. 1, in the semiconductor device according to the first embodiment, a first passivation layer 21 is provided in the running layer 3 near the interface between the carrier collection layer 1 and the running layer 3. Specifically, as shown in FIGS. 7(a) and 7(b), a first passivation layer 21 is provided in the intermediate growth layer 3e near the interface between the substrate 1s and the intermediate growth layer 3e, in which crystal defects are introduced to immobilize the growth layer side basal plane dislocations 22. The crystal defects are formed by ion implantation of atoms that immobilize the crystal defects. The first passivation layer 21 can immobilize the growth layer side Si cores 22s shown in FIG. 7(a), which remain in the intermediate growth layer 3e after the growth layer side basal plane dislocations 22 are converted to threading dislocations 14 at the interface between the substrate 1s and the intermediate growth layer 3e. As shown in FIG. 7B, for example, impurity ions that become atoms that immobilize the growth layer side basal plane dislocations 22 remaining in the intermediate growth layer 3e epitaxially grown to a thickness of about 1 μm are implanted from the surface of the intermediate growth layer 3e to form a first immobilization layer 21. In the first immobilization layer 21, defects induced by implanting atoms that immobilize the growth layer side basal plane dislocations 22 immobilize the growth layer side Si cores 22s of the growth layer side basal plane dislocations 22. Most of the growth layer side basal plane dislocations 22 are converted into threading dislocations 14 within a range of about 50 nm from the interface between the substrate 1s and the intermediate growth layer 3e. Therefore, the first immobilization layer 21 may be provided in the intermediate growth layer 3e within a range of about 50 nm from the interface between the substrate 1s and the intermediate growth layer 3e. As a result, when a forward current is passed through the semiconductor device according to the first embodiment, the expansion of stacking faults caused by the growth layer-side basal plane dislocations 22 can be prevented, and the deterioration of the forward characteristics of the semiconductor device can be suppressed.

In the structure of the semiconductor device according to the first embodiment shown in FIG. 1, the density of holes injected from the p-type carrier injection region 5 recombines with electrons in the n ⁺ -type substrate 1s and rapidly decreases. However, the decrease in hole density is small on the substrate 1s side near the interface between the substrate 1s and the intermediate growth layer 3e, and the Si-core partial dislocations of the substrate-side basal plane dislocations 12 are not immobilized. Therefore, the substrate-side basal plane dislocations 12 present near the surface of the substrate 1s can be the starting point for the expansion of stacking faults due to forward current application. Therefore, as shown in FIGS. 8(a) and 8(b), it is desirable to provide a second immobilization layer 11 and a first immobilization layer 21 on the substrate 1s side and the growth layer 3e side, respectively, near the interface between the substrate 1s and the intermediate growth layer 3e. For example, the accelerating voltage of ion implantation may be changed from the surface of the intermediate growth layer 3e having a thickness of 1 μm or less to adjust the peak position of the implantation dose distribution of atoms that immobilize the basal plane dislocations. The second passivation layer 11 is preferably provided within the substrate 1 .mu.m from the interface between the substrate 1s and the intermediate growth layer 3e, that is, in a region 1 .mu.m deep on the surface of the substrate 1s on the intermediate growth layer 3e side.

In the above description, the first passivation layer 21 is provided over the entire surface near the interface between the substrate 1s and the intermediate growth layer 3e in a plan view, but this is not limited thereto. For example, as shown in Figures 9(a) and (b), in a planar pattern, multiple first passivation layers 21a may be provided in parallel stripes in a direction perpendicular to the [11-20] direction. The substrate-side basal plane dislocations 12 tend to propagate in the [11-20] direction. For example, if the substrate 1s is off by 4°, and the spacing s of the first passivation layers 21a is about 2 μm, the height h can be set to about 0.14 μm or more to prevent the extension of the growth layer-side basal plane dislocations 22.

-Method of manufacturing semiconductor device-
Next, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described using a pin diode as an example, with reference to the impurity profile shown in Fig. 10 and the process diagrams shown in Fig. 11 to Fig. 15. Note that the method for manufacturing a pin diode described below is only an example, and it goes without saying that various other manufacturing methods, including modifications thereof, can be used within the scope of the spirit described in the claims.

As shown in Fig. 11, an n ⁺ type substrate 1s of 4H-SiC crystal is prepared. The main surface of the substrate 1s is a (0001) Si surface off-set by 4° in the <11-20> direction, and the thickness is about 100 µm to 600 µm. The substrate 1s is doped with an n-type impurity element such as nitrogen (N) at an impurity density of about 5 x 10 ¹⁷ cm ^-3 to 1 x 10 ¹⁸ cm ^-3 . The substrate 1s contains a large number of substrate-side basal plane dislocations 12, but Fig. 11 shows a schematic diagram of one substrate-side basal plane dislocation 12.

As shown in FIG. 12, an n-type intermediate growth layer 3e is epitaxially grown on a substrate 1s by vapor phase epitaxial growth or the like to produce a multilayer structure (1s, 3e) as an intermediate product. As shown in FIG. 10(a), an n-type impurity element such as N is doped in the intermediate growth layer 3e at a lower impurity density of about 1×10 ¹⁴ cm ⁻³ to 1×10 ¹⁷ cm ⁻³ than that of the substrate 1s. The thickness of the intermediate growth layer 3e is about 1 μm. The substrate-side basal plane dislocations 12 present in the substrate 1s propagate into the intermediate growth layer 3e as growth layer-side basal plane dislocations 22. In the intermediate growth layer 3e within a range of 50 nm or less from the interface between the substrate 1s and the intermediate growth layer 3e, the growth layer-side basal plane dislocations 22 are converted to threading dislocations 14 at a conversion rate of about 95%.

As shown in FIG. 13, the ion implantation technique is used to implant atoms that immobilize basal plane dislocations, such as Ar atoms 221, into the intermediate growth layer 3e so that the interface between the substrate 1s and the intermediate growth layer 3e is the projected range. As shown in FIG. 7(a), the growth layer side Si core 22s of the growth layer side basal plane dislocation 22 remains at the position where the growth layer side basal plane dislocation 22 rises from the basal plane to the threading dislocation 14. Therefore, as shown in FIG. 10(b), the dose peak P2 of the implantation of the Ar atoms 221 ions is adjusted to be near the rising position of the threading dislocation 14. In reality, the rising position at which the growth layer side basal plane dislocation 22 is converted to the threading dislocation 14 during epitaxial growth varies during epitaxial growth. Therefore, it is desirable to use multi-stage ion implantation in which the acceleration voltage of ion implantation is changed so that the peak of the dose of the implanted Ar ions is distributed near the interface between the intermediate growth layer 3e and the substrate 1s, for example, within the intermediate growth layer 3e at a distance of about 50 nm from the interface. Note that although Ar is used as an atom that immobilizes basal plane dislocations, any one or more of the following atoms may be used: H, He, Ar, Mg, Ca, Ba, Ti, V, Cr, Mn, and Fe.

Thereafter, as shown in FIG. 14, in order to control the state of the defects introduced by ion implantation, a heat treatment is performed at about 900° C. to 1400° C. for about 30 minutes to 2 hours to form a first passivation layer 21. An n-type main growth layer (upper growth layer) is further epitaxially grown on the intermediate growth layer 3e, and a travel layer 3 consisting of the first intermediate growth layer and the upper growth layer is formed on the substrate 1s. The travel layer 3 is doped with an n-type impurity element such as N at an impurity density of about 1×10 ¹⁴ cm ⁻³ to 1×10 ¹⁷ cm ⁻³ , which is lower than that of the substrate 1s. The thickness of the travel layer 3 is in the range of about 10 μm to several hundreds of μm, and the optimal thickness and impurity density are selected according to the withstand voltage specifications of the pin diode. For example, about 10 μm is selected for a withstand voltage of 1000 V, and about 100 μm is selected for a withstand voltage of 10 kV. The threading dislocations 14 present in the intermediate growth layer 3e propagate into the upper growth layer of the travel layer 3. The heat treatment of the ion-implanted layer may be carried out during the additional epitaxial growth of the traveling layer 3 .

Next, as shown in FIG. 15, a p-type carrier injection region 5 of Al or the like is selectively formed on the upper part of the running layer 3. For example, an ion injection mask may be formed by photolithography, and p-type impurity ions of Al or the like may be injected at a high impurity density on the upper part of the running layer 3. Next, the lower surface of the substrate 1s is polished by chemical mechanical polishing (CMP) or the like to adjust the thickness, and the carrier collection layer 1 is finished to a thickness required by the electrical characteristics of the semiconductor device. A back electrode (cathode electrode) 9 made of Au or the like is formed on the lower surface of the carrier collection layer 1 by sputtering or vacuum deposition. Furthermore, a metal film of Al or the like is deposited by sputtering or vacuum deposition to form a surface electrode (anode electrode) 7. In this way, the semiconductor device according to the first embodiment shown in FIG. 1 is completed.

In the structure shown in FIG. 1, the density of holes injected from the p-type carrier injection region 5 recombines with electrons in the n ⁺ -type carrier collection layer 1 and rapidly decreases. However, the decrease in the hole density in the carrier collection layer 1 is small near the interface between the carrier collection layer 1 and the running layer 3, and the Si-core partial dislocations of the substrate-side basal plane dislocations 12 are not immobilized. Therefore, the substrate-side basal plane dislocations 12 present near the surface of the carrier collection layer 1 can be the starting point for the expansion of stacking faults due to forward current flow. For this reason, when the first immobilization layer 21 is formed by ion implantation of Ar atoms 221, the second immobilization layer 11 may be formed at the same time. Here, the second immobilization layer 11 is preferably formed in the substrate 1s within 1 μm from the interface between the substrate 1s and the intermediate growth layer 3e. In addition, the first immobilization layer 21 may be formed so that the second immobilization layer 11 is in contact with the first immobilization layer 21 by ion implantation of Ar atoms 221 also at the interface between the carrier collection layer 1 and the running layer 3.

For example, as shown in FIG. 16, near the interface between the substrate 1s and the intermediate growth layer 3e, Ar atoms 221a are ion-implanted into the intermediate growth layer 3e, Ar atoms 221b are ion-implanted into the interface, and Ar atoms 221c are ion-implanted into the substrate side. Then, as shown in FIG. 17, an n-type main growth layer (upper growth layer) is epitaxially grown on the intermediate growth layer 3e to form a running layer 3 on the substrate 1s. Near the interface between the substrate 1s and the running layer 3, a second passivation layer 11 is formed on the substrate 1s side, and a first passivation layer 21 is formed on the running layer side. The first passivation layer 21 and the second passivation layer 11 can be formed into a nearly flat distribution, with the peaks P2a, P2b, and P2c of the dose distribution corresponding to the ion-implanted Ar atoms 221a, 221b, and 221c overlapping each other, as shown in FIG. 10(c). As a result, the first immobilization layer 21 and the second immobilization layer 11 come into contact at the interface between the substrate 1s and the intermediate growth layer 3e. This immobilizes the growth layer side Si core 22s of the growth layer side basal plane dislocation 22 that exists on the substrate 1s side near the interface between the substrate 1s and the running layer 3, making it possible to prevent the expansion of stacking faults due to forward current flow.

In the manufacturing method of the semiconductor device according to the first embodiment, the intermediate growth layer 3e is epitaxially grown on the substrate 1s, and Ar atoms 221 are ion-implanted from the upper surface of the intermediate growth layer 3e to form the first passivation layer 21. This allows the position of the crystal defect introduced by the ion implantation of the Ar atoms 221 to be controlled with high precision in the running layer 3 near the interface between the carrier collection layer 1 and the running layer 3, where the threading dislocation 14 rises. Therefore, it is possible to immobilize the partial dislocation of the growth layer side Si core 22s of the growth layer side basal plane dislocation 22 remaining in the running layer 3 near the interface between the carrier collection layer 1 and the running layer 3. In addition, the second passivation layer 11 is formed in the substrate 1s within 1 μm from the interface between the substrate 1s and the intermediate growth layer 3e by ion implantation. This immobilizes the partial dislocation in the substrate 1s, and increases the conversion rate of the substrate side basal plane dislocation 12 to the threading dislocation 14. As a result, when a forward current is passed through the semiconductor device according to the first embodiment, the expansion of stacking faults caused by the growth layer-side basal plane dislocations 22 can be prevented, and the deterioration of the forward characteristics of the semiconductor device can be suppressed.

(Modification of the first embodiment)
As described above, in the semiconductor device according to the first embodiment of the present invention, the intermediate growth layer 3e converts about 95% of the growth layer side basal plane dislocations 22 into threading dislocations 14, but about 5% of them propagate through the upper growth layer epitaxially grown on the intermediate growth layer 3e and can become the starting point for the expansion of stacking faults. In the modified example of the first embodiment, as shown in FIG. 18, a second passivation layer 11 in which crystal defects are introduced by ion implantation is provided in advance near the upper surface of the substrate 1s. The second passivation layer 11 can improve the conversion efficiency of the substrate side basal plane dislocations 12 into threading dislocations 14. The semiconductor device according to the modified example of the first embodiment differs from the first embodiment in that the second passivation layer 11 is provided by ion implantation in advance on the surface of the substrate 1s before the epitaxial growth of the intermediate growth layer 3e. Since the other configurations are the same as those of the first embodiment, the overlapping descriptions will be omitted.

-Method of manufacturing intermediate products-
A method for manufacturing a multilayer structure (1s, 3e) as an intermediate product according to a modified example of the first embodiment of the present invention will be described with reference to the process diagrams shown in Figures 18 and 19 and the impurity profile shown in Figure 20. Note that the method for manufacturing a multilayer structure (1s, 3e) as an intermediate product described below is one example before growing an upper growth layer, and it goes without saying that various other manufacturing methods, including this modified example, can be used within the scope of the spirit described in the claims.

18, before epitaxial growth, impurity ions that become atoms that immobilize substrate-side basal plane dislocations 12, such as Ar, are implanted from the top surface of a substrate 1s doped with an n-type impurity element such as N at an impurity density of about 5×10 ¹⁷ cm ^-3 to 1×10 ¹⁸ cm ^-3 to provide a second immobilization layer 11. The second immobilization layer 11 is formed by ion implantation with the projected range adjusted so that the atoms that immobilize basal plane dislocations are distributed within a range of about 1 μm from the top surface of the substrate 1s.

Thereafter, as shown in FIG. 19, an n-type intermediate growth layer 3e is epitaxially grown on the substrate 1s to produce a multilayer structure (1s, 3e) as an intermediate product. As shown in FIG. 20(a), an n-type impurity element such as N is doped in the intermediate growth layer 3e at a lower impurity density of about 1×10 ¹⁴ cm ⁻³ to 1×10 ¹⁷ cm ⁻³ than that of the substrate 1s. The thickness of the intermediate growth layer 3e is about 1 μm. The substrate-side basal plane dislocations 12 present in the substrate 1s propagate as growth layer-side basal plane dislocations 22 in the intermediate growth layer 3e. The partial dislocations of the substrate-side Si core 12s of the substrate-side basal plane dislocations 12 are immobilized by the second immobilization layer 11 as described in FIG. 6(a) and (b). Therefore, the growth layer-side basal plane dislocations 22 propagating from the substrate 1s are converted to threading dislocations 14 at a high conversion rate of about 99% within the intermediate growth layer 3e within a range of 50 nm or less from the interface between the substrate 1s and the intermediate growth layer 3e.

Furthermore, after the epitaxial growth of the intermediate growth layer 3e, ions of, for example, Ar atoms, which become atoms that immobilize the basal plane dislocations on the growth layer side, are implanted into the intermediate growth layer 3e near the interface between the substrate 1s and the intermediate growth layer 3e. After the ion implantation, a heat treatment is performed at about 900°C to 1400°C for about 30 minutes to 2 hours to control the state of the defects introduced by the ion implantation, and a first immobilization layer 21 is formed as shown in FIG. 19. As shown in FIGS. 20(a) and (b), Ar atoms are distributed in the second immobilization layer 11 so that the peak P1 of the dose distribution is located within 1 μm from the interface on the substrate 1s side, and the peak P2 of the dose distribution is located within 50 nm from the interface on the intermediate growth layer 3e side. In this way, a multilayer structure (1s, 3e) is produced as an intermediate product having a second passivation layer 11 on the side of the substrate 1s where N is highly doped, and a first passivation layer 21 on the side of the intermediate growth layer 3e where N is doped at a lower impurity density than the substrate 1s.

In a modified example of the first embodiment, impurity ions that become atoms that immobilize the substrate-side basal plane dislocations 12 are implanted in advance near the surface of the substrate 1s to form a second immobilization layer 11, and then an intermediate growth layer 3e of about 1 μm is epitaxially grown on the substrate 1s. Furthermore, impurity ions that become atoms that immobilize the growth layer-side basal plane dislocations 22 are implanted from the upper surface of the intermediate growth layer 3e to form a first immobilization layer 21. Since the second immobilization layer 11 is provided on the substrate 1s, partial dislocations of the substrate-side basal plane dislocations 12 present in the substrate 1s can be immobilized during the epitaxial growth of the intermediate growth layer 3e. Therefore, when the main growth layer is epitaxially grown on the multilayer structure (1s, 3e) as the intermediate product, the conversion rate of the growth layer-side basal plane dislocations 22 propagating to the intermediate growth layer 3e during epitaxial growth to threading dislocations 14 can be increased. As a result, it is possible to reduce the growth layer side basal plane dislocations 22 propagating to the main growth layer (upper growth layer) on the upper surface of the intermediate growth layer 3e. In addition, the intermediate growth layer 3e is epitaxially grown to a thickness of about 1 μm on the substrate 1s, and Ar atoms 221 are ion-implanted from the upper surface of the intermediate growth layer 3e near the interface between the substrate 1s and the intermediate growth layer 3e to provide a first immobilization layer 21. Therefore, it is possible to immobilize the partial dislocations of the growth layer side Si core 22s remaining in the intermediate growth layer 3e near the interface between the substrate 1s and the intermediate growth layer 3e after the growth layer side basal plane dislocations 22 are converted into threading dislocations 14. As a result, when a forward current is passed through a semiconductor device having a structure in which the main growth layer (upper growth layer) is epitaxially grown on the multilayer structure (1s, 3e) as an intermediate product, it is possible to prevent the expansion of stacking faults caused by the growth layer side basal plane dislocations 22 and suppress the deterioration of the forward characteristics of the semiconductor device.

Second Embodiment
As shown in FIG. 21, the semiconductor device according to the second embodiment of the present invention includes an n ⁺ type carrier collection layer 1, an n type buffer layer 2, an n ^- type running layer 3, a p ⁺ type carrier injection region 5, an anode electrode 7, and a cathode electrode 9. The carrier collection layer 1 is doped with an n type impurity element such as N at an impurity density of about 5×10 ¹⁷ cm ^-3 to 1×10 ¹⁸ cm ^-3 . The buffer layer 2 as the first intermediate growth layer is doped with an n type impurity element such as N at an impurity density lower than that of the carrier collection layer 1 and higher than that of the running layer 3, for example, about 1×10 ¹⁷ cm ^-3 to 5×10 ¹⁷ cm ^-3 . The buffer layer 2 is provided between the carrier collection layer 1 and the running layer 3, and converts the growth layer side basal plane dislocations 22 (not shown) into threading dislocations 14 (not shown). Furthermore, the electron density in the buffer layer 2 is higher than that in the running layer 3, and can be recombined with holes injected from the running layer 3 when a current is applied, thereby reducing the hole density. The second embodiment differs from the first embodiment in that the buffer layer 2 is provided between the carrier collection layer 1 and the upper growth layer, that is, the running layer 3, and has a higher impurity density than the running layer 3. Since the other configurations are the same as those of the first embodiment, repeated descriptions will be omitted.

In the semiconductor device according to the second embodiment, in the buffer layer 2 grown on the carrier collection layer 1, the growth layer side basal plane dislocations 22 are converted to threading dislocations 14 by about 95%. In this way, the growth layer side basal plane dislocations 22 that have propagated from the carrier collection layer 1 and changed to threading dislocations 14 are present in the buffer layer 2. The buffer layer 2 is doped with n-type impurity elements at a higher impurity density than the travel layer 3, so that the electron density is higher than that of the travel layer 3, and the density of holes injected as minority carriers from the carrier injection region 5 to the travel layer 3 can be greatly reduced in the buffer layer 2. As a result, the density of holes injected into the growth layer side basal plane dislocations 22 remaining in the buffer layer 2 can be reduced, and it is possible to prevent the expansion of stacking faults due to current flow. In addition, impurity ions that become atoms that immobilize the growth layer side basal plane dislocations 22 are implanted into the buffer layer 2 near the interface between the carrier collection layer 1 and the buffer layer 2 to provide a first immobilization layer 21. The ion-implanted atoms that immobilize the basal plane dislocations induce crystal defects in the first immobilization layer 21, immobilizing the partial dislocations of the growth layer side basal plane dislocations 22. Furthermore, the ion-implanted atoms that immobilize the basal plane dislocations can form a hole trapping level, which also has the effect of reducing the hole density. As a result, when a forward current is passed through the semiconductor device, the expansion of stacking faults caused by the growth layer side basal plane dislocations 22 can be prevented, and the deterioration of the forward characteristics of the semiconductor device can be suppressed.

-Method of manufacturing semiconductor device-
Next, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to the process diagrams shown in Fig. 22 and Fig. 24, taking a pin diode as an example. First, as shown in Fig. 22, an n ⁺ type substrate 1s of 4H-SiC crystal is prepared. The main surface of the substrate 1s is a (0001) Si surface off-set by 4° in the <11-20> direction. The substrate 1s is doped with an n-type impurity element such as nitrogen (N) at an impurity density of about 5 x 10 ¹⁷ cm ^-3 to 1 x 10 ¹⁸ cm ^-3 . Although not shown in the drawings, the substrate 1s contains a large number of substrate-side basal plane dislocations 12.

As shown in Fig. 23, an n-type buffer layer 2 is epitaxially grown on a substrate 1s to a thickness of about 1 µm to 10 µm by vapor phase epitaxial growth or the like. The buffer layer 2 as a first intermediate growth layer is doped with an n-type impurity element such as nitrogen (N) at an impurity density of about 1 x ¹⁰¹⁷ cm ^-3 to 5 x ¹⁰¹⁷ cm ^-3 . Then, by ion implantation, ions of, for example, Ar atoms, which become atoms that immobilize the growth layer side basal plane dislocations 22, are implanted into the buffer layer 2 near the interface between the substrate 1s and the buffer layer 2 at an implantation dose of about 1 x ¹⁰¹⁴ cm ^-3 to 1 x ¹⁰¹⁸ cm ^- 3. Subsequently, as shown in Fig. 24, in order to control the state of the defects introduced by the ion implantation, a heat treatment is performed at about 900°C to 1400°C for about 30 minutes to 2 hours to form a first immobilization layer 21.

Thereafter, an n-type main growth layer (upper growth layer) is epitaxially grown on the buffer layer 2 by vapor phase epitaxial growth technology or the like to form the travel layer 3 shown in FIG. 21. The travel layer 3 is doped with an n-type impurity element such as N at a lower impurity density of about 1×10 ¹⁴ cm ^-3 to 1×10 ¹⁷ cm ^-3 than the substrate 1s. The thickness of the travel layer 3 is in the range of about 10 μm to several hundreds of μm, and the optimum thickness and impurity density are selected according to the withstand voltage specifications of the pin diode. For example, about 10 μm is selected for a withstand voltage of 1000 V, and about 100 μm is selected for a withstand voltage of 10 kV.

Next, p-type impurity elements such as Al are ion-implanted into the upper part of the running layer 3 by photolithography and ion implantation techniques, etc., to selectively form a p-type carrier implantation region 5. Next, the underside of the substrate 1s is polished by chemical mechanical polishing (CMP) or the like to adjust the thickness, and the carrier collection layer 1 is finished to the specifications for the cathode region. A back electrode (cathode electrode) 9 made of Au or the like is formed on the underside of the carrier collection layer 1 by sputtering or vacuum deposition, etc. Furthermore, a metal film such as Al is deposited by sputtering or vacuum deposition, etc., to form a surface electrode (anode electrode) 7. In this way, the semiconductor device according to the second embodiment shown in FIG. 21 is completed.

In the semiconductor device according to the second embodiment, an n-type buffer layer 2 is epitaxially grown on a substrate 1s as a first intermediate growth layer. Therefore, the growth layer side basal plane dislocations 22 propagating from the substrate 1s are converted into threading dislocations in the buffer layer 2. In addition, the buffer layer 2 is doped with n-type impurity elements at a higher impurity density than the upper growth layer, the running layer 3. Therefore, the density of holes injected through the running layer 3 into the growth layer side basal plane dislocations 22 present at the interface between the substrate 1s and the buffer layer 2 can be reduced. As a result, the basal plane dislocations can be prevented from expanding into stacking faults.

As shown in FIG. 25, in order to improve the conversion rate of the growth layer side basal plane dislocations 22 propagating from the substrate 1s to the buffer layer 2 during the epitaxial growth of the buffer layer 2 into threading dislocations 14, a second immobilization layer 11 may be provided near the upper surface of the substrate 1s. For example, impurity ions that become atoms that immobilize the substrate side basal plane dislocations 12 are implanted in advance near the upper surface of the substrate 1s to form the second immobilization layer 11 in which crystal defects are introduced. Then, as shown in FIG. 26, an n-type buffer layer 2 is epitaxially grown on the substrate 1s to a thickness of about 1 μm by vapor phase epitaxial growth technology or the like. Next, impurity ions that become atoms that immobilize the growth layer side basal plane dislocations 22 are implanted in the buffer layer 2 near the interface between the substrate 1s and the buffer layer 2 by ion implantation technology to form a first immobilization layer 21. The second passivation layer 11 provided near the top surface of the substrate 1s can improve the conversion efficiency of the substrate-side basal plane dislocations 12 into threading dislocations 14.

(Modification of the second embodiment)
As shown in FIG. 27, the semiconductor device according to the modified example of the second embodiment of the present invention includes an n ⁺ type carrier collection layer 1, an n type buffer layer 2, an n ^- type running layer 3, a p ⁺ type carrier injection region 5, an anode electrode 7, and a cathode electrode 9. The buffer layer 2 is provided between the carrier collection layer 1 and the running layer 3, and includes a defect conversion layer 2a that converts basal plane dislocations into threading dislocations, and a recombination promotion layer 2b that reduces minority carriers injected from the running layer 3 side to the carrier collection layer 1 side. A first passivation layer 21 is provided in the defect conversion layer 2a near the interface between the carrier collection layer 1 and the defect conversion layer 2a, for example, within a range of about 50 nm from the interface. The semiconductor device according to the modified example of the second embodiment is different from the semiconductor device according to the first and second embodiments in that the buffer layer 2 provided between the carrier collection layer 1 and the running layer 3 has the defect conversion layer 2a and the recombination promotion layer 2b. Other configurations are the same as those of the semiconductor device according to the first and second embodiments, so duplicated descriptions will be omitted.

In the semiconductor device according to the modification of the second embodiment, in the defect conversion layer 2a grown as the first intermediate growth layer on the carrier collection layer 1, about 95% of the basal plane dislocations are converted to threading dislocations. The basal plane defects remaining in the defect conversion layer 2a after being converted to threading dislocations in the defect conversion layer 2a are immobilized near the interface with the carrier collection layer 1 by the first immobilization layer 21. Furthermore, in the recombination promotion layer 2b grown as the second and third intermediate growth layers on the defect conversion layer 2a, holes injected from the p ⁺ type carrier injection region 5 are recombined with electrons by current application. Thus, in the semiconductor device according to the modification of the second embodiment, the basal plane dislocations propagated from the carrier collection layer 1 are present in the defect conversion layer 2a. The thicker the defect conversion layer 2a, the lower the frequency of stacking faults. However, since a thicker layer leads to a decrease in the throughput of epitaxial growth, it is preferable to make the thickness as thin as about 1 μm. In order to reduce the hole density injected into the basal plane dislocations present in the defect conversion layer 2a, it is desirable to use an n-type epitaxial layer having a higher impurity density for the defect conversion layer 2a than the running layer 3. Furthermore, in order to reduce the hole density to the threshold value of 1× ¹⁰ cm ⁻³ or less, an n-type recombination promotion layer 2b having a higher impurity density than the defect conversion layer 2a is added.

For example, the carrier collection layer 1 is doped with an n-type impurity element such as N at an impurity density of about 5×10 ¹⁷ cm ^-3 to 1×10 ¹⁸ cm ^-3 . The defect conversion layer 2a as the first intermediate growth layer has a thickness of about 1 μm and is doped with an n-type impurity element such as N at an impurity density lower than that of the carrier collection layer 1 and higher than that of the running layer 3, for example, at about 1×10 ¹⁷ cm ^-3 . The recombination promotion layer 2b as the second and third intermediate growth layers has a thickness of about 5 μm to 10 μm and is doped with an n-type impurity element such as N at an impurity density two to three times higher than that of the defect conversion layer 2a, for example, at about 2×10 ¹⁷ cm ^-3 to 5×10 ¹⁷ cm ^-3 . The running layer 3 as the fourth intermediate growth layer has a thickness of about 10 μm to 100 μm, and is doped with an n-type impurity element such as N at about 1×10 ¹⁴ cm ^-3 to 1×10 ¹⁷ cm ^-3 . The first passivation layer 21 is provided in the defect conversion layer 2a near the interface between the carrier collection layer 1 and the defect conversion layer 2a, for example within a range of about 50 nm from the interface. The first passivation layer 21 is implanted with impurity ions that become atoms that passivate the growth layer side basal plane dislocations 22 at an impurity density of about 1×10 ¹⁴ cm ^-3 to 1×10 ¹⁸ cm ^-3 . More preferably, the impurity density is in the range of 3×10 ¹⁵ cm ^-3 to 3×10 ¹⁶ cm ^-3 . In addition to the n-type impurity element, the recombination-promoting layer 2b may be doped with impurity elements that form a hole capture level, such as B, V, Ti, Fe, and Cr.

In the semiconductor device according to the modified example of the second embodiment, a buffer layer 2 having a defect conversion layer 2a as a first intermediate growth layer and a recombination promotion layer 2b as a second and third intermediate growth layer is epitaxially grown on a carrier collection layer 1. Furthermore, a first passivation layer 21 is provided in the defect conversion layer 2a near the interface with the carrier collection layer 1 by ion implantation. Therefore, the growth layer side basal plane dislocations 22 propagating from the substrate 1s are converted into threading dislocations in the defect conversion layer 2a. Furthermore, the recombination promotion layer 2b is doped with an n-type impurity element having a higher impurity density than the travel layer 3 and the defect conversion layer 2a. Therefore, the density of holes injected from the defect conversion layer 2a through the travel layer 3 as a fourth intermediate growth layer into the growth layer side basal plane dislocations 22 present at the interface between the carrier collection layer 1 and the defect conversion layer 2a can be reduced to a threshold value of 1×10 ¹⁵ cm ⁻³ or less. As a result, when a forward current is passed through the semiconductor device, the growth layer-side basal plane dislocations 22 are prevented from expanding into stacking faults, and degradation of the forward characteristics of the semiconductor device can be suppressed.

As shown in FIG. 28, in order to improve the conversion rate of the growth layer side basal plane dislocations 22 to threading dislocations in the defect conversion layer 2a, a second immobilization layer 11 may be provided near the upper surface of the carrier collection layer 1. As shown in FIG. 29, a third immobilization layer 21d may be provided in the recombination promotion layer 2b as the second and third intermediate growth layers near the interface between the defect conversion layer 2a and the recombination promotion layer 2b. The third immobilization layer 21d immobilizes the growth layer side basal plane dislocations 22 propagating from the defect conversion layer 2a to the recombination promotion layer 2b, thereby improving the conversion rate of the growth layer side basal plane dislocations 22 to threading dislocations in the recombination promotion layer 2b. Furthermore, as shown in FIG. 30, a fourth immobilization layer 21e may be provided in the running layer 3 as the fourth intermediate growth layer near the interface between the recombination promotion layer 2b and the running layer 3. The fourth immobilization layer 21e immobilizes the growth layer side basal plane dislocations 22 that propagate from the recombination promotion layer 2b to the travel layer 3, thereby improving the conversion rate of the growth layer side basal plane dislocations 22 to threading dislocations in the travel layer 3.

-Method of manufacturing semiconductor device-
Next, a method for manufacturing a semiconductor device according to a modified example of the second embodiment will be described with reference to the process diagrams shown in Figures 31 to 34, taking the pin diode shown in Figure 30 as an example. First, as shown in Figure 31, an n-type defect conversion layer (first intermediate growth layer) 2a is epitaxially grown on an n ⁺ -type substrate 1s of 4H-SiC crystal on which a second passivation layer 11 is formed, using a vapor phase epitaxial growth technique or the like. The main surface of the substrate 1s is a (0001) Si surface that is off by 4° in the <11-20> direction. The defect conversion layer 2a has a thickness of, for example, about 1 µm, and is doped with an n-type impurity element such as N at an impurity density of about 1 x 10 ¹⁷ cm ^-3 . Then, by ion implantation technology, ions of, for example, Ar atoms, which become atoms that immobilize the growth layer-side basal plane dislocations 22, are implanted into the defect conversion layer 2a near the interface between the substrate 1s and the defect conversion layer 2a at a dosage of about 1×10 ¹⁴ cm ^-3 to 1×10 ¹⁸ cm ^-3 . Subsequently, in order to control the state of the defects introduced by the ion implantation, a heat treatment is performed at about 900° C. to 1400° C. for about 30 minutes to 2 hours to form a first immobilization layer 21.

As shown in Fig. 32, an n-type second intermediate growth layer 2bs is epitaxially grown on the defect conversion layer 2a by vapor phase epitaxial growth or the like. The second intermediate growth layer 2bs has a thickness of, for example, about 1 µm, and is doped with an n-type impurity element such as N at an impurity density of about 2 x ^{1017cm -3} to 5 x ^{1017cm -3} . Then, by ion implantation, ions of, for example, Ar atoms, which become atoms that immobilize the growth layer side basal plane dislocations 22, are implanted into the second intermediate growth layer 2bs near the interface between the first intermediate growth layer (defect conversion layer) 2a and the second intermediate growth layer 2bs, at an implantation dose of about 1 x ^{1014cm -3} to 1 x ^{1018cm -3} . More preferably, the impurity density is in the range of 3 x ^{1015cm -3} to 3 x ^{1016cm -3} . Subsequently, a heat treatment is performed at about 900° C. to 1400° C. for about 30 minutes to 2 hours to form a third passivation layer 21d.

33, a third intermediate growth layer is further epitaxially grown on the second intermediate growth layer 2bs by vapor phase epitaxial growth or the like, and a recombination promotion layer 2b consisting of the second intermediate growth layer 2bs and the third intermediate growth layer is formed on the defect conversion layer 2a. The recombination promotion layer 2b has a thickness of, for example, about 5 μm to 10 μm, and is doped with an n-type impurity element such as nitrogen (N) at an impurity density of about 2×10 ¹⁷ cm ^-3 to 5×10 ¹⁷ cm ^-3 .

As shown in Fig. 34, an intermediate growth layer 3e is epitaxially grown on the recombination promotion layer 2b as a fourth intermediate growth layer by vapor phase epitaxial growth or the like. The intermediate growth layer (fourth intermediate growth layer) 3e has a thickness of, for example, about 1 µm, and is doped with an n-type impurity element such as N at an impurity density of about 1 x ¹⁰¹⁴ cm ^-3 to 1 x ¹⁰¹⁷ cm ^-3 . Then, by ion implantation technology, ions of, for example, Ar atoms, which become atoms that immobilize the growth layer side basal plane dislocations 22, are implanted into the intermediate growth layer 3e near the interface between the recombination promotion layer 2b and the intermediate growth layer 3e, at an implantation dose of about 1 x ¹⁰¹⁴ cm ^-3 to 1 x ¹⁰¹⁸ cm ^-3 . Subsequently, a heat treatment is performed at about 900°C to 1400°C for about 30 minutes to 2 hours to form a fourth immobilization layer 21e.

Thereafter, an n-type upper growth layer, which will be the main epitaxial growth layer, is epitaxially grown on the intermediate growth layer (fourth intermediate growth layer) 3e by vapor phase epitaxial growth technology or the like, to form the running layer 3 shown in FIG. 30. The running layer 3 is doped with an n-type impurity element, for example, N, at a lower impurity density of about 1×10 ¹⁴ cm ^-3 to 1×10 ¹⁷ cm ^-3 than the defect conversion layer 2a and the recombination promotion layer 2b. The thickness of the running layer 3 is in the range of about 10 μm to several hundreds of μm, and the optimal thickness and impurity density are selected according to the withstand voltage specifications of the pin diode. For example, about 10 μm is selected for a withstand voltage of 1000 V, and about 100 μm is selected for a withstand voltage of 10 kV.

Next, as shown in FIG. 27, a p-type carrier injection region 5 of Al or the like is selectively formed on the upper part of the running layer 3 by photolithography and ion implantation techniques. Next, the lower surface of the substrate 1s is polished by chemical mechanical polishing (CMP) or the like to adjust the thickness, and the carrier collection layer 1 is finished to the specifications for the cathode region. A back electrode (cathode electrode) 9 made of Au or the like is formed on the lower surface of the carrier collection layer 1 by sputtering or vacuum deposition or the like. Furthermore, a metal film of Al or the like is deposited by sputtering or vacuum deposition or the like to form a surface electrode (anode electrode) 7. In this way, the semiconductor device according to the modified example of the second embodiment is completed.

In the manufacturing method of the semiconductor device according to the modified example of the second embodiment, a substrate 1s having a second passivation layer 11 on its upper surface is used. A first passivation layer 21, a third passivation layer 21d, and a fourth passivation layer 21e are provided near the interfaces of the defect conversion layer 2a on the substrate 1s, the recombination promotion layer 2b on the defect conversion layer 2a, and the running layer 3 on the recombination promotion layer 2b. Therefore, the conversion efficiency of the growth layer side basal plane dislocations 22 propagating during the epitaxial growth to threading dislocations can be improved. In addition, a recombination promotion layer 2b having a higher impurity density than the defect conversion layer 2a is epitaxially grown on the defect conversion layer 2a having a higher impurity density than the running layer 3. Therefore, the hole density injected from the running layer 3 into the growth layer side basal plane dislocations 22 present at the interface between the carrier collection layer 1 and the defect conversion layer 2a can be reduced to a threshold value of 1×10 ¹⁵ cm ⁻³ or less. As a result, when a forward current is passed through the semiconductor device, the expansion of stacking faults caused by the growth layer-side basal plane dislocations 22 can be prevented, and degradation of the forward characteristics of the semiconductor device can be suppressed.

In the semiconductor device according to the modified example of the second embodiment, the defect conversion layer 2a is epitaxially grown on the substrate 1s. Therefore, the growth layer side basal plane dislocations 22 propagating from the substrate 1s are converted into threading dislocations in the defect conversion layer 2a. The recombination promotion layer 2b is doped with an n-type impurity element having a higher impurity density than the intermediate growth layer (fourth intermediate growth layer) 3e. Therefore, the hole density injected from the intermediate growth layer 3e into the growth layer side basal plane dislocations 22 present at the interface between the substrate 1s and the buffer layer 2 can be reduced to a threshold value of 1×10 ¹⁵ cm ⁻³ or less. As a result, the growth layer side basal plane dislocations 22 can be prevented from expanding into stacking faults.

Other Embodiments
As described above, the embodiment of the present invention has been described, but the description and drawings forming a part of this disclosure should not be understood as limiting the present invention. From this disclosure, various alternative embodiments, examples and operating techniques will become apparent to those skilled in the art.

As described above, the growth layer side basal plane dislocations are immobilized by crystal defects introduced during the implantation of impurity ions that become atoms that immobilize the basal plane dislocations, but this is not limited to this. For example, the propagation of basal plane dislocations can also be prevented by a p-type semiconductor region. Therefore, as shown in FIG. 35, a plurality of p-type semiconductor regions 30 may be selectively provided in the buffer layer 2 on the carrier collection layer 1 to immobilize the growth layer side basal plane dislocations 22. The semiconductor regions 30 are provided so as to extend from the interface between the carrier collection layer 1 and the buffer layer 2 into the buffer layer 2. The surface of the carrier collection layer 1 is a (0001) Si surface, and has an off angle of about 0° to 8° in the [11-20] direction with respect to the [0001] (c-axis) direction. As shown in FIG. 36, a plurality of stripe-shaped semiconductor regions 30 extending parallel to each other in a direction perpendicular to the [11-20] direction are provided on the upper surface of the buffer layer 2 epitaxially grown on the carrier collection layer 1. As shown in FIG. 37, the multiple semiconductor regions 30 are arranged with a height h and a distance d between adjacent semiconductor regions 30. The width of the semiconductor regions 30 is preferably 5 μm or less. For example, if the off angle is θ, and if h/d>tan θ, then basal plane dislocations present between adjacent semiconductor regions 30 are prevented from propagating to the semiconductor region and are confined within the buffer layer 2. As a result, the movement of basal plane dislocations in the [11-20] direction is prevented, and the expansion of stacking faults can be prevented.

Using the process diagrams shown in Figures 38 and 39, the manufacturing process of the semiconductor region 30 in the manufacturing method of the multilayer structure according to another embodiment will be described. As shown in Figure 38, a plurality of masks 35 such as resist are selectively formed on the upper surface of the buffer layer 2 epitaxially grown on the substrate 1s by using photolithography or the like. Ions of p-type impurities such as Al are implanted into the buffer layer 2 through the openings between the adjacent masks 35. Multi-stage ion implantation is performed by adjusting the acceleration voltage so that the implantation depth of the p-type impurity ions reaches the interface between the substrate 1s and the buffer layer 2. After the ion implantation, the mask 35 is removed, and a heat treatment for activating the p-type impurities is performed. In this way, a plurality of semiconductor regions 30 extending from the interface between the substrate 1s and the buffer layer 2 into the buffer layer 2 are formed, as shown in Figure 39.

As shown in FIG. 40, a second immobilization layer 11 may be provided near the upper surface of the substrate 1s before the epitaxial growth of the buffer layer 2. This immobilizes the substrate-side basal plane dislocations 12 present in the substrate 1s, thereby increasing the conversion rate to threading dislocations. As shown in FIG. 41, each of the multiple semiconductor regions 30 may extend in the thickness direction of the buffer layer 2 from the interface with the substrate 1s to the interface with the travel layer 3.

As such, the present invention naturally includes various embodiments not described here, such as configurations that arbitrarily apply the configurations described in the above embodiments and each modified example. Therefore, the technical scope of the present invention is determined only by the invention-specific matters related to the scope of the claims that are appropriate from the above description.

1... carrier collection layer (cathode region)
1s...Substrate (1s, 3e)...Intermediate composite 2...Buffer layer 2a...Defect conversion layer 2b...Recombination promotion layer 3...Travel layer 3e...Intermediate growth layer (epitaxial growth layer)
5...Carrier injection region (anode region)
7...Anode electrode (surface electrode)
9...Cathode electrode (rear electrode)
11... second passivation layer 21... first passivation layer 21d... third passivation layer 21e... fourth passivation layer 12, 12a, 22... basal plane dislocation 12c, 22c... carbon core 12s, 22s... silicon core 14... threading dislocation 30... semiconductor region 221, 221a, 221b, 221c... atoms that passivate basal plane dislocation

Claims (18)

a silicon carbide substrate of a first conductivity type;
a buffer layer of a first conductivity type provided on the substrate and having a lower impurity concentration than the substrate;
an epitaxially grown layer of a first conductivity type provided on the buffer layer and having a lower impurity concentration than the buffer layer ;
a first passivation layer is provided inside the buffer layer, extending in a thickness direction of the buffer layer from an interface with the substrate to an interface with the epitaxial growth layer, the first passivation layer immobilizing basal plane dislocations occurring in the epitaxial growth layer continuously from basal plane dislocations present in the substrate;
the substrate has a (0001) surface having an off angle of more than 0° and less than 8° in a [11-20] direction with respect to a [0001] axial direction;
the first passivation layer is a plurality of stripe-shaped second conductivity type semiconductor regions extending parallel to each other in a direction perpendicular to the [11-20] direction ,
a distance d between the plurality of second conductive type semiconductor regions satisfies h/d>tan θ, where h is a thickness of the buffer layer and θ is an off-angle of the substrate;
a second passivation layer that immobilizes basal plane dislocations by crystal defects on the front surface side of the substrate below the interface between the buffer layer and the substrate ;
A multilayer structure, wherein the second passivation layer contains atoms that immobilize basal plane dislocations and is provided on the entire in-plane surface of the substrate. 2. The multi-layer structure of claim 1, wherein the first passivation layer and the second passivation layer meet at the interface between the buffer layer and the substrate . The multilayer structure according to claim 1 or 2, characterized in that the atoms contained in the second passivation layer that immobilize the basal plane dislocations are at least one type of atom selected from argon, magnesium, calcium, barium, titanium, vanadium, chromium, manganese, and iron. 4. The multilayer structure according to claim 1, wherein the impurity density of atoms that immobilize the basal plane dislocations contained in the second passivation layer is 1× ¹⁰ cm ⁻³ or more and 1× ¹⁰ cm ⁻³ or less. 4. The multilayer structure according to claim 1, wherein the impurity density of atoms that immobilize the basal plane dislocations contained in the second passivation layer is 3×10 ¹⁵ cm ^-3 or more and 3×10 ¹⁶ cm ^-3 or less. epitaxially growing a buffer layer of a first conductivity type on a silicon carbide substrate of a first conductivity type, the buffer layer having a lower impurity density than the substrate;
epitaxially growing an epitaxial growth layer of a first conductivity type on the buffer layer, the epitaxial growth layer having a lower impurity concentration than the buffer layer ;
forming a first passivation layer inside the buffer layer, the first passivation layer extending in a thickness direction of the buffer layer from an interface with the substrate to an interface with the epitaxial growth layer, the first passivation layer being continuous with a basal plane dislocation present inside the substrate and immobilizing a basal plane dislocation occurring inside the epitaxial growth layer;
forming a second passivation layer on the front surface side of the substrate below the interface between the buffer layer and the substrate, the second passivation layer immobilizing basal plane dislocations by crystal defects;
Including,
the substrate has a (0001) surface having an off angle of more than 0° and less than 8° in a [11-20] direction with respect to a [0001] axial direction;
the first passivation layer is a plurality of stripe-shaped second conductivity type semiconductor regions extending parallel to each other in a direction perpendicular to the [11-20] direction ,
a distance d between the plurality of second conductive type semiconductor regions satisfies h/d>tan θ, where h is a thickness of the buffer layer and θ is an off-angle of the substrate;
The second passivation layer includes atoms that immobilize basal plane dislocations, and is formed on the entire in-plane surface of the substrate. 7. The method of claim 6, wherein the step of forming the second passivation layer comprises implanting atoms that immobilize the basal plane dislocations from a top surface of the substrate with a projected range that is within 1 μm of the interior of the substrate from an interface between the buffer layer and the substrate. 8. The method for producing a multilayer structure according to claim 6, wherein the first passivation layer and the second passivation layer are formed so as to be in contact with each other at the interface between the buffer layer and the substrate . The method for manufacturing a multilayer structure according to claim 7, characterized in that the atoms implanted into the second passivation layer to immobilize the basal plane dislocations are at least one type of atom selected from the group consisting of argon, magnesium, calcium, barium, titanium, vanadium, chromium, manganese, and iron. epitaxially growing a buffer layer of a first conductivity type on a silicon carbide substrate of a first conductivity type, the buffer layer having a lower impurity density than the substrate;
forming a first passivation layer on the entire in-plane area of the buffer layer, the first passivation layer having a peak in a concentration distribution of atoms that immobilize basal plane dislocations within the buffer layer, the peak being located within 50 nm from an interface between the substrate and the buffer layer , and immobilizing basal plane dislocations that occur in the buffer layer successively from basal plane dislocations present in the substrate by using crystal defects;
epitaxially growing a first conductivity type traveling layer on the buffer layer with a lower impurity density than the buffer layer;
forming a second conductive type carrier injection region on a surface of the traveling layer for injecting carriers into the traveling layer ;
Including,
The step of epitaxially growing the buffer layer comprises:
epitaxially growing a defect conversion layer on the substrate to convert basal plane dislocations into threading dislocations;
epitaxially growing a recombination enhancement layer on the defect conversion layer, the recombination enhancement layer having a higher impurity density than the defect conversion layer and reducing injected minority carriers through recombination;
Including,
a third passivation layer having a peak in a concentration distribution of atoms that immobilize basal plane dislocations within the recombination promotion layer, the third passivation layer immobilizing basal plane dislocations in the recombination promotion layer by crystal defects, the third passivation layer being formed on the entire in-plane direction of the recombination promotion layer, the third passivation layer having a peak in a concentration distribution of atoms that immobilize basal plane dislocations in the recombination promotion layer, the third passivation layer being formed on the entire in-plane direction of ... by crystal defects. 11. The method of claim 10, wherein the step of forming the first passivation layer includes the step of implanting atoms that passivate the basal plane dislocations from an upper surface of the buffer layer with a projected range that is within 50 nm of the buffer layer from an interface between the substrate and the buffer layer. 12. The method for manufacturing a semiconductor device according to claim 10, further comprising the step of forming a second passivation layer, the second passivation layer having a peak in a concentration distribution of atoms that immobilize basal plane dislocations within the substrate within 1 μm from the top surface of the substrate , and immobilizing basal plane dislocations that exist from the inside of the substrate toward the top surface of the substrate by crystal defects, over the entire in-plane direction of the substrate . 13. The method of claim 12, wherein the step of forming the second passivation layer includes implanting atoms that passivate the basal plane dislocations into the substrate at a projected range that is within 1 μm of the interior of the substrate from the top surface of the substrate. The method for manufacturing a semiconductor device according to claim 12 or 13, characterized in that the first passivation layer and the second passivation layer are formed so as to be in contact with each other at the interface between the substrate and the buffer layer. The method for manufacturing a semiconductor device according to any one of claims 10 to 14, further comprising the step of forming a fourth passivation layer, the fourth passivation layer having a peak in a concentration distribution of atoms that passivate basal plane dislocations within 50 nm from the interface between the buffer layer and the current layer , over the entire in-plane direction of the current layer, the fourth passivation layer passing through the current layer and passing through the basal plane dislocations by crystal defects. The method for manufacturing a semiconductor device according to claim 11, characterized in that the atoms implanted into the first passivation layer to immobilize the basal plane dislocations are at least one type of atom selected from the group consisting of argon, magnesium, calcium, barium, titanium, vanadium, chromium, manganese, and iron. The method for manufacturing a semiconductor device according to claim 13, characterized in that the atoms implanted into the second passivation layer to immobilize the basal plane dislocations are at least one type of atom selected from the group consisting of argon, magnesium, calcium, barium, titanium, vanadium, chromium, manganese, and iron. epitaxially growing a buffer layer of a first conductivity type on a silicon carbide substrate of a first conductivity type, the buffer layer having a lower impurity density than the substrate;
forming a first passivation layer on the entire in-plane area of the buffer layer, the first passivation layer having a peak in a concentration distribution of atoms that immobilize basal plane dislocations within the buffer layer, the peak being located within 50 nm from an interface between the substrate and the buffer layer , and immobilizing basal plane dislocations that occur in the buffer layer successively from basal plane dislocations present in the substrate by using crystal defects;
epitaxially growing a first conductivity type traveling layer on the buffer layer with a lower impurity density than the buffer layer;
forming a second conductive type carrier injection region on a surface of the traveling layer, the second conductive type carrier injection region injecting carriers into the traveling layer;
Prior to the step of epitaxially growing the buffer layer, a second passivation layer is formed on the entire in-plane direction of the substrate, the second passivation layer having a peak in a concentration distribution of atoms that immobilize basal plane dislocations within 1 μm of the substrate from the top surface of the substrate, and immobilizing basal plane dislocations that exist from the inside of the substrate toward the top surface of the substrate by crystal defects;
a first passivation layer and a second passivation layer, the first passivation layer and the second passivation layer being both formed such that a peak position of a concentration distribution of atoms that immobilize the basal plane dislocations is away from an interface between the buffer layer and the substrate.

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