JP7600657B2 - Electronic circuits, power conversion devices - Google Patents

Description

The present invention relates to an electronic circuit and a power conversion device.

In a power conversion circuit, when leakage current flows through the parasitic capacitance of a switching element, a noise terminal voltage may be generated at the input terminal (for example, Patent Document 1).

JP 2009-77533 A

However, in Patent Document 1, a coil is used to generate an auxiliary current to cancel out the leakage current, which generally increases the manufacturing costs of the power conversion circuit.

The present invention was made in consideration of the above-mentioned problems in the conventional technology, and its purpose is to provide an electronic circuit that can cancel leakage current with an inexpensive configuration.

The electronic circuit of the present invention, which solves the above-mentioned problems, includes a first capacitor connected to a node on the power supply side of a switching element provided between a first line on the power supply side and a second line on the ground side, a first diode with a cathode connected to the first capacitor, a second capacitor connected to the node, a second diode with a cathode connected to the second capacitor, a first current mirror circuit that discharges a grounded third capacitor based on the current of the first capacitor when the switching element is turned off, and a second current mirror circuit that charges the third capacitor based on the current of the second capacitor when the switching element is turned on.

It is possible to provide an electronic circuit that can cancel leakage current with an inexpensive configuration.

1 is a diagram illustrating an example of a power conversion circuit 10. FIG. 1 is a diagram illustrating an example of a configuration of a power conversion circuit 10. FIG. 2 is a diagram showing an example of a current path flowing in a power conversion circuit 10. FIG. 2 is a diagram showing an example of a current path flowing in a power conversion circuit 10. FIG. 2 is a diagram showing main waveforms of the power conversion circuit 10. FIG. FIG. 2 is a diagram showing an example of the structure of a power conversion device 200. FIG. 2 is a diagram illustrating an example of a power conversion circuit 15.

The present specification and accompanying drawings make clear at least the following:

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<<<Outline of power conversion circuit 10>>>
1 is a diagram showing the configuration of a power conversion circuit 10 according to an embodiment of the present invention. The power conversion circuit 10 is a circuit that generates a U-phase AC voltage out of three-phase (U, V, W) AC voltages from an input voltage Vin, for example. The power conversion circuit 10 includes lines L1, L2, capacitors Cd, Ce, Cc, NMOS transistors 30, 31, and a charge/discharge circuit 32.

Capacitor Cd, which is provided between line L1 on the power supply side (P terminal side) and line L2 on the ground side (N terminal side), is an element for smoothing the voltage rectified by a rectifier circuit (not shown). In this embodiment, the voltage applied to capacitor Cd is the input voltage Vin. Capacitor Ce is an element for grounding the power conversion circuit 10. Line L1 corresponds to the "first line" and line L2 corresponds to the "second line."

NMOS transistor 30 is a high-side switching element, and NMOS transistor 31 is a low-side switching element. In this embodiment, NMOS transistors 30, 31 provided between line L1 and line L2 are complementarily turned on and off by a drive circuit (not shown), generating a U-phase AC voltage. In this embodiment, the node to which the source electrode of NMOS transistor 30, the drain electrode of NMOS transistor 31, and the U terminal (described later) are connected is referred to as node N0. Node N0 corresponds to the "power supply side node."

The NMOS transistors 30 and 31 are power transistors used for power conversion. For this reason, for example, a parasitic capacitance Cs occurs between the drain electrode of the NMOS transistor 31 and the ground. When the NMOS transistors 30 and 31 are switched and the voltage of the node N0 changes, a leakage current IL flows through the capacitor Ce via the parasitic capacitance Cs.

Specifically, when NMOS transistor 30 is turned on and NMOS transistor 31 is turned off, the voltage of node N0 rises to the level of the input voltage Vin (e.g., several hundred V, hereafter referred to as H level). As a result, leakage current IL shown by the dashed line flows from parasitic capacitance Cs to capacitor Ce. On the other hand, when NMOS transistor 30 is turned off and NMOS transistor 31 is turned on, the voltage of node N0 drops to the ground level (e.g., 0 V, hereafter referred to as L level). As a result, leakage current IL shown by the dotted line flows from capacitor Ce to parasitic capacitance Cs. Therefore, when NMOS transistors 30 and 31 are turned on and off, a noise terminal voltage corresponding to the leakage current IL is generated in capacitor Ce.

The noise terminal voltage generated in the capacitor Ce may adversely affect other circuits or electronic devices connected via, for example, the ground line L2. Therefore, it is preferable to suppress the noise terminal voltage generated in the capacitor Ce. In this embodiment, in order to suppress such noise terminal voltage, a capacitor Cc and a charge/discharge circuit 32 are provided that generate a compensation current to cancel the leakage current IL. Note that, in the power conversion circuit 10, the leakage current IL is actually canceled, but in FIG. 1, the leakage current IL is depicted for the sake of convenience in order to make it easier to understand.

<<Details of Capacitor Cc and Charge/Discharge Circuit 32>>
Here, the capacitor Cc and the charge/discharge circuit 32 will be described in detail with reference to Fig. 2. The capacitor Cc is an element for passing a compensation current, and one end is grounded. The charge/discharge circuit 32 is a circuit for passing a compensation current, which flows in the opposite direction to the leakage current IL, through the capacitor Cc. The charge/discharge circuit 32 includes a power supply circuit 40, a discharge circuit 41, and a charge circuit 42. In this embodiment, the charge/discharge circuit 32 including the capacitor Cc corresponds to an "electronic circuit."

<<Power supply circuit 40>>
The power supply circuit 40 is a circuit that generates a power supply voltage Vdd for operating the charging circuit 42 based on the voltage from the node N0. The power supply circuit 40 includes capacitors 50 and 52, diodes 51 and 53, and a Zener diode. A capacitor 50, a diode 51, and a capacitor 52 are connected in series between the node N0 and the ground line L2. The anode of the diode 51 is connected to the capacitor 50. The cathode is connected to a capacitor 52. The capacitor 52 in this embodiment is connected to a terminal connected to a terminal for storing charge and discharge of the charging circuit 42 so that the charging circuit 42 can be operated, as will be described in detail later. The capacity of the inverter must be such that it can sufficiently suppress voltage fluctuations.

Therefore, when node N0 changes from L level to H level, capacitor 52 is charged via capacitor 50 and diode 51. In addition, diode 53 is connected between capacitor 50 and line L2. Specifically, the cathode of diode 53 is connected to capacitor 50, and the anode is connected to line L2. Therefore, when node N0 changes from H level to L level, capacitor 50 is discharged to node N0 via diode 53.

As described above, the diode 51, the cathode of which is connected, is connected to the capacitor 52. Therefore, even if the node N0 changes from the H level to the L level, the charge stored in the capacitor 52 is not discharged. In other words, the capacitor 52 is charged from the node N0 every switching period, so that the power supply voltage Vdd that can stably operate the charging circuit 42 is generated in the capacitor 52.

A Zener diode 54 is connected between the capacitor 52 and the ground line L2, with the cathode connected to the capacitor 52 and the anode connected to the line L2. The Zener diode 54 therefore acts as an element that clamps the power supply voltage Vdd so that the power supply voltage Vdd does not become higher than a predetermined voltage. The "predetermined voltage" in this embodiment is the Zener voltage of the Zener diode 54 (e.g., 10V). Therefore, the power supply circuit 40 supplies a power supply voltage Vdd of, for example, 10V to the charging circuit 42.

In this embodiment, the wiring to which the power supply voltage Vdd is applied is referred to as "line L3", and line L3 corresponds to the "third line". Capacitor 52 corresponds to the "fourth capacitor", and capacitor 50 corresponds to the "fifth capacitor". Diode 51 corresponds to the "third diode", diode 53 corresponds to the "fourth diode", and Zener diode 54 corresponds to the "clamp element".

<<Discharge circuit 41>>
The discharge circuit 41 is a circuit that discharges the capacitor Cc so that a leakage current IL does not flow to the capacitor Ce when the parasitic capacitance Cs is charged. The discharge circuit 41 includes a capacitor 60, a diode 61, and an NPN transistor 62. , 63.

Capacitor 60, like parasitic capacitance Cs, is an element that passes a current according to changes in the voltage level of node N0. One end of capacitor 60 is connected to node N0, and the other end is connected to diode 61 and diode-connected NPN transistor 62. Therefore, when node N0 becomes H level, a current similar to that of parasitic capacitance Cs flows through diode-connected NPN transistor 62 via capacitor 60.

Figure 3 is a diagram for explaining an example of the path of the current flowing through the power conversion circuit 10 when node N0 changes to H level. Also, Figure 4 is a diagram showing an example of the main waveforms of the power conversion circuit 10. First, at time t1 in Figure 4, when NMOS transistor 30 turns on and NMOS transistor 31 turns off, node N0 becomes H level. As a result, as shown in Figure 3, a current shown by a dashed line flows from parasitic capacitance Cs to ground, and a current shown by a dashed line flows through capacitor 60 to NPN transistor 62.

Here, NPN transistor 62 and NPN transistor 63 form a current mirror circuit. Therefore, NPN transistor 63 discharges capacitor Cc based on the current flowing through NPN transistor 62. Specifically, NPN transistor 63 generates compensation current Ic (solid line) according to the current flowing through NPN transistor 62, and absorbs the charge from capacitor Cc. As a result, leakage current IL (dotted line) flowing from parasitic capacitance Cs to ground is absorbed by NPN transistor 63 via capacitor Cc as compensation current Ic (here, discharge current).

The current from NPN transistors 62 and 63 then circulates to node N0 via, for example, ground line L2, capacitor Cd, power supply line L1, and NMOS transistor 30.

In this embodiment, as shown in the enlarged view of the waveform at time t1 in Figure 4, the capacitance values of capacitors 60 and Cc are determined so that the time change in magnitude (absolute value) of leakage current IL (solid line) and compensation current Ic (dashed dotted line) is equal. Note that here, the direction of current flowing from power conversion circuit 10 to ground is defined as the "positive direction," and the direction of current flowing from ground to power conversion circuit 10 is defined as the "negative direction."

Therefore, in the power conversion circuit 10, when node N0 becomes H level, leakage current IL flows as compensation current Ic to NPN transistor 63 via capacitor Cc. Therefore, leakage current IL can be prevented from flowing to capacitor Ce, and changes in voltage Vce of capacitor Ce can be suppressed. Note that FIG. 4 illustrates the waveform of voltage Vce when there is no charge/discharge circuit 32 and capacitor Cc as a reference waveform. In this way, in this embodiment, when node N0 becomes H level, the generation of noise terminal voltage in capacitor Ce can be accurately suppressed.

When node N0 goes low, diode 61 turns on, and the charge in capacitor 60 is discharged by a current that passes through diode 61, capacitor 60, and node N0. Therefore, every time node N0 goes high, a current flows through capacitor 60, the waveform of which is similar to that of the current through parasitic capacitance Cs.

In this embodiment, the capacitor 60 corresponds to the "first capacitor," the diode 61 corresponds to the "first diode," the capacitor Cc corresponds to the "third capacitor," and the current mirror circuit formed by the NPN transistors 62 and 63 corresponds to the "first current mirror circuit."

<<Charging circuit 42>>
The charging circuit 42 is a circuit that charges the capacitor Cc so that the leakage current IL does not flow to the capacitor Ce when the parasitic capacitance Cs is discharged. The charging circuit 42 includes a capacitor 70, a diode 71, and a PNP transistor 72. , 73.

Capacitor 70, like parasitic capacitance Cs, is an element that passes a current according to changes in the voltage level of node N0. One end of capacitor 70 is connected to node N0, and the other end is connected to diode 71 and diode-connected PNP transistor 72. Therefore, when node N0 becomes an L level, a current similar to that of parasitic capacitance Cs flows through diode-connected PNP transistor 72 via capacitor 70.

Figure 5 is a diagram for explaining an example of a path of a current flowing through the power conversion circuit 10 when the NMOS transistor 30 turns off and the NMOS transistor 31 turns on, causing the node N0 to change to the L level. For example, at time t2 in Figure 4, when the NMOS transistor 30 turns off and the NMOS transistor 31 turns on, the node N0 becomes the L level. As a result, as shown in Figure 5, a current shown by a dashed line flows from the parasitic capacitance Cs to the node N0 (or the drain electrode of the NMOS transistor 31). Also, at this time, a current shown by a dashed line flows from the PNP transistor 72 to the node N0 via the capacitor 70.

Here, PNP transistor 72 and PNP transistor 73 form a current mirror circuit. Therefore, PNP transistor 73 charges capacitor Cc based on the current flowing through PNP transistor 72. Specifically, PNP transistor 73 generates compensation current Ic (solid line) according to the current flowing through PNP transistor 72 and supplies it to capacitor Cc. As a result, compensation current Ic (here, charging current) flowing from PNP transistor 73 to ground via capacitor Cc is supplied as leakage current IL flowing through parasitic capacitance Cs.

The current to node N0 then circulates to line L3 of power supply circuit 40 via, for example, NMOS transistor 31, ground line L2, and capacitor 52. As described above, capacitor 52 has a capacity that can sufficiently suppress voltage fluctuations due to the charge and discharge of charging circuit 42. Therefore, even if current is supplied from capacitor 52 to the current mirror circuit of charging circuit 42, power supply circuit 40 can generate a stable voltage Vdd.

In this embodiment, as shown in the enlarged view of the waveform at time t2 in FIG. 4, the capacitance values of capacitors 70 and Cc are determined so that the time change in the magnitude (absolute value) of the leakage current IL (solid line) and the compensation current Ic (dashed dotted line) is equal. Therefore, in the power conversion circuit 10, when node N0 becomes L level, the compensation current Ic flows as the leakage current IL through capacitor Cs. Therefore, since the leakage current IL can be prevented from flowing to capacitor Ce, the change in the voltage Vce of capacitor Ce can be suppressed. In this way, in this embodiment, the generation of noise terminal voltage in capacitor Ce can be accurately suppressed when node N0 becomes L level.

In this embodiment, the capacitor 70 corresponds to the "second capacitor," and the diode 71 corresponds to the "second diode." The current mirror circuit formed by the PNP transistors 72 and 73 corresponds to the "second current mirror circuit."

<<<<Example of a power conversion device>>>>
6 is an example of a plan view of a power conversion device 200 including the power conversion circuit 10. Note that the power conversion circuit 10 and the power conversion device 200 have the same configurations denoted by the same reference numerals. The power conversion device 200 includes a housing 210, a heat sink 220, a semiconductor module 230, and a circuit board 240.

The housing 210 is a substantially rectangular box-shaped member made of, for example, resin with an opening on its front surface, and houses the heat sink 220, the semiconductor module 230, and the circuit board 240. The metal heat sink 220, made of, for example, copper, is attached to the bottom surface of the housing, and the semiconductor module 230 is attached to the front surface of the heat sink 220.

The semiconductor module 230 is an electronic component that includes NMOS transistors 30 and 31, and has terminals P, N, and U on its front surface. For example, terminal P is a terminal connected to the drain electrode of NMOS transistor 30 and line L1 on the power supply side, and terminal N is a terminal connected to the source electrode of NMOS transistor 31 and line L2 on the ground side. Terminal U is a terminal connected to node N0 to which NMOS transistors 30 and 31 are connected.

The circuit board 240 is a rectangular printed circuit board on which the charge/discharge circuit 32 and the capacitor Cc of the power conversion circuit 10 are mounted, and is fixed to the semiconductor module 230 via a metal plate 250 connected to the terminal U and a metal plate 251 connected to the terminal N. The circuit board 240 has conductive patterns (not shown) formed thereon that are connected to the terminals U and N, respectively.

In addition, on the front surface of the circuit board 240, in the area on the side of the terminal U, capacitor 60 of the discharge circuit 41, capacitor 70 of the charge circuit 42, and capacitor Cc are mounted. Then, near the center of the circuit board 240, the components constituting the discharge circuit 41 excluding capacitor 60 and the components constituting the charge circuit 42 excluding capacitor 70 are mounted. Furthermore, in the area on the side of the circuit board 240 farther from terminal U, the components constituting the power supply circuit 40 are mounted. One end of capacitor Cc is attached to the heat sink 220, which functions as ground, via a metal wire 252 and a terminal 253.

In this way, since the capacitors 60, 70 are arranged in an area closer to the terminal U than the current mirror circuits of the discharge circuit 41 and the charge circuit 42, the impedance between the terminal U and the capacitors 60, 70 can be reduced. Therefore, the voltage applied to the capacitors 60, 70 and the voltage applied to the parasitic capacitance Cs of the NMOS transistor 30 become approximately equal. Therefore, in the power conversion device 200, it is possible to precisely match the waveform of the compensation current Ic with the waveform of the leakage current IL.

In the power conversion device 200, terminal U corresponds to the "first terminal", terminal N corresponds to the "second terminal", and terminal 253 corresponds to the "ground terminal".

<<<<Example of power conversion circuit 15>>>
FIG. 7 is a diagram showing an example of the power conversion circuit 15. The power conversion circuit 15 is a circuit used, for example, when generating a voltage of the U phase of a three-level inverter. The power conversion circuit 15 includes lines L1 and L2, capacitors Cdp, Cdn, Ce, and Cc, NMOS transistors 35 to 38, diodes D1 and D2, and a charge/discharge circuit 39. Note that the circuits and elements with the same reference numerals are the same in the power conversion circuit 10 shown in FIG. 2 and the power conversion circuit 15. For this reason, the following description will focus on circuits and elements that are different from the power conversion circuit 10.

Capacitors Cdp and Cdn are connected in series between line L1 on the power supply side (P terminal side) and line L2 on the ground side (N terminal side). The node to which capacitors Cdp and Cdn are connected is a node connected to the M terminal (not shown), and for example, half the voltage of the input voltage Vin (Vin/2) is applied as voltage Vm.

Four NMOS transistors 35 to 38 are connected in series between line L1 and line L2. In this embodiment, a terminal Up (not shown) of a semiconductor module including NMOS transistors 35 to 38 is connected to node N1, to which the source electrode of NMOS transistor 35 and the drain electrode of NMOS transistor 36 are connected.

A terminal U (not shown) of the semiconductor module is connected to node N2, which is connected to the source electrode of NMOS transistor 36 and the drain electrode of NMOS transistor 37. A terminal Un (not shown) of the semiconductor module is connected to node N3, which is connected to the source electrode of NMOS transistor 37 and the drain electrode of NMOS transistor 38.

The diodes D1 and D2 connected in series are connected between the node N1 and the node N3, and a voltage Vm is applied to the connection node of the diodes D1 and D2. The NMOS transistors 35 to 38 are turned on and off at a predetermined timing by a drive circuit (not shown), and a U-phase voltage corresponding to three levels (0, Vin/2, Vin) is output from the nodes N1 to N3.

The NMOS transistors 35 to 38 are power transistors used for power conversion. For this reason, for example, a parasitic capacitance Cs1 occurs between the drain electrode of the NMOS transistor 36 and the ground. Then, for example, when the NMOS transistors 35 and 36 are switched complementarily and the voltage of the node N1 changes, a leakage current IL flows through the capacitor Ce via the parasitic capacitance Cs1.

In this embodiment, a parasitic capacitance Cs2 occurs between the drain electrode of NMOS transistor 37 and ground, and a parasitic capacitance Cs3 occurs between the drain electrode of NMOS transistor 38 and ground. Therefore, the above-mentioned leakage current IL also occurs when the voltages of nodes N2 and N3 change. Therefore, the power conversion circuit 15 is provided with a capacitor Cc and a charge/discharge circuit 39 to cancel (or suppress) the leakage current IL, similar to the power conversion circuit 10.

<<Details of Capacitor Cc and Charging/Discharging Circuit 39>>
The capacitor Cc is an element for passing a compensation current, and one end of the capacitor Cc is grounded. The charge/discharge circuit 39 is a circuit for passing a compensation current, which flows in the opposite direction to the leakage current IL, through the capacitor Cc. The charge/discharge circuit 39 includes a power supply circuit 40, a discharge circuit 45, and a charge circuit 46. The power supply circuit (PS) 40 is the same as the circuit in Fig. 2 described above, and therefore a detailed description thereof will be omitted here.

<<Discharge circuit 45>>
The discharge circuit 45 is a circuit that discharges the capacitor Cc so that the leakage current IL does not flow to the capacitor Ce when each of the parasitic capacitances Cs1 to Cs3 is charged. The discharge circuit 45 includes a diode 61, an NPN transistor 62, and a , 63, and capacitors 64 to 66. Note that the diode 61 and the NPN transistors 62 and 63 are the same as the elements shown in FIG.

Like the parasitic capacitance Cs1, the capacitor 64 is an element that passes a current according to changes in the voltage level of the node N1. One end of the capacitor 64 is connected to the node N1, and the other end is connected to the diode 61 and the diode-connected NPN transistor 62. Therefore, when the level of the node N1 increases, a current similar to that of the parasitic capacitance Cs1 flows through the diode-connected NPN transistor 62 via the capacitor 64.

Capacitor 65, like parasitic capacitance Cs2, is an element that passes a current according to changes in the voltage level of node N2. One end of capacitor 65 is connected to node N2, and the other end is connected to diode 61 and diode-connected NPN transistor 62. Therefore, when the level of node N2 increases, a current similar to that of parasitic capacitance Cs2 flows through diode-connected NPN transistor 62 via capacitor 65.

Like the parasitic capacitance Cs3, the capacitor 66 is an element that passes a current according to changes in the voltage level of the node N3. One end of the capacitor 66 is connected to the node N3, and the other end is connected to the diode 61 and the diode-connected NPN transistor 62. Therefore, when the level of the node N3 increases, a current similar to that of the parasitic capacitance Cs3 flows through the diode-connected NPN transistor 62 via the capacitor 66.

In this manner, in this embodiment, capacitors 64-66 capable of generating a current similar to the leakage current IL flowing through the parasitic capacitances Cs1-Cs3 of NMOS transistors 36-38 are connected to nodes N1-N3. Then, based on the currents generated in these capacitors 64-66, a compensation current Ic in the opposite direction to the leakage current IL is generated in capacitor Cc. Therefore, in this embodiment, when the voltage levels of the respective nodes N1-N3 become high, the generation of noise terminal voltage in capacitor Ce can be accurately suppressed.

<<Charging circuit 46>>
The charging circuit 46 is a circuit that charges the capacitor Cc so that the leakage current IL does not flow to the capacitor Ce when each of the parasitic capacitances Cs1 to Cs3 is discharged. The charging circuit 46 includes a diode 71, a PNP transistor 72, and a , 73, and capacitors 74 to 76. Note that the diode 71 and the PNP transistors 72 and 73 are the same as those in FIG.

Capacitor 74, like parasitic capacitance Cs1, is an element that passes a current according to changes in the voltage level of node N1. One end of capacitor 74 is connected to node N1, and the other end is connected to diode 71 and diode-connected PNP transistor 72. Therefore, when the level of node N1 becomes low, a current similar to that of parasitic capacitance Cs1 flows through diode-connected PNP transistor 72 via capacitor 74.

Capacitor 75, like parasitic capacitance Cs2, is an element that passes a current according to changes in the voltage level of node N2. One end of capacitor 75 is connected to node N2, and the other end is connected to diode 71 and diode-connected PNP transistor 72. Therefore, when the level of node N2 becomes low, a current similar to that of parasitic capacitance Cs2 flows through diode-connected PNP transistor 72 via capacitor 75.

Capacitor 76, like parasitic capacitance Cs3, is an element that passes a current according to changes in the voltage level of node N3. One end of capacitor 76 is connected to node N3, and the other end is connected to diode 71 and diode-connected PNP transistor 72. Therefore, when the level of node N3 becomes low, a current similar to that of parasitic capacitance Cs3 flows through diode-connected PNP transistor 72 via capacitor 76.

In this manner, in this embodiment, capacitors 74-76 capable of generating a current similar to the leakage current IL flowing through the parasitic capacitances Cs1-Cs3 of NMOS transistors 36-38 are connected to nodes N1-N3. Then, based on the currents generated in these capacitors 74-76, a compensation current Ic in the opposite direction to the leakage current IL is generated in capacitor Cc. Therefore, in this embodiment, when the voltage levels of the respective nodes N1-N3 become low, the generation of noise terminal voltage in capacitor Ce can be accurately suppressed.

== ...
The power conversion circuits 10 and 15 of the present embodiment have been described above. For example, in the power conversion circuit 10, the capacitors 60 and 70 are connected to the node N0 at which the parasitic capacitance Cs between the NMOS transistor 31 and ground occurs. The charge/discharge circuit 32 generates a compensation current Ic in the capacitor Cc based on the current flowing through the capacitors 60 and 70, which cancels the leakage current IL. Therefore, the power conversion circuit 10 does not need to use electronic components such as an auxiliary coil, and can suppress the leakage current IL with an inexpensive configuration.

In addition, since the anodes of the diodes 61 and 71 are connected to the line L2, the diodes 61 and 71 can appropriately discharge the capacitors 60 and 70. For example, the anodes of the diodes 61 and 71 may be grounded. However, for example, when the diodes 61 and 71 are grounded in the power conversion device 200, it is necessary to connect the anodes to the heat sink 220 via wires (not shown). In this embodiment, the anodes of the diodes 61 and 71 can be connected to a conductive pattern (not shown) connected to the line L2 (i.e., the terminal N) of the circuit board 240, so that the number of components such as wires can be reduced.

Also, for example, as shown in FIG. 5, the compensation current Ic output from the charging circuit 42 flows through the capacitor Cc, the NMOS transistor 31, the line L2, the capacitor 52, and the line L3 to the current mirror circuit of the PNP transistors 72 and 73. By having the current flow through such a path, it is possible to prevent the leakage current IL from flowing into the capacitor Ce.

Also, for example, the power supply voltage Vdd that operates the charging circuit 42 may be generated using a voltage divider circuit that divides the voltage of lines L1 and L2. However, using such a voltage divider circuit increases the power consumed by the voltage divider circuit. The power supply circuit 40 of this embodiment generates the power supply voltage Vdd based on the voltage of node N0, which changes between H level and L level, so that power consumption can be reduced.

The power supply circuit 40 also includes capacitors 50 and 52 that divide the voltage of node N0, and a diode 51 that prevents the discharge of capacitor 52. It also includes a diode 53 that discharges capacitor 50 when node N0 becomes low level so that capacitor 52 is charged every switching period. By using a power supply circuit 40 configured in this way, a stable power supply voltage Vdd can be generated based on the voltage of node N0.

In addition, the anode of the diode 53 that discharges the capacitor 50 is not grounded but is connected to the ground side line L2. This allows the number of components, such as wires, to be reduced in the power conversion device 200, for example.

The power supply circuit 40 is also provided with a Zener diode 54 that clamps the power supply voltage Vdd so that the power supply voltage Vdd does not become higher than a Zener voltage (e.g., 10 V). Therefore, in this embodiment, it is possible to prevent a high voltage from being applied to the PNP transistors 72 and 73.

In addition, generally, when a device including a switching element is operated, leakage current may occur, resulting in a large noise terminal voltage. In such a case, for example, as shown in the power conversion device 200 of FIG. 6, a circuit board 240 on which the capacitor Cc and the charge/discharge circuit 32 are mounted may be attached to the semiconductor module 230. By attaching such a circuit board 240 to the semiconductor module 230, the leakage current is reliably canceled, thereby suppressing the generation of noise terminal voltage.

In addition, it is preferable to mount the capacitors 60 and 70, which have a function similar to that of the parasitic capacitance Cs, on the circuit board 240 near the terminal U. By placing the capacitors 60 and 70 in such a position, it is possible to match the compensation current Ic and the leakage current IL with higher accuracy.

In this embodiment, a MOS transistor is used as the switching element for power conversion provided between line L1 and line L2, but it may be, for example, a bipolar transistor or an IGBT (Insulated Gate Bipolar Transistor). Also, each of the NMOS transistors 30 and 31 has parasitic capacitance, for example, between the drain and source and between the gate and source, but this is omitted in this embodiment.

In addition, bipolar transistors are used in the current mirror circuit of the charge/discharge circuit 32, but MOS transistors, for example, may also be used.

The above embodiments are intended to facilitate understanding of the present invention, and are not intended to limit the scope of the present invention. Furthermore, the present invention may be modified or improved without departing from the spirit of the present invention, and it goes without saying that the present invention includes equivalents.

10, 15 Power conversion circuit 30, 31, 35 to 38 NMOS transistor 32, 39 Charge/discharge circuit 40 Power supply circuit 41 Discharge circuit 42 Charge circuit 50, 52, 60, 65, 66, 70, 75, 76, Cd, Cdp, Cdn, Ce, Cc, Cs, Cs1 to Cs3 Capacitor 51, 53, 61, 71, D1, D2 Diode 54 Zener diode 62, 63 NPN transistor 72, 73 PNP transistor 200 Power conversion device 210 Housing 220 Heat sink 230 Semiconductor module 240 Circuit board 250, 251 Metal plate 252 Wire 253, U, N, P Terminals L1 to L3 Lines N0 to N3 Node

Claims (9)

a first capacitor connected to a node on the output side of the first switching element on the power supply side and the second switching element on the ground side, the first switching element being provided between a first line on a power supply side and a second line on a ground side;
a first diode having a cathode connected to the first capacitor;
a second capacitor connected to the node;
a second diode having a cathode connected to the second capacitor;
a first current mirror circuit that discharges a grounded third capacitor based on a current through the first capacitor when the first switching element is turned on and the second switching element is turned off;
a second current mirror circuit that charges the third capacitor based on a current of the second capacitor when the first switching element is turned off and the second switching element is turned on;
Equipped with
the first current mirror circuit is operated by being supplied with a current flowing through the first capacitor, and discharges the third capacitor;
the second current mirror circuit operates by outputting a current flowing through the second capacitor, and charges the third capacitor;
Electronic circuit. 2. The electronic circuit of claim 1,
The anode of the first diode is connected to the second line;
The anode of the second diode is connected to the second line.
Electronic circuit. 3. An electronic circuit according to claim 1 or 2,
a fourth capacitor having one end connected to a third line to which a power supply voltage of the second current mirror circuit is applied and the other end connected to the second line;
Electronic circuit. 4. An electronic circuit according to claim 3,
a power supply circuit that generates the power supply voltage based on a voltage of the node;
Electronic circuit. 5. An electronic circuit according to claim 4,
The power supply circuit includes:
The fourth capacitor;
a fifth capacitor connected to the node;
a third diode having an anode connected to the fifth capacitor and a cathode connected to the fourth capacitor;
a fourth diode having a cathode connected to the fifth capacitor;
An electronic circuit comprising: 6. An electronic circuit according to claim 5,
The anode of the fourth diode is connected to the second line.
Electronic circuit. 7. An electronic circuit according to claim 5 or 6,
The power supply circuit includes:
further comprising a clamp element that clamps the power supply voltage so that the power supply voltage does not exceed a predetermined voltage;
Electronic circuit. An electronic circuit according to any one of claims 1 to 7;
a semiconductor module including the first and second switching elements;
A ground terminal to be grounded;
A power conversion device comprising: The power conversion device according to claim 8,
a circuit board on which the electronic circuit is mounted,
the semiconductor module has a first terminal connected to the node and a second terminal connected to the second line;
In the circuit board, the first and second capacitors are provided closer to the first terminal than elements constituting the first and second current mirror circuits.
Power conversion equipment.

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