JP7601540B2 - Semiconductor device manufacturing system and manufacturing method - Google Patents

Description

The present invention relates to a semiconductor device manufacturing system and manufacturing method.

The miniaturization and high integration of integrated circuits have already reached their limits, and the time it takes from development to manufacture of LSIs (Large Scale Integration), which require a huge amount of development time and process, is only getting longer.

However, because it is necessary to produce a large amount of LSIs at once in order to recoup the costs incurred in development and manufacturing, this type of LSI manufacturing has become a heavy, large-scale manufacturing industry that requires large investments in equipment over a long period of time.

However, to meet the ever-diversifying needs for LSIs, more flexible LSI development and manufacturing methods are also needed that take into account high-mix, low-volume production.

As one solution to the above problem, the idea of "minimal fab" has been proposed, which aims to standardize semiconductor manufacturing processes.

However, this method has problems such as restrictions on the line width of fine processing in exposure, problems with mass production, and restrictions on throughput in EB direct writing. In addition, designing more complex LSIs requires a lot of development time and labor.

For this reason, even in recent years, many LSIs are designed based on the concept of System in Package (SiP), in which multiple separate chips are later assembled into a system, and System on Chip (SoC), in which multiple separate functional circuits are integrated on a single chip.

For example, Patent Document 1 describes an invention related to a SiP that has an analog circuit chip and a computer chip and can be suitably used in a motor drive circuit.

Moreover, Patent Document 2 describes an invention relating to an SoC for driving a power inverter, in which a logic circuit, a voltage level shifter, and a sense circuit are integrally formed on a single IC.

Patent document 3 describes an invention related to an information management system that can improve the efficiency of manufacturing by managing manufacturing process information in association with design information and manufacturing information in the LSI manufacturing process, which becomes increasingly complex as separate chips and functional circuits are combined.

Re-table 2017/086054 publication JP 2013-223419 A JP 2015-12251 A

When the design and manufacturing of LSIs such as those described above are carried out within a single company, it takes time and effort to design and develop an entire collection of complex, separate functions, which is hardly efficient. In particular, when manufacturing SoCs, the time and effort required to create complex photomasks to match them is also required.

Therefore, the inventors wondered whether it would be possible to make good use of existing manufacturing devices, facilities, and circuit design information (IP cores, Intellectual Property Cores) owned by different companies in order to develop and manufacture LSIs more efficiently.
We also wondered whether the standardized processes could be used in the development and manufacturing of LSIs.

The present invention was made in consideration of the above problems, and aims to provide a manufacturing system for more efficiently manufacturing semiconductor devices.

In order to solve the above problems, the present invention provides a manufacturing system for manufacturing a semiconductor device in which a plurality of types of functional circuits based on different design information are formed on a single wafer, the system comprising:
The apparatus includes a design information storage unit, a first processing unit, a second processing unit, a correction process creation unit, and a processing process control unit,
the design information storage unit has first design information on a first functional circuit, second design information on a second functional circuit, and third design information on a third functional circuit formed by combining the first functional circuit and the second functional circuit; the first processing unit has a first processing device group capable of forming the first functional circuit on the wafer based on the first design information;
the second processing unit has a second processing device group capable of forming the second functional circuit on the wafer based on the second design information,
the corrected process creation unit creates corrected process information based on the first design information, the second design information, and the third design information, in which process conditions of one or more processes performed in the first processing device group and one or more processes performed in the second processing device group are corrected so as to be common to each other;
The processing step control section controls each processing step of the first processing apparatus group and the second processing apparatus group based on the corrected process information.

According to the present invention, the common processing can be performed in both the first and second processing units, so that it is possible to effectively utilize the resources and technologies of different companies, such as equipment groups and reticles, while forming multiple types of functional circuits on a single wafer, thereby manufacturing a variety of semiconductor devices.

In a preferred embodiment of the present invention, the correction process creation unit creates the correction process when one or more processes performed in the first processing device group and one or more processes performed in the second processing device group are standardized so that the stack heights of the wafers obtained as a result of each process are approximately the same.

By configuring in this way, even if the types of processing equipment are different, as long as the processing content is the same, it is possible to standardize each process and create a correction process based on the stack height of the wafers obtained after processing.

In addition, standard processes can be included in the types of processing equipment. It is also possible to create correction processes for those processes. By standardizing the processes, it becomes easier for IP developers to work on manufacturing the device as a semiconductor device.

In other words, the correction process is expected to have the effect of reducing the difficulty of starting from the standard process and working on manufacturing. The effect is that the standard process can be combined with various existing processing equipment and processing processes that have a proven track record. Therefore, it is possible to provide a method for achieving everything from IP development to manufacturing semiconductor devices in a shorter period of time and with greater ease.

In a preferred embodiment of the present invention, the device further includes a wiring design unit, which creates wiring design information for electrically connecting the first functional circuit and the second functional circuit based on the first design information, the second design information, and the third design information, and the processing process control unit controls each processing process of the first processing device group and the second processing device group based on the wiring design information, and electrically connects the first functional circuit and the second functional circuit.

This configuration ensures reliable electrical connection between the first and second functional circuits, making it possible to execute the combined and integrated functions of the first and second functional circuits.

In a preferred embodiment of the present invention, the system further includes a wafer transport unit, which transports the wafer between the first processing unit and the second processing unit based on the progress of the processing performed in the first processing unit group and the second processing unit group.

By configuring in this way, wafers can be exchanged appropriately between the first processing device group and the second processing device group, where some processes are shared, thereby increasing the operating rate of each processing device.

The present invention also provides a method for manufacturing a semiconductor device having a plurality of types of functional circuits formed on a single wafer based on different design information, comprising the steps of:
a correction process creating step of creating corrected process information in which process conditions of one or more processes performed in the process of forming the first functional circuit and one or more processes performed in the process of forming the second functional circuit are corrected so as to be common to each other, based on first design information on a first functional circuit, second design information on a second functional circuit, and third design information on a third functional circuit formed by combining the first functional circuit and the second functional circuit;
and forming the first functional circuit and the second functional circuit on one wafer based on the corrected process information.

According to the present invention, the common processing can be performed in both the first and second processing units, so that it is possible to effectively utilize the resources and technologies of different companies, such as equipment groups and reticles, while forming multiple types of functional circuits on a single wafer, thereby manufacturing a variety of semiconductor devices.

In a preferred embodiment of the present invention, when creating the correction process information, when one or more processes performed in the process of forming the first functional circuit and one or more processes performed in the process of forming the second functional circuit are made common, the correction process information is created so that the stack heights of the wafers obtained as a result of each process are approximately the same.

With this configuration, it becomes possible to standardize each process and create a correction process based on the stack height of the wafers.
In addition, a standard process can be included in the type of processing equipment. It is also possible to create a correction process for that. By making it a standard process, it becomes easier for IP developers to work on manufacturing it as a semiconductor device.

The present invention provides a manufacturing system for more efficiently manufacturing semiconductor devices.

1 is a schematic diagram of a manufacturing system according to an embodiment of the present invention. 11A to 11C are diagrams illustrating an example of creating a correction process according to an embodiment of the present invention. 11A to 11C are diagrams illustrating an example of creating a correction process according to an embodiment of the present invention. 1 is a schematic diagram of a manufacturing system according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a manufacturing system according to another embodiment of the present invention. 1 is an example in which a manufacturing system according to an embodiment of the present invention is applied to a system-in-package technology.

The manufacturing system and manufacturing method according to an embodiment of the present invention will be described below with reference to Figures 1 to 6. Note that the embodiment described below is an example of the present invention, and the present invention is not limited to the following embodiment. Also, the symbol X indicates a manufacturing system according to an embodiment of the present invention.

Figure 1 shows the state before correction process information is created in one embodiment of manufacturing system X.

As an example of a case in which manufacturing system X is utilized, we will assume a situation in which company A has third design information for a third functional circuit that combines a first functional circuit designed by the company A with a second functional circuit designed by company B. We will further assume that company A has a first processing unit 1 as a manufacturing base, and company B has a second processing unit as a manufacturing base.

As shown in FIG. 1, the manufacturing system X is composed of a first processing unit 1, a second processing unit 2, a design information storage unit 3, a correction process creation unit 4, a wiring design unit 5, a processing process control unit 6, and a wafer transport unit 7.

The first processing unit 1 has a first processing device group 11 capable of executing processing steps A1 to A7 for forming a first functional circuit on a wafer. The first processing device group 11 may include any number of devices as long as each of the processing steps A1 to A7 can be executed, but it is preferable that one device corresponds to one processing step.
Moreover, the process steps A1 to A7 are merely examples, and the number of process steps is not particularly limited.

The second processing unit 2 has a second processing device group 21 capable of executing processing steps B1 to B7 for forming a second functional circuit on a wafer, similar to the first processing unit 1. Note that the second processing device group 21 does not matter in total number of devices as long as each of the processing steps B1 to B7 can be executed, but it is preferable that one device corresponds to one processing step.
Moreover, the process steps B1 to B7 are merely examples, and the number of process steps is not particularly limited.

The design information storage unit 3 has first design information d31, second design information d32, and third design information d33.
The first design information d31, the second design information d32, and the third design information d33 include EDA (Electronic Design Automation) library information in the design stage of each functional circuit, information on the manufacturing process (processing method and processing conditions) of each functional circuit, and the like.
The correction process information d34 and the wiring design information d35 are created by a correction process creation unit 4 and a wiring design unit 5, which will be described later, and then stored in the design information storage unit 3. For this reason, in FIG. 1, the correction process information d34 and the wiring design information d35 are indicated by dotted lines.

The correction process creation unit 4 can create correction process information d34 based on the first design information d31, the second design information d32, and the third design information d33, in which the processing conditions of each process are corrected so as to make common the processing conditions of one or more processes performed in the first processing device group 11 and one or more processes performed in the second processing device group 21.
The details of the "standardization" of the process and the correction process information d34 will be described later.

The wiring design unit 5 can create wiring design information d35 for electrically connecting the first functional circuit and the second functional circuit based on the EDA library information of each functional circuit included in the first design information d31, the second design information d32, and the third design information d33.
That is, the wiring design information d35 can ensure the electrical connection between the first functional circuit and the second functional circuit.

The processing process control unit 6 can control the first processing device group 11, the second processing device group 21, and the wafer transport unit 7 described below based on the third design information d33, the correction process information d34, and the wiring design information d35, and execute a processing process for forming a third functional circuit on the wafer.

The design information storage unit 3, the correction process creation unit 4, the wiring design unit 5, and the processing process control unit 6 can be implemented using a general computer device equipped with an arithmetic unit such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), a main memory device such as a RAM (Random Access Memory), an auxiliary memory device such as a HDD (Hard Disk Drive), an SSD (Solid State Drive), or a flash memory, and various input/output devices including a means for connecting to a network.
Furthermore, the functions of the design information storage unit 3, the correction process creation unit 4, the wiring design unit 5, and the processing process control unit 6 may be integrated into one device, or may be distributed across multiple devices.

The wafer transport unit 7 transports wafers between the first processing unit 1 and the second processing unit 2 based on the progress of the processing performed in the first processing unit group 11 and the second processing unit group 21 .
A wafer transport robot is preferably used for short-distance transport, while an automatic driving vehicle is preferably used for long-distance transport, both of which are controlled by the processing step control unit 6.

Manufacturing system X as described above enables company A to combine the first and second function circuits it has designed to produce an LSI with a third function circuit of improved performance. Meanwhile, company B can effectively utilize its own designed second function circuit, reticles, manufacturing equipment, and technology to improve the technology and flexibility of the manufacturing process and increase factory operation and productivity.

FIG. 2 shows an example in which "standardization" of processing is performed based on first design information d31, second design information d32, and third design information d33, and correction process information d34 is obtained.
For example, consider the "commonization" of an etching process step Ax in the first design information d31, which is adjusted to etch a portion of the stack height h11 to a depth e1 to result in a stack height h12, and an etching process step Bx in the second design information d32, which is defined to etch a portion of the stack height h21 to a depth e2 to result in a stack height h22.
For the sake of simplicity, it is assumed that the stack heights h11 and h21 determined by the previous steps are equal to each other. Similarly, it is assumed that h31 is also equal to the stack heights h11 and h21.

The first design information d31 and the second design information d32 have different etching depths e1, e2, and the stack heights h12, h22 after etching are also different.
Moreover, in the third design information d33, the etching depth e3 is determined to be equal to the stack height h32.

The correction process creation unit 4 creates a "common" correction process Cx by adjusting the process conditions in each process Ax and Bx based on the first design information d31, the second design information d32, and the third design information d33 so that the stack heights h12 and h22 obtained by etching are equal to the stack height h32.

It is possible that the types of processing equipment may be different even if the processing contents are the same in steps Ax and Bx of each process. Even in such cases, the correction process creation unit 4 can adjust the processing conditions separately in steps Ax and Bx of each process by using the obtained stack height h32 as a reference.

It is more preferable to adjust stack height h32 to be equal to either stack height h12 or h22, since this requires only adjusting the processing conditions for either process Ax or Bx of each process, but a completely different value may be acceptable depending on the relationship with the other process.

FIG. 3 shows another example in which “standardization” of processing is performed based on first design information d31, second design information d32, and third design information d33, and correction process information d34 is obtained.
For example, consider the "commonization" of a film deposition process step Ax in the first design information d31, which is adjusted so that the shaded portion is deposited to a stacking height of h13, h14, and a thickness of t1, and a film deposition process step Bx in the second design information d32, which is adjusted so that the shaded portion is deposited to a stacking height of h23, h24, and a thickness of t2.
In order to simplify the conditions, it is assumed here that the laminated structure below the shaded area, which is determined by the previous process, is the same in the three diagrams of FIG.

The first design information d31 and the second design information d32 differ in stack heights h13, h23 and h14, h24, and also differ in thickness t1 and thickness t2.
In addition, in the third design information d33, the shaded areas are defined to be the stack heights h33 and h34 and the thickness t3.

The correction process creation unit 4 creates a "common" correction process Cx by adjusting the process conditions in each process Ax and Bx based on the first design information d31, the second design information d32, and the third design information d33 so that the stack heights h13, h14, thickness t1, and stack heights h23, h24, thickness t2 obtained by film deposition are equal to the stack heights h33, h34, thickness t3, respectively.

In each process, steps Ax and Bx, the processing contents may be the same, but the type of processing equipment may be different. In such cases, the correction process creation unit 4 can adjust the processing conditions separately in each process, steps Ax and Bx, by using the obtained stack heights h33, h34, and thickness t3 as a reference.

It is more preferable to adjust at least one of stacking heights h33, h34 and thickness t3 to be equal to stacking heights h13, h14 and thickness t1 or stacking heights h23, h24 and thickness t2, since this requires only adjusting the processing conditions of one of steps Ax or Bx of each process. However, depending on the relationship with other steps, stacking heights h13, h14 and thickness t1 or stacking heights h23, h24 and thickness t2 may be completely different values.

FIG. 4 shows the manufacturing system X after the corrected processes C1 to C7 have been created by the corrected process creation unit 4.
The correction processes C1 to C7 and the wiring processing process (not shown) created by the correction process creation unit 4 make it possible to form a third functional circuit on the wafer, which is formed by combining the first functional circuit and the second functional circuit.
In addition, the correction steps C1 to C7 are standardized in the manner described in Figures 2 and 3, and are divided into correction steps (C3, C6, C7) that can be executed by both the first processing unit 1 and the second processing unit 2, and correction steps (C1, C2, C4, C5) that are not standardized.

The common correction steps C3, C6, and C7 can be performed by both the first processing unit 1 and the second processing unit 2. Therefore, if there is an imbalance in the number of wafers waiting to be processed between the processing units, the wafers are transported by the wafer transport unit 7, thereby reducing the downtime of each processing unit.

In the correction processes C1, C2, C4, and C5 that are not shared, common wafers are distributed and transported in accordance with the throughput of each process.
For example, if the correction process C1 is an exposure process using electron beam lithography and the correction process C2 is a batch exposure process using a photomask, N times of the electron beam lithography process in the correction process C1 (one wafer per time) correspond to one batch exposure process in the correction process C2 (N wafers per time), where N is an arbitrary natural number. The same applies to the correction processes C4 and C5.

As a result, the manufacturing system X can more efficiently manufacture semiconductor devices by selecting a combination of executable processes from the equipment groups in each processing unit.

Fig. 5 is a diagram showing another embodiment of the manufacturing system X. The manufacturing system X shown in Fig. 5 differs from the manufacturing system X shown in Fig. 1 in that the manufacturing system X uses process management devices M1 and M2 originally provided in the first processing section 1 and the second processing section 2.
In the following, a description of parts that overlap with the manufacturing system X shown in FIG. 1 will be omitted.

The manufacturing system X includes a process management device M1 in the first processing unit 1, a process management device M2 in the second processing unit 2, a design information storage unit 3, a correction process creation unit 4, a wiring design unit 5, a processing process control unit 6, and a wafer transport unit 7, all of which are connected via a network NW.

The first processing section 1 shown in FIG. 5 has a first processing apparatus group 11 capable of executing processing steps A1 to A7 for forming a first functional circuit on a wafer, and a process management apparatus M1.
The process management device M1 includes first design information d31 and a processing process control unit 12(6), and is capable of causing the first processing device group 11 to execute a processing process for forming a first functional circuit on a wafer.

In addition, the second processing unit 2 shown in FIG. 5, like the first processing unit 1, has a second processing device group 21 capable of executing processing steps B1 to B7 for forming a second functional circuit on a wafer, and a process management device M2.
The process management device M2 includes second design information d32 and a processing process control unit 22(6), and is capable of causing the second processing device group 21 to execute a processing process for forming a second functional circuit on a wafer.

The design information storage unit 3 has third design information d33, correction process information d34, and wiring design information d35.

The processing process control units 12(6), 22(6) can control the first processing device group 11, the second processing device group 21, and the wafer transport unit 7 based on the third design information d33, the correction process information d34, and the wiring design information d35, and execute the correction processes C1 to C7 for forming the third functional circuit on the wafer.

This configuration allows the existing process management equipment M1 and M2 to be utilized, making it possible to manufacture a variety of semiconductor devices more efficiently.

Note that the configurations and functions shown in the above embodiments are merely examples and can be modified in various ways based on design requirements, etc.

Furthermore, the present invention is not limited to use between only two companies, such as company A and company B, as has been described so far. The method or system of the present invention can also be applied between three or more companies.

Furthermore, the present invention can be combined with SiP, system-in-package technology, as follows:

For example, suppose that Company A and Company B manufacture a semiconductor device chip by combining their functional circuits using the method of the present invention. In addition, if Company C manufactures a functional circuit on a different semiconductor device chip, the method of the present invention can be applied as follows, with the original goal of combining the functional circuits of these three companies using system-in-package technology.

Figure 6 shows an example of application in which a semiconductor device chip manufactured by companies A and B using the method of the present invention is called chip Ca, and a semiconductor device chip manufactured by company C is called chip Cb, and a system is formed using system-in-package technology to house chips Ca and Cb in a single package.

By applying the manufacturing system of the present invention, companies A, B, and C can manage and manufacture semiconductor device chips, package substrates, and systems in packages within the same system. This allows not only the wiring within chips Ca and Cb, but also the wiring on the package substrate to be managed within a single manufacturing system.

The following explanation focuses on wiring on the package substrate. For other parts, the above-mentioned methods and systems can be applied as is.

The wiring information for the package substrate and the system-in-package design information including the process are also managed by the design information storage unit 3, the correction process creation unit 4, the wiring design unit 5, the processing process control unit 6, and the wafer transport unit 7.

When creating the correction process, the aim is to standardize the processes for each processing device group in the manufacturing of the semiconductor device as described above, and the ease of manufacturing as a whole is also considered, including the wiring process of the package substrate. In that case, in order to facilitate the wiring process of the package substrate, it may be advantageous for the wiring process of the package substrate to deliberately create elements and parts that are considered to be additional or redundant in the manufacturing of the semiconductor device of chips Ca and Cb.

For example, in FIG. 6, the wiring in part P1 surrounded by a dotted circle is dense, and adding any more wiring to part P1 is technically difficult to manufacture. In that case, in the package board wiring L that connects bump Bu1, bump Bu6, wiring A in chip Ca, and wiring B in chip Cb, the wiring connected to wiring A in chip Ca can be modified in advance based on information from the design information storage unit 3, correction process creation unit 4, and wiring design unit 5 so that, in order to separate it from part P1 and other densely-spaced wiring parts, the wiring connected to wiring A in chip Ca passes through part P2, for example, and connects to wiring A in chip Ca.

In other words, there is no problem with the function of chip Ca and the wiring within chip Ca, but when trying to achieve functional integration with chip Cb using system-in-package manufacturing technology, a problem arises with the board wiring of the system-in-package. To solve this problem, the design and manufacturing of chip Cb are not changed, and elements and parts that are unnecessary for the function of chip Ca and the wiring within chip Ca but are considered to be additional or redundant are created in advance on chip Ca, which is advantageous for the entire manufacturing process up to the package board. This is made possible on this system based on information from the design information storage unit 3, correction process creation unit 4, and wiring design unit 5.

The wiring design section 5 handles not only the wiring in the chips Ca and Cb but also the wiring on the package substrate in a consistent manner. As a result, the technical ease of the wiring process in the chips Ca and Cb handled in the above-mentioned expanded correction process is compared with the technical ease of the wiring process on the package substrate, and the optimal balance between the two is determined.
Furthermore, the process control unit 6 handles the manufacture of semiconductor device chips, package substrates, and wiring within the substrates. Thus, according to the present invention, it is possible to carry out the manufacture of a system-in-package.

X Manufacturing system 1 First processing unit 11 First processing unit group 2 Second processing unit 21 Second processing unit group 3 Design information storage unit 4 Correction process creation unit 5 Wiring design unit 6 Processing process control unit 7 Wafer transfer unit

Claims (7)

A manufacturing system for manufacturing a semiconductor device in which a plurality of types of functional circuits based on different design information are formed on a single wafer, comprising:
The apparatus includes a design information storage unit, a first processing unit, a second processing unit, a correction process creation unit, and a processing process control unit,
the design information storage unit has first design information related to a first functional circuit, second design information related to a second functional circuit, and third design information related to a third functional circuit formed by combining the first functional circuit and the second functional circuit;
the first processing unit has a first processing device group capable of forming the first functional circuit on the wafer based on the first design information,
the second processing unit has a second processing device group capable of forming the second functional circuit on the wafer based on the second design information,
the corrected process creation unit creates corrected process information based on the first design information, the second design information, and the third design information, in which process conditions of one or more processes performed in the first processing device group and one or more processes performed in the second processing device group are corrected to be common to each other;
The processing step control unit controls each processing step of the first processing apparatus group and the second processing apparatus group based on the corrected processing step information. The semiconductor device manufacturing system of claim 1, wherein the correction process creation unit creates the correction process information when one or more processes performed in the first processing device group and one or more processes performed in the second processing device group are standardized so that the stack heights of the wafers obtained as a result of each process are approximately the same. A wiring design unit is further provided,
the wiring design unit creates wiring design information for electrically connecting the first functional circuit and the second functional circuit based on the first design information, the second design information, and the third design information;
2. The semiconductor device manufacturing system of claim 1, wherein the processing step control unit controls each processing step of the first processing device group and the second processing device group based on the wiring design information, and electrically connects the first functional circuit and the second functional circuit. Further comprising a wafer transport unit,
2. The semiconductor device manufacturing system of claim 1, wherein the wafer transport unit transports the wafer between the first processing unit and the second processing unit based on the progress of processing performed in the first processing unit group and the second processing unit group. The semiconductor device manufacturing system according to claim 3, wherein the wiring design unit designs inter-chip wiring information for electrically connecting multiple chips based on the density of the wiring between the multiple chips. A manufacturing method for manufacturing a semiconductor device in which a plurality of types of functional circuits based on different design information are formed on a single wafer, comprising the steps of:
a correction process creating step of creating corrected process information in which process conditions of one or more processes performed in the process of forming the first functional circuit and one or more processes performed in the process of forming the second functional circuit are corrected so as to be common to each other, based on first design information on a first functional circuit, second design information on a second functional circuit, and third design information on a third functional circuit formed by combining the first functional circuit and the second functional circuit;
and a circuit forming step of forming the first functional circuit and the second functional circuit on a single wafer based on the corrected process information. The method for manufacturing a semiconductor device according to claim 6, wherein, in the correction process creation step, when one or more processes performed in the process of forming the first functional circuit and one or more processes performed in the process of forming the second functional circuit are made common, the correction process information is created so that the stack heights of the wafers obtained as a result of each process are approximately the same.