JP7603379B2 - Solid-state imaging device, manufacturing method thereof, and electronic device - Google Patents

Description

The present invention relates to a solid-state imaging device, a method for manufacturing a solid-state imaging device, and an electronic device.

2. Description of the Related Art Complementary Metal Oxide Semiconductor (CMOS) image sensors are in practical use as solid-state imaging devices (image sensors) using photoelectric conversion elements that detect light and generate electric charges.
CMOS image sensors are widely used as part of various electronic devices such as digital cameras, video cameras, surveillance cameras, medical endoscopes, personal computers (PCs), mobile terminal devices such as mobile phones, and the like.

CMOS image sensors have a photodiode (photoelectric conversion element) and a floating diffusion (FD) amplifier with a floating diffusion layer for each pixel, and the mainstream readout method is a column-parallel output type that selects a row in the pixel array and simultaneously reads out the pixels in the column output direction.

Typically, each pixel of a CMOS image sensor is composed of four active elements: a transfer transistor as a transfer element, a reset transistor as a reset element, a source follower transistor as a source follower element (amplification element), and a selection transistor as a selection element, for example for one photodiode.

However, in recent years, with the increase in the number of pixels in CMOS image sensors, there has been a growing demand for smaller pixel size, and in response to this, a multi-pixel sharing technology has been proposed in which a single floating diffusion FD, reset transistor, source follower transistor, and selection transistor are shared by multiple photodiodes and transfer transistors.

Figure 1 is a circuit diagram showing an example of a pixel of a CMOS image sensor having a two-pixel sharing structure in which one floating diffusion FD, reset transistor, source follower transistor, and selection transistor are shared by two sets of photodiodes and transfer transistors (see, for example, Patent Document 1).

The shared pixel PXL1 in FIG. 1 has, for example, a first photodiode PD0 which is a first photoelectric conversion element, and a second photodiode PD1 which is a second photoelectric conversion element.
In the shared pixel PXL1, the first photodiode PD0 and the second photodiode PD1 share a floating diffusion FD as an output node.

The first photodiode PD0 and the second photodiode PD1 accumulate electric charges generated by photoelectric conversion during an accumulation period.
The first transfer transistor TG0-Tr is connected between the storage portion of the first photodiode PD0 and the floating diffusion FD.
In addition, a second transfer transistor TG1-Tr is connected between the storage portion of the second photodiode PD1 and the floating diffusion FD.

The shared pixel PXL1 has one reset transistor RST-Tr as a reset element, one source follower transistor SF-Tr as a source follower element, and one selection transistor SEL-Tr as a selection element, corresponding to the floating diffusion FD as an output node.

Figure 2 is a simplified plan view showing an example of the arrangement of two photodiodes, a transfer transistor, one floating diffusion FD, a reset transistor, a source follower transistor, and a selection transistor in the case of two shared pixels.

The shared pixel PXL1 is assigned a rectangular region RCT1 as an element formation region, including a central region CTAR1 in the center, and a first region FSAR1 and a second region SCAR1 on either side (Y direction) of the central region CTAR1.

In the central region CTAR1, a floating diffusion FD is formed in the center in the X and Y directions, and a reset transistor RST-Tr is formed on the right side in the X direction in the figure, and a source follower transistor SF-Tr and a selection transistor SEL-Tr are formed on the left side.
It should be noted that the left and right arrangements are merely examples and are not limited to the examples shown in the drawings.

In the first region FSAR1, a first photodiode PD0 and a first transfer transistor TG0-Tr are formed adjacent to each other.
In the example of FIG. 2, the first transfer transistor TG0-Tr is formed in a rectangular shape so as to be connected to the floating diffusion FD on the central region CTAR1 side.

In the second region SCAR1, a second photodiode PD1 and a second transfer transistor TG1-Tr are formed.
In the example of FIG. 2, the second transfer transistor TG1-Tr is formed on the central region CTAR1 side so as to be connected to the floating diffusion FD.

By adopting the configurations shown in Figures 1 and 2, pixel components can be shared between two pixels, maximizing the size of the photodiode PD per pixel, making it possible to miniaturize pixel size while maintaining sensitivity and saturation charge number.

Figure 3 is a circuit diagram showing an example of a pixel of a CMOS image sensor having a four-pixel shared structure in which one floating diffusion FD, reset transistor, source follower transistor, and selection transistor are shared by four sets of photodiodes and transfer transistors (see, for example, Patent Document 2).

The shared pixel PXL2 in FIG. 3 includes, in addition to the configuration of the pixel PXL1 in FIG. 1, a third photodiode PD2 which is a third photoelectric conversion element, and a fourth photodiode PD3 which is a fourth photoelectric conversion element.
That is, in the shared pixel PXL2, the first photodiode PD0, the second photodiode PD1, the third photodiode PD2, and the fourth photodiode PD3 share the floating diffusion FD as an output node.

The first photodiode PD0, the second photodiode PD1, the third photodiode PD2, and the fourth photodiode PD3 accumulate electric charges generated by photoelectric conversion during an accumulation period.
The first transfer transistor TG0-Tr is connected between the storage portion of the first photodiode PD0 and the floating diffusion FD.
The second transfer transistor TG1-Tr is connected between the storage portion of the second photodiode PD1 and the floating diffusion FD.
The third transfer transistor TG2-Tr is connected between the storage portion of the third photodiode PD2 and the floating diffusion FD.
The fourth transfer transistor TG3-Tr is connected between the storage portion of the fourth photodiode PD3 and the floating diffusion FD.

Figure 4 is a simplified plan view showing a first example of the arrangement of four photodiodes, a transfer transistor, one floating diffusion FD, a reset transistor, a source follower transistor, and a selection transistor in the case of four-pixel sharing formed with the same concept as in Figure 2.

The shared pixel PXL2 is assigned a rectangular region RCT2 as an element formation region, including a central region CTAR2 in the center, and a first region FSAR2 and a second region SCAR2 on either side (Y direction) of the central region CTAR2.

In the central region CTAR2, a floating diffusion FD is formed in the center in the X and Y directions, and a reset transistor RST-Tr is formed on the right side in the X direction in the figure, and a source follower transistor SF-Tr and a selection transistor SEL-Tr are formed on the left side.
It should be noted that the left and right arrangements are merely examples and are not limited to the examples shown in the drawings.

In the first region FSAR2, a first photodiode PD0, a first transfer transistor TG0-Tr, a third photodiode PD2, and a third transfer transistor TG2-Tr are formed adjacent to each other.
In the example of FIG. 4, the first photodiode PD0 and the first transfer transistor TG0-Tr are formed on the left side of the first region FSAR2 in the figure (left half of the region), and the third photodiode PD2 and the third transfer transistor TG2-Tr are formed on the right side of the first region FSAR2 in the figure (right half of the region).
The first transfer transistor TG0-Tr and the third transfer transistor TG2-Tr are formed in a rectangular shape so as to be connected to the floating diffusion FD on the central region CTAR2 side.

In the second region SCAR2, a second photodiode PD1, a second transfer transistor TG1-Tr, a fourth photodiode PD3, and a fourth transfer transistor TG3-Tr are formed adjacent to each other.
In the example of FIG. 4, the second photodiode PD1 and the second transfer transistor TG1-Tr are formed on the left side of the second region SCAR2 in the figure (left half region), and the fourth photodiode PD3 and the fourth transfer transistor TG3-Tr are formed on the right side of the second region SCAR2 in the figure (right half region).
The second transfer transistor TG1-Tr and the fourth transfer transistor TG3-Tr are formed in a rectangular shape so as to be connected to the floating diffusion FD on the central region CTAR2 side.

By adopting the configurations shown in Figures 3 and 4, the pixel components can be shared among four pixels, maximizing the size of the photodiode PD per pixel, making it possible to miniaturize the pixel size while maintaining the sensitivity and saturation charge number.

Figure 5 is a simplified plan view showing a second example of the arrangement of four photodiodes, a transfer transistor, one floating diffusion FD, a reset transistor, a source follower transistor, and a selection transistor in the case of four shared pixels.

The shared pixel PXL3 in FIG. 5 is a modified example of a four-pixel shared pixel, and has a configuration in which two floating diffusions FD are shared by eight pixels (see, for example, Patent Document 3).
The shared pixel PXL3 in FIG. 5 corresponds to the four-pixel sharing in FIG. 4 and has four photodiodes PD0 to PD3, as well as a first light receiving region RLT1 and a second light receiving region RLT2 in which transfer transistors TG0-Tr to TG3-Tr are formed.

Furthermore, the shared pixel PXL3 has a first transistor group GTR1 and a second transistor group GTR2.
In the first transistor group GTR1, a source follower transistor SF-Tr and a selection transistor SEL-Tr are arranged.
In the second transistor group GTR2, a reset transistor RST1-Tr and a dummy reset transistor RST2-Tr are arranged.

Although one reset transistor RST-Tr is sufficient, a dummy reset transistor RST2-Tr is provided in the second transistor group GTR2 to ensure layout symmetry with the first transistor group GTR1.

In the shared pixel PXL3 having such a configuration, the arrangement of the first light receiving region RLT1 and the first transistor group GTR1 and the arrangement of the second light receiving region PLT2 and the second transistor group GTR2 have structural symmetry with the floating diffusion FD as the optical center, so that it is possible to suppress variation in the sensitivity (output) characteristics between pixels of the same color.

JP 2007-81033 A JP 2006-302970 A JP 2013-627895 A

The two-pixel shared pixel PXL1 described above allows pixel components to be shared between two pixels, maximizing the size of the photodiode PD per pixel, making it possible to miniaturize pixel size while maintaining sensitivity and saturation charge number.

However, the shared pixel PXL1 in Figure 2 has a larger number of elements per shared pixel than when four pixels are shared, so there is a limit to how small the pixel size can be made.

In addition, the above-mentioned four-pixel shared pixel PXL2 allows pixel components to be shared among four pixels, maximizing the size of the photodiode PD per pixel, making it possible to miniaturize pixel size while maintaining sensitivity and saturation charge number.

However, the shared pixel PXL2 in Figure 4 has a large area for the floating diffusion FD portion, which has the disadvantage of increasing the capacity of the floating diffusion FD, reducing the conversion gain, and increasing noise.

In addition, in the shared pixel PXL3 in Fig. 5, for example, a photodiode PD is formed radially from the floating diffusion FD. If the diffusion layer part of the floating diffusion FD is placed in the center and arranged as in Fig. 5, the reset transistor RST-Tr cannot be arranged adjacently. Therefore, the diffusion layer part of the floating diffusion FD needs to be arranged not only in the center but also on the edge of the pixel, such as on the pixel isolation region, for wiring connection.
This leads to an increase in junction capacitance and wiring capacitance for electrical connection, which increases the capacitance of the FD node (Cfd), reducing the conversion gain and deteriorating noise characteristics.

Generally, when a signal (overflow charge) that exceeds the accumulated charge of a given photodiode PD flows into an adjacent pixel, mixing of the charges (becoming a false signal) occurs.
To prevent this, a configuration is adopted in which the overflow charge flows into a connected floating diffusion FD before leaking into an adjacent pixel.
In this configuration, if charge from a pixel sharing the floating diffusion FD leaks in while the charge is being read out, a false signal occurs. For example, in the case of a Bayer array, if an overflow charge of a G signal occurs while an R signal is being read out, charge mixing occurs in the floating diffusion FD as an output node.

The present invention provides a solid-state imaging device, a method for manufacturing a solid-state imaging device, and electronic equipment that not only enables pixel size to be reduced while maintaining sensitivity and saturation charge, but also suppresses an increase in junction capacitance and wiring capacitance, inhibits an increase in the capacitance of the floating diffusion as an output node, prevents a decrease in conversion gain, and ultimately improves noise characteristics.
Furthermore, the present invention aims to provide a solid-state imaging device, a method for manufacturing a solid-state imaging device, and electronic equipment that not only enables pixel size to be reduced while maintaining sensitivity and saturation charge, but also suppresses an increase in junction capacitance and wiring capacitance, suppresses an increase in the capacitance of the floating diffusion as an output node, prevents a decrease in conversion gain, and ultimately improves noise characteristics, while also preventing charge mixing in the floating diffusion.

A solid-state imaging device according to a first aspect of the present invention has a pixel section in which shared pixels that perform photoelectric conversion are arranged, and the shared pixels include at least three photoelectric conversion elements that accumulate charges generated by photoelectric conversion during an accumulation period, a plurality of transfer elements that can individually transfer the charges accumulated in each of the photoelectric conversion elements during a transfer period after the accumulation period, a floating diffusion as an output node to which the accumulated charges of each of the photoelectric conversion elements are transferred through each of the transfer elements, a reset element that resets the floating diffusion to a predetermined potential during a reset period, and a source follower element as an output buffer section that converts the charge of the floating diffusion into a voltage signal corresponding to the amount of charge and outputs the converted voltage signal, and one of the floating diffusions and one of the source follower elements are shared by the plurality of photoelectric conversion elements and the plurality of transfer elements, the floating diffusion is arranged in the central portion of an element formation region, the plurality of photoelectric conversion elements are arranged radially around the floating diffusion, and the floating diffusion The floating diffusion includes a first side and a second side opposed to each other, the source follower element is arranged adjacent to the first side of the floating diffusion in a first direction perpendicular to the first side of the floating diffusion, the reset element is arranged adjacent to the second side of the floating diffusion in the first direction, the floating diffusion and the source follower element are connected by wiring, and the photoelectric conversion elements adjacent to each other in the second direction are arranged at a first interval allowing at least the source follower element and the reset element to be formed. The photoelectric conversion elements adjacent in the first direction are arranged at a second interval narrower than the first interval, and the corresponding transfer elements are arranged to connect between a first side edge in the second direction of the first side of the floating diffusion and a first edge of the photoelectric conversion element that faces the first side edge, and between a second side edge in the second direction of the second side of the floating diffusion and a first edge of the photoelectric conversion element that faces the second side edge.

A second aspect of the present invention is a manufacturing method for a solid-state imaging device having a pixel section in which shared pixels that perform photoelectric conversion are arranged, the shared pixels including at least three photoelectric conversion elements that accumulate charges generated by photoelectric conversion during an accumulation period, a plurality of transfer elements that can individually transfer the charges accumulated in each of the photoelectric conversion elements during a transfer period following the accumulation period, a floating diffusion as an output node to which the accumulated charges of each of the photoelectric conversion elements are transferred through each of the transfer elements, a reset element that resets the floating diffusion to a predetermined potential during a reset period, and a source follower element as an output buffer section that converts the charge of the floating diffusion into a voltage signal corresponding to the amount of charge and outputs the converted voltage signal, wherein one of the floating diffusions and one of the source follower elements are shared by the plurality of photoelectric conversion elements and the plurality of transfer elements, the floating diffusion is arranged in the central portion of an element formation region, and the plurality of photoelectric conversion elements are arranged radially around the floating diffusion, The floating diffusion includes a first side and a second side opposed to each other, the source follower element is formed adjacent to the first side of the floating diffusion in a first direction perpendicular to the first side of the floating diffusion, the reset element is formed adjacent to the second side of the floating diffusion in the first direction, the floating diffusion and the source follower element are connected by wiring, and the photoelectric conversion elements adjacent to each other in the second direction have a first interval at which at least the source follower element and the reset element can be formed. The photoelectric conversion elements adjacent in the first direction are formed at a second interval narrower than the first interval, and the corresponding transfer elements are formed to connect between a first side edge in the second direction of the first side of the floating diffusion and a first edge of the photoelectric conversion element that faces the first side edge, and between a second side edge in the second direction of the second side of the floating diffusion and a first edge of the photoelectric conversion element that faces the second side edge.

An electronic device according to a third aspect of the present invention has a solid-state imaging device and an optical system for forming a subject image on the solid-state imaging device, the solid-state imaging device having a pixel section in which a shared pixel for performing photoelectric conversion is arranged, the shared pixel having at least three photoelectric conversion elements for storing electric charges generated by photoelectric conversion during an accumulation period, a plurality of transfer elements capable of individually transferring the electric charges stored in each of the photoelectric conversion elements during a transfer period following the accumulation period, a floating diffusion as an output node to which the accumulated electric charges of each of the photoelectric conversion elements are transferred through each of the transfer elements, and a reset period and a source follower element serving as an output buffer unit that converts a charge of the floating diffusion into a voltage signal corresponding to the charge amount and outputs the converted voltage signal, one of the floating diffusions and one of the source follower elements are shared by the plurality of photoelectric conversion elements and the plurality of transfer elements, the floating diffusion is disposed in a central portion of an element formation region, and the plurality of photoelectric conversion elements are disposed radially with the floating diffusion as a center, the floating diffusion includes a first side portion and a second side portion opposed to each other, the source follower elements are disposed adjacent to each other in a first direction perpendicular to the first side portion of the floating diffusion, and the reset element is disposed adjacent to the second side portion of the floating diffusion in the first direction, the floating diffusion and the source follower element are connected by wiring, and the photoelectric conversion elements adjacent to each other in the second direction are at least a first side portion in which the source follower element and the reset element can be formed. The photoelectric conversion elements adjacent in the first direction are arranged at a second interval narrower than the first interval, and the corresponding transfer elements are arranged to connect between a first side edge in the second direction of the first side of the floating diffusion and a first edge of the photoelectric conversion element that faces the first side edge, and between a second side edge in the second direction of the second side of the floating diffusion and a first edge of the photoelectric conversion element that faces the second side edge.

According to the present invention, it is possible to reduce pixel size while maintaining sensitivity and saturation charge, and also to suppress an increase in junction capacitance and wiring capacitance, thereby suppressing an increase in the capacitance of the floating diffusion serving as an output node, preventing a decrease in conversion gain, and ultimately improving noise characteristics.
Furthermore, according to the present invention, it is possible to reduce pixel size while maintaining sensitivity and saturation charge, and it is also possible to suppress an increase in junction capacitance and wiring capacitance, thereby suppressing an increase in the capacitance of the floating diffusion as an output node and preventing a decrease in conversion gain, thereby improving noise characteristics, and also preventing charge mixing in the floating diffusion.

FIG. 1 is a circuit diagram showing an example of a pixel of a CMOS image sensor having a two-pixel shared structure in which one floating diffusion FD, reset transistor, source follower transistor, and selection transistor are shared by two sets of photodiodes and transfer transistors. FIG. 11 is a simplified plan view showing an example of the arrangement of two photodiodes, a transfer transistor, one floating diffusion FD, a reset transistor, a source follower transistor, and a selection transistor in the case of two-pixel sharing. FIG. 1 is a circuit diagram showing an example of a pixel of a CMOS image sensor having a four-pixel shared structure in which one floating diffusion FD, reset transistor, source follower transistor, and selection transistor are shared by four sets of photodiodes and transfer transistors. FIG. 11 is a simplified plan view showing a first arrangement example of four photodiodes, a transfer transistor, one floating diffusion FD, a reset transistor, a source follower transistor, and a selection transistor in the case of four-pixel sharing. FIG. 11 is a simplified plan view showing a second example of the arrangement of four photodiodes, a transfer transistor, one floating diffusion FD, a reset transistor, a source follower transistor, and a selection transistor in the case of four-pixel sharing. 1 is a block diagram showing an example of the configuration of a solid-state imaging device according to a first embodiment of the present invention; 2 is a circuit diagram showing an example of a shared pixel of the solid-state imaging device according to the first embodiment of the present invention. 2 is a diagram for explaining an example of the configuration of a readout system for column outputs of a pixel unit of a solid-state imaging device according to an embodiment of the present invention. FIG. 1 is a simplified cross-sectional view showing an example of the configuration of a charge accumulation and transfer system including a buried photodiode and a transfer transistor, which are the main parts of a shared pixel of a solid-state imaging device according to a first embodiment of the present invention. FIG. 1 is a simplified plan view showing an example of the arrangement of four photodiodes, a transfer transistor, one floating diffusion FD, a reset transistor, a source follower transistor, and a selection transistor of a shared pixel according to the first embodiment. FIG. 2 is a simplified cross-sectional view of a main part of a shared pixel according to the first embodiment, illustrating an additional capacitance component added to the capacitance of a floating diffusion. This is a simplified cross-sectional view of the main parts of a shared pixel that is a comparative example to the shared pixel of Figure 11 which does not have the characteristic configuration of the shared pixel of the first embodiment, and is a figure for explaining the additional capacitance component added to the capacitance of the floating diffusion. 1A to 1C are diagrams showing the layout of a solid-state imaging device according to a first embodiment of the present invention, which is used for comparison of FD node capacitance, wiring capacitance, and their total capacitance, as well as pixel size, a layout of a first comparative example, and a layout of a second comparative example. FIG. 11 is a table showing a comparison of the FD node capacitance, wiring capacitance, and their total capacitance, as well as pixel size, in the layout of the solid-state imaging device according to the first embodiment of the present invention, the layout of the first comparative example, and the layout of the second comparative example. FIG. 11 is a circuit diagram showing an example of a shared pixel of a solid-state imaging device according to a second embodiment of the present invention. FIG. 11 is a simplified plan view showing an example of the arrangement of four photodiodes, a transfer transistor, one floating diffusion FD, a reset transistor, a source follower transistor, and a selection transistor of a shared pixel according to the second embodiment. FIG. 11 is a simplified cross-sectional view showing an example of the configuration of a charge accumulation and transfer system having a shutter gate transistor which is a main part of a shared pixel according to a second embodiment of the present invention. FIG. 13 is a circuit diagram showing an example of a shared pixel of a solid-state imaging device according to a third embodiment of the present invention. FIG. 13 is a simplified plan view showing an example of the arrangement of four photodiodes, a transfer transistor, one floating diffusion FD, a reset transistor, a source follower transistor, and a selection transistor of a shared pixel according to the third embodiment. 13 is a timing chart for explaining an example of a readout sequence in a readout mode for shared pixels in a solid-state imaging device according to a third embodiment of the present invention. 13 is a circuit diagram showing an example of the configuration of a shared pixel of a solid-state imaging device 10C according to a fourth embodiment of the present invention. FIG. 13 is an operation sequence diagram for explaining a global shutter readout operation of the solid-state imaging device according to the fourth embodiment in comparison with a rolling shutter readout operation. FIG. 13 is a diagram showing an example of a timing chart of a rolling shutter readout operation. FIG. 13 is a diagram showing an example of a timing chart of a global shutter read operation. 1 is a diagram showing an example of a configuration of an electronic device to which a solid-state imaging device according to an embodiment of the present invention is applied;

The following describes an embodiment of the present invention with reference to the drawings.

(First embodiment)
FIG. 6 is a block diagram showing an example of the configuration of a solid-state imaging device according to the first embodiment of the present invention.
In this embodiment, the solid-state imaging device 10 is formed of, for example, a CMOS image sensor.

As shown in FIG. 6 , the solid-state imaging device 10 has as its main components a pixel section 20 as an imaging section, a vertical scanning circuit (row scanning circuit) 30, a readout circuit (column readout circuit) 40, a horizontal scanning circuit (column scanning circuit) 50, and a timing control circuit 60.
Of these components, for example, the vertical scanning circuit 30, the readout circuit 40, the horizontal scanning circuit 50, and the timing control circuit 60 constitute a pixel signal readout section 70.

In the first embodiment, as described in detail later, in the solid-state imaging device 10, the pixels (or pixel section 20) arranged in a matrix in the pixel section 20 have one floating diffusion FD as an output node and a source follower element (source follower transistor) forming an output buffer, which are shared by at least three (four in this embodiment) photoelectric conversion elements (photodiodes) and transfer elements (transfer transistors).
A floating diffusion FD is disposed in the center of the element formation region of the shared pixel, and a plurality of photoelectric conversion elements are disposed radially (in this embodiment, in a square) with this floating diffusion FD as the center.

The shared pixel of the solid-state imaging device 10 according to this embodiment not only enables pixel size to be reduced while maintaining sensitivity and saturation charge number, but also has the following characteristic configuration, which makes it possible to suppress an increase in junction capacitance and wiring capacitance, inhibit an increase in the capacitance of the floating diffusion as an output node, prevent a decrease in conversion gain, and ultimately improve noise characteristics.
That is, as will be described later, the floating diffusion FD is formed in a rectangular shape (rectangular shape in this example) including a first side portion SDP1 and a second side portion SDP2 opposing each other in a plan view.
A source follower element is arranged in a central portion CTR of the element formation region adjacent to a first direction (e.g., the X direction) perpendicular to a first side portion SDP1 of the floating diffusion FD10, a reset element is arranged adjacent to a second side portion SDP2 of the floating diffusion FD10 in the first direction, and the floating diffusion FD10 and the source follower element are connected by wiring.

Adjacent photoelectric conversion elements in a second direction (e.g., the Y direction) are arranged at a first distance D1 that allows for the formation of at least a source follower element and a reset element (MOS transistor), and adjacent photoelectric conversion elements in the first direction are arranged at a second distance D2 that is narrower than the first distance D1.
Corresponding transfer elements are arranged to connect between the first side edge portions SDT11, STD12 in the second direction of the first side portion SDP1 of the floating diffusion FD10 and the first edge portions ED111, ED112 facing the first side edge portion SDT11 of the photoelectric conversion element, and between the second side edge portions SDT21, SDT22 in the second direction of the second side portion SDP2 of the floating diffusion FD and the first edge portions ED121, ED122 facing the second side edge portions SDT21, SDT22 of the photoelectric conversion element.
Each transfer element is disposed so as to straddle between a side edge of the floating diffusion FD and a corresponding photoelectric conversion element.

The solid-state imaging device 10 may be configured to have a global shutter operation function.

Below, we will provide an overview of the configuration and function of each part of the solid-state imaging device 10, and then provide a detailed description of the configuration of the buried photodiode (PPD) part and an example of the arrangement of each element in the shared pixel.

(Configuration of pixel section 20 and shared pixel PXL20)
FIG. 7 is a circuit diagram showing an example of a shared pixel of the solid-state imaging device according to the first embodiment of the invention.

The shared pixel PXL20 in FIG. 1 has, for example, a first photodiode PD10 which is a first photoelectric conversion element, a second photodiode PD11 which is a second photoelectric conversion element, a third photodiode PD12 which is a third photoelectric conversion element, and a photodiode PD13 which is a fourth photoelectric conversion element.
In the shared pixel PXL20, a first photodiode PD10, a second photodiode PD11, a third photodiode PD12, and a fourth photodiode PD13 share a floating diffusion FD10 as an output node ND10.

The first photodiode PD10, the second photodiode PD11, the third photodiode PD12, and the fourth photodiode PD13 accumulate electric charges generated by photoelectric conversion during an accumulation period.
The first transfer transistor TG10-Tr is connected between the storage portion PND10 of the first photodiode PD10 and the floating diffusion FD10.
The second transfer transistor TG11-Tr is connected between the storage portion PND11 of the second photodiode PD11 and the floating diffusion FD10.
The third transfer transistor TG12-Tr is connected between the storage portion PND12 of the third photodiode PD12 and the floating diffusion FD10.
A fourth transfer transistor TG13-Tr is connected between the storage portion PND13 of the fourth photodiode PD13 and the floating diffusion FD10.

The shared pixel PXL20 corresponds to the floating diffusion FD10 as one output node ND10, and has one reset transistor RST10-Tr as a reset element, one source follower transistor SF10-Tr as a source follower element, and one selection transistor SEL10-Tr as a selection element.

The first photodiode PD10, the second photodiode PD11, the third photodiode PD12, and the fourth photodiode PD13 generate and accumulate signal charges (electrons in this case) in amounts corresponding to the amount of incident light.
In the following, a case will be described in which the signal charges are electrons and each transistor is an n-type transistor, but the signal charges may be holes and each transistor may be a p-type transistor.

In the shared pixel PXL20, a buried photodiode (PPD) is used as the photodiode (PD).
Since there are interface states due to defects such as dangling bonds on the surface of the substrate on which the photodiode (PD) is formed, a large amount of charge (dark current) is generated by thermal energy, making it impossible to read out a correct signal.
In a buried photodiode (PPD), the charge storage portion of a photodiode (PD) is buried in a substrate, making it possible to reduce the inclusion of dark current in a signal.

The first transfer transistor TG10-Tr of the shared pixel PXL20 is connected between the first photodiode PD10 and the floating diffusion FD10, and is controlled by a control signal TG10 applied to the gate through a control line.
The first transfer transistor TG10-Tr is selected and turned on during the transfer period PT when the control signal TG10 is at a high (H) level, and transfers the charges (electrons) photoelectrically converted and accumulated in the first photodiode PD10 to the floating diffusion FD10.
After the first photodiode PD10 and the floating diffusion FD10 are reset to a predetermined reset potential, the first transfer transistor TG10-Tr becomes non-conductive with the control signal TG10 at a low (L) level, and the first photodiode PD10 enters the accumulation period PI. At this time, if the intensity (amount) of the incident light is extremely high, charges that exceed the saturation charge amount overflow into the floating diffusion FD10 as overflow charges through the overflow path below the first transfer transistor TG10-Tr.

The second transfer transistor TG11-Tr of the shared pixel PXL20 is connected between the second photodiode PD11 and the floating diffusion FD10, and is controlled by a control signal TG11 applied to its gate via a control line.
The second transfer transistor TG11-Tr is selected and turned on during the transfer period PT when the control signal TG11 is at a high (H) level, and transfers the charges (electrons) photoelectrically converted and accumulated in the second photodiode PD11 to the floating diffusion FD10.
After the second photodiode PD11 and the floating diffusion FD10 are reset to a predetermined reset potential, the second transfer transistor TG11-Tr becomes non-conductive with the control signal TG11 at a low (L) level, and the second photodiode PD11 enters the accumulation period PI. At this time, if the intensity (amount) of the incident light is extremely high, charge that exceeds the saturation charge amount overflows into the floating diffusion FD10 as overflow charge through the overflow path below the second transfer transistor TG11-Tr.

The third transfer transistor TG12-Tr of the shared pixel PXL20 is connected between the third photodiode PD12 and the floating diffusion FD10, and is controlled by a control signal TG12 applied to its gate through a control line.
The third transfer transistor TG12-Tr is selected and turned on during the transfer period PT when the control signal TG12 is at a high (H) level, and transfers the charges (electrons) photoelectrically converted and accumulated in the third photodiode PD12 to the floating diffusion FD10.
After the third photodiode PD12 and the floating diffusion FD10 are reset to a predetermined reset potential, the third transfer transistor TG12-Tr becomes non-conductive with the control signal TG12 at a low (L) level, and the third photodiode PD12 enters the accumulation period PI. At this time, if the intensity (amount) of the incident light is extremely high, charges that exceed the saturation charge amount overflow into the floating diffusion FD10 as overflow charges through the overflow path below the third transfer transistor TG12-Tr.

The fourth transfer transistor TG13-Tr of the shared pixel PXL20 is connected between the fourth photodiode PD13 and the floating diffusion FD10, and is controlled by a control signal TG13 applied to its gate through a control line.
The fourth transfer transistor TG13-Tr is selected and turned on during the transfer period PT when the control signal TG13 is at a high (H) level, and transfers the charges (electrons) photoelectrically converted and accumulated in the fourth photodiode PD13 to the floating diffusion FD10.
After the fourth photodiode PD13 and the floating diffusion FD10 are reset to a predetermined reset potential, the fourth transfer transistor TG13-Tr becomes non-conductive with the control signal TG13 at a low (L) level, and the fourth photodiode PD13 enters the accumulation period PI. At this time, if the intensity (amount) of the incident light is extremely high, charges that exceed the saturation charge amount overflow into the floating diffusion FD10 as overflow charges through the overflow path below the fourth transfer transistor TG13-Tr.

The reset transistor RST10-Tr is connected between a power supply line Vaapix of a power supply voltage VAAPIX and a floating diffusion FD10, and is controlled by a control signal RST10 applied to the gate via a control line.
The reset transistor RST10-Tr is selected and turned on during the reset period when the control signal RST10 is at H level, and resets the floating diffusion FD10 to the potential of the power supply line Vaapix of the power supply voltage VAAPIX.

The source follower transistor SF10-Tr and the selection transistor SEL10-Tr are connected in series between the power supply line Vaapix and the vertical signal line LSGN10.
A floating diffusion FD10 is connected to the gate of the source follower transistor SF10-Tr, and the selection transistor SEL10-Tr is controlled via a control signal SEL10.
The source follower transistor SF10-Tr serving as a source follower element has a source connected to the read node ND11, a drain connected to the power supply line Vaapix, and a gate connected to the floating diffusion FD10.
An output node ND10 forming an output buffer section is connected to a vertical signal line LSGN10 via a selection transistor SEL10-Tr.
The selection transistor SEL10-Tr is selected and turned on while the control signal SEL10 is at H level, so that the source follower transistor SF10-Tr outputs a column output read signal VSL (PIXOUT) obtained by converting the charge of the floating diffusion FD10 into a voltage signal with gain to the vertical signal line LSGN10.
These operations are performed simultaneously in parallel for each pixel in one row, since the gates of the transfer transistor TG10-Tr, the reset transistor RST10-Tr, and the selection transistor SEL10-Tr are connected in row units.

The vertical scanning circuit 30 drives pixels in the shutter row and the readout row through row scanning control lines under the control of the timing control circuit 60 .
Furthermore, the vertical scanning circuit 30 outputs a row selection signal of the row address of a read row for reading out a signal and a shutter row for resetting the charge accumulated in the photodiode PD in accordance with the address signal.

As described above, in normal pixel readout operation, shutter scanning is performed by driving the vertical scanning circuit 30, and then readout scanning is performed.

The readout circuit 40 may include multiple column signal processing circuits (not shown) arranged corresponding to each column output of the pixel section 20, and may be configured to enable column parallel processing by the multiple column signal processing circuits.

The readout circuit 40 can be configured to include a correlated double sampling (CDS) circuit, an analog-to-digital converter (ADC), an amplifier (AMP), a sample-and-hold (S/H) circuit, etc.

In this way, the readout circuit 40 may be configured to include an ADC 41 that converts the readout signal VSL of each column output of the pixel section 20 into a digital signal, as shown in FIG. 8A, for example.
Alternatively, the readout circuit 40 may include an amplifier (AMP) 42 that amplifies the readout signal VSL of each column output of the pixel section 20, as shown in FIG. 8B, for example.
Furthermore, the readout circuit 40 may include a sample-and-hold (S/H) circuit 43 that samples and holds the readout signal VSL of each column output of the pixel section 20, as shown in FIG. 8C, for example.

The horizontal scanning circuit 50 scans the signals processed by multiple column signal processing circuits such as the ADC of the readout circuit 40, transfers them in the horizontal direction, and outputs them to a signal processing circuit (not shown).

The timing control circuit 60 generates timing signals necessary for signal processing of the pixel section 20, vertical scanning circuit 30, readout circuit 40, horizontal scanning circuit 50, etc.

The configuration and function of each part of the solid-state imaging device 10 according to the first embodiment have been described above.
Next, a specific configuration example of the buried photodiode PPD as the photoelectric conversion section according to the first embodiment and an example of a pixel arrangement will be described.

(Specific Configuration Example of Buried Photodiode PD)
Here, a specific configuration example of the embedded photodiode PD forming the shared pixel PXL20 of the solid-state imaging device 10 according to the first embodiment will be described with reference to FIG.

FIG. 9 is a simplified cross-sectional view showing an example of the configuration of a charge accumulation and transfer system including a buried photodiode PD and a transfer transistor, which are the main components of the shared pixel PXL20 of the solid-state imaging device according to the first embodiment of the present invention.
In this embodiment, the embedded photodiode (PD) portion is denoted by reference numeral 200 .

The shared pixel PXL20 is formed on a substrate (in this example, the first substrate 110) having a first substrate surface 1101 side (e.g., the back side) onto which light L is irradiated, and a second substrate surface 1102 side opposite to the first substrate surface 1101 side, and is separated by a separation layer SPL.
The shared pixel PLX20 according to this embodiment of FIG. 9 is configured to include, for example, a first photodiode PD10, a first transfer transistor TG10-Tr, a floating diffusion FD10, an isolation layer SPL, and further a color filter section and a microlens (not shown).

Note that while the pixel in FIG. 9 is shown as an example of a back-illuminated type, the present invention may also be of a front-illuminated type.

(Photodiode configuration)
The first photodiode PD10 includes a first conductivity type (n type in this embodiment) semiconductor layer (n layer in this embodiment) 2102 formed so as to be embedded in a second conductivity type (p type in this embodiment) epitaxial layer (p-epi) 2101 of a semiconductor substrate having a first substrate surface 1101 side and a second substrate surface 1102 side opposite the first substrate surface 1101 side, and is formed so as to have a photoelectric conversion function of received light and a charge storage function.
On both sides of the first photodiode PD10 in the direction (X direction) perpendicular to the normal to the substrate, second conductivity type (p-type in this embodiment) isolation layers SPL (SPL1, SPL2) are formed via epitaxial layers (p-epi) 2101R, 2101L.

In the first photodiode PD10 in FIG. 9, a p+ layer 2103 is formed on the second substrate surface 1102 side of an n layer (first conductivity type semiconductor layer) 2102 .
A color filter section is formed on the light incident side of the epitaxial layer (p-epi) 2101, and further, a microlens is formed on the light incident side of the color filter section so as to appropriately focus light on the first photodiode PD10.

(Configuration of Separation Layer in X-Direction (Column Direction))
An n+ layer 2105 that becomes the floating diffusion FD10 is formed on the second substrate surface 1102 side of the p-type isolation layer 2104 (SPL1) on the right side in the X direction (column direction) of FIG.
On the left side in the X direction (column direction) of FIG. 9, a p-type isolation layer 2106 (SPL2) is formed.
A gate electrode 2107 of the first transfer transistor TG0-Tr is formed on the epitaxial layer (p-epi) 2101R on the second substrate surface 1102 side via a gate insulating film.
An overflow path OVP extending from the first photodiode PD10 to the floating diffusion FD10 is formed below the first transfer transistor TG10-Tr.
The potential of the overflow path OVP can also be controlled by gate control, for example.

The shared pixel PXL20 of the first embodiment not only enables the pixel size to be miniaturized while maintaining the sensitivity and saturation charge number, but also suppresses the increase in junction capacitance and wiring capacitance, suppresses the increase in the capacitance of the floating diffusion FD10 as the output node, prevents a decrease in conversion gain, and ultimately improves noise characteristics. In this way, the following characteristic arrangement configuration is adopted for the arrangement of the four PDs, one FD, etc.

(Example of arrangement of shared pixel PXL 20, four PDs, one FD, etc.)
Next, an example of the arrangement of the four photodiodes PD10, PD11, PD12, and PD13 of the shared pixel PXL20, the transfer transistors TG10-Tr, TG11-Tr, TG12-Tr, and TG13-Tr, as well as one floating diffusion FD10, the reset transistor RST10-Tr, the source follower transistor SF10-Tr, and the selection transistor SEL10-Tr will be described.
In the following description, the left and right arrangement positions of the elements are merely examples and do not necessarily have to be the examples shown in the drawings.

Figure 10 is a simplified plan view showing an example arrangement of four photodiodes, a transfer transistor, one floating diffusion FD, a reset transistor, a source follower transistor, and a selection transistor of a shared pixel according to the first embodiment.

The shared pixel PXL20 is assigned a rectangular region RCT20 as an element formation region, including a central region CTAR20 in the central portion, and a first region FSAR20 and a second region SCAR20 on either side (Y direction) of the central region CTAR20.

In the central region CTAR20, a floating diffusion FD10 is formed in the center in the X and Y directions, with a reset transistor RST10-Tr formed on the right side in the X direction as shown in the figure, and a source follower transistor SF10-Tr and a selection transistor SEL10-Tr formed on the left side.

In the first region FSAR20, a first photodiode PD10, a first transfer transistor TG10-Tr, a third photodiode PD12, and a third transfer transistor TG12-Tr are formed adjacent to each other in the X direction.
In the example of FIG. 10, the first photodiode PD10 and the first transfer transistor TG10-Tr are formed on the left side of the first region FSAR20 in the figure (left half of the region), and the third photodiode PD12 and the third transfer transistor TG12-Tr are formed on the right side of the first region FSAR20 in the figure (right half of the region).
The first transfer transistor TG10-Tr and the third transfer transistor TG12-Tr are formed in a triangular shape in plan view so as to be connected to the floating diffusion FD10 on the central region CTAR20 side.

In the second region SCAR20, a second photodiode PD11, a second transfer transistor TG11-Tr, a fourth photodiode PD13, and a fourth transfer transistor TG13-Tr are formed adjacent to each other in the X direction.
In the example of FIG. 10, the second photodiode PD11 and the second transfer transistor TG11-Tr are formed on the left side of the first region FSAR2 in the figure (left half of the region), and the fourth photodiode PD13 and the fourth transfer transistor TG13-Tr are formed on the right side of the first region FSAR20 in the figure (right half of the region).
The second transfer transistor TG11-Tr and the fourth transfer transistor TG13-Tr are formed in a triangular shape in plan view so as to be connected to the floating diffusion FD10 on the central region CTAR20 side.

In the shared pixel PXL20 of the first embodiment, the floating diffusion FD10 has a diffusion layer backbone FBS formed in a rectangular shape including a first side portion SDP1 and a second side portion SDP2 opposed to each other in a plan view. The backbone FBS has a branch portion FBR for forming the reset transistor RST10-Tr and the like, which extends in the X direction (to the right) from the center of the second side portion SDP2. In other words, the floating diffusion FD10 is formed in a substantially T-shape.
A source follower transistor SF10-Tr is arranged in a central portion CTR of the element formation region adjacent to a first direction (e.g., the X direction) perpendicular to a first side portion SDP1 of the floating diffusion FD10, and a reset transistor RST10-Tr is arranged adjacent to a second side portion SDP2 of the floating diffusion FD10 in the first direction.
The floating diffusion FD10 and the source follower transistor SF10-Tr are connected by a wire WR20.
Furthermore, a selection transistor SEL10-Tr is disposed adjacent to the source follower transistor SF10-Tr on the left side in the X direction.

Adjacent photodiodes in a second direction (e.g., the Y direction), i.e., the first photodiode PD10 and the second photodiode PD11, as well as the third photodiode PD12 and the fourth photodiode PD13, are arranged at a first distance D1 that allows for the formation of at least a source follower transistor SF10-Tr, a selection transistor SEL10-Tr, and a reset transistor SF10-Tr (MOS transistors).
Adjacent photoelectric conversion elements in the first direction (X direction), i.e., the first photodiode PD10 and the third photodiode PD12, as well as the second photodiode PD11 and the fourth photodiode PD13, are arranged at a second distance D2 (D1>D2) narrower than the first distance D1.

The first transfer transistor TG10-Tr is arranged (formed) to connect between a first side edge portion SDT11 (the upper left end portion of FD10 in FIG. 10) in the second direction (Y direction) of the first side portion SDP1 of the floating diffusion FD10 and a first edge portion ED111 (the lower right end portion of PD10 in FIG. 10) of the first photodiode PD10 that faces this first side edge portion SDT11.
That is, the first transfer transistor TG10-Tr is disposed so as to straddle between the first side edge portion SDT11 of the floating diffusion FD10 and the first edge portion ED111 of the corresponding photodiode PD10.

A second transfer transistor TG11-Tr is arranged (formed) so as to connect between a first side edge portion SDT12 (the lower left end portion of FD10 in FIG. 10) in the second direction (Y direction) of the first side portion SDP1 of the floating diffusion FD10 and a first edge portion ED112 (the upper right end portion of PD11 in FIG. 10) of the second photodiode PD11 facing the first side edge portion SDT12.
That is, the second transfer transistor TG11-Tr is disposed so as to straddle between the first side edge portion SDT12 of the floating diffusion FD10 and the first edge portion ED112 of the corresponding photodiode PD10.

A third transfer transistor TG12-Tr is arranged (formed) so as to connect between a second side edge portion SDT21 (the upper right end portion of FD10 in FIG. 10) in the second direction (Y direction) of the second side portion SDP2 of the floating diffusion FD10 and a first edge portion ED121 (the lower left end portion of PD12 in FIG. 10) of the third photodiode PD12 facing the second side edge portion SDT12.
That is, the third transfer transistor TG12-Tr is disposed so as to straddle between the second side edge portion SDT21 of the floating diffusion FD10 and the corresponding edge portion ED121 of the photodiode PD10.

A fourth transfer transistor TG13-Tr is arranged (formed) so as to connect between a second side edge portion SDT22 (the lower right end portion of FD10 in FIG. 10) in the second direction (Y direction) of the second side portion SDP2 of the floating diffusion FD10 and a first edge portion ED122 (the upper left end portion of PD13 in FIG. 10) of the fourth photodiode PD13 facing the second side edge portion SDT22.
That is, the fourth transfer transistor TG13-Tr is disposed so as to straddle between the second side edge portion SDT22 of the floating diffusion FD10 and the corresponding edge portion ED122 of the photodiode PD10.

FIG. 11 is a simplified cross-sectional view of a main part of a shared pixel according to the first embodiment, and is a diagram for explaining an additional capacitance component added to the capacitance of the floating diffusion.
Figure 12 is a simplified cross-sectional view of the main parts of a shared pixel that is a comparative example to the shared pixel of Figure 11 which does not have the characteristic configuration of the shared pixel of the first embodiment, and is a figure for explaining the additional capacitance component added to the capacitance of the floating diffusion.

As described above, according to the first embodiment, in the central portion CTR of the element formation region between the photodiodes PD10 and PD11 adjacent in the Y direction and the photodiodes PD12 and PD13, the source follower transistor SF10-Tr is arranged adjacent in a first direction (for example, the X direction) perpendicular to the first side portion SDP1 of the floating diffusion FD10, and the reset transistor RST10-Tr is arranged adjacent in the first direction to the second side portion SDP2 of the floating diffusion FD10. In addition, the selection transistor SEL10-Tr is arranged adjacent to the source follower transistor SF10-Tr on the left side in the X direction.
As shown in FIG. 11, the floating diffusion FD10 and the source follower transistor SF10-Tr are connected by a wiring WR20.

Therefore, according to the first embodiment, the wiring WR20 for connecting the floating diffusion FD10 and the gate of the source follower transistor SF10-Tr is significantly shorter than in the comparative example shown in FIG.
That is, in the comparative example shown in FIG. 12, the wiring length LMC of the wiring WR20c from the source follower transistor SF10-Tr and the reset transistor RST-Tr connected to the floating diffusion FD10 is significantly longer than the wiring length LPE in the arrangement configuration according to this embodiment shown in FIG.
Therefore, in the comparative example, the junction capacitance and the wiring capacitance for electrical connection increase, the capacitance of the FD node (Cfd) increases, the conversion gain decreases, and the noise characteristics deteriorate.
In the comparative example of Figure 12, examples of additional capacitance components include a junction capacitance C1 in the n+ diffusion layer 2015 that forms the floating diffusion FD, an inter-wiring capacitance C2 between the wiring WR20c and the photodiode PD, an inter-wiring capacitance C3 between the wiring WR20c and the isolation layer STI, a gate capacitance C4 of the source follower transistor SF-Tr, and a junction capacitance C5 in the n+ diffusion layer of the reset transistor RST-Tr.

In contrast, according to the layout configuration of the first embodiment, the wiring length LPE of the wiring WR20 from the source follower transistor SF10-Tr and the reset transistor RST-Tr connected to the floating diffusion FD10 is significantly shorter than the wiring length LMC in the comparative example shown in FIG.
Therefore, in this example, the junction capacitance and the wiring capacitance for electrical connection are reduced, the capacitance of the FD node (Cfd) is reduced, the conversion gain can be increased, and noise characteristics can be improved.
In the layout configuration of this embodiment in Figure 11, examples of additional capacitance components include a junction capacitance C11 in the n+ diffusion layer 2015 that forms the floating diffusion FD, an inter-wiring capacitance C12 between the wiring WR20 and the isolation layer STI, and a gate capacitance C13 of the source follower transistor SF10-Tr.

In the first embodiment, the semiconductor lasers are further arranged in a square shape (arranged radially) with the floating diffusion FD10 at the center.
The first photodiode PD10 and the second photodiode PD11, as well as the third photodiode PD12 and the fourth photodiode PD13, which are adjacent in the second direction (for example, the Y direction), are arranged at a first distance D1 that allows for the formation of at least a source follower transistor SF10-Tr, a selection transistor SEL10-Tr, and a reset transistor SF10-Tr (MOS transistors).
The first photodiode PD10 and the third photodiode PD12, as well as the second photodiode PD11 and the fourth photodiode PD13, which are adjacent to each other in the first direction (X direction), are arranged with a second distance D2 (D1>D2) narrower than the first distance D1.

Therefore, according to the first embodiment, it is possible to form the shape of the backbone FBS of the floating diffusion FD10 in a long and narrow rectangular shape, and it is possible to make the area of the floating diffusion FD10 as small as possible.
This has the advantage that the capacitance of the floating diffusion FD 10 can be reliably reduced, the conversion gain can be increased, and noise can be significantly reduced.
Furthermore, since the area of the floating diffusion FD 10 is reduced, it is possible to reliably achieve miniaturization of the pixel size.

Here, we show an example of a comparison by simulation of the floating diffusion FD node capacitance, wiring capacitance, their total capacitance, and pixel size in the layout of FIG. 10 of the solid-state imaging device 10 according to the first embodiment of the present invention, the layout of FIG. 4 as a first comparative example, and the layout of FIG. 5 as a second comparative example.

13A to 13C are diagrams showing the layout of a solid-state imaging device according to the first embodiment of the present invention, which is used for comparison of the FD node capacitance, wiring capacitance, and their total capacitance, as well as pixel size, a layout of a first comparative example, and a layout of a second comparative example.
FIG. 14 is a table comparing the FD node capacitance, wiring capacitance, their total capacitance, and pixel size in the layout of the solid-state imaging device according to the first embodiment of the present invention, the layout of the first comparative example, and the layout of the second comparative example.
In FIG. 13, FD W indicates the junction area of the floating diffusion FD, and W indicates the width of the inlet of the transfer transistors TG0-10.
In FIG. 14, the FD node capacitance NCAP, the wiring capacitance WCAP, and the total capacitance TCAP are shown in relative ratio with the capacitance of the present invention being set to 1.

According to a simulation, in the layout of the present invention, the node capacitance NCP of the floating diffusion FD is 0.5, the wiring capacitance WCAP is 0.5, and the total capacitance TCAP is 1. The pixel size PSZ is 1.5 μm.
In the first comparative example, the node capacitance NCP of the floating diffusion FD is 1, the wiring capacitance WCAP is 0.5, the total capacitance TCAP is 1.5, and the pixel size PSZ is 2 μm.
In the second comparative example, the node capacitance NCP of the floating diffusion FD is 0.5, the wiring capacitance WCAP is 1, and the total capacitance TCAP is 1.5. The pixel size PSZ is 1.5 μm.

As can be seen from this, according to the solid-state imaging device of the first embodiment, the junction area FDW of the floating diffusion FD can be significantly reduced compared to the first and second comparative examples, and therefore the FD node capacitance NCAP and the wiring capacitance WCAP can be reduced. This ensures that the total capacitance TCAP can be reduced, making it possible to increase the conversion gain and improve the noise characteristics.
Furthermore, since the area of the floating diffusion FD 10 is reduced, it is possible to reliably achieve miniaturization of the pixel size PSZ.

As described above, according to the first embodiment, pixel components can be shared among four pixels, and therefore the size of the photodiode PD per pixel can be maximized. This not only makes it possible to reduce the pixel size while maintaining the sensitivity and the number of saturation charges, but also simplifies the layout, significantly shortens the wiring WR20 for connecting the floating diffusion FD10 and the gate of the source follower transistor SF10-Tr, and makes it possible to form the floating diffusion FD10 sufficiently small, thereby making it possible to maintain a high conversion gain of the floating diffusion FD10.
In other words, according to the first embodiment, not only can it be possible to reduce the pixel size while maintaining the sensitivity and the number of saturation charges, but it is also possible to suppress an increase in the junction capacitance and the wiring capacitance, and to suppress an increase in the capacitance of the floating diffusion FD10 serving as the output node, thereby preventing a decrease in the conversion gain, and ultimately improving the noise characteristics.

Second Embodiment
FIG. 15 is a circuit diagram showing an example of a shared pixel of a solid-state imaging device according to the second embodiment of the present invention.
FIG. 16 is a simplified plan view showing an example of the arrangement of four photodiodes, a transfer transistor, one floating diffusion FD, a reset transistor, a source follower transistor, and a selection transistor of a shared pixel according to the second embodiment.

The shared pixel PXL20A of the solid-state imaging device 10A according to the second embodiment differs from the shared pixel PXL20 of the solid-state imaging device 10 according to the first embodiment described above in the following ways.

The shared pixel PXL20A of the solid-state imaging device 10A according to the second embodiment has shutter gate transistors SG10-Tr, SG11-Tr, SG12-Tr, and SG13-Tr that are connected between each storage section PND10, PND11, PND12, and PND13 of each photodiode PD10, PD11, PD12, and PD13 and a power supply line Vaapix of a power supply voltage VAAPIX and serve as a plurality of charge overflow gate elements that can cause charge to overflow from each photodiode PD10, PD11, PD12, and PD13 toward the floating diffusion region or toward the outside of the floating diffusion region.
The shutter gate transistors SG10-Tr, SG11-Tr, SG12-Tr, and SG13-Tr as charge overflow gate elements are arranged so as to connect to second edge portions ED211, ED212, ED221, and EED222 on the outer edge side spaced apart from first edge portions ED111, ED112, ED121, and ED122 in which the transfer transistors TG10-Tr, TG11-Tr, TG2-Tr, and TG13-Tr are arranged in each photodiode PD10, PD11, PD12, and PD13.

Specifically, a first transfer transistor TG10-Tr serving as a first transfer element is connected between the first photodiode PD10 and the floating diffusion FD10, and a first shutter gate transistor SG10-Tr serving as a first charge overflow gate element is connected between the first photodiode PD10 and a predetermined fixed potential VAAPIX.
As shown in FIG. 16, the first shutter gate transistor SG10-Tr is arranged so as to be connected to a second edge portion ED211 on the outer edge side of the first photodiode PD10, which is spaced apart from the first edge portion ED111 in which the first transfer transistor TG10-Tr is arranged.

A second transfer transistor TG11-Tr serving as a second transfer element is connected between the second photodiode PD11 and the floating diffusion FD10, and a second shutter gate transistor SG11-Tr serving as a second charge overflow gate element is connected between the second photodiode PD11 and a predetermined fixed potential VAAPIX.
As shown in FIG. 16, the second shutter gate transistor SG11-Tr is arranged so as to be connected to a second edge portion ED212 on the outer edge side of the second photodiode PD11, which is spaced apart from the first edge portion ED112 in which the second transfer transistor TG11-Tr is arranged.

A third transfer transistor TG12-Tr serving as a third transfer element is connected between the third photodiode PD12 and the floating diffusion FD10, and a third shutter gate transistor SG12-Tr serving as a third charge overflow gate element is connected between the third photodiode PD12 and a predetermined fixed potential VAAPIX.
As shown in FIG. 16, the third shutter gate transistor SG12-Tr is arranged so as to be connected to a second edge portion ED221 on the outer edge side of the third photodiode PD12, which is spaced apart from the first edge portion ED121 in which the third transfer transistor TG12-Tr is arranged.

A fourth transfer transistor TG13-Tr serving as a fourth transfer element is connected between the fourth photodiode PD13 and the floating diffusion FD10, and a fourth shutter gate transistor SG13-Tr serving as a fourth charge overflow gate element is connected between the fourth photodiode PD13 and a predetermined fixed potential VAAPIX.
As shown in FIG. 16, the fourth shutter gate transistor SG13-Tr is arranged so as to be connected to a second edge portion ED222 on the outer edge side of the fourth photodiode PD13, which is spaced apart from the first edge portion ED122 in which the fourth transfer transistor TG13-Tr is arranged.

As described above, the first shutter gate transistor SG10-Tr serving as the first charge overflow gate element is connected between the first photodiode PD10 and a predetermined fixed potential VAAPIX, and is controlled by a control signal SG10 applied through a control line.
The first shutter gate transistor SG10-Tr is selected and turned on during the period when the control signal SG10 is at H level, and forms a blooming path between the first photodiode PD10 and a predetermined fixed potential VAAPIX to discharge the charge generated in the first photodiode PD10 (forms an anti-blooming path toward the floating diffusion FD side), thereby discharging unnecessary charge to the fixed potential VAAPIX.

In this way, the first transfer transistor TG10-Tr and the first shutter gate transistor SG10-Tr are driven and controlled at separate timings.

The first transfer transistor TG10-Tr is connected to the first photodiode PD1 and the floating diffusion FD10, and is controlled by a control signal TG10 applied to the gate through a control line.
The first transfer transistor TG10-Tr is selected and turned on during the transfer period PT when the control signal TG10 is at a high (H) level, and transfers the charges (electrons) photoelectrically converted and accumulated in the first photodiode PD10 to the floating diffusion FD10.
After the first photodiode PD10 and the floating diffusion FD10 are reset to a predetermined reset potential, the first transfer transistor TG10-Tr becomes non-conductive with the control signal TG10 at a low (L) level, and the first photodiode PD10 enters the accumulation period PI. At this time, if the intensity (amount) of the incident light is extremely high, charges that exceed the saturation charge amount overflow into the fixed potential VAAPIX as overflow charges through the overflow path below the first shutter gate transistor SG10-Tr.

The second shutter gate transistor SG11-Tr serving as a second charge overflow gate element is connected between the second photodiode PD11 and a predetermined fixed potential VAAPIX, and is controlled by a control signal SG11 applied through a control line.
The second shutter gate transistor SG11-Tr is selected and turned on during the period when the control signal SG11 is at H level, and forms a blooming path between the second photodiode PD11 and a predetermined fixed potential VAAPIX to discharge the charge generated in the second photodiode PD11 (forms an anti-blooming path toward the floating diffusion FD side), thereby discharging unnecessary charge to the fixed potential VAAPIX.

In this manner, the second transfer transistor TG11-Tr and the second shutter gate transistor SG11-Tr are driven and controlled at separate timings.
After the second photodiode PD11 and the floating diffusion FD10 are reset to a predetermined reset potential, the second transfer transistor TG11-Tr becomes non-conductive with the control signal TG11 at the low (L) level, and the second photodiode PD11 enters the accumulation period PI. At this time, if the intensity (amount) of the incident light is extremely high, charges that exceed the saturation charge amount overflow into the fixed potential VAAPIX as overflow charges through the overflow path below the second shutter gate transistor SG11-Tr.

The third shutter gate transistor SG12-Tr serving as a third charge overflow gate element is connected between the third photodiode PD12 and a predetermined fixed potential VAAPIX, and is controlled by a control signal SG12 applied through a control line.
The third shutter gate transistor SG12-Tr is selected and turned on during the period when the control signal SG12 is at H level, and forms a blooming path between the third photodiode PD12 and a predetermined fixed potential VAAPIX for discharging the charge generated in the third photodiode PD12 (forms an anti-blooming path toward the floating diffusion FD side), thereby discharging unnecessary charge to the fixed potential VAAPIX.

In this manner, the third transfer transistor TG12-Tr and the third shutter gate transistor SG12-Tr are driven and controlled at separate timings.
After the third photodiode PD12 and the floating diffusion FD10 are reset to a predetermined reset potential, the third transfer transistor TG12-Tr becomes non-conductive with the control signal TG12 at a low (L) level, and the third photodiode PD12 enters the accumulation period PI. At this time, if the intensity (amount) of the incident light is extremely high, charges that exceed the saturation charge amount overflow into the fixed potential VAAPIX as overflow charges through the overflow path below the third shutter gate transistor SG12-Tr.

The fourth shutter gate transistor SG13-Tr serving as a fourth charge overflow gate element is connected between the fourth photodiode PD13 and a predetermined fixed potential VAAPIX, and is controlled by a control signal SG13 applied through a control line.
The fourth shutter gate transistor SG13-Tr is selected and turned on during the period when the control signal SG13 is at H level, and forms a blooming path between the fourth photodiode PD13 and a predetermined fixed potential VAAPIX to discharge the charge generated in the fourth photodiode PD13 (forms an anti-blooming path toward the floating diffusion FD side), thereby discharging unnecessary charge to the fixed potential VAAPIX.

In this manner, the fourth transfer transistor TG13-Tr and the fourth shutter gate transistor SG13-Tr are driven and controlled at individual timings.
After the fourth photodiode PD13 and the floating diffusion FD10 are reset to a predetermined reset potential, the fourth transfer transistor TG13-Tr becomes non-conductive with the control signal TG13 at a low (L) level, and the fourth photodiode PD12 enters the accumulation period PI. At this time, if the intensity (amount) of the incident light is extremely high, charges that exceed the saturation charge amount overflow into the fixed potential VAAPIX as overflow charges through the overflow path below the fourth shutter gate transistor SG13-Tr.

The first shutter gate transistor SG10-Tr as the first charge overflow gate element, the second shutter gate transistor SG11-Tr as the second charge overflow element, the third shutter gate transistor SG12-Tr as the third charge overflow element, and the fourth shutter gate transistor SG13-Tr as the fourth charge overflow element may each have an individually adjusted threshold.

Figure 17 is a simplified cross-sectional view showing an example of the configuration of a charge accumulation and transfer system having a shutter gate transistor, which is a main part of a shared pixel according to the second embodiment of the present invention.

The configuration in Figure 17 differs from the configuration in Figure 9 in that it has a shutter gate transistor configuration.

(Configuration of Separation Layer in X-Direction (Column Direction))
An n+ layer 2105 that becomes a floating diffusion FD is formed on the second substrate surface 1102 side of the p-type isolation layer 2104 (SPL1) on the right side in the X direction (column direction) of FIG.
An n+ layer 2108 that will become the drain of the shutter gate transistor TSG0-Tr is formed on the second substrate surface 1102 side of the p-type isolation layer 2106 (SPL2) on the left side in the X direction (column direction) of FIG.
A gate electrode 2107 of the first transfer transistor TG0-Tr is formed on the epitaxial layer (p-epi) 2101R on the second substrate surface 1102 side via a gate insulating film.
An overflow path OVP extending from the first photodiode PD10 to the floating diffusion FD10 is formed below the first transfer transistor TG10-Tr.
The potential of the overflow path OVP can also be controlled by gate control, for example.

On the other hand, a gate electrode 2109 of the first shutter gate transistor SG10-Tr is formed on the epitaxial layer (p-epi) 2101L on the second substrate surface 1102 side via a gate insulating film.
A blooming path EFP that discharges charges generated in the first photodiode PD10 from the photodiode PD10 to the n+ layer 2108 is formed under the first shutter gate transistor SG10-Tr (an anti-blooming path toward the floating diffusion FD side is formed).

In such a structure, when the intensity (amount) of incident light is very high, charge that exceeds the saturation charge amount overflows into the floating diffusion FD as overflow charge through the overflow path OVP below the first transfer transistor TG10-Tr.

Furthermore, if, for example, irregular strong light is incident on the first photodiode PD10 during comparison processing such as AD conversion, charge will overflow from the photodiode PD10 to the floating diffusion FD10, causing the level of the floating diffusion FD10, which is the output node, to fluctuate, which may make it impossible to achieve normal AD conversion processing.
Therefore, in this embodiment, even if irregular strong light is incident on the first photodiode PD10 during the comparison process, for example, a first shutter gate transistor SG10-Tr is provided which discharges unnecessary charges from the first photodiode PD10 to outside the floating diffusion FD10 region, thereby preventing charges from overflowing from the first photodiode PD10 to the floating diffusion FD10 and causing the FD level to fluctuate.
This prevents the FD level from fluctuating even if irregular strong light is incident on the first photodiode PD10 during comparison processing such as AD conversion, making it possible to achieve normal AD conversion processing.
The same applies to the remaining photodiodes PD11, PD12, and PD13.

As described above, according to the second embodiment, the device has shutter gate transistors SG10-Tr, SG11-Tr, SG12-Tr, and SG13-Tr that are connected between each storage section of each photodiode PD10, PD11, PD12, and PD13 and the power supply line Vaapix of the power supply voltage VAAPIX, and serve as a plurality of charge overflow gate elements that can cause charge to overflow from the photodiode PD toward the floating diffusion region or toward the outside of the floating diffusion region.
Therefore, according to the second embodiment, in addition to the same effects as those of the first embodiment described above, the following effects can be obtained.

In other words, according to the second embodiment, it is possible to prevent a signal (overflow charge) that exceeds the accumulated charge of a given photodiode PD from flowing into an adjacent pixel and causing charge mixing (resulting in a false signal).

Third Embodiment
FIG. 18 is a circuit diagram showing an example of a shared pixel of a solid-state imaging device according to the third embodiment of the present invention.
FIG. 19 is a simplified plan view showing an example of the arrangement of four photodiodes, a transfer transistor, one floating diffusion FD, a reset transistor, a source follower transistor, and a selection transistor of a shared pixel according to the third embodiment.

The shared pixel PXL20B of the solid-state imaging device 10B according to the third embodiment realizes a dual gain configuration, which is easier to configure as a result of the solid-state imaging devices 10 and 10A according to the first and second embodiments being able to reduce the capacitance of the floating diffusion FD10.
The shared pixel PXL20B of the solid-state imaging device 10B according to the third embodiment differs from the shared pixel PXL20A of the solid-state imaging device 10A according to the second embodiment described above in the following respects.

The shared pixel PXL20B of the third embodiment is provided with a gain switching section 210 that switches the conversion gain of the source follower transistor SF10-Tr as an output buffer section.
The gain switching unit 210 is configured to be able to change the amount of charge of the floating diffusion FD10 as the output node to a first capacitance or a second capacitance, and to switch the conversion gain of the source follower transistor SF10-Tr as the output buffer unit to a first conversion gain (for example, high conversion gain: HCG) determined by the first capacitance or a second conversion gain (for example, low conversion gain: LCG) determined by the second capacitance. Note that in the third embodiment, the first conversion gain and the second conversion gain are used depending on the amount of charge read out in so-called two-time readout.

The gain switching unit 210 includes a storage transistor BIN10-Tr as a storage element connected to the floating diffusion FD10, and a storage capacitor CS1 as a storage capacitance element that stores the charge of the floating diffusion FD10 via the storage transistor BIN10-Tr.

The storage transistor BIN10-Tr is connected between the floating diffusion FD10 and the reset transistor RST10-Tr, and a storage capacitor CS is connected between a connection node ND12 thereof and the reference potential VSS.
The storage transistor BIN10-Tr is controlled by a control signal BIN10 applied to its gate through a control line.
The storage transistor BIN10-Tr is selected during the reset period when the control signal BIN10 is at H level and is turned on, connecting the floating diffusion FD10 and the storage capacitor CS1.

In the third embodiment, the storage transistor BIN10-Tr is disposed between the floating diffusion FD10 and the reset transistor RST10-Tr in the central region CTAR20 of the element formation region, as shown in FIG. 19.

In the third embodiment, the readout process involving gain conversion is performed as follows.
During the first conversion gain read process HCGSRD, the storage transistor BIN10-Tr is held in a non-conductive state, and the charge of the floating diffusion FD10, which is the output node ND10, and the charge of the storage capacitor CS are separated to execute the read process.
During the first conversion gain reset read process HCGRRD, the storage transistor BIN10-Tr is held in a non-conductive state, and the charge of the floating diffusion FD10, which is the output node ND10, and the charge of the storage capacitor CS are separated to execute the read process.
During the second conversion gain read process LCGSRD, the storage transistor BIN10-Tr is held in a conductive state, and the read process is executed by sharing the charge of the floating diffusion FD10, which is the output node ND10, and the charge of the storage capacitor CS.
During the second conversion gain reset read process LCGRRD, the reset transistor RST120-Tr and the storage transistor BIN10-Tr are held in a conductive state, and the charge of the floating diffusion FD10, which is the output node ND10, and the charge of the storage capacitor CS are cleared to execute the read process.

In this manner, in the third embodiment, a gain switching section 210 is provided which has a storage transistor BIN10-Tr and a storage capacitor CS, and which can change the amount of charge of the floating diffusion FD10 as the output node to a first capacitance or a second capacitance, thereby switching the conversion gain of the source follower transistor SF10-Tr as the output buffer section to a first conversion gain determined by the first capacitance (e.g., high conversion gain: HCG) or a second conversion gain determined by the second capacitance (e.g., low conversion gain: LCG).
As a result, the full well capacity (FWC) is small during high conversion gain (HCG), and the full well capacity (FWC) is large during low conversion gain (LCG).

Here, we will explain an example of a readout sequence for a shared pixel in a solid-state imaging device according to the third embodiment.

Figures 20(A) to (J) are timing charts for explaining an example of a readout sequence in a readout mode for a shared pixel in a solid-state imaging device according to the third embodiment of the present invention.

Figure 20 (A) shows the control signal TG10 of the first transfer transistor TG10-Tr, which is the object of access in the read mode, Figure 20 (B) shows the control signal SG10 of the first shutter gate transistor SG10-Tr, Figure 20 (C) shows the control signal TG11 of the second transfer transistor TG11-Tr, which is the object of access in the read mode, Figure 20 (D) shows the control signal SG11 of the second shutter gate transistor SG11-Tr, and Figure 20 (E) shows the control signal TG12 of the third transfer transistor TG12, which is the object of access in the read mode. -Tr control signal TG12, Figure 20 (F) shows the control signal SG12 of the third shutter gate transistor SG12-Tr, Figure 20 (G) shows the control signal TG13 of the fourth transfer transistor TG13-Tr that is the access target in the read mode, Figure 20 (H) shows the control signal SG13 of the fourth shutter gate transistor SG13-Tr, Figure 20 (I) shows the control signal BIN10 of the storage transistor BIN10-Tr, and Figure 20 (J) shows the control signal RST10 of the reset transistor RST10-Tr.

In the read mode RMD, the control signals TG10, TG11, TG12, and TG13 are set to a low level to hold the transfer transistors TG10-Tr, TG11-Tr, TG12-Tr, and TG13-Tr in a non-conductive state, and the control signals SG10, SG11, SG12, and SG13 are switched from a high level to a low level to switch the shutter gate transistors SG10-Tr, SG11-Tr, SG12-Tr, and SG13-Tr from a conductive state to a non-conductive state.
The exposure time starts at the timing when the shutter gate transistors SG10-Tr, SG11-Tr, SG12-Tr, and SG13-Tr are switched from the conductive state to the non-conductive state.
In addition, the control signal RST10 is set to a high level for a predetermined period to hold the reset transistor RST10-Tr in a conductive state, and the control signal BIN10 is set to a high level for a predetermined period to hold the storage transistor BIN10-Tr in a conductive state, thereby maintaining the reset state of the floating diffusion FD10, which is the output node ND10 during the reset period RP.

First, the charge stored in the first photodiode PD10 is read out.
In this case, the control signal RST10 and the control signal BIN10 are set to a high level to reset the floating diffusion FD10 which is the output node ND10.
Then, the control signal BIN10 is maintained at a high level for a predetermined period of time to hold the storage transistor BIN10-Tr in a conductive state, and the charge of the floating diffusion FD10 which is the output node ND10 is shared with the charge of the storage capacitor CS which is a storage capacitance element, and the amount of charge of the floating diffusion FD10 is held in the second capacitance. This makes it possible to execute the second conversion gain reset read process LCGRRD.
In this state, during the reset read period PRRD after the reset period PR, a read reset signal LCGVRST converted with a second conversion gain determined by the second capacitance of the floating diffusion FD10 as the output node ND10 is read out from the source follower transistor SF10-Tr as an output buffer, and a second conversion gain reset read process LCGRRD is performed to process this read reset signal LCGVRST.

Next, the control signal BIN10 is switched to a low level, the storage transistor BIN10-Tr is held in a non-conductive state, and the charge 10 of the floating diffusion FD, which is the output node ND10, is separated from the charge of the storage capacitor CS, which is a storage capacitance element, and the charge amount of the floating diffusion FD10 is held in the first capacitance. This makes it possible to execute the first conversion gain reset read process HCGRRD.
In this state, during a further reset read period PRRD following the reset period PR, a read reset signal HCGVRST converted with a first conversion gain (high conversion gain: HCG) determined by the first capacitance of the floating diffusion FD10 as the output node ND10 is read out from the source follower transistor SF10-Tr as an output buffer, and a first conversion gain reset read process HCGRRD is performed to process this read reset signal HCGVRST.

Furthermore, after the reset readout period PPRD, the control signal TG10 is set to a high level for a predetermined period, and the charge stored in the photodiode PD10 is transferred to the floating diffusion FD10 during this first transfer period PT1.
Then, during a first read period PRD1 following the first transfer period PT1, a read signal HCGVSIG converted with a first conversion gain determined by the first capacitance of the floating diffusion FD10 serving as the output node ND10 is read out from the source follower transistor SF10-Tr serving as an output buffer, and a first conversion gain read process HCGSRD is performed to process this read signal HCGVSIG.

Furthermore, after the first read period PRD1, the control signal BIN10 is switched to a high level, the storage transistor BIN10-Tr is held in a conductive state, the charge of the floating diffusion FD10 which is the output node ND10 is shared with the charge of the storage capacitor CS which is a storage capacitance element, and the amount of charge of the floating diffusion FD10 is held in the second capacitance. This makes it possible to execute the second conversion gain reset read process LCGRRD.
In this state, after the first readout period PRD1, the control signal TG0 is set to a high level for a predetermined period, and the accumulated charge in the photodiode PD10 is transferred to the floating diffusion FD10 during the second transfer period PT2.
Then, after the second transfer period PT2, the control signal SG10 is switched to a high level to hold the first shutter gate transistor SG10-Tr in a conductive state, and during the subsequent second readout period PRD2, a readout signal LCGVSIG converted with a second conversion gain determined by the second capacitance of the floating diffusion FD10 as the output node ND10 is read out from the source follower transistor SF10-Tr as an output buffer, and a second conversion gain readout process LCGSRD is performed to process this readout signal LCGVSIG.

In this way, when the readout process for the accumulated charge in the first photodiode PD10 is completed, the readout process for the accumulated charge in the second photodiode PD11 is subsequently carried out.
In this case, with the control signal BIN10 held at a high level, the control signal RST10 is set to a high level for a predetermined period to hold the reset transistor RST10-Tr in a conductive state, and the reset state of the floating diffusion FD10, which is the output node ND10 during the reset period PR, is maintained.
Thereafter, the same process as that for the accumulated charge in the first photodiode PD10 described above is sequentially performed on the accumulated charges in the second photodiode PD11, the third photodiode PD12, and the fourth photodiode PD13.
Therefore, a detailed description thereof will be omitted here.

According to the third embodiment, it is possible to expand the dynamic range with a small pixel size by using a predetermined readout mode.
Moreover, according to the third embodiment, it is possible to realize a substantially wide dynamic range and a high frame rate, while also achieving low noise and maximizing the effective pixel area, thereby maximizing value per cost.

Fourth Embodiment
FIG. 21 is a circuit diagram showing an example of the configuration of a shared pixel in a solid-state imaging device 10C according to the fourth embodiment of the present invention.

In this fourth embodiment, the solid-state imaging device 10C includes a photoelectric conversion readout section 220 and a signal holding section 230 as unit pixels PXLC in the pixel section 20C, has a global shutter operation function, and is configured as, for example, a stacked CMOS image sensor that can substantially achieve a wide dynamic range and a high frame rate.

In such a stacked structure, the read node ND11 of each photoelectric conversion readout unit 220 of the pixel array of the first substrate 110 and the input node ND20 of the signal holding unit 230 of each shared pixel PXL20C of the second substrate 120 are electrically connected using via microbumps BMP or die-to-die vias, for example, as shown in FIG. 21.

In the solid-state imaging device 10C according to the fourth embodiment, as described in detail later, the pixel signals are sampled simultaneously and in parallel for all pixels in a voltage mode in a signal holding section serving as pixel signal storage, and conversion signals corresponding to the readout signals held in the first to eighth signal holding capacitors are read out to a specified signal line, and a conversion signal corresponding to the readout reset signal is read out simultaneously and in parallel to a specified signal line and supplied to the column readout circuit 40.

The configuration and function of pixel section 20C of solid-state imaging device 10C are described below.

(Configuration of unit pixel PXLC and pixel section 20C)
As shown in FIG. 21, the shared pixel PXL20C arranged in the pixel section 20C includes a photoelectric conversion readout section 220 and a signal holding section 230.
The pixel section 20C of the fourth embodiment is configured as a stacked CMOS image sensor of a first substrate 110 and a second substrate 120, but in this example, as shown in FIG. 21 , a photoelectric conversion readout section 220 is formed on the first substrate 110, and a signal holding section 230 is formed on the second substrate 120.

The photoelectric conversion readout unit 220 includes a photodiode (photoelectric conversion element) and an in-pixel amplifier.
In the example of FIG. 21, the photoelectric conversion readout section 220 employs, as an example, a modified example of the shared pixel PXL20B according to the third embodiment of FIG.

Specifically, the photoelectric conversion readout unit 220 differs from the shared pixel PXL20B in FIG. 18 in the following respects.
In the present photoelectric conversion readout section 220, an output buffer section 221 is configured including a source follower transistor SF10-Tr, a current transistor IC10-Tr, and a readout node ND11.
That is, in the photoelectric conversion readout section 220, a current transistor IC10-Tr is provided in place of the selection transistor SEL10-Tr of the shared pixel PXL20B in FIG.
The drain and source of a current transistor IC10-Tr serving as a current source element are connected between the read node ND11 and a reference potential VSS (for example, GND). The gate of the current transistor IC10-Tr is connected to a supply line of a control signal VBNPIX.
A signal line LSGN10 between the read node ND11 and the input of the signal holding section 230 is driven by a current transistor IC10-Tr as a current source element.

In the photoelectric conversion readout section 220 according to the fourth embodiment, a readout node ND 11 of an output buffer section 221 is connected to an input section of a signal holding section 230 .
The photoelectric conversion readout section 220 converts the charge of the floating diffusion FD 10 serving as the output node ND 10 into a voltage signal according to the amount of charge, and outputs the converted voltage signal VSL to the signal holding section 230 .

Furthermore, the photoelectric conversion readout section 220 outputs a voltage signal VSL according to the accumulated charges of the photodiodes PD10, PD11, PD12, and PD14 transferred to the floating diffusion FD10 as an output node during a transfer period PT after the accumulation period PI.
The photoelectric conversion readout unit 220 outputs a readout reset signal (signal voltage) (VRST) and a readout signal (signal voltage) (VSIG) as pixel signals to the signal holding unit 230.

The signal holding section 230 of pixel 200C basically includes an input section 231 including an input node ND20, a sample hold section 232, a first output section 233, a second output section 234, a third output section 235, a fourth output section 236, a fifth output section 237, a sixth output section 238, a seventh output section 239, an eighth output section 240, and holding nodes ND21, ND22, ND23, ND24, ND25, ND26, ND27, and ND28.

The input unit 231 is connected to the read node ND11 of the photoelectric conversion read unit 220 via the signal line LSGN10, and inputs the read signal (VSIG1) and read reset signal (VRST1) output from the read node ND11 to the sample hold unit 232.

The sample hold unit 232 includes a first sampling transistor SHR1-Tr as a first switch element, a second sampling transistor SHS1-Tr as a second switch element, a third sampling transistor SHR2-Tr as a third switch element, a fourth sampling transistor SHS2-Tr as a fourth switch element,
It is configured to include a fifth sampling transistor SHR3-Tr as a fifth switch element, a sixth sampling transistor SHS3-Tr as a sixth switch element, a fourth sampling transistor SHR4-Tr as a seventh switch element, and an eighth sampling transistor SHS4-Tr as an eighth switch element.
Furthermore, the sample hold section 232 is configured to include a first signal holding capacitor CR21, a second signal holding capacitor CS21, a third signal holding capacitor CR22, a fourth signal holding capacitor CS22, a fifth signal holding capacitor CR23, a sixth signal holding capacitor CS23, a seventh signal holding capacitor CR24, and an eighth signal holding capacitor CS24.

The first sampling transistor SHR1-Tr is connected between an input node ND20 connected to a signal line LSGN10 and a hold node ND21.
The first sampling transistor SHR1-Tr selectively connects the first signal holding capacitor CR21 of the sample hold unit 232 to the read node ND11 of the photoelectric conversion readout unit 220 via the hold node ND21 during a global shutter period or a clear period of the signal holding capacitor.
The first sampling transistor SHR1-Tr is in a conductive state, for example, while the control signal SHR1 is at a high level.
The first signal holding capacitor CR21 is connected between the holding node ND21 and the reference potential VSS.

The second sampling transistor SHS1-Tr is connected between an input node ND20 connected to a signal line LSGN10 and a hold node ND22.
The second sampling transistor SHS1-Tr selectively connects the second signal holding capacitor CS21 of the sample hold unit 232 to the read node ND11 of the photoelectric conversion readout unit 220 via the hold node ND22 during the global shutter period or the clear period of the signal holding capacitor.
The second sampling transistor SHS1-Tr is in a conductive state, for example, while the control signal SHS1 is at a high level.
The second signal holding capacitor CS21 is connected between the holding node ND22 and the reference potential VSS.

The third sampling transistor SHR2-Tr is connected between an input node ND20 connected to the signal line LSGN10 and a hold node ND23.
The third sampling transistor SHR2-Tr selectively connects the third signal holding capacitor CR22 of the sample hold unit 232 to the read node ND11 of the photoelectric conversion readout unit 220 via the hold node ND23 during the global shutter period or the clear period of the signal holding capacitor.
The third sampling transistor SHR2-Tr is in a conductive state, for example, while the control signal SHR2 is at a high level.
The third signal holding capacitor CR22 is connected between the holding node ND23 and the reference potential VSS.

The fourth sampling transistor SHS2-Tr is connected between an input node ND20 connected to the signal line LSGN10 and a hold node ND24.
The fourth sampling transistor SHS2-Tr selectively connects the fourth signal holding capacitor CS22 of the sample hold unit 232 to the read node ND112 of the photoelectric conversion readout unit 220 via the hold node ND24 during the global shutter period or the clear period of the signal holding capacitor.
The fourth sampling transistor SHS2-Tr is in a conductive state, for example, while the control signal SHS2 is at a high level.
The fourth signal holding capacitor CS22 is connected between the holding node ND24 and the reference potential VSS.

The fifth sampling transistor SHR3-Tr is connected between an input node ND20 connected to the signal line LSGN10 and a hold node ND25.
The fifth sampling transistor SHR3-Tr selectively connects the fifth signal holding capacitor CR23 of the sample hold unit 232 to the read node ND11 of the photoelectric conversion readout unit 220 via the hold node ND25 during the global shutter period or the clear period of the signal holding capacitor.
The fifth sampling transistor SHR3-Tr is in a conductive state, for example, while the control signal SHR3 is at a high level.
The fifth signal holding capacitor CR23 is connected between the holding node ND25 and the reference potential VSS.

The sixth sampling transistor SHS3-Tr is connected between an input node ND20 connected to the signal line LSGN10 and a hold node ND26.
The sixth sampling transistor SHS3-Tr selectively connects the sixth signal holding capacitor CS23 of the sample hold unit 232 to the read node ND11 of the photoelectric conversion readout unit 220 via the hold node ND26 during the global shutter period or the clear period of the signal holding capacitor.
The sixth sampling transistor SHS3-Tr is in a conductive state, for example, while the control signal SHS3 is at a high level.
The sixth signal holding capacitor CS23 is connected between the holding node ND26 and the reference potential VSS.

The seventh sampling transistor SHR4-Tr is connected between an input node ND20 connected to the signal line LSGN10 and a hold node ND27.
The seventh sampling transistor SHR4-Tr selectively connects the third signal holding capacitor CR24 of the sample hold unit 232 to the read node ND11 of the photoelectric conversion readout unit 220 via the hold node ND27 during the global shutter period or the clear period of the signal holding capacitor.
The third sampling transistor SHR4-Tr is in a conductive state, for example, while the control signal SHR4 is at a high level.
The seventh signal holding capacitor CR24 is connected between the holding node ND27 and the reference potential VSS.

The eighth sampling transistor SHS4-Tr is connected between an input node ND20 connected to the signal line LSGN10 and a hold node ND28.
The eighth sampling transistor SHS4-Tr selectively connects the eighth signal holding capacitor CS24 of the sample and hold unit 232 to the read node ND112 of the photoelectric conversion readout unit 220 via the hold node ND28 during the global shutter period or the signal holding capacitor clear period.
The eighth sampling transistor SHS4-Tr is in a conductive state, for example, while the control signal SHS4 is at a high level.
The eighth signal holding capacitor CS24 is connected between the holding node ND28 and the reference potential VSS.

The first sampling transistor SHR1-Tr, the second sampling transistor SHS1-Tr, the third sampling transistor SHR2-Tr, the fourth sampling transistor SHS2-Tr, the fifth sampling transistor SHR3-Tr, the sixth sampling transistor SHS3-Tr, the seventh sampling transistor SHR4-Tr, and the eighth sampling transistor SHS4-Tr are formed of MOS transistors, for example, p-channel MOS (PMOS) transistors.

The first output section 233 includes a source follower transistor SF2R-Tr as a second source follower element that basically outputs the signal held in the first signal holding capacitor CR21 in accordance with the holding voltage during the global shutter period, and selectively outputs the held signal to the vertical signal line LSGN11 via the selection transistor SEL1R-Tr.

The source follower transistor SF2R-Tr and the selection transistor SEL1R-Tr are connected in series between the reference potential VSS and the vertical signal line LSGN11.

The gate of the source follower transistor SF2R-Tr is connected to the hold node ND21, and the selection transistor SEL1R-Tr is controlled by a control signal SEL1 applied to the gate through a control line.
The selection transistor SEL1R-Tr is selected and turned on during a selection period when the control signal SEL1 is at the L level, so that the source follower transistor SF2R-Tr outputs a column output read voltage (VRST) corresponding to the voltage held by the first signal holding capacitor CR21 to the vertical signal line LSGN11.

The second output section 234 includes a source follower transistor SF3S-Tr as a third source follower element that basically outputs the signal held in the second signal holding capacitor CS21 in accordance with the holding voltage during the global shutter period, and selectively outputs the held signal to the vertical signal line LSGN12 via the selection transistor SEL2S-Tr.

The source follower transistor SF3S-Tr and the selection transistor SEL2S-Tr are connected in series between the reference potential VSS and the vertical signal line LSGN12.

A hold node ND22 is connected to the gate of the source follower transistor SF3S-Tr, and the selection transistor SEL2S-Tr is controlled by a control signal SEL2 applied to the gate through a control line.
The selection transistor SEL2S-Tr is selected and turned on during a selection period when the control signal SEL2 is at the L level, so that the source follower transistor SF3S-Tr outputs a column output read voltage (VSIG) corresponding to the voltage held by the second signal holding capacitor CS21 to the vertical signal line LSGN12.

The third output section 235 includes a source follower transistor SF4R-Tr as a fourth source follower element that basically outputs the signal held in the third signal holding capacitor CR22 in accordance with the holding voltage during the global shutter period, and selectively outputs the held signal to the vertical signal line LSGN11 via the selection transistor SEL3R-Tr.

The source follower transistor SF4R-Tr and the selection transistor SEL3R-Tr are connected in series between the reference potential VSS and the vertical signal line LSGN11.

The gate of the source follower transistor SF4R-Tr is connected to the hold node ND23, and the selection transistor SEL3R-Tr is controlled by a control signal SEL3 applied to the gate through a control line.
The selection transistor SEL3R-Tr is selected and turned on during a selection period when the control signal SEL3 is at the L level, so that the source follower transistor SF4R-Tr outputs a column output read voltage (VRST) corresponding to the voltage held by the third signal holding capacitor CR22 to the vertical signal line LSGN11.

The fourth output section 236 includes a source follower transistor SF5S-Tr as a fifth source follower element that basically outputs the signal held in the fourth signal holding capacitor CS22 in response to the holding voltage during the global shutter period, and selectively outputs the held signal to the vertical signal line LSGN12 via the selection transistor SEL4S-Tr.

The source follower transistor SF5S-Tr and the selection transistor SEL4S-Tr are connected in series between the reference potential VSS and the vertical signal line LSGN12.

A hold node ND24 is connected to the gate of the source follower transistor SF5S-Tr, and the selection transistor SEL4S-Tr is controlled by a control signal SEL4 applied to the gate through a control line.
The selection transistor SEL4S-Tr is selected and turned on during a selection period when the control signal SEL4 is at the L level, so that the source follower transistor SF5S-Tr outputs a column output read voltage (VSIG) corresponding to the voltage held by the fourth signal holding capacitor CS22 to the vertical signal line LSGN12.

The fifth output section 237 includes a source follower transistor SF6R-Tr as a sixth source follower element that basically outputs the signal held in the fifth signal holding capacitor CR23 in accordance with the holding voltage during the global shutter period, and selectively outputs the held signal to the vertical signal line LSGN11 via the selection transistor SEL5R-Tr.

The source follower transistor SF6R-Tr and the selection transistor SEL5R-Tr are connected in series between the reference potential VSS and the vertical signal line LSGN11.

The gate of the source follower transistor SF6R-Tr is connected to the hold node ND25, and the selection transistor SEL5R-Tr is controlled by a control signal SEL5 applied to the gate through a control line.
The selection transistor SEL5R-Tr is selected and turned on during a selection period when the control signal SEL5 is at the L level, so that the source follower transistor SF6R-Tr outputs a column output read voltage (VRST) corresponding to the voltage held by the fifth signal holding capacitor CR23 to the vertical signal line LSGN11.

The sixth output section 238 includes a source follower transistor SF7S-Tr as a seventh source follower element that basically outputs the signal held in the sixth signal holding capacitor CS23 in accordance with the holding voltage during the global shutter period, and selectively outputs the held signal to the vertical signal line LSGN12 via the selection transistor SEL6S-Tr.

The source follower transistor SF7S-Tr and the selection transistor SEL6S-Tr are connected in series between the reference potential VSS and the vertical signal line LSGN12.

The gate of the source follower transistor SF37-Tr is connected to the hold node ND26, and the selection transistor SEL6S-Tr is controlled by a control signal SEL6 applied to the gate through a control line.
The selection transistor SEL6S-Tr is selected and turned on during a selection period when the control signal SEL6 is at the L level, so that the source follower transistor SF7S-Tr outputs a column output read voltage (VSIG) corresponding to the voltage held by the second signal holding capacitor CS23 to the vertical signal line LSGN12.

The seventh output section 239 includes a source follower transistor SF8R-Tr as an eighth source follower element that basically outputs the signal held in the seventh signal holding capacitor CR24 in accordance with the holding voltage during the global shutter period, and selectively outputs the held signal to the vertical signal line LSGN11 via the selection transistor SEL7R-Tr.

The source follower transistor SF8R-Tr and the selection transistor SEL7R-Tr are connected in series between the reference potential VSS and the vertical signal line LSGN11.

A hold node ND27 is connected to the gate of the source follower transistor SF8R-Tr, and the selection transistor SEL7R-Tr is controlled by a control signal SEL7 applied to the gate through a control line.
The selection transistor SEL7R-Tr is selected and turned on during a selection period when the control signal SEL7 is at the L level, so that the source follower transistor SF8R-Tr outputs a column output read voltage (VRST) corresponding to the voltage held by the seventh signal holding capacitor CR24 to the vertical signal line LSGN11.

The eighth output section 240 includes a source follower transistor SF9S-Tr as a ninth source follower element that basically outputs the signal held in the eighth signal holding capacitor CS24 in accordance with the holding voltage during the global shutter period, and selectively outputs the held signal to the vertical signal line LSGN12 via the selection transistor SEL8S-Tr.

The source follower transistor SF9S-Tr and the selection transistor SEL8S-Tr are connected in series between the reference potential VSS and the vertical signal line LSGN12.

The gate of the source follower transistor SF9S-Tr is connected to the hold node ND28, and the selection transistor SEL8S-Tr is controlled by a control signal SEL8 applied to the gate through a control line.
The selection transistor SEL8S-Tr is selected and turned on during a selection period when the control signal SEL8 is at the L level, so that the source follower transistor SF9S-Tr outputs a column output read voltage (VSIG) corresponding to the voltage held by the eighth signal holding capacitor CS24 to the vertical signal line LSGN12.

In this way, in the solid-state imaging device 10C according to the fourth embodiment, the pixel signals are sampled simultaneously for all pixels in the signal holding unit 230 as pixel signal storage in voltage mode, and converted signals corresponding to the readout signals held in the first signal holding capacitor CR21, the second signal holding capacitor CS21, the third signal holding capacitor CR22, the fourth signal holding capacitor CS22, the fifth signal holding capacitor CR23, the sixth signal holding capacitor CS23, the seventh signal holding capacitor CR24, and the eighth signal holding capacitor CS24 are read out to the vertical signal lines LSGN11 and LSGN12 and supplied to the column readout circuit 40.

In the solid-state imaging device 10C according to the third embodiment, one photoelectric conversion readout section 220 has charge storage sections for multiple photodiodes PD, and has a signal holding section 230 as a memory section capable of holding each signal globally. The signals held globally in the signal holding section 230 are read out sequentially (rolling readout).

22A and 22B are operation sequence diagrams for explaining the global shutter readout operation of the solid-state imaging device 10C according to the fourth embodiment in comparison with the rolling shutter readout operation.
23A to 23C are diagrams showing an example of a timing chart of a rolling shutter readout operation.
24A to 24C are diagrams showing an example of a timing chart of a global shutter read operation.

23A and 24A show an example of timing when the four photodiodes PD10, PD11, PD12, and PD13 are simultaneously read out in parallel under a single exposure condition.
FIG. 23B and FIG. 24B show examples of timing when the four photodiodes PD10, PD11, PD12, and PD13 are simultaneously read out in parallel under individual exposure conditions.
Figures 23(C) and 24(C) show examples of timing when four photodiodes PD10, PD11, PD12, and PD13 are read out simultaneously in parallel under individual exposure conditions, and the readout period can be handled by one set of memory capacitance.

In the circuit configuration example of FIG. 21, the accumulated charge of the first photodiode PD10 which is the first photoelectric conversion element, the accumulated charge of the second photodiode PD11 which is the second photoelectric conversion element, the accumulated charge of the third photodiode PD12 which is the third photoelectric conversion element, and the accumulated charge of the fourth photodiode PD13 which is the fourth photoelectric conversion element are each read out independently.
First, the reset level of the floating diffusion FD10 is read out in the photoelectric conversion readout unit 220 and is held in the signal holding capacitors CR21, CR22, CR23, and CR24 of the signal holding unit 230.
Next, a signal corresponding to the accumulated charge in the first photodiode PD 10 is read out and held in the signal holding capacitor CH 21 of the signal holding section 240 .

For example, in the column readout circuit 40, the readout reset signal VRST and readout signal VSIG of the pixel signal pixout, which are supplied differentially and simultaneously in parallel, are amplified and AD converted, and the difference between the two signals {VRST-VSIG} is taken and CDS processing is performed.

Similarly, a signal corresponding to the accumulated charge in the second photodiode PD11 is read out and held in the signal holding capacitor CH22 of the signal holding unit 230. That is, signal readout, signal holding, CDS processing, AD conversion processing, etc. are similarly performed for the second photodiode PD11.
Next, a signal corresponding to the accumulated charge in the third photodiode PD12 is read out and held in the signal holding capacitor CH23 of the signal holding unit 230. That is, signal readout, signal holding, CDS processing, AD conversion processing, etc. are similarly performed on the third photodiode PD12.
Next, a signal corresponding to the accumulated charge in the fourth photodiode PD13 is read out and held in the signal holding capacitor CH24 of the signal holding unit 230. That is, signal readout, signal holding, CDS processing, AD conversion processing, etc. are similarly performed on the fourth photodiode PD13.
As a result, pixel signals read out with low noise from each of the first photodiode PD10, the second photodiode PD11, the third photodiode PD12, and the fourth photodiode PD13 are processed as, for example, phase difference information without distortion.

The pixel gain can be controlled by the storage transistor BIN10-Tr (BIN switch) and can be controlled according to the PD signal amount (illuminance), enabling PDAF signal processing over a wide range, i.e., enabling the PDAF (Phase Detection Auto Focus) function in HDR.

As shown in Figures 22(A) and 23(A) to (C), in the case of existing rolling readout, the accumulation period start time differs depending on the position of the pixel in the row direction (Y direction), and therefore the phase difference information differs depending on the vertical coordinate.
In particular, when the object is moving at high speed, the readout timing differs between the upper and lower ends of the pixel array, and the phase difference information differs depending on the position of the object, resulting in distortion of the phase difference information.
On the other hand, in the case of the global shutter, as shown in FIG. 22(B) and FIGS. 24(A) to 24(C), this problem is solved and no distortion of phase difference information occurs even in moving images.

In addition, in the fourth embodiment, by arranging a signal holding unit 230 as a memory unit within the pixel, it becomes possible to almost simultaneously capture read information of the accumulated charge of the first photodiode PD10, which is the first photoelectric conversion element, the accumulated charge of the second photodiode PD11, which is the second photoelectric conversion element, the accumulated charge of the third photodiode PD12, which is the third photoelectric conversion element, and the accumulated charge of the fourth photodiode PD13, which is the fourth photoelectric conversion element. However, by arranging shutter gate transistors SG10-Tr, SG11-Tr, SG12-Tr, and SG13-Tr as AB (anti-blooming) gates in the photodiode PD, it becomes possible to prevent the signal of one side (PD10) from being mixed in when reading out the signal of one side (for example, PD11), and normal photoelectric conversion characteristics can be obtained.

As described above, according to the fourth embodiment, the solid-state imaging device 10C includes a photoelectric conversion readout section 220 and a signal holding section 230 as pixels in the pixel section 20C, has a global shutter operation function, and is configured as, for example, a stacked CMOS image sensor that can substantially achieve a wide dynamic range and a high frame rate.

Therefore, according to the solid-state imaging device 10C of the fourth embodiment, not only can a global shutter be realized, but also, by utilizing the charge overflowing from the photodiode during the accumulation period in real time, it is possible to achieve a wide dynamic range and a high frame rate.
Moreover, according to the fourth embodiment, it is possible to realize a substantially wide dynamic range and a high frame rate, while also achieving low noise and maximizing the effective pixel area, thereby maximizing value per cost.

In addition, the solid-state imaging device 10C of the fourth embodiment can prevent the configuration from becoming complicated while preventing a decrease in layout area efficiency.

The solid-state imaging device 10C according to the fourth embodiment has a laminated structure of a first substrate (upper substrate) 110 and a second substrate (lower substrate) 120.
Therefore, in the fourth embodiment, the first substrate 110 side is basically formed only from NMOS elements, and the effective pixel area is maximized by the pixel array, thereby maximizing value per cost.

In the above description, a stacked solid-state imaging device having an analog global shutter function has been described.
However, the present invention can also be applied to a solid-state imaging device having a digital pixel sensor (DPS) that enables a global shutter to be realized in which exposure starts and ends at the same timing for all pixels in the pixel array by, for example, arranging an ADC (and even a memory section) including a comparator in each pixel.

The solid-state imaging devices 10, 10A, 10B, and 10C described above can be used as imaging devices in electronic devices such as digital cameras, video cameras, mobile terminals, surveillance cameras, and medical endoscope cameras.

FIG. 25 is a diagram showing an example of the configuration of an electronic device equipped with a camera system to which a solid-state imaging device according to an embodiment of the present invention is applied.

As shown in FIG. 25, the electronic device 300 has a CMOS image sensor 310 to which the solid-state imaging devices 10, 10A, 10B, and 10C according to the present embodiment can be applied.
Furthermore, the electronic device 300 has an optical system (lens or the like) 320 that guides incident light to the pixel region of the CMOS image sensor 310 (forming an image of a subject).
The electronic device 300 includes a signal processing circuit (PRC) 330 that processes an output signal from the CMOS image sensor 310 .

The signal processing circuit 330 performs predetermined signal processing on the output signal of the CMOS image sensor 310 .
The image signal processed by the signal processing circuit 330 can be displayed as a moving image on a monitor such as an LCD display, or output to a printer. It can also be recorded directly on a recording medium such as a memory card, and various other forms are possible.

As described above, by mounting the above-described solid-state imaging devices 10, 10A, 10B, and 10C as the CMOS image sensor 310, it is possible to provide a high-performance, small-sized, low-cost camera system.
This makes it possible to realize electronic devices such as surveillance cameras and medical endoscope cameras that are used in applications where the camera installation requirements include constraints such as mounting size, number of connectable cables, cable length, and installation height.

10, 10A, 10B, 10C...solid-state imaging device, 20...pixel section, PD10...first photodiode, PD11...second photodiode, PD12...third photodiode, PD13...fourth photodiode, TG0-Tr...tenth transfer transistor, TG11-Tr...second transfer transistor, TG12-Tr...third transfer transistor, TG13-Tr...fourth transfer transistor, SG10-Tr...first shutter gate transistor, SG11-Tr...second shutter gate transistor, SG122-Tr...third shutter gate transistor, SG13-Tr...fourth shutter gate transistor, FD10...floating diffusion, RST10-Tr...reset transistor, SF10-Tr...source follower transistor, BIN10-Tr...storage transistor, CS...storage capacitor, 220...photoelectric conversion readout section, 230...signal holding section, 30...vertical scanning circuit, 40...output circuit, 50...timing control circuit, 60...readout section, 300...electronic device, 310...CMOS image sensor, 320...optical system, 330...signal processing circuit (PRC).

Claims (16)

a pixel section in which shared pixels that perform photoelectric conversion are arranged;
a readout unit that reads out pixel signals from the shared pixels of the pixel unit,
The shared pixel is
At least three photoelectric conversion elements that accumulate charges generated by photoelectric conversion during an accumulation period;
a plurality of transfer elements capable of individually transferring the charges accumulated in each of the photoelectric conversion elements during a transfer period following the accumulation period;
a floating diffusion serving as an output node to which the accumulated charges of each of the photoelectric conversion elements are transferred through each of the transfer elements;
a reset element that resets the floating diffusion to a predetermined potential during a reset period;
a source follower element serving as an output buffer unit that converts the charge of the floating diffusion into a voltage signal corresponding to the amount of charge and outputs the converted voltage signal;
a storage element connected to the floating diffusion;
a storage capacitance element that stores the charge of the floating diffusion through the storage element;
a plurality of charge overflow gate elements connected to the respective photoelectric conversion elements and capable of overflowing charge from the connected photoelectric conversion elements toward the floating diffusion region or toward an outside of the floating diffusion region;
the storage element is disposed between the floating diffusion and the reset element;
a gain switching unit capable of switching a conversion gain of the source follower element as the output buffer unit to a first conversion gain determined by the first capacitance or a second conversion gain determined by the second capacitance by changing an amount of charge of a floating diffusion as the output node to a first capacitance or a second capacitance,
one of the floating diffusions and one of the source follower elements are shared by the plurality of photoelectric conversion elements and the plurality of transfer elements;
the floating diffusion is disposed in a central portion of an element forming region, and the plurality of photoelectric conversion elements are disposed radially around the floating diffusion;
the floating diffusion includes a first side and a second side opposed to each other, the source follower element is disposed adjacent to the first side of the floating diffusion in a first direction perpendicular to the first side, and the reset element is disposed adjacent to the second side of the floating diffusion in the first direction;
the floating diffusion and the source follower element are connected by wiring;
the photoelectric conversion elements adjacent to each other in a second direction perpendicular to the first direction are arranged at a first interval that allows at least the source follower element and the reset element to be formed;
the photoelectric conversion elements adjacent to each other in the first direction are disposed at a second interval that is narrower than the first interval;
the transfer elements are arranged so as to connect between a first side edge portion in a second direction of the first side portion of the floating diffusion and a first edge portion of the photoelectric conversion element that faces the first side edge portion, and between a second side edge portion in a second direction of the second side portion of the floating diffusion and a first edge portion of the photoelectric conversion element that faces the second side edge portion,
the charge overflow gate element is arranged to be connected to a second edge portion of the photoelectric conversion element on an outer edge side spaced apart from the first edge portion,
The readout unit is
With respect to the accumulated charges of at least two of the plurality of photoelectric conversion elements of the shared pixel,
a second conversion gain reset read process for reading out a second read reset signal converted with a second conversion gain determined by a second capacitance of the floating diffusion as the output node from the source follower element as the output buffer unit during a reset read period after the reset period, and performing a predetermined process on the second read reset signal;
a first conversion gain reset read process for switching a gain by the gain switching unit, reading out a first read reset signal converted with a first conversion gain determined by a first capacitance of the floating diffusion as the output node from the source follower element as the output buffer unit, and performing a predetermined process on the first read reset signal;
a first conversion gain readout process for reading out a first readout signal converted with a first conversion gain determined by a first capacitance of the floating diffusion as the output node from the source follower element as the output buffer unit during a first readout period following the first transfer period after the reset readout period, and performing a predetermined process on the first readout signal;
a second conversion gain readout process in which a gain is switched by the gain switching unit after the first readout period, and a second readout signal converted with a second conversion gain determined by a second capacitance of the floating diffusion as the output node is read out from the source follower element as the output buffer unit during a second readout period following the second transfer period after the first readout period, and a predetermined process is performed on the second readout signal;
The readout unit is
The second conversion gain reset read process is
The transfer element, the charge overflow gate element, and the reset element are held in a non-conductive state, and the storage element is held in a conductive state, so that the charge of the floating diffusion as the output node and the charge of the storage capacitance element are shared;
The first conversion gain reset read process and the first conversion gain read process,
The transfer element, the charge overflow gate element, and the reset element are maintained in a non-conductive state, and the storage element is maintained in a non-conductive state, thereby separating the charge of the floating diffusion as the output node from the charge of the storage capacitance element;
The second conversion gain readout process is
A solid-state imaging device which holds the transfer element and the reset element in a non-conductive state, holds the charge overflow gate element in a conductive state, and holds the storage element in a conductive state, thereby sharing the charge of the floating diffusion as the output node and the charge of the storage capacitance element. 2. The solid-state imaging device according to claim 1, wherein an overflow path is formed in a layer deeper than at least a channel forming region of the transfer element. The solid-state imaging device according to claim 2 , wherein the potential of the overflow path is controllable by a gate potential of the transfer element. The solid-state imaging device according to claim 1 , wherein an overflow path is formed under at least a channel formation region of the charge overflow gate element. 5. The solid-state imaging device according to claim 1, wherein the charge overflow gate element functions as a shutter gate that transfers the accumulated charge of the photoelectric conversion element to an outside of a floating diffusion region serving as the output node. 6. The solid-state imaging device according to claim 5, wherein the transfer element and the charge overflow gate element are driven and controlled at separate timings. 5. The solid-state imaging device according to claim 1, wherein a threshold value of each of the charge overflow gate elements is individually adjusted. The shared pixel is
a first photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period;
a first transfer element capable of transferring the charge accumulated in the first photoelectric conversion element during a transfer period following the accumulation period;
a second photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period;
a second transfer element capable of transferring the charge accumulated in the second photoelectric conversion element during a transfer period following the accumulation period;
a third photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period;
a third transfer element capable of transferring the charge accumulated in the third photoelectric conversion element during a transfer period following the accumulation period;
a fourth photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period;
a fourth transfer element capable of transferring the charge accumulated in the fourth photoelectric conversion element during a transfer period following the accumulation period;
The floating diffusion is
the accumulated charge of the first photoelectric conversion element is transferred through the first transfer element, the accumulated charge of the second photoelectric conversion element is transferred through the second transfer element, the accumulated charge of the third photoelectric conversion element is transferred through the third transfer element, or the accumulated charge of the fourth photoelectric conversion element is transferred through the fourth transfer element;
the floating diffusion is disposed in a central portion of an element formation region, and the first photoelectric conversion element, the second photoelectric conversion element, the third photoelectric conversion element, and the fourth photoelectric conversion element are radially disposed around the floating diffusion;
The source follower element is disposed adjacent to the first side of the floating diffusion in the first direction perpendicular to the first side of the floating diffusion, and the reset element is disposed adjacent to the second side of the floating diffusion in the first direction;
the floating diffusion and the source follower element are connected by wiring;
the first photoelectric conversion element and the second photoelectric conversion element, and the third photoelectric conversion element and the fourth photoelectric conversion element adjacent to each other in the second direction are arranged at the first interval at which at least the source follower element and the reset element can be formed;
the first photoelectric conversion element and the third photoelectric conversion element, and the second photoelectric conversion element and the fourth photoelectric conversion element adjacent to each other in the first direction are disposed at the second interval which is narrower than the first interval;
the first transfer element and the second transfer element are arranged so as to connect between the first side edge portions at both ends of the first side portion of the floating diffusion in the second direction and first edges of the first photoelectric conversion element and the second photoelectric conversion element that face the first side edge portions;
8. The solid-state imaging device according to claim 1, wherein the corresponding third transfer element and the fourth transfer element are arranged to connect between second side edge portions at both ends of the second side of the floating diffusion in the second direction and first edges of the third photoelectric conversion element and the fourth photoelectric conversion element that face the second side edge portions. The shared pixel is
a first charge overflow gate element connected to the first photoelectric conversion element and capable of overflowing charge from the connected first photoelectric conversion element toward the floating diffusion region or toward the outside of the floating diffusion region;
a second charge overflow gate element connected to the second photoelectric conversion element and capable of overflowing charge from the connected second photoelectric conversion element toward the floating diffusion region or toward the outside of the floating diffusion region;
a third charge overflow gate element connected to the third photoelectric conversion element and capable of overflowing charge from the connected third photoelectric conversion element toward the floating diffusion region or toward the outside of the floating diffusion region;
a fourth charge overflow gate element connected to the fourth photoelectric conversion element and capable of overflowing charge from the connected fourth photoelectric conversion element toward the floating diffusion region or toward an outside of the floating diffusion region;
the first charge overflow gate element is arranged to be connected to a second edge portion of the first photoelectric conversion element on an outer edge side spaced apart from the first edge portion;
the second charge overflow gate element is arranged to be connected to a second edge portion of the second photoelectric conversion element on an outer edge side spaced apart from the first edge portion,
the third charge overflow gate element is arranged to be connected to a second edge portion of the third photoelectric conversion element on an outer edge side spaced apart from the first edge portion,
The solid-state imaging device according to claim 8 , wherein the fourth charge overflow gate element is arranged so as to be connected to a second edge portion of the fourth photoelectric conversion element on an outer edge side spaced apart from the first edge portion. The readout unit is
With respect to the accumulated charges of at least two of the first photoelectric conversion element, the second photoelectric conversion element, the third photoelectric conversion element, and the fourth photoelectric conversion element of the shared pixel,
a second conversion gain reset read process for reading out a second read reset signal converted with a second conversion gain determined by a second capacitance of the floating diffusion as the output node from the source follower element as the output buffer unit during a reset read period after the reset period, and performing a predetermined process on the second read reset signal;
a first conversion gain reset read process for switching a gain by the gain switching unit, reading out a first read reset signal converted with a first conversion gain determined by a first capacitance of the floating diffusion as the output node from the source follower element as the output buffer unit, and performing a predetermined process on the first read reset signal;
a first conversion gain readout process for reading out a first readout signal converted with a first conversion gain determined by a first capacitance of the floating diffusion as the output node from the source follower element as the output buffer unit during a first readout period following the first transfer period after the reset readout period, and performing a predetermined process on the first readout signal;
10. The solid-state imaging device according to claim 9, further comprising: a gain switching unit that switches a gain after the first readout period; and during a second readout period following a second transfer period after the first readout period, a second readout signal converted with a second conversion gain determined by a second capacitance of the floating diffusion as the output node is read out from the source follower element as the output buffer unit, and a second conversion gain readout process is performed on the second readout signal. The readout unit is
The second conversion gain reset read process is
The transfer element, the charge overflow gate element, and the reset element are held in a non-conductive state, and the storage element is held in a conductive state, so that the charge of the floating diffusion as the output node and the charge of the storage capacitance element are shared;
The first conversion gain reset read process and the first conversion gain read process,
The transfer element, the charge overflow gate element, and the reset element are maintained in a non-conductive state, and the storage element is maintained in a non-conductive state, thereby separating the charge of the floating diffusion as the output node from the charge of the storage capacitance element;
The second conversion gain readout process is
The solid-state imaging device according to claim 10, wherein the transfer element and the reset element are held in a non-conductive state, the charge overflow gate element is held in a conductive state, and the storage element is held in a conductive state, thereby sharing the charge of the floating diffusion as the output node and the charge of the storage capacitance element. The shared pixel is
a photoelectric conversion readout unit including at least the first photoelectric conversion element, the second photoelectric conversion element, the third photoelectric conversion element, and the fourth photoelectric conversion element, reading out charges accumulated in each of the photoelectric conversion elements to a floating diffusion as an output node, converting the charges in the floating diffusion into a voltage signal according to the amount of charge in a source follower element as an output buffer, and outputting the converted voltage signal;
12. The solid-state imaging device according to claim 8, further comprising: a signal holding unit capable of holding pixel signals corresponding to the accumulated charges of the first photoelectric conversion element, the second photoelectric conversion element, the third photoelectric conversion element, and the fourth photoelectric conversion element read out by the photoelectric conversion readout unit. The signal holding unit is
An input node;
a plurality of signal holding capacitors capable of holding a read reset signal and a read signal that are output from a read node of the photoelectric conversion readout unit of the shared pixel and input to the input node when reading out the accumulated charge of the first photoelectric conversion element, the accumulated charge of the second photoelectric conversion element, the accumulated charge of the third photoelectric conversion element, or the accumulated charge of the fourth photoelectric conversion element;
a plurality of signal holding capacitors capable of holding a read signal output from a read node of the photoelectric conversion readout unit of the shared pixel and input to the input node when reading out the accumulated charge of the first photoelectric conversion element, the accumulated charge of the second photoelectric conversion element, the accumulated charge of the third photoelectric conversion element , or the accumulated charge of the fourth photoelectric conversion element;
a plurality of switch elements selectively connecting the plurality of signal holding capacitors to a readout node of the photoelectric conversion readout unit;
The solid-state imaging device according to claim 12 , further comprising: a source follower element that outputs the signals held in the signal holding capacitors in accordance with a holding voltage, and a plurality of output sections that selectively output the converted signals to signal lines. The signal holding unit is
An input node;
a first signal holding capacitor capable of holding a first read reset signal that is output from a read node of the photoelectric conversion read unit of the shared pixel and input to the input node when reading out the accumulated charge of the first photoelectric conversion element;
a second signal holding capacitor capable of holding a first read signal that is output from a read node of the photoelectric conversion read unit of the shared pixel and input to the input node when reading out the accumulated charge of the first photoelectric conversion element;
a third signal holding capacitor capable of holding a second read reset signal that is output from a read node of the photoelectric conversion read unit of the shared pixel and input to the input node when the accumulated charge of the second photoelectric conversion element is read out;
a fourth signal holding capacitor capable of holding a second read signal that is output from a read node of the photoelectric conversion read unit of the shared pixel and input to the input node when the accumulated charge of the second photoelectric conversion element is read out;
a fifth signal holding capacitor capable of holding a third read reset signal that is output from a read node of the photoelectric conversion read unit of the shared pixel and input to the input node when the accumulated charge of the third photoelectric conversion element is read out;
a sixth signal holding capacitor capable of holding a third read signal that is output from a read node of the photoelectric conversion read unit of the shared pixel and input to the input node when reading out the accumulated charge of the third photoelectric conversion element;
a seventh signal holding capacitor capable of holding a fourth read reset signal that is output from a read node of the photoelectric conversion read unit of the shared pixel and input to the input node when the accumulated charge of the fourth photoelectric conversion element is read out;
an eighth signal holding capacitor capable of holding a fourth read signal that is output from a read node of the photoelectric conversion read unit of the shared pixel and input to the input node when the accumulated charge of the fourth photoelectric conversion element is read;
a first switch element that selectively connects the first signal holding capacitor to a readout node of the photoelectric conversion readout unit;
a second switch element that selectively connects the second signal holding capacitor to a read node of the photoelectric conversion readout unit;
a third switch element that selectively connects the third signal holding capacitor to a read node of the photoelectric conversion readout unit;
a fourth switch element that selectively connects the fourth signal holding capacitor to a read node of the photoelectric conversion readout unit;
a fifth switch element that selectively connects the fifth signal holding capacitor to a read node of the photoelectric conversion readout unit;
a sixth switch element that selectively connects the sixth signal holding capacitor to a read node of the photoelectric conversion readout unit;
a seventh switch element that selectively connects the seventh signal holding capacitor to a read node of the photoelectric conversion readout unit;
an eighth switch element that selectively connects the eighth signal holding capacitor to a read node of the photoelectric conversion readout unit;
a first output section including a source follower element that outputs the signal held in the first signal holding capacitor in response to a holding voltage, and that selectively outputs the converted signal to a signal line;
a second output section including a source follower element that outputs the signal held in the second signal holding capacitor in response to a holding voltage, and that selectively outputs the converted signal to a signal line;
a third output section including a source follower element that outputs the signal held in the third signal holding capacitor in response to a holding voltage, and that selectively outputs the converted signal to a signal line;
a fourth output section including a source follower element that outputs the signal held in the fourth signal holding capacitor in response to a holding voltage, and that selectively outputs the converted signal to a signal line;
a fifth output section including a source follower element that outputs the signal held in the fifth signal holding capacitor in response to a holding voltage, and that selectively outputs the converted signal to a signal line;
a sixth output section including a source follower element that outputs the signal held in the sixth signal holding capacitor in response to a holding voltage, and that selectively outputs the converted signal to a signal line;
a seventh output section including a source follower element that outputs the signal held in the seventh signal holding capacitor in response to a holding voltage, and that selectively outputs the converted signal to a signal line;
The solid-state imaging device according to claim 13 , further comprising: an eighth output section including a source follower element that outputs the signal held in the eighth signal holding capacitor in accordance with a holding voltage, and selectively outputs the converted signal to a signal line. a pixel section in which shared pixels that perform photoelectric conversion are arranged;
a readout unit that reads out pixel signals from the shared pixels of the pixel unit,
The shared pixel is
At least three photoelectric conversion elements that accumulate charges generated by photoelectric conversion during an accumulation period;
a plurality of transfer elements capable of individually transferring the charges accumulated in each of the photoelectric conversion elements during a transfer period following the accumulation period;
a floating diffusion serving as an output node to which the accumulated charges of each of the photoelectric conversion elements are transferred through each of the transfer elements;
a reset element that resets the floating diffusion to a predetermined potential during a reset period;
a source follower element serving as an output buffer unit that converts the charge of the floating diffusion into a voltage signal corresponding to the amount of charge and outputs the converted voltage signal;
a storage element connected to the floating diffusion;
a storage capacitance element that stores the charge of the floating diffusion through the storage element;
a plurality of charge overflow gate elements connected to the respective photoelectric conversion elements and capable of overflowing charge from the connected photoelectric conversion elements toward the floating diffusion region or toward an outside of the floating diffusion region;
the storage element is disposed between the floating diffusion and the reset element;
a gain switching unit capable of switching a conversion gain of the source follower element as the output buffer unit to a first conversion gain determined by the first capacitance or a second conversion gain determined by the second capacitance by changing an amount of charge of a floating diffusion as the output node to a first capacitance or a second capacitance,
one of the floating diffusions and one of the source follower elements are shared by the plurality of photoelectric conversion elements and the plurality of transfer elements;
A method for manufacturing a solid-state imaging device in which the floating diffusion is disposed in a central portion of an element formation region, and the plurality of photoelectric conversion elements are radially disposed around the floating diffusion, the floating diffusion including a first side portion and a second side portion opposed to each other, the source follower element is disposed adjacent to the first side portion of the floating diffusion in a first direction perpendicular to the first side portion of the floating diffusion, and the reset element is formed adjacent to the second side portion of the floating diffusion in the first direction;
The floating diffusion and the source follower element are connected by wiring,
the photoelectric conversion elements adjacent to each other in a second direction perpendicular to the first direction are formed at a first interval that allows at least the source follower element and the reset element to be formed;
the photoelectric conversion elements adjacent to each other in the first direction are formed at a second interval that is narrower than the first interval;
forming the transfer elements corresponding to each other so as to connect between a first side edge portion in a second direction of the first side portion of the floating diffusion and a first edge portion of the photoelectric conversion element that faces the first side edge portion, and between a second side edge portion in a second direction of the second side portion of the floating diffusion and a first edge portion of the photoelectric conversion element that faces the second side edge portion;
the charge overflow gate element is formed so as to be connected to a second edge portion of the photoelectric conversion element on an outer edge side spaced apart from the first edge portion;
The readout unit is
With respect to the accumulated charges of at least two of the plurality of photoelectric conversion elements of the shared pixel,
a second conversion gain reset read process for reading out a second read reset signal converted with a second conversion gain determined by a second capacitance of the floating diffusion as the output node from the source follower element as the output buffer unit during a reset read period after the reset period, and performing a predetermined process on the second read reset signal;
a first conversion gain reset read process for switching a gain by the gain switching unit, reading out a first read reset signal converted with a first conversion gain determined by a first capacitance of the floating diffusion as the output node from the source follower element as the output buffer unit, and performing a predetermined process on the first read reset signal;
a first conversion gain readout process for reading out a first readout signal converted with a first conversion gain determined by a first capacitance of the floating diffusion as the output node from the source follower element as the output buffer unit during a first readout period following the first transfer period after the reset readout period, and performing a predetermined process on the first readout signal;
a second conversion gain readout process in which a gain is switched by the gain switching unit after the first readout period, and a second readout signal converted with a second conversion gain determined by a second capacitance of the floating diffusion as the output node is read out from the source follower element as the output buffer unit during a second readout period following the second transfer period after the first readout period, and a predetermined process is performed on the second readout signal;
The readout unit is
The second conversion gain reset read process is
The transfer element, the charge overflow gate element, and the reset element are held in a non-conductive state, and the storage element is held in a conductive state, so that the charge of the floating diffusion as the output node and the charge of the storage capacitance element are shared;
The first conversion gain reset read process and the first conversion gain read process,
The transfer element, the charge overflow gate element, and the reset element are maintained in a non-conductive state, and the storage element is maintained in a non-conductive state, thereby separating the charge of the floating diffusion as the output node from the charge of the storage capacitance element;
The second conversion gain readout process is
The method for manufacturing a solid-state imaging device includes holding the transfer element and the reset element in a non-conductive state, holding the charge overflow gate element in a conductive state, and holding the storage element in a conductive state, so as to share the charge of the floating diffusion as the output node and the charge of the storage capacitance element. A solid-state imaging device;
an optical system that forms a subject image on the solid-state imaging device;
The solid-state imaging device includes:
a pixel section in which shared pixels that perform photoelectric conversion are arranged;
a readout unit that reads out pixel signals from the shared pixels of the pixel unit,
The shared pixel is
At least three photoelectric conversion elements that accumulate charges generated by photoelectric conversion during an accumulation period;
a plurality of transfer elements capable of individually transferring the charges accumulated in each of the photoelectric conversion elements during a transfer period following the accumulation period;
a floating diffusion serving as an output node to which the accumulated charges of each of the photoelectric conversion elements are transferred through each of the transfer elements;
a reset element that resets the floating diffusion to a predetermined potential during a reset period;
a source follower element serving as an output buffer unit that converts the charge of the floating diffusion into a voltage signal corresponding to the amount of charge and outputs the converted voltage signal;
a storage element connected to the floating diffusion;
a storage capacitance element that stores the charge of the floating diffusion through the storage element;
a plurality of charge overflow gate elements connected to the respective photoelectric conversion elements and capable of overflowing charge from the connected photoelectric conversion elements toward the floating diffusion region or toward an outside of the floating diffusion region;
the storage element is disposed between the floating diffusion and the reset element;
a gain switching unit capable of switching a conversion gain of the source follower element as the output buffer unit to a first conversion gain determined by the first capacitance or a second conversion gain determined by the second capacitance by changing an amount of charge of a floating diffusion as the output node to a first capacitance or a second capacitance,
one of the floating diffusions and one of the source follower elements are shared by the plurality of photoelectric conversion elements and the plurality of transfer elements;
the floating diffusion is disposed in a central portion of an element formation region, and the plurality of photoelectric conversion elements are disposed radially around the floating diffusion;
the floating diffusion includes a first side and a second side opposed to each other, the source follower element is disposed adjacent to the first side of the floating diffusion in a first direction perpendicular to the first side, and the reset element is disposed adjacent to the second side of the floating diffusion in the first direction;
the floating diffusion and the source follower element are connected by wiring;
the photoelectric conversion elements adjacent to each other in a second direction perpendicular to the first direction are arranged at a first interval that allows at least the source follower element and the reset element to be formed;
the photoelectric conversion elements adjacent to each other in the first direction are disposed at a second interval that is narrower than the first interval;
the transfer elements are arranged so as to connect between a first side edge portion in a second direction of the first side portion of the floating diffusion and a first edge portion of the photoelectric conversion element that faces the first side edge portion, and between a second side edge portion in a second direction of the second side portion of the floating diffusion and a first edge portion of the photoelectric conversion element that faces the second side edge portion,
the charge overflow gate element is arranged to be connected to a second edge portion of the photoelectric conversion element on an outer edge side spaced apart from the first edge portion,
The readout unit is
With respect to the accumulated charges of at least two of the plurality of photoelectric conversion elements of the shared pixel,
a second conversion gain reset read process for reading out a second read reset signal converted with a second conversion gain determined by a second capacitance of the floating diffusion as the output node from the source follower element as the output buffer unit during a reset read period after the reset period, and performing a predetermined process on the second read reset signal;
a first conversion gain reset read process for switching a gain by the gain switching unit, reading out a first read reset signal converted with a first conversion gain determined by a first capacitance of the floating diffusion as the output node from the source follower element as the output buffer unit, and performing a predetermined process on the first read reset signal;
a first conversion gain readout process for reading out a first readout signal converted with a first conversion gain determined by a first capacitance of the floating diffusion as the output node from the source follower element as the output buffer unit during a first readout period following the first transfer period after the reset readout period, and performing a predetermined process on the first readout signal;
a second conversion gain readout process in which a gain is switched by the gain switching unit after the first readout period, and a second readout signal converted with a second conversion gain determined by a second capacitance of the floating diffusion as the output node is read out from the source follower element as the output buffer unit during a second readout period following the second transfer period after the first readout period, and a predetermined process is performed on the second readout signal;
The readout unit is
The second conversion gain reset read process is
The transfer element, the charge overflow gate element, and the reset element are held in a non-conductive state, and the storage element is held in a conductive state, so that the charge of the floating diffusion as the output node and the charge of the storage capacitance element are shared;
The first conversion gain reset read process and the first conversion gain read process,
The transfer element, the charge overflow gate element, and the reset element are maintained in a non-conductive state, and the storage element is maintained in a non-conductive state, thereby separating the charge of the floating diffusion as the output node from the charge of the storage capacitance element;
The second conversion gain readout process is
The electronic device is executed by holding the transfer element and the reset element in a non-conductive state, holding the charge overflow gate element in a conductive state, and holding the storage element in a conductive state, and sharing the charge of the floating diffusion as the output node and the charge of the storage capacitance element.

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