JP7604111B2 - Plasma Processing Equipment - Google Patents

Description

This relates to a plasma processing apparatus that processes a wafer by placing the wafer in a processing chamber inside a vacuum vessel and generating plasma in the processing chamber, and in particular, to a plasma processing apparatus that electrostatically attracts the wafer and holds it on a sample stage, and processes the wafer while adjusting the temperature of the sample stage to different temperatures.

An example of the above-mentioned plasma processing apparatus is disclosed in Japanese Patent Laid-Open Publication No. 2010-010236 (Patent Document 1). This conventional technique monitors the Vpp of the high frequency bias power supplied to the electrode of the sample stage arranged in the processing chamber inside the vacuum vessel, calculates the wafer potential (Vdc) from the Vpp value using a self-bias voltage calculation means, compares the Vdc with Vchuck, which is the potential difference between the Vdc and the ESC voltage, and controls the ESC voltage output from the ESC power supply to be switched between Vesc ⁺ = Vdc + Vchuck and Vesc ^- = Vdc - Vchuck depending on the magnitude of the Vdc, thereby suppressing the occurrence of abnormal discharge and obtaining a suitable chucking force.

JP 2010-010236 A

The above conventional technology had problems because it did not sufficiently consider the following points:

In other words, in the above-mentioned conventional technology, the ESC voltage output from the ESC power supply was set from the chucking voltage set according to Vpp. However, in JR-type electrodes, the resistance of the JR film changes with temperature, so even if the chucking voltage is constant, the current flowing through the film changes with temperature. The chucking force changes with the current flowing. In other words, at high temperatures, the resistance value decreases, causing the current value to increase, which can lead to chucking errors and wafer cracks due to excessive chucking force. Conversely, at low temperatures, there is a risk of wafer chucking failure due to insufficient chucking force.

As a result, the conventional technology had problems in that the yield of wafer processing for manufacturing devices was compromised, and the efficiency of processing was reduced. These points were not taken into consideration in the above conventional technology.

The object of the present invention is to provide a plasma processing apparatus that improves yield.

The object of the present invention is to provide a method for manufacturing a wafer processing apparatus comprising: a processing chamber which is disposed within a vacuum vessel and inside which plasma is generated; a sample stage which is disposed within the processing chamber and on whose upper surface a wafer to be processed using the plasma is placed and held; a dielectric film which is disposed on the upper surface of the sample stage and has a plurality of film-shaped electrostatic adsorption electrodes to whose inner side DC power is supplied for electrostatically adsorbing the wafer; an electrode which is disposed inside the sample stage below the dielectric film and to which high frequency power is supplied; a plurality of through holes which have openings on the upper surface of the dielectric film and house pins on the inside which push the wafer upward from the upper surface and hold it at its tip; and a ring-shaped second convex portion arranged to surround each of the plurality of through holes inside the ring-shaped first convex portion, upper surfaces of the first and second convex portions constitute chucking surfaces that come into contact with a back surface of the wafer when the wafer is placed on it and electrostatically attracted to it, and a control device that calculates a difference between the voltage of the electrostatic chucking electrode and the self -bias voltage Vdc of the wafer caused by the high frequency power in accordance with a temperature of the chucking surface of the first or second convex portion, and adjusts the DC power supplied to the electrostatic chucking electrode so that the voltage of the electrostatic chucking electrode becomes a target value obtained by using the difference .

The present invention reduces wafer suction failures, such as wafer cracking due to excessive suction force or wafer peeling due to insufficient suction force, and improves wafer processing yields.

1 is a vertical cross-sectional view showing an outline of calibration of the entire plasma processing apparatus according to an embodiment of the present invention; FIG. 2 is a vertical sectional view for explaining the outline of the configuration of the main part of the sample stage of the embodiment shown in FIG. 1 . 2 is a top view showing a schematic configuration of the top surface of a dielectric film of the sample stage of the embodiment shown in FIG. 1. 2 is a top view showing a schematic configuration of the top surface of a dielectric film of the sample stage of the embodiment shown in FIG. 1. 2 is a top view showing a schematic configuration of the top surface of a dielectric film of the sample stage of the embodiment shown in FIG. 1. 4 is a flowchart showing a procedure for setting an ESC voltage in the plasma processing apparatus according to the embodiment shown in FIG. 1 . 4 is a graph showing an example of changes in temperature and ESC voltage over time during an etching process performed by the plasma processing apparatus according to the embodiment shown in FIG. 1 . 2 is a graph showing a schematic relationship between a DC voltage, a high frequency bias voltage, and an electrostatic attraction voltage outputted from an electrostatic attraction power supply supplied to a sample stage of the plasma processing apparatus according to the present embodiment shown in FIG. 1 .

The following describes an embodiment of the present invention with reference to the drawings.

An embodiment of the present invention will be described with reference to Figures 1 to 8. Figure 1 is a vertical cross-sectional view showing a schematic overview of the overall calibration of a plasma processing apparatus according to an embodiment of the present invention. The plasma processing apparatus 100 of this embodiment is an etching processing apparatus that etches a film layer to be processed of a film structure including a mask layer formed in advance on the upper surface of a wafer 113 placed in a processing chamber 105, which is a space inside a vacuum vessel 116 and in which plasma is formed, and a film layer to be processed below the mask layer.

The plasma processing apparatus 100 includes a plasma generating high frequency power supply 101 that forms a high frequency electric field that is supplied to the processing chamber 105 to generate plasma 106 in the processing chamber 105, and a sample stage 109 that is arranged in the processing chamber 105 and holds a wafer 113 on its upper surface. Inside the sample stage 109, a metal disk or cylindrical electrode 108 is arranged and electrically connected to a bias high frequency power supply 110 that generates a high frequency bias power to form a bias potential having a potential difference with the plasma above the upper surface of the wafer 113 during processing. A dielectric film 120, which is a dielectric film made of a ceramic material such as aluminum oxide or yttrium oxide, is arranged on the upper surface of the cylindrical convex part that is arranged on the upper part of the electrode 108 and has a central upper surface elevated upward.

Inside the dielectric film 120, there are arranged a number of film-shaped electrodes electrically connected to the DC power source 111, which generate electrostatic forces to attract, adsorb, and hold the wafer 113 placed above the upper surface of the dielectric film 120 by the supplied DC power, and a number of film-shaped heater electrodes connected to another DC power source, which generate heat by the supplied DC power to heat the wafer 113. These film-shaped electrodes arranged inside the dielectric film 120 will be described later with reference to FIG. 2. In this figure, they are shown as one film-shaped electrode 121.

In addition, this embodiment is equipped with a Vpp monitor 112 that is connected to the sample stage 109 and detects the amplitude (peak-to-peak) value of the high frequency bias power supplied from the high frequency bias power supply 110, a self-bias voltage calculator 114 that calculates the self-bias voltage of the wafer 113 using a signal value indicating the peak-to-peak of the high frequency bias power supplied to the electrode 108 output from the Vpp monitor, and a control device 115 that receives the output signal from the self-bias voltage calculator 114 and adjusts the magnitude of the DC voltage output by the DC power supply 111 based on the self-bias voltage indicated by the output signal. The self-bias voltage calculator 114 may be an internal circuit of the control device 115.

In addition, a cylindrical or ring-shaped earth electrode 107 electrically connected to a ground point is arranged along the inner wall of the processing chamber 105 above the sample stage 109 in this embodiment, and has the function of stabilizing the potential of the plasma 106 or the electrode 108 to which high-frequency bias power is supplied as a ground electrode. Furthermore, a disk-shaped window member 104 made of ceramics such as aluminum oxide is placed on the upper end of the side wall of the vacuum vessel 116 surrounding the periphery of the cylindrical processing chamber 105 with a sealing means such as an O-ring sandwiched between the upper end, and an induction coil 103 is arranged concentrically or spirally wound outside the vacuum vessel 116 above the window member 104, and is supplied with high-frequency power from the high-frequency power source 101 for plasma generation to form an induction magnetic field in the upper part of the processing chamber 105 below the window member 104. Furthermore, a matching box 102 is arranged on the power supply path such as a cable that electrically connects between the induction coil 103 and the high-frequency power source 101.

Furthermore, although not shown, the vacuum vessel 116 is connected to a processing gas supply line that supplies processing gas into the processing chamber 105, for forming plasma 106 in the processing chamber 105 by the induction magnetic field from the induction coil 103. The processing gas supply line is connected to the cylindrical upper end of the vacuum vessel 116, and the processing gas supplied through the supply line is supplied to the gap between the window member 104 and a disk-shaped shower plate made of a ceramic material such as quartz (not shown) that is disposed in the processing chamber 105 below the window member 104 and forms the top surface of the processing chamber 105, and diffuses inside, and is then introduced downward into the processing chamber 105 through a plurality of through holes arranged in the center of the shower plate.

Figure 2 shows an outline of the configuration of the electrode 108, which is a metal disk-shaped substrate of the sample stage 109 of the plasma processing apparatus 100 of this embodiment and to which high-frequency bias power is supplied, and the dielectric film 120 arranged on its upper surface. Figure 2 is a vertical cross-sectional view that illustrates the outline of the configuration of the main parts of the sample stage of the embodiment shown in Figure 1.

In this figure, the dielectric film 120 arranged on the top of the metal electrode 108, which is the base material of the sample stage 109, is arranged to cover the upper surface of the convex part arranged in the center of the upper part of the electrode 108, and is provided with a film-like electrode 121 that forms two layers in the vertical direction inside. The lower film-like electrode is a heater electrode 202 that occupies multiple areas (zones) on the upper surface of the convex part or dielectric film 120 when viewed from above, and in this embodiment, as described later, it is arranged so as to substantially occupy each area within a central circular area including the center of the dielectric film 120 and multiple ring-shaped areas arranged concentrically around the center surrounding it on the outer periphery, and further, the ring-shaped area is divided into multiple (in this example, three or more) arc-shaped small areas around the center, and the heater electrodes 202 are arranged occupying each small area. That is, the heater electrode of this embodiment is disposed within the dielectric film 120 in a central circular zone and multiple arc-shaped zones surrounding it, occupying substantially the same area as these zones, and covering the entire upper surface of the convex portion of the electrode 108.

On the other hand, the upper layer of the film-like electrode 121 is an ESC electrode 201 for electrostatic attraction, which occupies a circular area including the center of the dielectric film 120 when viewed from above, and at least one ring-shaped area on the outer periphery that surrounds the circular area concentrically with respect to the center. As described later, in the radial direction from the sample stage 109 or center in this example, the separated points of two adjacent ESC electrodes are also located at the same specific radial position with respect to the center and are separated concentrically, and the separation position overlaps with the point where the two adjacent ring-shaped areas in which the heater electrodes 202 are arranged are separated concentrically at the same specific radial position with respect to the center, and one includes the projected area of the other when viewed from above.

A DC power supply 111 is connected to each of the multiple ESC electrodes 201 in this embodiment, and a voltage determined in response to a command signal from the control device 115 is applied, and a polarity corresponding to this is assigned. Charges are accumulated in the area above each electrode in the upper wafer 113 in response to the polarity corresponding to these voltages, generating an electrostatic force. The multiple ESC electrodes 201 in this embodiment are assigned either positive or negative polarity, forming a pair of positive and negative electrodes, forming a so-called bipolar type. The sum of the areas of the ESC electrodes 201 to which the positive and negative polarities are assigned is shaped to have the same value or a value that is close enough to be considered as such.

Furthermore, in the sample stage 109 of this embodiment, a plurality of temperature sensors 203 are arranged inside the electrode 108, each in the region or zone projected region in which the heater electrode 202 is arranged in the dielectric film 120 when viewed from above, to detect the temperature of the electrode 108. The temperature of the electrode 108 or sample stage 109 is also adjusted by a coolant adjusted to a predetermined temperature that circulates inside the sample stage 109 and has a coolant flow path 204 arranged concentrically or spirally around the central axis in the vertical direction of the sample stage 109, located below the tip that detects the temperature of the temperature sensor 203 inside the electrode 108 along with the heat generated by the heater electrode 202.

In this example, one temperature sensor 203 corresponding to each heater electrode 202 in each zone may be placed below. Also, as shown in this example, one temperature sensor corresponding to each circular or ring-shaped region may be placed at a location within the projection range of that region.

The upper surface of the dielectric film 120 above the ESC electrode 201 is provided with a ring-shaped convex portion 206 arranged at the outermost periphery and surrounding the inside, and a plurality of convex portions 207 arranged on the upper part of the dielectric film 120 inside the ring-shaped convex portion 206, and the upper surfaces of these convex portions come into contact with the back surface of the wafer 113, which is placed on the top surface of the dielectric film 120 and electrostatically attracted, and press against each other. When DC power is supplied from the DC power source 111 to the ESC electrode 201 inside the dielectric film 120 and a specific potential is applied, the molecules or atoms in the member including the back surface of the wafer 133 are polarized according to the charge inside the ESC electrode 201, generating charges, and an electrostatic force is generated between the dielectric material of the dielectric film 120 above the ESC electrode, generating an electrostatic force that attracts the wafer 113 and the ESC electrode 201, and as a result, the wafer 113 is attracted to the dielectric film 120 with a predetermined attraction force.

Meanwhile, an exhaust device having a vacuum pump including a turbo molecular pump and a roughing pump such as a rotary pump is connected to the bottom of the vacuum vessel 116 below the bottom, and is arranged in communication with the processing chamber 105 through an exhaust opening at the bottom of the vacuum vessel 116. By driving the vacuum pump, the pressure inside the processing chamber 105 is maintained at a high degree of vacuum with the wafer 113 inside. Normally, the pressure inside the processing chamber 105 during processing of the wafer 113 is set to a value within a range suitable for processing the wafer 113 by balancing the flow rate or speed of the supply of a mixed gas of the processing gas and dilution gas from the processing gas supply path and the flow rate or speed of the exhaust from the exhaust opening.

In such a plasma processing apparatus 100, the wafer 113 is transported inside an opening formed in advance in a cylindrical sidewall member of a vacuum vessel 116 (not shown), and placed on the upper surface of the dielectric film 120 of the sample stage 109 in the processing chamber 105 through a gate, which is a passage for the wafer 113 to be carried into or out of the processing chamber 105 inside the plasma processing apparatus 100. Electric power is supplied from a DC power source 111 to a film-like electrode inside the dielectric film 120, generating an electrostatic force, and the wafer 113 is attracted to the upper surface of the dielectric film 120, adsorbed, and held. In this state, a gas with high thermal conductivity such as He gas from a gas source is supplied through a gas passage (not shown) to the gap (hereinafter also referred to as a gap) between the wafer 113 and the upper surface of the dielectric film 120, promoting the transfer of heat between the wafer 113 and the coolant circulating and flowing in the coolant flow passage formed in the electrode 108.

In this state, a processing gas is supplied into the processing chamber 105, and a plasma 106 is formed inside the processing chamber 105 by an interaction between the processing gas and an induced current formed by an induction magnetic field formed by the induction coil 103 at the top of the processing chamber 105 immediately below the window member 104 or the shower plate by high-frequency power supplied from the high-frequency power source 101, and particles of the plasma 106 are used to etch the film layer to be processed on the upper surface of the wafer 113. The etching process of the film layer to be processed on one wafer 113 performed in this embodiment includes multiple processes (steps) with different processing conditions including a suitable temperature range for implementation, as described below, and includes a transition step for transitioning the temperature of the wafer 113 or the sample stage 109 on which it is placed and held, or the upper surface of the dielectric film 120, from the conditions of the previous process to the conditions of the subsequent process between the previous and subsequent etching processes.

When the control device 115 detects that the etching process has reached the target remaining film thickness or the end point upon receiving an output signal from an end point detector (not shown), the plasma 106 is extinguished in response to a command signal from the control device 115, and the supply of high frequency bias power from the high frequency bias power supply 110 is stopped. After this, a process is carried out to release the static electricity or electrostatic force of the wafer 113 electrostatically attracted to the top surface of the dielectric film 120, and the wafer 113 is moved upward from inside the electrode 108 of the sample stage 109 by driving a number of pins stored in a number of through holes (three in this example) (not shown) arranged inside the sample stage 109. As a result, the wafer 113 placed in contact with the tips of these pins is lifted up and held above the top surface of the dielectric film 120.

In this state, the wafer 113 is unloaded from the plasma processing apparatus 100, and if there is an unprocessed wafer 113 to be processed next, the unprocessed wafer 113 is loaded into the processing chamber 105 in the same manner as above and placed on the multiple pins. The pins are then driven down and stored again inside the sample stage 109, so that the wafer 113 is placed in contact with the upper surface of the dielectric film 120. After this, the wafer 113 is adsorbed and held on the upper surface of the dielectric film 120 in the same manner as above, and processing begins.

When the control device 115 determines that there is no wafer 113 to be processed next, the etching process of the wafer 113 that manufactures the semiconductor device in the plasma processing device 100 is stopped based on a command signal from the control device 115.

A DC voltage is applied to the electrostatic attraction electrode, one of the film-like electrodes 121 provided in the dielectric film 120, by power from the DC power supply 111, to generate an electrostatic force. The value of this DC voltage is called the ESC voltage (output voltage) of the electrostatic attraction power supply. The average potential of the wafer 113, which is generated by applying the output of the high frequency bias power supply 110 to the electrode 108, is called the self-bias voltage (hereinafter, Vdc). Usually, Vdc is a negative DC voltage.

At this time, the potential difference between the electrode 108 and the wafer 113, i.e., the difference between the ESC voltage and Vdc (Vesc-Vdc), becomes the electrostatic chucking voltage (hereinafter, Vchuck). Vdc depends on the value of the amplitude (peak-to-peak, Vpp) of the high-frequency bias power applied to the wafer 113, and is related by the following equation:

α=|Vdc/Vpp|≦0.5
Here, α is a constant that varies depending on the configuration of the plasma processing apparatus 100, and in a typical etching processing apparatus for semiconductor manufacturing, the value is about 0.3 to 0.45. In this case, Vpp is calculated by a self-bias voltage calculator 114 upon receipt of the output from a Vpp monitor 112 .

Figure 8 shows the relationship between the ESC voltage, Vdc, Vpp, and Vchuck in this embodiment. Figure 8 is a graph that shows a schematic relationship between the DC voltage, high frequency bias voltage, and electrostatic chucking voltage output from the electrostatic chucking power supply supplied to the sample stage of the plasma processing apparatus according to this embodiment shown in Figure 1.

In this diagram, Vdc appears as a negative value with a magnitude equal to the positive real coefficient α times the positive value of Vpp. It can also be seen that there are two ESC voltages, one on the positive side and one on the negative side, that produce a voltage value Vchuck of the same absolute value for the Vdc value. Here, the ESC voltage on the positive side with respect to Vdc is called Vesc+, and the ESC voltage on the negative side is called Vesc-.

As mentioned above, the relationship between the ESC voltage and Vchuck and Vdc in this case is expressed by the following equation:

Vesc ⁺ = Vdc + Vchuck
Vesc ^- = Vdc - Vchuck
Here, Vdc is a negative value, and Vchuck is a positive value.

Here, if Vchuck is too small, the wafer 113 may not be attracted by electrostatic force and may become detached from the sample stage 109 during processing. On the other hand, if Vchuck is excessively large, the electrostatic attraction force may be too strong and the wafer 113 may crack, or even if a process to release the electrostatic force is performed, static electricity may remain and the wafer 113 may not be able to be detached from the sample stage 109, or the wafer 113 may be damaged or fall off when trying to peel it off with a large force. Therefore, in order to improve the efficiency of processing the wafer 113, it is necessary to adjust the value of Vchuck to an appropriate range to prevent problems with peeling or damage to the wafer 113.

In addition, if the resistance of the inner wall of the processing chamber 105 with which the plasma 106 comes into contact is high, there is a problem of abnormal discharge occurring between the plasma 106 and the inner wall. For example, when a positive ESC voltage is applied to the electrode 108 using the monopole method and plasma 106 is generated for processing, a minute leakage current I, shown by the dotted line in FIG. 1, flows into the plasma. At this time, if the resistance R of the inner wall of the processing chamber 105 is high, the plasma is positively charged by V=IR, and the plasma potential becomes positive. When the plasma potential becomes higher than a certain level, abnormal discharge occurs due to dielectric breakdown of the insulator layer on the inner wall surface of the processing chamber. Then, there is a risk of a problem of contamination occurring inside the processing chamber 105 and on the wafer 113 due to the generation of foreign matter caused by the abnormal discharge.

The flow of operations performed by the control device 115 to set the ESC voltage in this embodiment will be described below with reference to FIG. 6. FIG. 6 is a flowchart showing the flow of operations for setting the ESC voltage in the plasma processing apparatus according to the embodiment shown in FIG. 1.

First, the value of Vchuck is set in advance, and while high frequency bias power from the high frequency power supply 110 is being supplied to the electrostatic chucking electrode of the film-like electrode 121, the Vpp monitor 112 detects Vpp and outputs a signal to the control device 115 and the self-bias voltage calculator 114 (step 601). The control device 115 calculates Vdc using the Vpp value sent by the self-bias voltage calculator 114 and a constant α determined by a test performed in advance or by theory, and sends the Vdc to the control device 115 (step 602).

Next, the control device 115 reads out the software stored in the storage device (not shown) and calculates the area of the seal part on the upper surface of the ring-shaped protrusion that is placed on the upper surface of the dielectric film 120 (described later) and that contacts the back surface of the wafer 113 placed and held above it by electrostatic attraction and presses against each other to seal the inside and outside (step 603). After that, taking into account the area of the seal part, the control device 115 calculates Vchuck from the values of Vpp and Vdc (step 604). Furthermore, the control device 115 calculates the ESC voltage Vesc ⁺ or ^Vesc- from the calculated value of Vchuck and sends a command signal to the DC power source 111 to adjust the output to the ESC voltage (step 605).

In this case, the control device 115 compares the positive and negative of Vesc ⁺ , i.e., the magnitude between the absolute value of Vdc and Vchuck. When Vesc ⁺ is positive (>0), i.e., |Vdc|<Vchuck, Vesc- is used as the ESC ^voltage , and when Vesc ⁺ is negative (<0), i.e., |Vdc|>Vchuck, Vesc ⁺ is used.

Furthermore, when Vesc ⁺ is used, the ^control device 115 transmits a command signal to the DC power supply 111 so as to add voltage in the negative direction so as to increase the absolute value of the ESC voltage in the negative range at the time of ignition of the plasma 106 if |Vesc ⁺ |<β, and to adjust the ESC voltage to Vesc ⁺ after ignition of the plasma 106, and to adjust the ESC voltage to Vesc ⁺ from the time of ignition of the plasma 106 if |Vesc+|>β. Here, β is a predetermined threshold voltage of a positive value.

By determining the ESC voltage according to the above chart, it is possible to provide a plasma processing apparatus and a plasma processing method that can obtain an appropriate electrostatic adsorption force without causing abnormal discharge.

On the other hand, even if a predetermined operation is performed in a process for releasing the electrostatic force or static electricity of the wafer 113 attracted by electrostatic force after the etching process is completed, the electrostatic force or amount of static electricity may not be reduced enough to peel and lift the wafer 113 from the top surface of the dielectric film 120 by the subsequent upward movement of the pins, and it has been found that the operation of the plasma processing apparatus 100 for manufacturing devices may not be continued. If such a phenomenon occurs, a problem occurs in which the efficiency of processing the wafer 113 using the plasma processing apparatus 100 to manufacture devices is significantly impaired. This phenomenon occurs because an electrostatic force greater than that sufficient to obtain a favorable result of the process is generated during the etching process, causing the wafer 113 to be excessively attracted to the dielectric film 120, and even if the static electricity is reduced according to a predetermined process, static electricity that still attracts the wafer 113 remains. To achieve the goal of preventing the occurrence of such a phenomenon, it is necessary to appropriately increase or decrease the DC power supplied to the film-like electrode for electrostatic attraction in the dielectric film 120 in order to attract the wafer 113, so that the attraction force is within a range that allows the wafer 113 to be detached above the sample stage using a pin.

In this embodiment, the value of the DC power voltage (ESC voltage) output by the electrostatic chucking power supply 111 to the membrane-like electrode for electrostatic chucking is calculated or selected using the Vpp value of the high-frequency bias power detected by the Vpp monitor 112, a preset electrostatic chucking voltage Vchuck, and predetermined constants α and β.

For example, in the case where Vchuck=300V, α=0.4, β=200V, first, if Vpp=300V is detected from the output from the Vpp monitor 112, the self-bias voltage calculation means 114 calculates Vdc as Vpp*α=-120V and transmits this as a signal to the control device 115. The control device 115 that receives this signal reads out software stored in an internal storage device (not shown), compares the detected Vdc with a predetermined condition according to the algorithm, and transmits a command signal to the DC power supply 111 so that |Vdc|<Vchuck (Vesc ⁺ =Vdc+Vchuck>0 in this example) and the ESC voltage ^Vesc- becomes -420V.

Also, when the Vpp monitor 112 detects Vpp=1000V, the self-bias voltage calculation means 114 calculates Vdc=-400V. The control device 115 compares Vdc with Vchuck and determines that |Vdc|>Vchuck, and since Vesc ⁺ <0, transmits a command signal to the DC power supply 111 to adjust the output so that the ESC voltage becomes Vesc ⁺ . Here, since Vesc ⁺ is -100V, |Vesc ⁺ |<β, and only when the plasma 106 is ignited, a command signal is transmitted to the DC power supply 111 to adjust the ESC voltage so that a voltage of about -700V is added to ^Vesc- in the negative direction. The DC power supply 111 in this embodiment is a variable voltage power supply equipped with a function of variably increasing and decreasing the main voltage.

Furthermore, when Vpp=2000V detected by the Vpp monitor 112, the self-bias voltage calculation means 114 that receives the output calculates Vdc to be -800V. The control device 115 then compares Vdc with Vchuck and determines that |Vdc|>Vchuck, and further transmits a command signal to the DC power supply 111 to set the ESC voltage value to Vesc ⁺ since Vesc ⁺ <0. Here, Vesc ⁺ is -500V, and therefore |Vesc ⁺ |>β, it is determined that there is no need to add voltage in the negative direction when the plasma 106 is ignited, and the ESC voltage is maintained at -500V when the plasma 106 is ignited.

As described above, in this embodiment, the value of Vchuck is detected based on the values of Vpp and Vdc detected during processing and the value of the seal area, and the value of Vesc ⁺ or ^Vesc- is calculated using these values, and the ESC voltage is adjusted to the calculated value. This maintains the voltage for electrostatically attracting the wafer 113 within the allowable range of the value of Vchuck, suppressing the occurrence of damage due to cracking, peeling, or dropping of the wafer 113. In addition, the rise in the potential of the plasma 106 due to a positive leakage current is reduced, suppressing the occurrence of abnormal discharge.

An example of an etching process for a wafer 113 having multiple processing steps as described above and a transition step for transitioning the temperature will be described with reference to FIG. 7. FIG. 7 is a graph showing a schematic example of changes in temperature and ESC voltage over time during an etching process performed by the plasma processing apparatus according to the embodiment shown in FIG. 1.

In FIG. 7(a), the film layer to be processed on the wafer 113 is processed under different temperature conditions in each of steps 1 and 2, and a transition step is arranged in which the temperature of the sample stage 109 or wafer 113 is raised after step 1 is completed to approach the temperature conditions of step 2. At this time, the temperature of the sample stage 109 is raised by supplying a predetermined DC power to the heater electrode 202 of the dielectric film 120 to increase the amount of heat generated and heat the wafer 113 and sample stage 109.

As shown in this diagram, when the processing of the wafer 113 in step 1 reaches its end point, the plasma 106 is extinguished and the high frequency bias power is stopped. After this, the absolute values of the ESC voltages Vesc+, Vesc- generated by the power supplied to the ESC electrode 201 are reduced to suit the processing in the next step where the temperature of the wafer 113 is increased. When step 1 is completed, the DC current supplied to the heater electrode 202 and the resulting amount of heat generated from the heater electrode 202 are increased as a transition step, and the temperature of the wafer 113 or sample stage 109 increases toward the set temperature value, which is a processing condition for step 2, the next processing step.

In the transition step, when the control device 115 receives the output from the temperature sensor 203 and determines that the temperature has reached a predetermined tolerance range, the heat generation amount of the heater 202 and the flow of the coolant through the coolant passage 204 are adjusted so that the temperature set value of the step 2 is within the tolerance range. After this, step 2 is started and the next etching process step is performed for the film layer to be processed on the wafer 113. In this example, the ESC voltages Vesc ⁺ and Vesc ^- of the ESC electrodes during the step are maintained at the values of the previous step.

7B shows an example in which the temperature condition of step 2 is lower than that of step 1. In this example as well, when the control device determines that the end point of the etching process of step 1 has been reached, the output from the DC power supply 111 is adjusted, and the absolute values of the ESC voltages Vesc ⁺ and Vesc ^- generated in the ESC electrode 201 are increased to values within a range conforming to the conditions of the next step 2. Thereafter, a transition step is started, the amount of heat generated from the heater electrode 202 is reduced, and the temperature of the sample stage 109 or wafer 113 is reduced and adjusted to a value within the allowable range of the temperature conditions in the etching process of the next step 2.

When the control device 115 detects that the temperature has reached the allowable range, the amount of heat generated by the heater electrode 202 is adjusted so that the temperature is maintained, and the etching process of step 2 is started in this state. Note that in both the examples of Figures 7(a) and (b), the absolute values of Vesc+ and Vesc- are set to values smaller than Vpp.

[Means for determining attraction voltage]
In this embodiment, the wafer 113 is attracted and held on the upper surface of the dielectric film 120 by electrostatic attraction using the Johnson-Rahbek (JR) effect. Such electrostatic attraction using the JR effect or JR force is categorized as JR type. The attraction force Fchuck generated between the ESCESC electrode 201 and the wafer 113 is expressed as Fchuck=Fgap+Fbulk.

Fgap is the electrostatic attraction force generated between the back surface of the wafer 113, which is the upper surface of the gap between the wafer 113 held on the dielectric film 120 and the dielectric film 120, and the upper surface of the dielectric film 120, which is the lower surface of the gap, and Fbulk is the attraction force that pinches the portion of the dielectric material inside the dielectric film 120 between the upper surface of the dielectric film 120, which is the lower surface of the gap, and the ESC electrode. In the case of the JR type, the attraction force Fchuck is predominantly influenced by the attraction force Fgap in the gap between the upper surface of the dielectric film and the back surface of the wafer, and this Fgap is determined by the potential difference Vgap in the gap. That is,
Fgap=1/2*(ε _gap *S*Vgap ² /Tgap ² )
Here, ε _gap is the dielectric constant in the gap, S is the area of the gap as viewed from above, Vgap is the potential difference in the gap, and Tgap is a representative value of the temperature in the gap. Meanwhile, the potential difference Vgap is determined by the current i(T) flowing between the wafer 113 and the dielectric film 120 and the resistance value Rgap of the gap as follows, where T represents temperature.

Vgap(T)=i(T)*Rgap
The current i(T) is calculated as i(T)=Vbulk(T)/Rbulk(T), where Vbulk and Rbulk are the voltage and dielectric constant between the ESC electrode and the upper surface of the ceramic dielectric film. This is the resistance value of the membrane material.
Since the resistance value Rbulk of the ceramic material constituting the dielectric film decreases as the temperature increases, when the voltage Vbulk is constant, the current i(T) increases as the temperature of the electrode increases. Current i(T) If Vgap becomes large, Vgap becomes large, and Fgap becomes large, and there is a risk that the chucking force of the ESC becomes excessive. For this reason, in order to keep the voltage Vgap or Vgap within the allowable range, the wafer 113 or the sample stage 109 It is necessary to reduce the voltage Vbulk as the temperature of the dielectric film including the upper ESC electrode increases.

In this embodiment, a voltage value is calculated by multiplying a predetermined initial value V0 by a coefficient A(T) that changes proportionally with temperature, such as Vbulk = A(T) * V0, and the output from the power supply is adjusted to obtain this Vbulk. Furthermore, the coefficient A(T) may be used as a function of temperature T. For example, when the temperature of the dielectric film is 25°C, A(T) = 1.0, and A(T) = A0 * (T-25) + 1.0 may be used as a linear function of temperature with a certain negative slope A0. This slope A0 is detected and obtained in advance by an experiment or the like. On the other hand, if the temperature of the wafer 113 or the sample stage 109 is to be lowered as a processing condition, the value of the voltage Vbulk is increased.

From the value of Vbulk(T) thus calculated, Vchuck=Vgap+Vbulk is calculated in the control unit 115. Furthermore, using this Vchuck value and the Vdc value obtained from the signal output from the self-bias voltage calculator 114, the output from the DC power supply 111 is adjusted so that the voltage of the ESC electrode (ESC voltage) becomes Vesc ⁺ =Vdc+Vchuck, ^Vesc- =Vdc-Vchuck.

[Means for weighting temperature dependent coefficients]
In this embodiment, the dielectric film 120 has a plurality of zones divided in the radial or circumferential direction, and a plurality of heater electrodes 202 are arranged in each zone, each of which occupies a corresponding one of the zones, and the heater electrodes 202 generate heat by controlling the current supplied from a direct current heater (not shown) connected to each of the zones by the control device 115. Therefore, the upper surface of the dielectric film 120 above each zone and the portion of the wafer 113 above it may be at a different temperature from the portions above the other zones. For this reason, in order to precisely adjust the chucking force affected by Vgap(T) so as to be kept within an allowable range so as to suppress cracking or detachment of the wafer 113, it is necessary to precisely adjust each zone to a target voltage value based on its temperature.

In this embodiment, the above temperature is calculated taking into consideration the suction surface, which is the upper surface of the ring-shaped convex portion 207 arranged around the outer periphery of the dielectric film 120 and surrounding the upper surface of the inner dielectric film 120 along the periphery, and the ring-shaped convex portion made of a dielectric material arranged around the upper opening of the pusher hole in which the pusher pin for moving the wafer 113 up and down above the upper surface of the dielectric film 120 is housed, which is arranged penetrating the dielectric film 120. When the dielectric film 120 is viewed from above, the suction surface of the ring-shaped convex portion 207 and the projection surface of the suction surface on the ring-shaped convex portion around the opening of the pusher pin hole are divided into a specific radial position from the center of each of the ESC electrode 201 regions (ESC regions) are weighted by a coefficient value according to the overlapping ratio of the projection surface of the suction surface on the ring-shaped convex portion around the opening of the pusher pin hole.

The arrangement of the film-like electrode 121 and the convex portions 206, 207 in the dielectric film 120 of the sample stage 109 of this embodiment will be described below with reference to Figs. 3 to 5. Figs. 3 to 5 are top views that typically show the configuration of the upper surface of the dielectric film of the sample stage of the embodiment shown in Fig. 1. In these figures, the outer peripheral adsorption surface 301, which is the upper surface of the ring-shaped convex portion 206 arranged on the outer peripheral edge portion arranged on the upper surface of the dielectric film 120, and the pin hole adsorption surface 302, which is the upper surface of the ring-shaped convex portion arranged surrounding the opening periphery at the upper end of the pusher pin hole 308, are shown by solid lines, and further, the ESC region where the ESC electrode 201 is arranged and the zone where the heater electrode 202 is arranged are displayed superimposed and are each shown by dashed lines.

In FIG. 3, the ESC electrode 201 includes an ESCin electrode 303 having a circular center and a ring-shaped ESCout electrode 304 arranged on its outer periphery. The heater electrode 202 further includes a zone 305 having a circular center including the innermost center, three zones 306 arranged in an adjacent ring-shaped area on the outer periphery and having arc-shaped strip shapes that have the same radial length and extend over the same angular range in the circumferential direction around the same center, and four zones 307 arranged concentrically adjacent to the outer periphery of these zones 306 and similarly have four arc-shaped strip shapes. When the areas are divided in the radial direction, the zone 305 is divided so that it belongs to the central area, the four zones 307 belong to the peripheral area, and the three zones 306 belong to the intermediate area between them.

In this embodiment, the heater electrodes 202 in each region are supplied with the same amount of adjusted current, and the heater electrodes 302 in the same zone are made of substantially the same material and have substantially the same dimensions and shape, so they are adjusted to generate substantially the same amount of heat. Furthermore, the central region to which zone 305 belongs and the intermediate region to which zone 306 belongs are all included in the ESCin region projected by the ESCin electrode 303, while the peripheral region to which zone 307 belongs is included in the ESCout region projected by the ESCout electrode 304, and are separated from each other. In addition, when viewed from above, the projected region of the ESCin region overlaps with all three pinhole suction surfaces 302, and it can be said that all of the pinhole suction surfaces 302 are within the ESCin region.

In this configuration, the temperature T of each attraction surface is detected using a coefficient B weighted by the proportion of the area of the pusher hole attraction surface 302 where the area of the multiple heater electrodes 202 overlaps with each of the in-out areas of the multiple ESC electrodes 201 to which the ESC voltage is applied, and a coefficient C weighted by the proportion of the area of the peripheral attraction surface 301, and the ESC voltage is calculated from Vgap(T) at the detected temperature, and the control device 115 adjusts the output of the DC power supply 111 so that the voltage of the ESC electrode 201 becomes the ESC voltage.

For the embodiment shown in Fig. 3, the control device 115 calculates the temperature of the ESCin area, which is required to calculate Vgap(T) of the ESCin area, which is required to set the ESC voltage in the ESCin area. This temperature is the temperature Tin that represents the ESCin area in order to calculate Vgap(T). The temperature Tin corresponds to the temperature of the portion of the pusher hole suction surface 302 that overlaps with the ESCin area, which is obtained by interpolating the temperature or heat of other areas. The temperature Tin is expressed as follows, where Bi (i = c, m, e) is a coefficient indicating the influence from other areas: Tin = Bc ⁱⁿ * Tc + Bm ⁱⁿ * Tm + Be ⁱⁿ * Te
The coefficient Bi (i=c, m, e) is determined as follows based on the ratio of the area of the entire pusher hole suction surface 302 that overlaps with the ESCin area and the ESCout area. That is, for example, when the area of the pusher hole suction surface 302 is 200 ^mm2 ,
Dc ⁱⁿ =200mm ^2
Dmin = ^0mm2
De ⁱⁿ =0mm ²
It becomes.

Therefore, the coefficient B is Bi ⁱⁿ =Di ⁱⁿ /ΣDi ⁱⁿ (i=c, m, e)
Then,
Bc ⁱⁿ =200/(200+0+0)=1
Bm ⁱⁿ =0/(200+0+0)=0
Be ⁱⁿ =0/(200+0+0)=0
Therefore, the temperature Tin in the ESCin region is Tin = Bc ⁱⁿ * Tc + Bm ⁱⁿ * Tm + Be ⁱⁿ * Te = Tc + 0 + 0
Using this Tin value, Vbulk(T) of the ESCin area 304 is found, and Vgap(T) and Vchuck(T) are calculated. The temperature Tout, which represents the temperature T, is 0, but Vesc ⁺ and ^Vesc- are calculated from the value of Vchuck(T) in the ESCin area 304, and the target value of the ESC voltage of the ESCout electrode 303 is determined.

On the other hand, in the examples shown in Figures 4 and 5, the projected area of the pusher hole suction surface 302 overlaps both the ESCin area and the ESCout area, and has an area overlapping each area. In this case, each area is expressed as Dc ⁱⁿ = 150 mm ^2
Dmin = ^50mm2
De ⁱⁿ =0mm ²
Therefore, the coefficient Bi ⁱⁿ is
Bc ⁱⁿ =150/(200+0+0)=0.75
Bm ⁱⁿ =50/(200+0+0)=0.25
Be ⁱⁿ =0/(200+0+0)=0
Therefore, the temperature Tin of the ESCin region of the pusher hole suction surface 302 is Tin=Bc ⁱⁿ *Tc+Bm ⁱⁿ *Tm+Be ⁱⁿ *Te=0.75Tc+0.25Tm+0
Similarly, the temperature Tm of the portion of the pusher hole suction surface 302 overlapping with each ESC region is also calculated.

Furthermore, in this example, the ESCout region does not overlap with the region projected from above the pusher hole suction surface 302, and the temperature representing the ESCout region is Tout, which corresponds to the temperature of the peripheral suction surface 301 interpolated with the temperature or heat from other regions. The temperature Tout is expressed by the following equation, where Ci (i=c, m, e) is a coefficient indicating the influence from other regions:
Tout=Cc ^out *Tc+Cm ^out *Tm+Ce ^out *Te
The coefficient Ci (i=c, m, e) is determined by the proportion of the ESCout portion to the entire area of the peripheral suction surface 301. For example, when the area of the peripheral suction surface 301 is 5000 ^mm2 , the coefficient Ci is expressed as follows:
Dc ^out =0mm ²
Dm ^out =0mm ²
De ^out =5000mm ²
It becomes.

Therefore, the coefficient C is Ci ^out = Ci ^out / ΣCi ^out (i = c, m, e)
Then,
Cc ^out =0/(0+0+5000)=0
Cm ^out =0/(0+0+5000)=0
Ce ^out =5000/(0+0+5000)=1
Therefore, the temperature Tout of the ESCout region is Tout=Cc ^out *Tc+Cm ^out *Tm+Ce ^out *Te=0+0+Te
and is the same as the temperature of the outer peripheral region. Using this Tout value, Vbulk(T) of the ESCout region 303 is found, and Vgap(T) and Vchuck(T) are calculated. Meanwhile, the temperature Tin representing the ESCin region 304 is 0, but Vesc ⁺ and ^Vesc- are calculated from the value of Vchuck(T) of the ESCout region 303, and the target value of the ESC voltage of the ESCin electrode 304 is determined.

According to the above embodiment, the ESC voltage of each area is adjusted according to the temperature of the chucking surface overlapping each ESC area, and excessive chucking force is prevented from occurring, which may cause cracking or falling off of the wafer 113, or poor chucking such as insufficient chucking, thereby improving the efficiency or yield of processing the wafer 113.

101 High frequency power source,
102 Matching box,
103 induction coil,
104 Window member,
105 Processing chamber,
106 Plasma,
107 Earth electrode,
108 electrode,
109 sample stage,
110 high frequency bias power supply,
111 DC power source,
112 Vpp monitor,
113 wafer,
114 Self-bias voltage calculator;
115 control device.
116 vacuum vessel.

Claims (4)

a dielectric film disposed on the upper surface of the sample stage and having a plurality of film-like electrostatic adsorption electrodes to which DC power is supplied for electrostatically adsorbing the wafer; an electrode disposed inside the sample stage below the dielectric film and to which radio-frequency power is supplied; a plurality of through holes having openings on the upper surface of the dielectric film and housing pins on the inside thereof for pushing the wafer upward from the upper surface and holding it at its tip; a ring-shaped first convex portion disposed on the upper surface of the dielectric film and arranged on the outer periphery of the upper surface of the dielectric film surrounding the inside including the openings of the plurality of through holes; and a ring-shaped second convex portion disposed on the upper surface of the dielectric film and surrounding the periphery of each of the plurality of through holes inside the ring-shaped first convex portion,
a control device that calculates a difference between a voltage of the electrostatic chucking electrode and a self-bias voltage Vdc of the wafer based on a magnitude of amplitude Vpp of the high frequency power and a self-bias voltage Vdc of the wafer caused by the high frequency power in accordance with a temperature of the chucking surface of the first or second convex portion , and adjusts the DC power supplied to the electrostatic chucking electrode so that the voltage of the electrostatic chucking electrode reaches a target value obtained by using the difference , 2. The plasma processing apparatus according to claim 1, wherein the control device adjusts the DC power supplied to the electrostatic attraction electrodes in response to a temperature of the attraction surface detected in response to a proportion of an area of an overlapping surface of a projection of the attraction surface of the first or second convex portion as viewed from above with each of the plurality of electrostatic attraction electrodes. The plasma processing apparatus according to claim 1 or 2, wherein the control device adjusts the DC power supplied to the electrostatic adsorption electrode based on the potential difference between the electrostatic adsorption electrode and the wafer, which changes in proportion to the detected temperature of the adsorption surface, so that the electrostatic force for electrostatically adsorbing the wafer is within an allowable range. The plasma processing apparatus according to claim 1 or 2, further comprising a plurality of temperature sensors arranged at locations within the projection plane of each of the plurality of electrostatic chucking electrodes inside the sample stage as viewed from above, and the control device adjusts the DC power supplied to the electrostatic chucking electrodes according to the result of calculating the temperature of the chucking surface by weighting the temperature detected from the output of each of the temperature sensors according to the proportion of the area of the chucking surface that overlaps with each of the plurality of electrostatic chucking electrodes.

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