JP7607286B2 - Nitride semiconductor light emitting device - Google Patents

Description

The present invention relates to a nitride semiconductor light-emitting device, and in particular to a nitride semiconductor light-emitting device in which multiple nitride semiconductor layers are formed on a GaN substrate.

Recent research and development into laser diodes (hereafter abbreviated as "LD") using nitride semiconductors has led to progress in increasing output and longer oscillation wavelengths (blue to green region). In detail, for example, blue LDs with a wavelength of 455 nm and an optical output of over 5 W, and green LDs with a wavelength of 532 nm and an optical output of over 1 W have been realized.

Such nitride semiconductor LDs have a structure in which multiple nitride semiconductor layers are formed on a GaN substrate (see, for example, Patent Document 1).

JP 2015-159327 A

The characteristics of an LD are determined by the parameters of the optical confinement coefficient Γ, the injection efficiency ηi, and the internal loss αi. Note that ηi is generally defined as the internal efficiency, which is the product of the internal quantum efficiency and the current injection efficiency, but since the carrier density in an LD is sufficiently high, the internal quantum efficiency is considered to be approximately 1. Therefore, in an LD, ηi is essentially synonymous with the current injection efficiency, so here ηi is used as the injection efficiency. Here, the optical confinement coefficient Γ refers to the proportion of light that is confined in the active layer among the light propagating in the LD resonator. The injection efficiency ηi refers to the proportion of carriers that are injected into the active layer among the generated carriers. The internal loss αi refers to the amount of light absorbed in the LD resonator while propagating through the resonator.

At present, LDs in the visible light region using nitride semiconductors are estimated to have an optical confinement factor Γ in the low 2% range, an injection efficiency ηi of about 60%, and an internal loss αi of about 1 cm ^-1 . When considering the realization of LD characteristics higher than those currently available, it is considered important to further increase the value of ηi, since the value of αi is already sufficiently small and the value of Γ is already sufficiently large.

One way to increase the injection efficiency ηi is to suppress the phenomenon in which electrons injected into the active layer pass through the active layer without recombining with holes, i.e., electron overflow. One way to suppress electron overflow is to reverse the internal electric field in the active layer. This will be explained with reference to Figures 1A to 2B.

Figure 1A is a cross-sectional view showing a typical structure of a nitride semiconductor LD in the visible light region, in which a laminate of nitride semiconductors including an active layer 72 is formed on a GaN substrate 3. Figure 1B is a graph showing the energy of the conduction band near the active layer 72 in the nitride semiconductor LD shown in Figure 1A. In Figure 1B, the horizontal axis shows the height position, and the vertical axis shows the energy of the conduction band. Figure 1B is illustrated so that the direction moving to the right of the paper becomes farther away from the GaN substrate 3 (the upward direction of the paper in Figure 1A). In other words, in Figure 1A, it is assumed that an n-type semiconductor layer 71, an active layer 72, and a p-type semiconductor layer 73 are laminated in this order on the upper surface of the GaN substrate 3.

General nitride semiconductor LDs, including the nitride semiconductor LD described in Patent Document 1, are manufactured by epitaxially growing nitride semiconductors (71, 72, 73) on the +C side main surface (Ga polarity surface) of the GaN substrate 3. At this time, an internal electric field is inevitably generated due to the difference in lattice constants. The details are as follows. Note that the "+C side main surface" is appropriately written as the "+C surface."

In a nitride semiconductor LD, a nitride semiconductor containing In (typically InGaN) is used for the active layer 72. InGaN is a mixed crystal of GaN and InN. Note that in this specification, the notation InGaN omits the composition ratio of In and Ga, and does not mean that the two are mixed in a 1:1 ratio. The same is true for AlGaN and AlInGaN, etc.

Here, there is a difference in lattice constant between GaN and InN. Specifically, in the a-axis direction, the lattice constant of GaN is 0.319 nm, while the lattice constant of InN is 0.354 nm. Therefore, when an InGaN layer containing InN with a larger lattice constant than GaN is grown above the GaN layer in the c-axis direction, the InGaN layer is subjected to compressive strain in the growth plane direction. At this time, the balance of polarization between positively charged Ga and In and negatively charged N is lost, and an electric field is generated along the c-axis direction (piezoelectric field). This piezoelectric field becomes more pronounced as the In composition increases. Longering the oscillation wavelength of a nitride semiconductor LD to a blue to green band means increasing the In composition of the nitride semiconductor that constitutes the active layer, which inevitably increases the piezoelectric field.

The piezoelectric field causes distortion of the energy band of the active layer 72. Specifically, the polarization phenomenon caused by the piezoelectric field causes the energy bands of both the well layer and the barrier layer that make up the active layer 72 to tilt in different directions. This polarization phenomenon caused by the piezoelectric field is generally called the Quantum Confined Stark Effect (QCSE).

Figure 1B shows a case where the active layer 72 includes barrier layers (B1, B2, B3) and well layers (W1, W2). When nitride semiconductors (71, 72, 73) are stacked on the +C face of the GaN substrate 3, a piezoelectric field is generated from the p-side to the n-side. Due to the piezoelectric field, the bottom of the band of the well layers (W1, W2) drops in the direction from the n-side to the p-side. On the other hand, the change near the top of the band of the barrier layers (B1, B2, B3) rises in the direction from the n-side to the p-side.

According to FIG. 1B, the energy corresponding to the top of the band of the barrier layer B3 closest to the p-side is lower than the energy corresponding to the top of the band of the barrier layers B1 and B2. Therefore, when a voltage is applied and electrons are injected from the n-side, many of these electrons that do not remain in the well layer W1 but exceed the barrier layer B2 flow out to the semiconductor layer on the p-side without recombining with holes in the well layer W2 (overflow phenomenon). In other words, the overflowed electrons cannot be retained in the active layer, and this phenomenon causes the above-mentioned injection efficiency ηi to decrease.

One method of suppressing overflow is to reverse the direction of the piezoelectric field. For this purpose, for example, as shown in FIG. 2A, a method of epitaxially growing nitride semiconductors (71, 72, 73) on the -C side principal surface (N polarity surface) of GaN substrate 3 is considered. FIG. 2B is a graph showing the conduction band energy in the vicinity of active layer 72 in the nitride semiconductor LD shown in FIG. 2A, following the example of FIG. 1B. In the following, the "-C side principal surface" will be referred to as the "-C surface" as appropriate.

Compared to FIG. 1B, in FIG. 2B, the direction of the piezoelectric field is reversed, so that the bottom of the band in the well layers (W1, W2) is lowered in the direction from the p-side to the n-side. Meanwhile, the top of the band in the barrier layers (B1, B2, B3) is raised in the direction from the p-side to the n-side. As a result, when a voltage is applied and electrons are injected from the n-side, many of these electrons that pass over the barrier layer B2 tend to remain in the well layer W2. As a result, compared to the case of FIG. 1B, the probability of holes and electrons recombining is increased, and it is expected that the luminous efficiency will increase.

However, at the time of filing this application, there is no known technology for growing a nitride semiconductor layer with good film quality on the -C plane of a GaN substrate. When a nitride semiconductor layer is grown on the -C plane of a GaN substrate, there is a tendency for significant unevenness to appear on the surface, as well as numerous crystal defects and cracks.

Another method is to stack an active layer and an n-type semiconductor layer in that order on the +C plane of a p-type GaN substrate. However, as of the time of filing this application, p-type GaN substrates have not been realized or put into practical use, so this method is also difficult to use as a manufacturing method for industrial nitride semiconductor LDs.

As yet another method, a method can be considered in which a nitride semiconductor layer is grown on the +C plane of an n-type GaN substrate in the order of a p-type semiconductor layer, an active layer, and an n-type semiconductor layer. However, with this method, a diode connection is formed between the n-type GaN substrate and the p-type semiconductor layer, with a bias opposite to that between the p-type semiconductor layer and the n-type semiconductor layer that sandwich the active layer. As a result, it is necessary to apply an extremely high voltage to pass a current through the active layer.

In view of the above problems, the present invention aims to provide a nitride semiconductor light-emitting device that can be manufactured using a method that allows for mass production and that can reverse the direction of the piezoelectric field compared to conventional methods.

The nitride semiconductor light emitting device according to the present invention comprises:
an n-type GaN substrate;
a first semiconductor layer located on an upper layer of a main surface on the +C side of the GaN substrate and made of a nitride semiconductor containing an n-type impurity;
a second semiconductor layer located above the first semiconductor layer, made of a nitride semiconductor containing both n-type impurities and p-type impurities, and forming a tunnel junction;
a third semiconductor layer located above the second semiconductor layer, made of a nitride semiconductor containing p-type impurities, and forming a p-side clad layer;
a fourth semiconductor layer located above the third semiconductor layer, made of a nitride semiconductor containing p-type impurities or undoped, and forming a p-side guide layer;
an active layer made of a nitride semiconductor and located above the fourth semiconductor layer;
a fifth semiconductor layer formed on the active layer, made of an n-type impurity-containing or undoped nitride semiconductor, and forming an n-side guide layer;
a sixth semiconductor layer located above the fifth semiconductor layer, made of a nitride semiconductor containing n-type impurities, and forming an n-side clad layer;
a semiconductor stack including the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the fourth semiconductor layer, the active layer, the fifth semiconductor layer, and the sixth semiconductor layer has three or more different widths when viewed in a direction parallel to the primary surface, and exhibits a stepped shape in which the widths become wider as the stack approaches the GaN substrate in a direction perpendicular to the primary surface;
The semiconductor laminate is characterized in that, when viewed from a direction parallel to the main surface, the width changes at a first height position within the fifth semiconductor layer and at a second height position within a region sandwiched between a surface of the third semiconductor layer closer to the active layer and a surface of the first semiconductor layer closer to the GaN substrate.

In the nitride semiconductor light-emitting element having the above configuration, an n-type first semiconductor layer, a p-type third semiconductor layer, an active layer, and an n-type sixth semiconductor layer are stacked in this order from the side closest to the +C surface on the upper layer of the main surface (+C surface) of the +C surface of an n-type GaN substrate (however, notation of some semiconductor layers is omitted). For this reason, if the nitride semiconductor light-emitting element does not include the second semiconductor layer, when a voltage is applied so that the GaN substrate side becomes the anode and the sixth semiconductor layer side becomes the cathode, a reverse bias voltage is applied between the first semiconductor layer and the third semiconductor layer, and therefore an extremely high voltage is required to pass a current through the active layer.

However, in the nitride semiconductor light-emitting device having the above configuration, the second semiconductor layer made of a nitride semiconductor containing both n-type impurities and p-type impurities is arranged so as to be sandwiched between the n-type first semiconductor layer and the p-type third semiconductor layer. The second semiconductor layer is configured to form a tunnel junction. More specifically, the second semiconductor layer contains high concentrations of both n-type impurities and p-type impurities, forming a narrow gap that separates the n-type first semiconductor layer and the p-type third semiconductor layer. For this reason, electrons can be moved from the valence band of the third semiconductor layer to which a reverse bias is applied, via the second semiconductor layer, toward the conduction band of the first semiconductor layer. As a result, a current can be passed from the n-type first semiconductor layer toward the p-type third semiconductor layer at a low voltage.

And, according to this configuration, an active layer is formed on top of the p-type third semiconductor layer, and an n-type sixth semiconductor layer is formed on top of that active layer. Therefore, by sequentially growing each semiconductor layer on the +C face of the n-type GaN substrate, in terms of device structure, it is essentially equivalent to growing the active layer on the -C face side of the n-type semiconductor layer. As a result, the energy of the conduction band near the active layer becomes the same as in FIG. 2B, and the effect of suppressing the overflow phenomenon is obtained.

However, it is known that it is more difficult to convert nitride semiconductors to p-type than to n-type. The reason for this is thought to be that hydrogen contained in the raw material gas used to introduce acceptors such as magnesium (Mg) inhibits the activation of the acceptors. Therefore, in conventional nitride semiconductor light-emitting devices, after the p-type semiconductor layer is grown, an annealing process for activation using an infrared lamp or the like is generally performed. This annealing process removes hydrogen and generates holes, thereby realizing activation (p-type conversion).

As shown in FIG. 1A, in the manufacture of a conventional nitride semiconductor light-emitting device, an n-type semiconductor layer 71, an active layer 72, and a p-type semiconductor layer 73 are epitaxially grown in this order on the upper layer of an n-type GaN substrate 3, and then an annealing process is performed. In other words, when the annealing process is performed, the p-type semiconductor layer 73 is exposed on the upper surface, so hydrogen can be easily removed.

However, in the nitride semiconductor light-emitting device having the above configuration, the p-type third semiconductor layer is not located on the top surface, and an active layer and an n-type sixth semiconductor layer are formed above it. In addition, an n-type first semiconductor layer is also formed below the third semiconductor layer. For this reason, even if an annealing process is performed after the epitaxial growth of all the semiconductor layers is completed, hydrogen cannot be sufficiently removed.

It is also possible to stop epitaxial growth immediately after the formation of the third or fourth semiconductor layer, perform an annealing treatment to convert the semiconductor layer to p-type, and then continue epitaxial growth again to form the remaining semiconductor layers. However, this method cannot be adopted for the following reasons. Ammonia is used as a source gas when growing an n-type semiconductor layer (sixth semiconductor layer, etc.). This is because hydrogen derived from this ammonia may be incorporated into the lattice in the third semiconductor layer, which has been converted to p-type, inhibiting the generation of holes.

Here, the semiconductor laminate included in the nitride semiconductor light-emitting device according to the present invention has three or more different widths when viewed in a direction parallel to the main surface, and exhibits a stepped shape in which the width increases in a direction perpendicular to the main surface toward the GaN substrate. More specifically, when viewed in a direction parallel to the main surface, the semiconductor laminate has a structure in which the width changes at the boundaries of a position in the fifth semiconductor layer (first height position) and a position in the region sandwiched between the surface of the third semiconductor layer closer to the active layer and the surface of the first semiconductor layer closer to the GaN substrate (second height position). In practice, after epitaxial growth of the semiconductor laminate, it is processed by etching or the like to form the above-mentioned stepped structure, and then annealed.

When the second height position exists within the third semiconductor layer, the upper surface of the p-type third semiconductor layer is exposed immediately before the annealing process is performed. Therefore, hydrogen is removed through the upper surface of the third semiconductor layer, and the third semiconductor layer can be converted to p-type. It is also possible to provide a p-type contact layer between the second semiconductor layer and the third semiconductor layer, and the same discussion is also possible when the second height position exists within this p-type contact layer.

Furthermore, when the second height position exists within the second semiconductor layer forming the tunnel junction, the upper surface within the second semiconductor layer is exposed immediately before the annealing process is performed. Since the second semiconductor layer also contains p-type impurities, the desorption of hydrogen is similarly promoted.

The second height position may be present within the first semiconductor layer. In this case, the top surface of the n-type first semiconductor layer is exposed immediately before the annealing process is performed. However, with this configuration, each semiconductor layer (p-type semiconductor layer) that needs to be converted to p-type is largely etched, and the volume of the p-type semiconductor layer that needs to be activated is reduced. In other words, the p-type conversion can be achieved by desorption of hydrogen only through the exposed side surface of each semiconductor layer that contains p-type impurities.

The semiconductor stack provided in the nitride semiconductor light-emitting device according to the present invention has a structure in which the width becomes narrower as one moves away from the GaN substrate, starting from a position (first height position) in the fifth semiconductor layer constituting the n-side guide layer. In detail, the n-side guide layer (fifth semiconductor layer) and cladding layer (sixth semiconductor layer) located above the first height position (in the direction away from the GaN substrate) are narrower than the active layer located below them. Hereinafter, the area above this first height position will be referred to as the "ridge portion."

By adopting a structure having the ridge portion, when a voltage is applied, current tends to concentrate only in the region directly below the ridge portion in the active layer. As a result, the region directly below the ridge in the active layer selectively emits light, making it easier to create standing waves in the horizontal transverse mode. This increases the output of the extracted laser light.

In a direction perpendicular to the main surface, the distance between the first height position and the surface of the active layer facing the fifth semiconductor layer may be 30 nm to 350 nm.

This increases the effect of concentrating the current only in the region directly below the ridge in the active layer, thereby improving the output of the laser light.

The fourth semiconductor layer may be made of an undoped nitride semiconductor and may have a thickness of 100 nm to 300 nm.

As described above, the semiconductor laminate included in the nitride semiconductor light-emitting device according to the present invention has an active layer formed on the p-type third semiconductor layer. In other words, the active layer is epitaxially grown after the p-type third semiconductor layer is epitaxially grown.

Here, when a p-type semiconductor layer is epitaxially grown in a furnace, atoms (especially Mg) derived from the p-type impurities remain in the furnace, and these atoms are likely to be incorporated during the subsequent growth of the semiconductor layer. In addition, some of the Mg introduced into the p-type semiconductor layer during epitaxial growth may diffuse into the semiconductor layer that is subsequently epitaxially grown. When Mg is incorporated into the active layer, the non-radiative levels of Mg form non-radiative recombination centers, which may reduce the luminous efficiency.

In contrast, by forming an undoped fourth semiconductor layer with a thickness of 100 nm or more between the third semiconductor layer and the active layer as described above, the p-type impurities remaining in the furnace after the growth of the third semiconductor layer are incorporated into the fourth semiconductor layer, thereby reducing the amount of p-type impurities incorporated into the subsequently grown active layer. This prevents a decrease in luminous efficiency.

However, if the fourth semiconductor layer is made too thick, it will form a pseudo-resistance, increasing the applied voltage. From this perspective, it is preferable for the thickness of the fourth semiconductor layer to be 300 nm or less.

the third semiconductor layer and the sixth semiconductor layer are both made of a nitride semiconductor containing Al,
The Al composition of the sixth semiconductor layer may be lower than the Al composition of the third semiconductor layer.

Semiconductor lasers usually emit light in an oscillation mode that is a mixture of many higher-order transverse modes. For this reason, as the output increases, the mode can easily shift to a different transverse mode or a combination of different modes, causing the position of the light-emitting point to move and the light output to fluctuate (a phenomenon known as a kink).

One possible solution to the kink problem is to increase the difference in refractive index in the lateral direction to control the light confinement. In particular, one possible method is to increase the difference in refractive index between the region directly below the ridge and the region outside of the ridge in the semiconductor stack. Specifically, one possible method is to make the Al composition of the semiconductor layer present in the ridge above the active layer lower than the Al composition of the layer below the active layer.

However, as shown in FIG. 1A, in the conventional nitride semiconductor light emitting device, the p-type semiconductor layer is located on the side farther from the GaN substrate (upper side). Therefore, if the Al composition of the semiconductor layer present in the ridge portion is made lower than the Al composition of the layer below the active layer, the peak position of the light intensity distribution in the active layer approaches the ridge side, i.e., the p-type semiconductor layer side. However, in the case of GaN, the activation rate of p-type is lower than that of n-type, so in order to realize p-type, it is necessary to dope p-type impurities (Mg, etc.) at a concentration of 1×10 ¹⁹ /cm ³ or more. As a result, there is a problem that the light absorption loss due to Mg increases. Furthermore, since the p-type impurity diffuses to the active layer side, the light absorption loss due to Mg tends to increase, so it is not preferable to move the peak position of the light intensity distribution in the active layer closer to the p-type semiconductor layer side. 1A, in order to suppress the decrease in quantum efficiency due to optical absorption loss in conventional nitride semiconductor light-emitting devices, it is necessary to make the Al composition of the semiconductor layer present in the ridge portion higher than the Al composition of the layers below the active layer, and to shift the peak position of the light intensity distribution in the active layer to the side away from the p-type semiconductor layer (the n-type semiconductor layer side). However, in that case, the refractive index difference cannot be achieved, and kinks are likely to occur.

In contrast, with the above configuration, the n-type semiconductor layer (sixth semiconductor layer) is located on the side farther (upper) from the GaN substrate. In this case, the Al composition of the semiconductor layer present in the ridge portion can be made lower than the Al composition of the layer below the active layer, and the peak position of the light intensity distribution in the active layer can be moved closer to the n-type semiconductor layer side. In this case, a refractive index difference can be obtained, and the problem of reduced quantum efficiency, as in the conventional nitride semiconductor light-emitting device shown in Figure 1A, is less likely to occur. In other words, measures can be taken against kinks while suppressing the reduction in quantum efficiency.

The nitride semiconductor light-emitting device of the present invention allows a semiconductor layer to be formed on the +C plane of an n-type GaN substrate while reversing the direction of the piezoelectric field from that of conventional devices.

FIG. 1 is a cross-sectional view showing a schematic structure of a typical nitride semiconductor LD in the visible light region. 1B is a graph showing the energy of the conduction band in the vicinity of the active layer in the nitride semiconductor LD shown in FIG. 1A. FIG. 1 is a cross-sectional view that illustrates a schematic structure of a nitride semiconductor LD in which a nitride semiconductor is epitaxially grown on a main surface (N-polarity surface) on the −C side of a GaN substrate. 2B is a graph showing the energy of the conduction band in the vicinity of the active layer in the nitride semiconductor LD shown in FIG. 2A. 1 is a cross-sectional view showing a schematic structure of an embodiment of a nitride semiconductor light-emitting device according to the present invention. FIG. 4 is a cross-sectional view that shows a schematic view of only a stacked portion of semiconductor layers extracted from FIG. 3. FIG. 5 is a schematic plan view of FIG. 4 as viewed from the +Z side. 5 is a diagram showing an enlarged portion of FIG. 4 with current flows indicated in a simulated manner. 1 is a graph showing the relationship between the injection current and the optical output when d1=50 nm and when d1=500 nm. This shows the results of measuring the near field pattern (NFP) of the light-emitting element while increasing the current when d1=50 nm. 4A to 4C are cross-sectional views illustrating a step of a method for manufacturing the nitride semiconductor light-emitting device shown in FIG. 3. FIG. 2 is a schematic enlarged partial cross-sectional view of the epitaxial layer at the time when step S3 is completed. FIG. 2 is a schematic enlarged partial cross-sectional view of the epitaxial layer at the time when step S3 is completed. FIG. 11 is another schematic partially enlarged cross-sectional view of the epitaxial layer at the time when step S3 is completed. FIG. 11 is another schematic partially enlarged cross-sectional view of the epitaxial layer at the time when step S3 is completed. 13 is a graph showing Mg concentration distribution in the third semiconductor layer, the electron blocking layer, and the fourth semiconductor layer. 1 is a diagram showing a cross-sectional view that typically shows a structure of a semiconductor laminate included in a conventional light-emitting element, together with a schematic diagram of light output distribution in the Z direction. 4 is a diagram showing a cross-sectional view that typically shows the structure of a semiconductor laminate included in the light-emitting element shown in FIG. 3, together with a schematic diagram of the light output distribution in the Z direction. 4 is a cross-sectional view illustrating a structure of another embodiment of a nitride semiconductor light-emitting device according to the present invention. FIG. 4 is a cross-sectional view illustrating a structure of another embodiment of a nitride semiconductor light-emitting device according to the present invention. FIG.

Embodiments of nitride semiconductor light-emitting devices according to the present invention will be described with reference to the drawings. Note that the following drawings are merely schematic illustrations, and the dimensional ratios in the drawings do not necessarily match the actual dimensional ratios. Furthermore, the dimensional ratios between the various drawings do not necessarily match.

In this specification, the expression "a layer Q2 is formed on top of a layer Q1" is intended to include the case where layer Q2 is formed directly on the surface of layer Q1, as well as the case where layer Q2 is formed on the surface of layer Q1 via a thin layer Q3. Here, "thin film" refers to a layer with a thickness of 10 nm or less, and preferably a layer with a thickness of 5 nm or less. Note that in the above, "Q1" and "Q2" are symbols added for convenience of explanation and are not symbols in the drawings.

[structure]
3 is a cross-sectional view showing a schematic structure of an embodiment of a nitride semiconductor light-emitting device (hereinafter, abbreviated as "light-emitting device") according to the present invention. The light-emitting device 1 shown in FIG. 3 includes a GaN substrate 3, and a first semiconductor layer 11, a second semiconductor layer 12, a third semiconductor layer 13, a fourth semiconductor layer 14, an active layer 5, a fifth semiconductor layer 15, and a sixth semiconductor layer 16 formed on the GaN substrate 3.

In the following description, an X-Y-Z coordinate system will be referred to where appropriate, with the main surface of the GaN substrate 3 being the XY plane, and the direction in which the semiconductor layers are stacked relative to the main surface of the GaN substrate 3 being the Z direction. Using this notation, FIG. 3 corresponds to a schematic plan view of the light-emitting element 1 when cleaved in the YZ plane. In this embodiment, the light-emitting element 1 is a laser diode element (LD element), and the resonance direction, i.e., the light emission direction, is the X direction. In this case, the YZ plane corresponds to the light emission surface.

In the following description, when a positive or negative direction needs to be distinguished, it is described with a positive or negative sign, such as "+X direction" and "-X direction". When a direction is described without distinguishing between positive and negative directions, it is simply described as "X direction". In other words, in this specification, when it is simply described as "X direction", both the "+X direction" and the "-X direction" are included. The same applies to the Y direction and the Z direction.

(GaN substrate 3)
The GaN substrate 3 is an n-type substrate. The GaN substrate 3 has a +C surface exhibiting Ga polarity and a -C surface exhibiting N polarity. In Fig. 3, the surface on the +Z side of the GaN substrate 3 is the "+C surface" and the surface on the -Z side is the "-C surface."

(First semiconductor layer 11)
The first semiconductor layer 11 is formed on the +C plane of the GaN substrate 3 and is made of an n-type nitride semiconductor. The first semiconductor layer 11 is doped with an n-type impurity such as Si, Ge, S, Se, Sn, or Te, and preferably the dopant is Si. The first semiconductor layer 11 is, for example, n-type AlGaN.

The film thickness of the first semiconductor layer 11 is 0.1 μm to 10 μm, and preferably 0.5 μm to 5 μm. The n-type impurity concentration of the first semiconductor layer 11 is 1×10 ¹⁷ /cm ³ to 3×10 ¹⁹ /cm ³ , and preferably 5×10 ¹⁷ /cm ³ to 1×10 ¹⁹ /cm ^3. The Al composition ratio of the first semiconductor layer 11 is greater than 0% and equal to or less than 10%, and preferably 1% to 5%.

As a typical example, the first semiconductor layer 11 is made of Al _0.03 Ga _0.97 N having a film thickness of 1 μm and an n-type impurity concentration of 5×10 ¹⁸ /cm ³ .

The first semiconductor layer 11 may be a laminate of an n-type AlGaN layer and an n-type GaN layer. Alternatively, instead of the n-type AlGaN layer, the first semiconductor layer 11 may have a structure including at least one of an n-type AlInN layer, an n-type InGaN layer, and an n-type AlInGaN layer.

(Second semiconductor layer 12)
3 is located above the first semiconductor layer 11 and is made of a nitride semiconductor containing both n-type impurities and p-type impurities. In detail, the second semiconductor layer 12 contains a higher concentration of n-type impurities than the first semiconductor layer 11, and also contains a higher concentration of p-type impurities than the third semiconductor layer 13 described below. The second semiconductor layer 12 is GaN, AlGaN with an Al composition ratio of 0.1% to 5%, or InGaN with an In composition ratio of more than 0% and not more than 10%, and is preferably GaN.

As the n-type impurity contained in the second semiconductor layer 12, Si, Ge, S, Se, Sn, Te, or the like can be used, and Si is preferred. As the p-type impurity contained in the second semiconductor layer 12, Mg, Be, Zn, C, or the like can be used, and Mg is preferred.

The second semiconductor layer 12 is doped with n-type impurities and p-type impurities at a high concentration of 1×10 ²⁰ /cm ³ or more. Preferably, the n-type impurity concentration and the p-type impurity concentration are 1×10 ²⁰ /cm ³ to 3×10 ²¹ /cm ^3. The film thickness of the second semiconductor layer 12 is 2 nm to 30 nm, and preferably 5 nm to 20 nm.

As a typical example, the second semiconductor layer 12 is made of GaN having a thickness of 15 nm, an n-type impurity concentration of 5×10 ²⁰ /cm ³ , and a p-type impurity concentration of 3×10 ²⁰ /cm ³ .

The second semiconductor layer 12 may be a laminate of a GaN layer doped with a high concentration of n-type impurities and a GaN layer doped with a high concentration of p-type impurities. However, even in this case, since a layer doped with a high concentration of n-type impurities and a layer doped with a high concentration of p-type impurities are laminated adjacent to each other, the n-type impurities may diffuse into the p-type layer, and the p-type impurities may diffuse into the n-type layer, resulting in a layer in which both impurities are mixed.

(p-type contact layer 21)
3 includes a p-type contact layer 21 formed on the second semiconductor layer 12. However, it is optional whether the light-emitting element 1 includes the p-type contact layer 21 or not.

The p-type contact layer 21 is doped with a p-type impurity such as Mg, Be, Zn, or C, and preferably the dopant is Mg. The p-type contact layer 21 is, for example, p-type GaN or AlGaN.

The p-type impurity concentration of the p-type contact layer 21 is 5×10 ¹⁸ /cm ³ to 1×10 ²¹ /cm ³ , and preferably 1×10 ¹⁹ /cm ³ to 1×10 ²⁰ /cm ^3. The film thickness of the p-type contact layer 21 is 2 nm to 30 nm, and preferably 5 nm to 20 nm.

(Third semiconductor layer 13)
3 is located above the second semiconductor layer 12 and is made of a nitride semiconductor containing p-type impurities. The third semiconductor layer 13 constitutes a p-side cladding layer with respect to the active layer 5.

The third semiconductor layer 13 is doped with a p-type impurity such as Mg, Be, Zn, or C, and preferably the dopant is Mg. The third semiconductor layer 13 is, for example, p-type AlGaN.

The film thickness of the third semiconductor layer 13 is 100 nm to 1000 nm, and preferably 200 nm to 800 nm. The p-type impurity concentration of the third semiconductor layer 13 is 1×10 ¹⁷ /cm ³ to 5×10 ¹⁹ /cm ³ , and preferably 1×10 ¹⁸ /cm ³ to 3×10 ¹⁹ /cm ^3. When the third semiconductor layer 13 is made of AlGaN, the Al composition ratio is 0.1% to 10%, and preferably 1% to 7% or less.

As an example, the third semiconductor layer 13 is made of p-type Al _0.06 Ga _0.94 N having a thickness of 300 nm and a p-type impurity concentration of 1×10 ¹⁹ /cm ³ .

In this embodiment, the width (length in the Y direction) of the third semiconductor layer 13 varies in some places. More specifically, the width is wider on the side closer to the GaN substrate 3 and narrower on the side farther from the GaN substrate 3.

(Electron Blocking Layer 23)
3 includes an electron blocking layer 23 formed on the third semiconductor layer 13. However, it is optional whether the light-emitting element 1 includes the electron blocking layer 23. Like the third semiconductor layer 13, the electron blocking layer 23 is doped with a p-type impurity such as Mg, Be, Zn, or C, and preferably the dopant is Mg. The electron blocking layer 23 is, for example, p-type AlGaN.

The film thickness of the electron blocking layer 23 is 3 nm to 30 nm, and preferably 5 nm to 20 nm. The p-type impurity concentration of the electron blocking layer 23 is 1×10 ¹⁸ /cm ³ to 5×10 ¹⁹ /cm ³ , and preferably 5×10 ¹⁸ /cm ³ to 3×10 ¹⁹ /cm ^3. When the electron blocking layer 23 is made of AlGaN, the Al composition ratio is 5% to 50%, and preferably 10% to 30%.

As an example, the electron blocking layer 23 is made of p-type Al _0.15 Ga _0.85 N with a film thickness of 10 nm and a p-type impurity concentration of 1×10 ¹⁹ /cm ^3. The electron blocking layer 23 is provided to prevent electrons that have not recombined with holes in the active layer 5 from overflowing toward the third semiconductor layer 13. However, in the light-emitting element 1 of this embodiment, for the same reason as described above with reference to Figures 2A and 2B, the piezoelectric field is in the opposite direction, and therefore the function of suppressing overflow is inherently realized, and therefore the presence of the electron blocking layer 23 is optional, as described above.

(Fourth semiconductor layer 14)
3 is made of a nitride semiconductor, is located above the third semiconductor layer 13, and constitutes a p-side guide layer with respect to the active layer 5. In this embodiment, the fourth semiconductor layer 14 includes a GaN layer 14a and an InGaN layer 14b. However, the fourth semiconductor layer 14 may be configured to include only one of the GaN layer 14a and the InGaN layer 14b.

The GaN layer 14a is, for example, an undoped GaN layer, and has a thickness of 20 nm to 300 nm or less, preferably 50 nm to 200 nm. As an example, the GaN layer 14a is undoped GaN with a thickness of 100 nm.

The InGaN layer 14b is, for example, an undoped InGaN layer. The In composition ratio of the InGaN layer 14b is 0.1% to 10%, and preferably 1% to 7% or less. The thickness of the InGaN layer 14b is 20 nm to 300 nm or less, and preferably 50 nm to 200 nm. As an example, the InGaN layer 14b is undoped InGaN with a thickness of 150 nm.

It is more preferable that the fourth semiconductor layer 14 has an overall thickness of 100 nm to 300 nm. This will be described later.

(Active Layer 5)
3 is made of a nitride semiconductor and is formed on the fourth semiconductor layer 14. The active layer 5 has a quantum well structure, and may be a multiple quantum well structure or a single quantum well structure, but is preferably a multiple quantum well structure.

The emission wavelength of the light-emitting element 1 is determined by the material constituting the active layer 5. As an example, the active layer 5 is formed by repeating two periods of a well layer made of InGaN with a thickness of 10 nm and an In composition ratio of 0.1% to 30%, and a barrier layer made of InGaN with a thickness of 10 nm and an In composition ratio of 0.1% to 5%, which has a larger band gap energy than the well layer. However, the material constituting the active layer 5, the thickness, and the number of periods are set appropriately.

(Fifth semiconductor layer 15)
3 is made of a nitride semiconductor, is located above the active layer 5, and constitutes an n-side guide layer for the active layer 5. In this embodiment, the fifth semiconductor layer 15 includes an InGaN layer 15a and a GaN layer 15b. However, the fifth semiconductor layer 15 may be configured to include only one of the InGaN layer 15a and the GaN layer 15b.

The InGaN layer 15a is, for example, an n-type InGaN layer. The In composition ratio of the InGaN layer 15a is 0.1% to 10%, and preferably 1% to 7% or less. The thickness of the InGaN layer 15a is 20 nm to 300 nm or less, and preferably 50 nm to 200 nm. The n-type impurity concentration of the InGaN layer 15a is 2×10 ¹⁶ /cm ³ to 1×10 ¹⁹ /cm ³ , and preferably 1×10 ¹⁷ /cm ³ to 1×10 ¹⁸ /cm ^3. As an example, the InGaN layer 15a is made of n-type In _0.03 Ga _0.97 N having a thickness of 150 nm and an n-type impurity concentration of 5×10 ¹⁷ /cm ³ .

The GaN layer 15b is, for example, an n-type GaN layer. The thickness of the GaN layer 15b is 20 nm to 300 nm or less, and preferably 50 nm to 200 nm. The n-type impurity concentration of the GaN layer 15b is 2×10 ¹⁶ /cm ³ to 1×10 ¹⁹ /cm ³ , and preferably 1×10 ¹⁷ /cm ³ to 1×10 ¹⁸ /cm ^3. As an example, the GaN layer 15b is n-type GaN with a thickness of 100 nm and an n-type impurity concentration of 5×10 ¹⁷ /cm ³ .

In this embodiment, the width (length in the Y direction) of the fifth semiconductor layer 15 varies in a portion (in this example, in the InGaN layer 15a). More specifically, the fifth semiconductor layer 15 is wide on the side closer to the GaN substrate 3 and narrow on the side farther from the GaN substrate 3.

(Sixth semiconductor layer 16)
3 is located above the fifth semiconductor layer 15 and is made of a nitride semiconductor containing n-type impurities. The sixth semiconductor layer 16 constitutes an n-side cladding layer with respect to the active layer 5.

The sixth semiconductor layer 16 is doped with an n-type impurity such as Si, Ge, S, Se, Sn, or Te, and preferably the dopant is Si. The sixth semiconductor layer 16 is, for example, n-type AlGaN.

The film thickness of the sixth semiconductor layer 16 is 100 nm to 800 nm, and preferably 200 nm to 500 nm. The n-type impurity concentration of the sixth semiconductor layer 16 is 1×10 ¹⁷ /cm ³ to 3×10 ¹⁹ /cm ³ , and preferably 5×10 ¹⁷ /cm ³ to 1×10 ¹⁹ /cm ^3. When the sixth semiconductor layer 16 is made of AlGaN, the Al composition ratio is 3% to 15%, and preferably 5% to 10%.

It is preferable that the Al composition ratio of the sixth semiconductor layer 16 is lower than the Al composition ratio of the third semiconductor layer 13. This point will be described later.

As a typical example, the sixth semiconductor layer 16 is made of Al _0.04 Ga _0.96 N having a film thickness of 350 nm and an n-type impurity concentration of 5×10 ¹⁸ /cm ³ .

(First electrode 61, second electrode 62)
As shown in FIG. 3 , the light emitting element 1 includes a first electrode 61 connected to the sixth semiconductor layer 16 , and a second electrode 62 formed on the rear surface of the GaN substrate 3 .

The first electrode 61 is specifically formed on the surface of the sixth semiconductor layer 16 made of n-type AlGaN, and is preferably made of ITO. However, a contact layer doped with a higher concentration of n-type impurities may be provided on the upper surface of the sixth semiconductor layer 16, and the first electrode 61 may be formed on the upper surface of this contact layer.

The refractive index of ITO is approximately 2.2, which is lower than and close to the refractive index of 2.4 of the GaN layer 15b constituting the n-side guide layer and the refractive index of 2.35 of the AlGaN (sixth semiconductor layer 16) constituting the n-side cladding layer. Therefore, when the first electrode 61 is made of ITO, it is possible to confine light even within the first electrode 61 formed at a position farther away than the fifth semiconductor layer 15 and the sixth semiconductor layer 16 when the active layer 5 is used as a reference.

The first electrode 61 does not necessarily have to have the function of trapping light. In this case, the first electrode 61 is composed of Cr/Pt/Au, Cr/Au, Ti/Au, Ti/Pt/Au, Ti/Al/Ti/Au, Ni/Au, Ni/Al/Ni/Ti/Pt/Au, etc.

In this embodiment, the second electrode 62 is formed on the back surface (-C surface) of the GaN substrate 3. The second electrode 62 is composed of, for example, Cr/Pt/Au, Cr/Au, Ti/Au, Ti/Pt/Au, Ti/Al/Ti/Au, Ni/Au, Ni/Al/Ni/Ti/Pt/Au, etc.

(Pad electrode 63)
3, a pad electrode 63 is formed on the upper surface of the first electrode 61. The pad electrode 63 forms a region for connecting a bonding wire, and is made of, for example, Ti/Au or Ti/Pt/Au.

(Insulating layer 81)
3, the light emitting element 1 includes a protective insulating layer 81 that covers a part of the upper surface and side surfaces of the semiconductor layer. The insulating layer 81 is made of, for example, SiO ₂ , Al ₂ O ₃ , SiN or the like.

[Step structure]
Fig. 4 is a cross-sectional view showing only a stacked portion of semiconductor layers (hereinafter, referred to as "semiconductor stack 8") extracted from the light-emitting element 1 shown in Fig. 3. Fig. 5 is a schematic plan view of Fig. 4 as viewed from the +Z side.

As shown in FIG. 4, the semiconductor laminate 8 has three different widths (W1, W2, W3) when viewed in a direction parallel to the GaN substrate 3 (here, the X direction). Furthermore, these widths increase as they approach the GaN substrate 3 in the Z direction, i.e., as they progress in the -Z direction.

More specifically, in the example of FIG. 4, the width of the semiconductor laminate 8 changes from W1 to a wider W2 when moving in the -Z direction from the first height position H1. Furthermore, the width of the semiconductor laminate 8 changes from W2 to a wider W3 when moving in the -Z direction from the second height position H2.

By narrowing the distance d1 from the first height position H1 to the main surface on the +Z side of the active layer 5, the function of constricting the current in the active layer 5 is realized. Figure 6 is a drawing for explaining the flow of current flowing in the active layer 5, and is a drawing in which the current flow is simulated by adding it to a drawing that is an enlarged portion of Figure 4. However, in Figure 6, the electron blocking layer 23 is omitted from the illustration.

When the distance d1 is longer, the current I2 flows more easily from the p-side, i.e., the third semiconductor layer 13, through the active layer 5 located outside the ridge portion 9 toward the n-side (the fifth semiconductor layer 15 and the sixth semiconductor layer 16). The current I2 does not contribute to the emission of light in the region 5a directly below the ridge portion 9 in the active layer 5. Therefore, the current I2 does not contribute to laser oscillation, and an increase in the current I2 leads to a decrease in the emission efficiency.

In contrast, by shortening the distance d1, the current I1 flowing through the region directly below the ridge portion 9 becomes dominant in the current flowing from the p-side when a voltage is applied. This allows the region 5a directly below the ridge portion 9 in the active layer 5 to selectively emit light, improving the light emission efficiency.

The following Table 1 shows the results of creating samples of light-emitting element 1 while varying the distance d1, and evaluating the I-L (current-light output) characteristics of each. In Table 1, the light output when d1 = 50 nm is taken as the reference light output, and those that showed a light output equivalent to the reference light output (0.9 to 1.1 times) were given an "Evaluation A", those that showed a light output of about 0.6 to 0.7 times the reference light output were given an "Evaluation B", and those that showed a light output of 0.5 times or less the reference light output were given an "Evaluation C".

Figure 7 is a graph showing the relationship between the injection current and the optical output when d1 = 50 nm and when d1 = 500 nm. From Figure 7, it can be seen that when d1 = 500 nm, the optical output remains at an extremely low value and changes very little even when the injection current is increased. In contrast, when d1 = 50 nm, it can be seen that the optical output shows a tendency to increase as the injection current is increased. This result suggests that when the value of d1 is increased to about 500 nm, it is not possible to selectively emit light from the region 5a directly below the ridge portion 9 in the active layer 5, and light is obtained that hardly contributes to oscillation.

Figure 8 shows the results of measuring the NFP (Near Field Pattern), which is the output distribution near the light emission surface of the light-emitting element 1, while increasing the current when d1 = 50 nm. In Figure 8, the dashed line shows the NFP before oscillation occurs, and the solid line shows the NFP after oscillation occurs. Figure 8 shows that the width of the NFP (light emission width) before and after oscillation hardly changes. This also suggests that when d1 = 50 nm, current flows selectively to the region 5a directly below the ridge portion 9 in the active layer 5, and this region emits light. Combined with the results in Table 1, it can be seen that by setting the value of d1 to 30 nm to 350 nm, it is possible to selectively emit light in the region 5a directly below the ridge portion 9 in the active layer 5.

[Production method]
An example of a method for manufacturing the light-emitting element 1 will be described.

(Step S1)
A GaN substrate 3 is prepared.

(Step S2)
As shown in Fig. 9, each semiconductor layer (11, 12, 21, 13, 23, 14, 5, 15, 16) is epitaxially grown on the +C plane of the GaN substrate 3. During epitaxial growth, the GaN substrate 3 is placed in a processing furnace of a MOCVD (Metal Organic Chemical Vapor Deposition) device, and while flowing a carrier gas such as nitrogen gas or hydrogen gas, the temperature and pressure are set to predetermined values, and raw material gas corresponding to each layer is flowed. The film thickness is controlled by the introduction time of the raw material gas.

For example, when growing a GaN layer, trimethylgallium (TMG) is used as the source gas. When growing an AlGaN layer, TMG and trimethylaluminum (TMA) are used as the source gas. When growing an InGaN layer, TMG and trimethylindium (TMI) are used as the source gas.

When doping the semiconductor layer with an n-type impurity, tetraethylsilane and ammonia are supplied into the furnace in addition to the source gas for the semiconductor layer. When doping the semiconductor layer with a p-type impurity, biscyclopentadienyl magnesium ( _Cp2Mg ) and ammonia are supplied into the furnace in addition to the source gas for the semiconductor layer. The impurity concentration is adjusted by controlling the flow rate of the gas for supplying these dopants.

(Step S3)
The wafer (epitaxial wafer) that has been subjected to step S2 is removed from the MOCVD apparatus, and the semiconductor laminate 8 is etched to have the shape shown in Fig. 4. The etching method may be either dry etching or wet etching.

In this embodiment, the second height position H2 is located within the third semiconductor layer 13. Therefore, after step S3, a portion of the upper surface of the third semiconductor layer 13 is exposed. Also, since the first height position H1 is located within the fifth semiconductor layer 15, a portion of the upper surface of the fifth semiconductor layer 15 is exposed after step S3.

(Step S4)
After the process of step S3 is completed, the epitaxial wafer is subjected to an activation process. As a specific example, the epitaxial wafer is heated in an oxygen atmosphere or an air atmosphere using an RTA (Rapid Thermal Anneal) device. This process is performed for the purpose of activating p-type impurities contained in the p-type semiconductors such as the third semiconductor layer 13. As an example, the heat treatment is performed at 720° C. for 30 minutes.

In step S2, ammonia gas is used to grow the third semiconductor layer 13, and some of the hydrogen contained in the ammonia may become mixed into the crystal lattice and hinder the generation of holes. In other words, at the completion of step S2, the third semiconductor layer 13 is doped with p-type impurities but has a low carrier concentration. By carrying out a heat treatment in this step S4, the hydrogen bonded to the lattice is released and holes appear.

As shown in FIG. 10, after step S3, a portion of the top surface of the third semiconductor layer 13 is exposed. Therefore, when step S4 is performed, hydrogen can be released from the third semiconductor layer 13 through not only the side surfaces but also the top surface of the third semiconductor layer 13. This makes it possible to make the third semiconductor layer 13 p-type. In FIG. 10, the state in which hydrogen is released is shown diagrammatically by arrows.

In step S3, etching may be performed so that the second height position H2 is located within the p-type contact layer 21. In this case, in step S4, hydrogen can be removed not only from the side surface of the third semiconductor layer 13 and the side surface of the contact layer 21, but also through the top surface of the contact layer 21 (see FIG. 11A).

In addition, in step S3, etching may be performed so that the second height position H2 is located within the second semiconductor layer 12 containing p-type impurities and n-type impurities. In this case, in step S4, hydrogen can be desorbed not only from the side surface of the third semiconductor layer 13, the side surface of the contact layer 21, and the side surface of the second semiconductor layer 12, but also through the upper surface of the second semiconductor layer 12 (see FIG. 11B).

Furthermore, in step S3, etching may be performed so that the second height position H2 is located within the first semiconductor layer 11. In this case, in step S4, the paths through which hydrogen can be desorbed include the side surfaces of the third semiconductor layer 13, the side surfaces of the contact layer 21, and the side surfaces of the second semiconductor layer 12, and hydrogen cannot be desorbed from the top surface of the first semiconductor layer 11 (see FIG. 11C). However, in this embodiment, since the amount of the semiconductor layer containing p-type impurities that is etched in step S3 is large, the volume of the semiconductor layer that needs to be converted to p-type is reduced. For this reason, hydrogen can be sufficiently desorbed only from the above-mentioned side surfaces, and conversion to p-type may be achieved.

(Step S5)
3, a first electrode 61 is formed on the upper surface of the sixth semiconductor layer 16. As a specific example, ITO is evaporated or applied to a predetermined thickness, and then annealed to reduce resistance. This annealing may be performed in combination with the annealing in step S4.

(Step S6)
As shown in FIG. 3, an insulating layer 81 made of, for example, SiO ₂ is formed to cover the exposed surface of the semiconductor layer located above (on the +Z side) the second height position H2 and a portion of the upper surface of the first electrode 61.

(Step S7)
3, a pad electrode 63 is formed on the upper surface of the first electrode 61. The pad electrode 63 is formed by photolithography, vacuum deposition, and lift-off.

(Step S8)
3, the second electrode 62 is formed on the back surface of the GaN substrate 3. As a more detailed example, a material for the second electrode 62 (e.g., Cr/Pt/Au, Ti/Pt/Au) is formed using a vacuum deposition apparatus, and then an annealing process is performed by heating at 450° C. for 10 minutes, for example.

After the GaN substrate 3 is thinned to a thickness of, for example, about 100 μm, it is cleaved to form the resonator end faces. Then, the front and rear resonator end faces are coated with a coating of, for example, AlN/Al ₂ O ₃ /SiO ₂ /Ta ₂ O _5. The material and thickness of the coating film formed on both resonator end faces can be appropriately changed according to the required reflectance. Then, a scribe line process is performed to separate each element in a direction parallel to the resonator. Then, after being divided into each element along the scribe line, they are assembled and mounted in a package.

[Verification of Thickness of Fourth Semiconductor Layer 14]
9 , in step S2, the active layer 5 is formed after the third semiconductor layer 13, which is a p-type semiconductor layer. For this reason, there is a risk that the p-type impurity will diffuse and penetrate into the active layer 5.

In particular, when magnesium (Mg) is used as a p-type impurity, Mg is likely to remain in the processing furnace after the third semiconductor layer 13 is grown, and there is a risk that the Mg remaining in the furnace may be incorporated even if an undoped or n-type semiconductor layer is subsequently grown. It is also possible that Mg may diffuse from the third semiconductor layer 13. If Mg is incorporated into the active layer 5, the non-radiative level of Mg will form a non-radiative recombination center, which may reduce the luminous efficiency.

From this perspective, it is preferable that the fourth semiconductor layer 14, which is formed between the third semiconductor layer 13 and the active layer 5, has a certain degree of thickness, with at least the layer located closest to the active layer 5 being an undoped layer.

The following Table 2 shows the results of evaluating the I-L (current-light output) and I-V (current-voltage) characteristics of samples of the light-emitting element 1 produced according to steps S1 to S7 above, with the thickness d2 of the fourth semiconductor layer 14 being varied (see Figures 6 and 9).

In the I-L characteristics in Table 2, the optical output when d2 = 250 nm is set as the reference optical output, and those that showed an optical output equivalent to the reference optical output (0.9 to 1.1 times) were given an "Evaluation A," those that showed an optical output of about 0.7 to 0.8 times the reference optical output were given an "Evaluation B," and those that showed an optical output of 0.6 times or less the reference optical output were given an "Evaluation C."

In the I-V characteristics in Table 2, the rise voltage when current begins to flow when d2 = 250 nm is set as the reference voltage, and those that showed a rise voltage equal to the reference voltage (a difference from the reference voltage of less than 0.1 V) were rated "Rating A", those that showed a rise voltage that was 0.1 V or more but less than 0.2 V higher than the reference voltage were rated "Rating B", and those that showed a rise voltage that was 0.2 V or more higher than the reference voltage were rated "Rating C".

According to Table 2, it was confirmed that when d2 = 50 nm, the light output was significantly reduced compared to when d2 = 250 nm. When d2 = 50 nm, the active layer 5 and the p-type third semiconductor layer 13 are close to each other, so this is thought to be due to Mg that has diffused from the third semiconductor layer 13 or from inside the furnace penetrating into the active layer 5, and a level that does not contribute to light emission is generated in the active layer 5.

Figure 12 is a graph showing the results of analyzing the third semiconductor layer 13, the electron blocking layer 23, and the fourth semiconductor layer 14 by SIMS (Secondary Ion Mass Spectroscopy) to examine the distribution of Mg concentration. Note that Figure 12 shows the results when the Mg flow rate during deposition of the electron blocking layer 23 was set to three different conditions: 0 sccm, 70 sccm, and 200 sccm. Note that since the fourth semiconductor layer 14 was an undoped layer, the gas used during deposition did not contain Mg.

According to FIG. 12, when the Mg flow rate is 70 sccm and 200 sccm, the Mg concentration in the fourth semiconductor layer 14 is high near the electron block layer 23, and is confirmed to drop to a value close to the detection limit at a distance of about 100 nm from the interface with the electron block layer 23. When the Mg flow rate is 0 sccm, the Mg concentration in the fourth semiconductor layer 14 is high near the electron block layer 23, and is confirmed to drop to a value close to the detection limit at a distance of about 100 nm from the interface with the electron block layer 23.

The results in Figure 12 are believed to support the above considerations regarding why the light output was significantly lower when d2 = 50 nm than when d2 = 250 nm in Table 2.

In addition, according to Table 2, it was confirmed that when the value of d2 reaches 350 nm or more, it causes a non-negligible increase in the applied voltage. The reason for this is believed to be that the undoped fourth semiconductor layer 14 located between the active layer 5 and the p-type third semiconductor layer 13 becomes too thick, forming a substantial resistance component.

Considering the above results, from the viewpoint of improving both the IL characteristics and the IV characteristics, it is preferable to set the thickness d2 of the undoped semiconductor layer (fourth semiconductor layer 14) located adjacent to the active layer 5 to 100 nm to 300 nm.

[Al composition]
As described above, in the light emitting element 1, it is preferable that the Al composition ratio of the sixth semiconductor layer 16 is lower than the Al composition ratio of the third semiconductor layer 13. The reason for this will be described with reference to Figs. 13A and 13B.

Figure 13A is a diagram showing a cross-sectional view of the structure of the semiconductor laminate 78 of the conventional light-emitting element 91 described above with reference to Figure 1A, together with a schematic diagram of the light output distribution in the Z direction. Figure 13B is a diagram showing a cross-sectional view of the structure of the semiconductor laminate 8 of the light-emitting element 1 of this embodiment described above with reference to Figure 3, together with a schematic diagram of the light output distribution in the Z direction.

Note that, in order to correspond to FIG. 13B, FIG. 13A illustrates a case in which an n-side guide layer 74 is disposed between an n-type semiconductor layer 71 and an active layer 72, and a p-side guide layer 75 is disposed between the active layer 72 and a p-type semiconductor layer 73.

In the conventional light-emitting device 91 shown in FIG. 13A, the p-type semiconductor layer 73 is disposed on the +Z side of the active layer 72. In the case of GaN, the activation rate of p-type is lower than that of n-type, so in order to realize p-type conversion, it is necessary to dope p-type impurities such as Mg at a concentration of 1×10 ¹⁹ /cm ³ or more, and the light absorption loss due to Mg becomes large. In addition, as described above with reference to FIG. 12, p-type impurities have a tendency to diffuse easily. Therefore, Mg may invade the region of the active layer 72 close to the p-type semiconductor layer 73, causing an increase in the light absorption loss, and in order to suppress the decrease in the light emission efficiency of the light-emitting device 91, it is necessary to shift the peak position of the light intensity distribution from the center of the active layer 72 to the -Z side, that is, to the side away from the p-type semiconductor layer. This is possible by increasing the Al composition of the p-type semiconductor layer 73 located on the +Z side of the active layer 72 to be higher than the Al composition of the n-type semiconductor layer 71 located on the -Z side of the active layer 72.

In the light-emitting element 91, from the viewpoint of confining light to a specific location in the active layer 72 and oscillating it, it is conceivable to give the p-type semiconductor layer 73 a shape similar to the ridge portion 9 in FIG. 6. However, if the Al concentration of the p-type semiconductor layer 73 constituting the ridge portion is made higher than the Al concentration of the wide n-type semiconductor layer 71, the refractive index difference between the region directly under the ridge portion and the region outside it cannot be sufficiently achieved in the semiconductor laminate 78, and kinks are likely to occur.

In contrast, in the light-emitting element 1 of this embodiment, the n-type sixth semiconductor layer 16 is disposed on the +Z side of the active layer 5, so that even if the peak position of the light intensity distribution is shifted from the center of the active layer 5 to the +Z side, there is little risk of a decrease in light emission efficiency. Therefore, the Al composition of the n-type sixth semiconductor layer 16 located on the +Z side of the active layer 5 can be made lower than the Al composition of the p-type third semiconductor layer 13 located on the -Z side of the active layer 5. This provides a sufficient refractive index difference between the region directly under the ridge portion 9 and the region outside it in the semiconductor laminate 8, and provides the effect of suppressing kinks.

[Another embodiment]
Another embodiment will be described below.

<1> In the above embodiment, the second electrode 62 is formed on the back surface (main surface on the -Z side) of the GaN substrate 3, but like the first electrode 61, it may be formed on the +Z side of the GaN substrate 3. As a more detailed example, as shown in FIG. 14, a method can be used in which a part of the first semiconductor layer 11 is exposed at the third height position H3, and the second electrode 62 and pad electrode 64 are disposed on the upper surface of this exposed surface. In this case, the semiconductor laminate has four different widths.

To realize the light-emitting element 1 shown in FIG. 14, in step S3, etching is performed so as to expose the fifth semiconductor layer 15 at the first height position H1, the third semiconductor layer 13 at the second height position H2, and the first semiconductor layer 11 at the third height position H3. However, the second height position H2 may be located within the contact layer 21 or within the second semiconductor layer 12, as described above with reference to FIGS. 11A to 11B. Also, as described above with reference to FIG. 11C, the second height position H2 may be located within the first semiconductor layer 11, and in this case, since the third height position H3 and the second height position are common, the number of etching steps can be at least two.

〈2〉 In the above embodiment, the light-emitting element 1 is an LD element, but it may be an SLD (Super Luminescent Diode) element with a coating layer formed on the end surface to suppress reflection.

〈3〉 The light-emitting element 1 may be an element whose main emission wavelength is in the ultraviolet region of 365 nm to 430 nm, or an element whose main emission wavelength is in the blue to green region of 430 nm to 550 nm. The material composition of each semiconductor layer constituting the semiconductor laminate 8 is appropriately selected according to the emission wavelength.

<4> In order to further enhance the function of confining the current in the active layer 5, the light-emitting element 1 may have buried layers 31 having a higher resistance than the fourth semiconductor layer 14 on both sides in the Y direction in the fourth semiconductor layer 14 (see FIG. 15). FIG. 15 shows an example in which a buried layer 31 made of a material having a higher resistance than GaN is formed in the GaN layer 14a of the fourth semiconductor layer 14.

Figure 15 shows a configuration in which a buried layer 31 is additionally provided to the light-emitting element 1 shown in Figure 3. However, this buried layer 31 can also be applied to the other configurations described above with reference to Figures 11A to 11C and the other configuration shown in Figure 14.

The buried layer 31 may be any layer having a higher resistance than the fourth semiconductor layer 14, and may be, for example, AlN or AlInN. In particular, when the buried layer 31 is provided in the GaN layer 14a, the buried layer 31 is preferably AlInN from the viewpoint of ensuring good lattice matching with GaN. As a specific example, the buried layer 31 is undoped Al _0.82 In _0.18 N having a film thickness of 100 nm. When the buried layer 31 is buried in the GaN layer 14a, it may be any layer having a film thickness smaller than that of the GaN layer 14a.

Of the regions in the fourth semiconductor layer 14, the region 32 sandwiched between the buried layers 31 in the Y direction overlaps with the ridge portion 9 (see also FIG. 6) in the Z direction. More preferably, the width of the region 32 in the Y direction is narrower than the width of the ridge portion 9 in the Y direction. By providing such a buried layer 31 in the fourth semiconductor layer 14, when a voltage is applied to the light-emitting element 1, most of the current flowing in the active layer 5 can be caused to flow to the region directly below the ridge portion 9. In other words, with this configuration, the amount of the current I2 described above with reference to FIG. 6 is further reduced, and the region 5a directly below the ridge portion 9 in the active layer 5 can be more selectively emitted, thereby further improving the light-emitting efficiency.

The buried layer 31 can be formed in the fourth semiconductor layer 14, for example, by the following method.

In step S2 described above, each semiconductor layer (11, 12, 21, 13, 23) is epitaxially grown on the +C surface of the GaN substrate 3, and then a portion of the fourth semiconductor layer 14 is epitaxially grown. Then, a material (e.g., AlInN) that will form the buried layer 31 is grown on top of the fourth semiconductor layer 14.

Next, a mask made of patterned _SiO2 or the like is formed on the upper surface of this AlInN, and the AlInN is removed through this mask using a solution such as hot phosphoric acid to expose the upper surface of the fourth semiconductor layer 14. Thereafter, the mask is removed, and the fourth semiconductor layer 14 is subsequently epitaxially grown, and then the remaining semiconductor layers (5, 15, 16) are epitaxially grown. The rest is the same as in the above-mentioned embodiment.

1: Light-emitting element 3: GaN substrate 5: Active layer 5a: Region directly below the ridge portion in the active layer 8: Semiconductor laminate 9: Ridge portion 11: First semiconductor layer 12: Second semiconductor layer 13: Third semiconductor layer 14: Fourth semiconductor layer 14a: GaN layer 14b: InGaN layer 15: Fifth semiconductor layer 15a: InGaN layer 15b: GaN layer 16: Sixth semiconductor layer 21: Contact layer 23: Electron blocking layer 31: Buried layer 32: Region sandwiched between buried layers 61: First electrode 62: Second electrode 63: Pad electrode 64: Pad electrode 71: N-type semiconductor layer 72: Active layer 73: P-type semiconductor layer 74: N-side guide layer 75: P-side guide layer 78: Semiconductor laminate 81: Insulating layer 91: Light-emitting element

Claims (4)

an n-type GaN substrate;
a first semiconductor layer located on an upper layer of a main surface on the +C side of the GaN substrate and made of a nitride semiconductor containing an n-type impurity;
a second semiconductor layer located above the first semiconductor layer, made of a nitride semiconductor containing both n-type impurities and p-type impurities, and forming a tunnel junction;
a third semiconductor layer located above the second semiconductor layer, made of a nitride semiconductor containing p-type impurities, and forming a p-side clad layer;
a fourth semiconductor layer located above the third semiconductor layer, made of a nitride semiconductor containing p-type impurities or undoped, and forming a p-side guide layer;
an active layer made of a nitride semiconductor and located above the fourth semiconductor layer;
a fifth semiconductor layer located above the active layer, made of an n-type impurity-doped or undoped nitride semiconductor, and forming an n-side guide layer;
a sixth semiconductor layer located above the fifth semiconductor layer, made of a nitride semiconductor containing n-type impurities, and forming an n-side clad layer;
a semiconductor stack including the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the fourth semiconductor layer, the active layer, the fifth semiconductor layer, and the sixth semiconductor layer has three or more different widths when viewed in a direction parallel to the primary surface, and exhibits a stepped shape in which the widths become wider as the stack approaches the GaN substrate in a direction perpendicular to the primary surface;
When viewed in a direction parallel to the main surface, the width of the semiconductor laminate changes at a first height position in the fifth semiconductor layer and at a second height position in a region sandwiched between a surface of the third semiconductor layer closer to the active layer and a surface of the first semiconductor layer closer to the GaN substrate,
a distance between the first height position and a surface of the active layer on the fifth semiconductor layer side in a direction perpendicular to the main surface is 30 nm to 350 nm. The nitride semiconductor light-emitting device according to claim 1, characterized in that the second height position is located within the third semiconductor layer. The nitride semiconductor light-emitting device according to claim 1 or 2, characterized in that the fourth semiconductor layer is made of an undoped nitride semiconductor and has a thickness of 100 nm to 300 nm. the third semiconductor layer and the sixth semiconductor layer are both made of a nitride semiconductor containing Al,
3 . The nitride semiconductor light-emitting device according to claim 1 , wherein the Al composition of the sixth semiconductor layer is lower than the Al composition of the third semiconductor layer.

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