JP7610168B2 - Time synchronization device, time synchronization method, and program - Google Patents

Description

The present disclosure relates to a time synchronization device, a time synchronization method, and a program.

PTP (Precision Time Protocol) defined in the IEEE-1588 standard is a protocol that synchronizes the time (internal device time) of computers on a LAN (Local Area Network) with high precision (see Non-Patent Document 1). Figure 11 is a diagram showing an example of the configuration of a time synchronization system 1 that uses the PTP protocol to synchronize the time of devices on a network.

The time synchronization system 1 shown in Figure 11 comprises a Grand Master Clock 2, a conventional Boundary Clock 100a, and a client device 3. The Grand Master Clock 2 and the Boundary Clock 100a can communicate with each other via a network such as a LAN. The Boundary Clock 100a and the client device 3 can communicate with each other via a network such as a LAN.

The Grand Master Clock 2 is equipped with a GNSS antenna that receives signals (GNSS signals) from satellites of a Global Navigation Satellite System (GNSS) such as the Global Positioning System (GPS). The Grand Master Clock 2 receives the GNSS signals via the GNSS antenna and acquires Universal Time Coordinated (UTC) from the received GNSS signals. The Grand Master Clock 2 is equipped with a master function that distributes the acquired UTC as a reference time via a network.

The Boundary Clock 100a functions as a slave device with a function to synchronize its own internal time with the time distributed from a higher-level device with a master function, and functions as a master device with a function to a lower-level device with a slave function. In the time synchronization system 1 shown in FIG. 11, the Boundary Clock 100a functions as a slave device with the Grand Master Clock 2, and functions as a master device with the client device 3. Therefore, the Boundary Clock 100a synchronizes its internal time with the time (reference time) distributed from the Grand Master Clock 2 by transmitting and receiving PTP packets with the Grand Master Clock 2. The Boundary Clock 100a also distributes its internal time to the client device 3 by transmitting and receiving PTP packets with the client device 3, and synchronizes the internal time of the client device 3 with the internal time of the own device.

The client device 3 has a slave function that synchronizes the time within the device with the time distributed from a device with a master function. In the time synchronization system 1 shown in Figure 11, the client device 3 synchronizes the time within the device with the time distributed from the Boundary Clock 100a. The client device 3 is, for example, a base station device in a mobile phone network.

IEEE Std 1588TM-2008 “IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems”

In the time synchronization system 1 shown in Figure 11, a failure may occur in the GNSS antenna equipped to the Grand Master Clock 2, in the Grand Master Clock 2 itself, or in the transmission path between the Grand Master Clock 2 and the Boundary Clock 100a, resulting in a large discrepancy between the internal time of the Grand Master Clock 2 and the internal time of the Boundary Clock 100a.

If a fault occurs on the transmission path, the time delivered by Grand Master Clock 2 is accurate, and Boundary Clock 100a does not synchronize to an incorrect time.

On the other hand, if a fault occurs in the GNSS antenna of the Grand Master Clock 2 or in the Grand Master Clock 2 itself, the time distributed from the Grand Master Clock 2 may become an incorrect time with a large deviation from UTC. In this case, the conventional Boundary Clock 100a may synchronize with the internal time of the Grand Master Clock 2, which includes a large error, and continue to distribute the incorrect time with a large error from UTC to the subordinate client device 3. If such an incorrect time is distributed, the internal time of the user device subordinate to the client device 3 may also be shifted, causing a system failure or communication failure. In addition, it may cause a system failure or communication failure not only to the user device subordinate to the client device 3, but also to the user device subordinate to the client device 3, whose internal time is not shifted by synchronizing with another Grand Master Clock 2 or Boundary Clock 100a. In this way, if synchronization with an incorrect time occurs, a problem with a very large impact may occur. Therefore, it is necessary to more accurately determine the occurrence of a failure in the synchronization between the internal time of the host device and the internal time of the own device and the location of the failure.

The objective of the present disclosure, made in consideration of the above-mentioned problems, is to provide a time synchronization device, a time synchronization method, and a program that can more accurately determine the occurrence of a failure in synchronization between the internal time of a higher-level device and the internal time of the device itself, and the location of the failure, when synchronizing the internal time of the device itself with the time distributed from a higher-level device and synchronizing the internal time of a lower-level device with the internal time of the device itself.

In order to solve the above problems, the time synchronization device disclosed herein is a time synchronization device that synchronizes the internal time of its own device with the internal time of the higher-level device and synchronizes the internal time of a lower-level device with the internal time of its own device by transmitting and receiving packets with a higher-level device, and is equipped with an offset calculation unit that calculates an offset, which is the difference between the internal time of the higher-level device and the internal time of the local device, a transmission delay time calculation unit that calculates the transmission delay time of packets transmitted and received between the higher-level device and its own device, an offset pattern determination unit that determines the fluctuation pattern of the offset, a transmission delay time pattern determination unit that determines the fluctuation pattern of the transmission delay time, and a fault location determination unit that determines the location of a fault in time synchronization with the higher-level device based on the fluctuation pattern of the offset and the fluctuation pattern of the transmission delay time.

In addition, in order to solve the above problem, the time synchronization method disclosed herein is a time synchronization method for synchronizing the internal time of a device with the internal time of a higher-level device and synchronizing the internal time of a lower-level device with the internal time of the device by transmitting and receiving packets with a higher-level device, and includes the steps of calculating an offset, which is the difference between the internal time of the higher-level device and the internal time of the device, calculating the transmission delay time of packets transmitted and received between the higher-level device and the device, determining the fluctuation pattern of the offset, determining the fluctuation pattern of the transmission delay time, and determining the location of a failure in time synchronization with the higher-level device based on the fluctuation pattern of the offset and the fluctuation pattern of the transmission delay time.

In addition, to solve the above problem, the program disclosed herein causes a computer to operate as the above-mentioned time synchronization device.

With the time synchronization device, time synchronization method, and program disclosed herein, when the internal time of a device is synchronized with the time distributed from a higher-level device and the internal time of a lower-level device is synchronized with the internal time of the device itself, it is possible to more accurately determine the occurrence of a failure in synchronization between the internal time of the higher-level device and the internal time of the device itself and the location of the failure.

1 is a diagram illustrating a configuration example of a Boundary Clock as a time synchronization device according to a first embodiment of the present disclosure. 11 is a diagram for explaining calculation of an offset and a transmission delay time. FIG. 2 is a flowchart showing an example of an operation of the Boundary Clock shown in FIG. 1 . FIG. 13 is a diagram illustrating an example of an offset fluctuation pattern. FIG. 13 is a diagram showing another example of an offset fluctuation pattern. FIG. 11 is a diagram illustrating an example of a fluctuation pattern of a transmission delay time. FIG. 11 is a diagram illustrating another example of a fluctuation pattern of a transmission delay time. FIG. 11 is a diagram illustrating yet another example of a fluctuation pattern of a transmission delay time. 2 is a diagram for explaining determination of a fault location by a fault location determination unit shown in FIG. 1; FIG. FIG. 2 is a diagram illustrating an example of a hardware configuration of the Boundary Clock illustrated in FIG. 1 . FIG. 11 is a diagram illustrating a configuration example of a Boundary Clock as a time synchronization device according to a second embodiment of the present disclosure. 9 is a flowchart showing an example of the operation of the Boundary Clock shown in FIG. 8 . 9 is a diagram for explaining selection of a target for time synchronization by a time selection unit shown in FIG. 8 . FIG. FIG. 1 is a diagram illustrating an example of the configuration of a conventional time synchronization system.

Below, the embodiments of the present disclosure are described with reference to the drawings.

(First embodiment)
Fig. 1 is a diagram showing an example of the configuration of a Boundary Clock 100 as a time synchronization device according to a first embodiment of the present disclosure. The Boundary Clock 100 according to this embodiment distributes time distributed from a Grand Master Clock 2 to a client device 3 in place of the Boundary Clock 100a in the time synchronization system 1 shown in Fig. 11. That is, the Boundary Clock 100 as a time synchronization device according to this embodiment synchronizes its own internal time with the internal time of the higher-level device (Grand Master Clock 2) and synchronizes the internal time of a lower-level device (client device 3) with the internal time of its own device by transmitting and receiving packets (PTP packets) to and from the higher-level device (Grand Master Clock 2).

As shown in FIG. 1, the Boundary Clock 100 of this embodiment includes packet transmission/reception units 101, 105, an offset calculation unit 102, a transmission delay time calculation unit 103, a time synchronization processing unit 104, a threshold memory unit 106, an offset pattern determination unit 107, a transmission delay time pattern determination unit 108, a count flag unit 109, a Clock Class rewriting unit 110, and a fault location determination unit 111.

The packet transmission/reception unit 101 transmits and receives PTP packets with the Grand Master Clock 2. The packet transmission/reception unit 101 outputs packets received from the Grand Master Clock 2 to the offset calculation unit 102 and the transmission delay time calculation unit 103.

The offset calculation unit 102 calculates an offset, which is the difference between the internal time of the higher-level device, Grand Master Clock 2, and the internal time of its own device (Boundary Clock 100). Specifically, the offset calculation unit 102 acquires a timestamp from a packet output from the packet transmission/reception unit 101, and calculates an offset based on the acquired timestamp. The calculation of the offset by the offset calculation unit 102 will be described below with reference to FIG. 2.

As shown in FIG. 2, Grand Master Clock 2 transmits a Sync message to Boundary Clock 100. Grand Master Clock 2 transmits the Sync message to Boundary Clock 100, including a timestamp indicating time T1, which is the transmission time of the Sync message.

When the Boundary Clock 100 receives a Sync message sent from the Grand Master Clock 2 at time T2, it sends a Delay_Req message (delay request message) to the Grand Master Clock 2 at time T3.

When Grand Master Clock 2 receives the Delay_Req message sent from Boundary Clock 100 at time T4, it sends a Delay_Resp message (delay response message) to Boundary Clock 100. Grand Master Clock 2 includes a timestamp indicating time T4, which is the time when the Delay_Req message was received, in the Delay_Resp message and sends it to Boundary Clock 100.

The offset calculation unit 102 obtains a timestamp included in the Sync message indicating the time T1 when the Grand Master Clock 2 transmitted the Sync message, a timestamp indicating the time T2 when the Boundary Clock 100 received the Sync message, a timestamp indicating the time T3 when the Boundary Clock 100 transmitted the Delay_Req message, and a timestamp included in the Delay_Resp message indicating the time T4 when the Grand Master Clock 2 transmitted the Delay_Req message. The offset calculation unit 102 then calculates the offset based on the following formula 1.
Offset = ((T2 - T1) - (T4 - T3)) / 2 ... Equation 1

Referring again to Figure 1, the offset calculation unit 102 outputs the offset calculation result to the time synchronization processing unit 104 and the offset pattern determination unit 107.

The transmission delay time calculation unit 103 calculates the transmission delay time of the PTP packets transmitted and received between the higher-level device Grand Master Clock 2 and Boundary Clock 100. The transmission delay time calculation unit 103 calculates, as the transmission delay time, the average of the difference between the time T2 when Boundary Clock 100 receives the Sync message and the time T1 when Grand Master Clock 2 transmits the Sync message, and the difference between the time T4 when Grand Master Clock 2 receives the Delay_Req message and the time T3 when Boundary Clock 100 transmits the Delay_Req message. That is, the transmission delay time calculation unit 103 calculates the transmission delay time based on the following formula 2 using the timestamps indicating the times T1, T2, T3, and T4 described with reference to FIG. 2.
Transmission delay time = ((T2 - T1) + (T4 - T3)) / 2 ... Equation 2

The transmission delay time calculation unit 103 outputs the calculation result of the transmission delay time to the time synchronization processing unit 104 and the transmission delay time pattern determination unit 108.

The time synchronization processing unit 104 synchronizes the device time of the Boundary Clock 100 with the device time of the Grand Master Clock 2 based on the offset calculated by the offset calculation unit 102 and the transmission delay time calculated by the transmission delay time calculation unit 103.

The packet transmission/reception unit 105 transmits and receives PTP packets to and from the client device 3. Packets transmitted and received to and from the client device 3 contain time information of the internal time of the Boundary Clock 100, and by transmitting and receiving these packets, the internal time of the client device 3 can be synchronized with the internal time of the Boundary Clock 100.

The threshold storage unit 106 stores thresholds (first threshold TH1, second threshold TH2, third threshold TH3, and fourth threshold TH4) required for processing in the offset pattern determination unit 107 and the transmission delay time pattern determination unit 108 described later. Methods for setting each threshold include a method of setting a predetermined fixed value, a method of acquiring offset and transmission delay time data for a certain period of time and setting the threshold based on the average value, etc.

The offset pattern determination unit 107 determines the fluctuation pattern of the offset calculated by the offset calculation unit 102. Specifically, the offset pattern determination unit 107 determines whether the absolute value of the offset is greater than a first threshold TH1. Then, as the fluctuation pattern of the offset, the offset pattern determination unit 107 determines whether the time or the number of times that the absolute value of the offset is determined to be greater than the first threshold TH1 is greater than a second threshold TH2. The offset pattern determination unit 107 outputs the determination result to the fault location determination unit 111.

The transmission delay time pattern determination unit 108 determines the fluctuation pattern of the transmission delay time calculated by the transmission delay time calculation unit 103. Specifically, the transmission delay time pattern determination unit 108 determines whether the transmission delay is greater than a third threshold value TH3. Then, as the fluctuation pattern of the transmission delay time, the transmission delay time pattern determination unit 108 determines whether the time or number of times the transmission delay time is determined to be greater than the third threshold value TH3 is greater than a fourth threshold value TH4. The transmission delay time pattern determination unit 108 outputs the determination result to the fault location determination unit 111.

The count flag unit 109 manages an offset count flag indicating whether or not the time or the number of times that the absolute value of the offset is determined to be greater than the first threshold value TH1 is being counted. The count flag unit 109 also manages a transmission delay time count flag indicating whether or not the time or the number of times that the transmission delay time is determined to be greater than the third threshold value TH3 is being counted.

The Clock Class rewriting unit 110, under the control of the fault location determination unit 111, rewrites the Clock Class indicating whether the internal time of the Boundary Clock 100 is synchronized with the internal time of the Grand Master Clock 2, and outputs it to the packet transmission/reception unit 105. The Clock Class is included in the PTP packet transmitted and received between the Boundary Clock 100 and the client device 3, and is transmitted to the client device 3. In the client device 3, if the Clock Class indicates that the internal time of the Boundary Clock 100 is synchronized with the internal time of the Grand Master Clock 2, the internal time of the client device 3 is synchronized with the internal time of the Boundary Clock 100. In addition, if the Clock Class indicates that the internal time of the Boundary Clock 100 is not synchronized with the internal time of the Grand Master Clock 2, the synchronization of the internal time of the client device 3 with the internal time of the Boundary Clock 100 is stopped.

The fault location determination unit 111 determines the occurrence of a fault in time synchronization with the higher-level device, Grand Master Clock 2, and the location of the fault, based on the offset fluctuation pattern determined by the offset pattern determination unit 107 and the transmission delay time fluctuation pattern determined by the transmission delay time pattern determination unit 108.

Possible locations of time synchronization failures include the GNSS antenna equipped to the Grand Master Clock 2, the Grand Master Clock 2 itself, or the transmission path between the Grand Master Clock 2 and the Boundary Clock 100. If the failure occurs in the GNSS antenna, it is possible that the failure has been caused by a signal attack such as jamming (interfering radio waves) or spoofing (impersonation). If the failure occurs in the Grand Master Clock 2 itself, it is possible that some function within the Grand Master Clock 2 has failed. If the failure occurs in the transmission path between the Grand Master Clock 2 and the Boundary Clock 100, it is possible that a temporary cable abnormality has occurred, for example.

The fault location determination unit 111 determines whether the fault occurs in the Grand Master Clock 2 (the GNSS antenna provided in the Grand Master Clock 2, or the Grand Master Clock 2 itself) or in the transmission path between the Grand Master Clock 2 and the Boundary Clock 100. The determination of the fault location by the fault location determination unit 111 will be described in detail later.

When the fault location determination unit 111 determines that the fault has occurred in Grand Master Clock 2, it stops synchronizing the client device 3's internal time with its own internal time. Specifically, the fault location determination unit 111 instructs the Clock Class rewriting unit 110 to rewrite the Clock Class so that the Clock Class indicates that the Boundary Clock 100's internal time is not synchronized with the Grand Master Clock 2's internal time.

Next, we will explain the operation of the Boundary Clock 100 in this embodiment.

Figure 3 is a flowchart showing an example of the operation of the Boundary Clock 100 in this embodiment, and is a diagram for explaining the time synchronization method using the Boundary Clock 100.

The offset calculation unit 102 obtains a timestamp from the packet output from the packet transceiver unit 101 and calculates the offset (step S101).

The offset pattern determination unit 107 determines whether the absolute value of the offset calculated by the offset calculation unit 102 is greater than the first threshold TH1 stored in the threshold storage unit 106 (step S102). The first threshold TH1 is a threshold for determining whether the offset has fluctuated significantly. For example, in normal operation, when the absolute value of the offset between the device time of the Grand Master Clock 2 and the device time of the Boundary Clock 100 is smaller than 1 ms, the first threshold TH1 is set to, for example, 1 ms. In this case, the offset pattern determination unit 107 sequentially determines whether the absolute value of the offset is greater than 1 ms. The offset pattern determination unit 107 counts the number of consecutive times that the absolute value of the offset is determined to be greater than the first threshold TH1. Hereinafter, this count value will be referred to as the offset count.

As described above, the first threshold TH1 may be set to the average value of data over a certain period of time. For example, during the first minute after PTP communication is started between the Grand Master Clock 2 and the Boundary Clock 100, the offset may be calculated every second, and the average value of 60 pieces of data may be set as the first threshold TH1.

If it is determined that the absolute value of the offset is greater than the first threshold TH1 (step S102: Yes), the offset pattern determination unit 107 increments the offset count by 1 (step S103) and turns on the offset count flag. If the offset count flag is already on, the offset pattern determination unit 107 leaves the offset count flag on.

Next, the offset pattern determination unit 107 determines whether the offset count is greater than a second threshold TH2 (step S104). The second threshold TH2 is a threshold for determining whether the change in offset is temporary. The second threshold TH2 is set to, for example, 10 times. In this case, the offset pattern determination unit 107 determines whether the absolute value of the offset is greater than the first threshold TH1 (for example, 1 ms) 10 times in a row.

If the offset pattern determination unit 107 determines that the offset count is less than or equal to the second threshold TH2 (0 < offset count ≦ second threshold TH2) (step S104: No), processing is repeated from step S101.

When it is determined that the offset count is greater than the second threshold TH2 (second threshold TH2<offset count) (step S104: Yes), the offset pattern determination unit 107 notifies the fault location determination unit 111 that the offset count has become greater than the second threshold TH2. In other words, the offset pattern determination unit 107 can notify the fault location determination unit 111 that, as a fluctuation pattern of the offset, a state in which the absolute value of the offset is greater than the first threshold TH1 has continued for a predetermined time period according to the second threshold TH2.

If it is determined that the absolute value of the offset is equal to or less than the first threshold value TH1 (step S102: No), the offset pattern determination unit 107 sets the offset count to 0 and turns off the offset count flag (step S105). If the state in which the absolute value of the offset is equal to or less than the first threshold value TH1 continues, the offset count is 0 and the offset count flag remains off. Therefore, the offset pattern determination unit 107 can notify the fault location determination unit 111 that the state in which the absolute value of the offset is equal to or less than the first threshold value TH1 continues as the offset fluctuation pattern.

Note that even if the absolute value of the offset is greater than the first threshold value TH1, the Boundary Clock 100 synchronizes the internal time of the device with the internal time of the Grand Master Clock 2, so that the offset eventually becomes smaller than the first threshold value TH1. Therefore, the offset pattern determination unit 107 determines whether the fluctuation pattern of the offset is a pattern (pattern 0) shown in FIG. 4A in which the offset remains smaller than the first threshold value TH1, or a pattern (pattern 1) shown in FIG. 4B in which the offset becomes larger than the first threshold value TH1 and becomes smaller than the first threshold value TH1 after a predetermined time corresponding to the second threshold value TH2 has elapsed, and outputs the determination result to the fault location determination unit 111.

In parallel with the processing of steps S101 to S105 described above, the processing of steps S106 to S109 described below is performed.

The transmission delay time calculation unit 103 obtains a timestamp from the packet output from the packet transmission/reception unit 101 and calculates the transmission delay time (step S106).

The transmission delay time pattern determination unit 108 determines whether the transmission delay time calculated by the transmission delay time calculation unit 103 is greater than the third threshold value TH3 stored in the threshold value storage unit 106 (step S107). The third threshold value TH3 is a threshold value for determining whether the transmission delay time has fluctuated significantly. For example, in normal cases, when packets are transmitted and received within 10 ms between the Grand Master Clock 2 and the Boundary Clock 100, the third threshold value TH3 is set to, for example, 10 ms. In this case, the transmission delay time pattern determination unit 108 sequentially determines whether the transmission delay time is greater than 10 ms. The transmission delay time pattern determination unit 108 counts the number of times that it has been determined that the transmission delay time is greater than the third threshold value TH3. Hereinafter, this count value will be referred to as the transmission delay time count.

As described above, the third threshold TH3 may be set to the average value of data over a certain period of time. For example, the transmission delay time may be calculated every second for one minute after PTP communication is started between the Grand Master Clock 2 and the Boundary Clock 100, and the average value of 60 pieces of data may be set as the third threshold TH3.

If it is determined that the transmission delay time is greater than the third threshold value TH3 (step S107: Yes), the transmission delay time pattern determination unit 108 increments the transmission delay time count by 1 (step S108) and turns on the transmission delay time count flag. If the transmission delay time count flag is already on, the transmission delay time pattern determination unit 108 leaves the transmission delay time count flag on.

Next, the transmission delay time pattern determination unit 108 determines whether the transmission delay time count is greater than a fourth threshold TH4 (step S109). The fourth threshold TH4 is a threshold for determining whether a change in the transmission delay time is temporary. The fourth threshold TH4 is set to, for example, 10 times. In this case, the transmission delay time pattern determination unit 108 determines whether the transmission delay time is greater than the third threshold TH3 (for example, 10 ms) 10 consecutive times.

If the transmission delay time pattern determination unit 108 determines that the transmission delay time count is less than or equal to the fourth threshold value TH (0 < transmission delay time count ≦ fourth threshold value TH4) (step S109: No), processing is repeated from step S106.

When it is determined that the transmission delay time count is greater than the fourth threshold TH4 (fourth threshold TH4<transmission delay time count) (step S109: Yes), the transmission delay time pattern determination unit 108 notifies the fault location determination unit 111 that the transmission delay time count has become greater than the fourth threshold TH4. In other words, the transmission delay time pattern determination unit 108 can notify the fault location determination unit 111 that, as a fluctuation pattern of the transmission delay time, a state in which the transmission delay time is greater than the third threshold TH3 has continued for a predetermined time according to the fourth threshold TH4.

If it is determined that the transmission delay time is equal to or less than the third threshold TH3 (step S107: No), the transmission delay time pattern determination unit 108 sets the transmission delay time count to 0 and turns off the transmission delay time count flag (step S105). If the state in which the transmission delay time is equal to or less than the third threshold TH3 continues, the transmission delay time count is 0 and the transmission delay time count flag remains off. Therefore, the transmission delay time pattern determination unit 108 can notify the fault location determination unit 111 that the state in which the transmission delay time is equal to or less than the third threshold TH3 continues as a fluctuation pattern of the transmission delay time. Also, if the transmission delay time becomes greater than the third threshold TH3 and becomes equal to or less than the third threshold TH3 before a predetermined time corresponding to the fourth threshold TH4 has elapsed, the transmission delay time count is 0 and the transmission delay time count flag is changed from on to off. Therefore, the transmission delay time pattern determination unit 108 can notify the fault location determination unit 111 that, as a fluctuation pattern of the transmission delay time, the transmission delay time becomes greater than the third threshold value TH3 and then becomes equal to or less than the third threshold value TH3 before a predetermined time corresponding to the fourth threshold value TH4 has elapsed.

Therefore, the transmission delay time pattern determination unit 108 determines whether the fluctuation pattern of the transmission delay time is a pattern (pattern 0) shown in Figure 5A in which the transmission delay time remains smaller than the third threshold value TH3, a pattern (pattern 1) shown in Figure 5B in which the transmission delay time becomes larger than the third threshold value TH3 and becomes smaller than the third threshold value TH3 before a predetermined time corresponding to the fourth threshold value TH4 has elapsed, or a pattern shown in Figure 5C in which the state in which the transmission delay time is larger than the third threshold value TH3 continues even after a predetermined time corresponding to the fourth threshold value TH4 has elapsed, and outputs the determination result to the fault location determination unit 111.

After receiving the offset fluctuation pattern determination result by the offset pattern determination unit 107 and the transmission delay time fluctuation pattern determination result by the transmission delay time pattern determination unit 108 (after the processing of step S104, step S105, or step S109), the fault location determination unit 111 determines the occurrence of a fault in time synchronization with the Grand Master Clock 2 and the location of the fault based on the offset fluctuation pattern and the transmission delay time fluctuation pattern (step S110). The determination of the fault location by the fault location determination unit 111 will be described with reference to FIG. 6.

As explained with reference to Figures 4A and 4B, there are two offset fluctuation patterns, pattern 0 and pattern 1. Also, as explained with reference to Figures 5A, 5B, and 5C, there are three transmission delay time fluctuation patterns, pattern 0, pattern 1, and pattern 2. Therefore, by combining the offset fluctuation patterns and the transmission delay time fluctuation patterns, there are six patterns (patterns A to F), as shown in Figure 6.

Pattern A is a pattern in which the offset fluctuation pattern is pattern 0 and the transmission delay time fluctuation pattern is pattern 0. That is, pattern A is a state in which the absolute value of the offset is equal to or less than the first threshold value TH1 (Figure 4A) and the transmission delay time is equal to or less than the third threshold value TH3. Therefore, there is no abnormality in the offset and the transmission delay time, and it is considered that no problem has occurred in the synchronization between the internal time of Grand Master Clock 2 and the internal time of Boundary Clock 100.

Pattern B is a pattern in which the offset fluctuation pattern is pattern 1 and the transmission delay time fluctuation pattern is pattern 0. That is, pattern B is a state in which the absolute value of the offset is greater than the first threshold value TH1 and the transmission delay time is equal to or less than the third threshold value TH3. In this case, in pattern B, there is no abnormality in the transmission path between Grand Master Clock 2 and Boundary Clock 100, but the absolute value of the offset has a deviation that is greater than the first threshold value TH1, so it is considered that an abnormality has occurred in the time within the device of Grand Master Clock 2 (a fault has occurred in Grand Master Clock 2).

Pattern C is a pattern in which the offset fluctuation pattern is pattern 0 and the transmission delay time fluctuation pattern is pattern 1. That is, pattern C is a state in which the absolute value of the offset is equal to or less than the first threshold TH1, and the transmission delay time becomes greater than the third threshold TH3, and then becomes smaller than the third threshold TH3. In this case, in pattern C, even if the transmission delay time temporarily fluctuates greatly, the offset does not deviate by more than the first threshold TH1, so it is considered that a temporary failure (e.g., congestion) has occurred in the transmission path between Grand Master Clock 2 and Boundary Clock 100.

Pattern D is a pattern in which the offset fluctuation pattern is pattern 1 and the transmission delay time fluctuation pattern is pattern 1. That is, pattern D is a state in which the absolute value of the offset becomes larger than the first threshold TH1, then becomes equal to or smaller than the first threshold TH1, and the transmission delay time becomes larger than the third threshold TH3, then becomes smaller than the third threshold TH3. In this case, in pattern D, even if the transmission delay time temporarily increases, it returns to the original value, so it is considered that there is no failure in the transmission path between Grand Master Clock 2 and Boundary Clock 100 and a failure has occurred in Grand Master Clock 2 itself.

Pattern E is a pattern in which the offset fluctuation pattern is pattern 0 and the transmission delay time fluctuation pattern is pattern 2. That is, in pattern E, the absolute value of the offset is equal to or less than the first threshold TH1, and the transmission delay time remains greater than the third threshold TH3. Pattern F is a pattern in which the offset fluctuation pattern is pattern 1 and the transmission delay time fluctuation pattern is pattern 2. That is, in pattern F, the absolute value of the offset becomes greater than the first threshold TH1, and then becomes equal to or less than the first threshold TH1, and the transmission delay time remains greater than the third threshold TH3. In patterns E and F, the abnormality in the transmission delay time continues for a long time, so it is considered that an abnormality has occurred in the transmission path (e.g., cable) between the Grand Master Clock 2 and the Boundary Clock 100.

The fault location determination unit 111 determines the location of the fault based on a combination of the offset fluctuation pattern and the transmission delay time fluctuation pattern as described with reference to Fig. 6. Specifically, in the cases of patterns A, C, E, and F, the fault location determination unit 111 determines that no fault has occurred or that a fault has occurred in the transmission path between Grand Master Clock 2 and Boundary Clock 100. On the other hand, in the cases of patterns B and D, the fault location determination unit 111 determines that a fault has occurred in Grand Master Clock 2.

Referring again to Figure 3, if the fault location determination unit 111 determines that no fault has occurred or that a fault has occurred in the transmission path between Grand Master Clock 2 and Boundary Clock 100 (when the combination of the offset fluctuation pattern and the transmission delay time fluctuation pattern is pattern A, C, E, or F), the time itself delivered from Grand Master Clock 2 is accurate, so the internal time of client device 3 continues to be synchronized with the internal time of its own device.

If the fault location determination unit 111 determines that a fault has occurred in Grand Master Clock 2 (if the combination of the offset fluctuation pattern and the transmission delay time fluctuation pattern is pattern B or D), it notifies the Clock Class rewrite unit 110 that a fault has occurred in Grand Master Clock 2 (step S111).

When the Clock Class rewriting unit 110 receives a notification from the fault location determination unit 111, it rewrites the Clock Class so that the Clock Class indicates that the internal time of the Boundary Clock 100 is not synchronized with the internal time of the Grand Master Clock 2. As a result, synchronization of the internal time of the client device 3 with the internal time of the Boundary Clock 100 is stopped.

Note that in FIG. 3, the second threshold TH2 is described as the number of times the absolute value of the offset is determined to be greater than the first threshold TH1, but this is not limited to the above. The second threshold TH2 may be the time during which the absolute value of the offset is consecutively determined to be greater than the first threshold TH1. In this case, the offset pattern determination unit 107 determines, for example, whether the time during which the absolute value of the offset exceeds the first threshold TH1 is longer than the second threshold TH2 (e.g., 30 seconds).

In addition, in FIG. 3, the fourth threshold TH4 is described as the number of times the transmission delay time is determined to be greater than the third threshold TH3, but this is not limited to the above. The fourth threshold TH4 may be the time during which the transmission delay time is consecutively determined to be greater than the third threshold TH3. In this case, the transmission delay time pattern determination unit 108 determines, for example, whether the time during which the transmission delay time exceeds the third threshold TH3 is longer than the fourth threshold TH4 (for example, 30 seconds).

Then, the fault location determination unit 111 determines that the fault location is Grand Master Clock 2 if the time or number of times that the absolute value of the offset is determined to be greater than the first threshold TH1 is greater than the second threshold TH2 and the transmission delay time is equal to or less than the third threshold TH3. Alternatively, the fault location determination unit 111 determines that the fault location is Grand Master Clock 2 if the time or number of times that the absolute value of the offset is determined to be greater than the first threshold TH1 is greater than the second threshold TH2 and the time or number of times that the transmission delay time is determined to be greater than the third threshold TH3 is less than the fourth threshold TH4.

It is also possible to consider a method of determining the occurrence and location of a fault using only the fluctuation pattern of the transmission delay time. For example, if the fluctuation pattern of the transmission delay time fluctuates as shown in pattern 1 in FIG. 5B, it is determined that a fault has occurred in Grand Master Clock 2, and if it fluctuates as shown in pattern 2 in FIG. 5C, it is determined that a fault has occurred in the transmission path between Grand Master Clock 2 and Boundary Clock 100. However, with this method, it may not be possible to accurately determine the occurrence and location of the fault.

For example, if time T1 and time T4 are shifted by the same amount, as is clear from equation 2 above, time T1 and time T4 cancel each other out, and it may not be possible to determine the change in transmission delay time due to the shift between time T1 and time T4.

On the other hand, in this embodiment, by using not only the fluctuation pattern of the transmission delay time but also the fluctuation pattern of the offset, it is possible to more accurately determine the occurrence of a fault and the location of the fault. In the above example, even if time T1 and time T4 are shifted by the same amount, as is clear from the above formula 1, time T1 and time T4 are not canceled out, so the shift between time T1 and time T4 can be determined as a fluctuation in the offset.

In this embodiment, the time synchronization device according to the present disclosure has been described using an example in which the device performs time synchronization between the Grand Master Clock 2 and the client device 3, but this is not limited to the above. The time synchronization device according to the present disclosure may perform time synchronization between one Boundary Clock and another Boundary Clock, for example.

Next, we will explain the hardware configuration of the Boundary Clock 100 as a time synchronization device in this embodiment.

Figure 7 is a diagram showing an example of the hardware configuration of the Boundary Clock 100 as a time synchronization device according to this embodiment. Figure 7 shows an example of the hardware configuration of the Boundary Clock 100 when the Boundary Clock 100 is configured by a computer capable of executing program instructions. Here, the computer may be a general-purpose computer, a dedicated computer, a workstation, a PC (Personal computer), an electronic notepad, etc. The program instructions may be program code, code segments, etc. for performing the required tasks.

As shown in Figure 7, the Boundary Clock 100 has a processor 11, a ROM (Read Only Memory) 12, a RAM (Random Access Memory) 13, a storage 14, an input unit 15, a display unit 16, and a communication interface (I/F) 17. Each component is connected to each other via a bus 19 so that they can communicate with each other. The processor 11 is specifically a CPU (Central Processing Unit), an MPU (Micro Processing Unit), a GPU (Graphics Processing Unit), a DSP (Digital Signal Processor), a SoC (System on a Chip), etc., and may be composed of multiple processors of the same or different types.

The processor 11 is a control unit that controls each component and executes various arithmetic processing. That is, the processor 11 reads a program from the ROM 12 or the storage 14, and executes the program using the RAM 13 as a working area. The processor 11 controls each component and executes various arithmetic processing according to the program stored in the ROM 12 or the storage 14. In this embodiment, the ROM 12 or the storage 14 stores a program for causing a computer to function as the Boundary Clock 100 according to the present disclosure. The program is read and executed by the processor 11, thereby realizing each component of the Boundary Clock 100, namely, the offset calculation unit 102, the transmission delay time calculation unit 103, the time synchronization processing unit 104, the offset pattern determination unit 107, the transmission delay time pattern determination unit 108, the count flag unit 109, the Clock Class rewriting unit 110, and the fault location determination unit 111.

The program may be provided in a form stored in a non-transitory storage medium such as a CD-ROM (Compact Disk Read Only Memory), a DVD-ROM (Digital Versatile Disk Read Only Memory), or a USB (Universal Serial Bus) memory. The program may also be provided in a form downloaded from an external device via a network.

ROM 12 stores various programs and various data. RAM 13 temporarily stores programs or data as a working area. Storage 14 is configured with a HDD (Hard Disk Drive) or SSD (Solid State Drive) and stores various programs including an operating system and various data. ROM 12 or storage 14 stores, for example, the first threshold TH1, the second threshold TH2, the third threshold TH3, and the fourth threshold TH4 described above.

The input unit 15 includes a pointing device such as a mouse and a keyboard, and is used to make various types of input.

The display unit 16 is, for example, a liquid crystal display, and displays various information. The display unit 16 may be a touch panel type and function as the input unit 15.

The communication interface 17 is an interface for communicating with other devices (e.g., the Grand Master Clock 2 and the client device 3), for example, an interface for a LAN.

A computer can be suitably used to function as each part of the Boundary Clock 100 described above. Such a computer can be realized by storing a program describing the processing contents for realizing the functions of each part of the Boundary Clock 100 in the memory of the computer, and having the processor of the computer read and execute this program. In other words, the program can cause the computer to function as the Boundary Clock 100 described above. The program can also be recorded on a non-transitory storage medium. The program can also be provided via a network.

Thus, the Boundary Clock 100 as a time synchronization device according to this embodiment includes an offset calculation unit 102, a transmission delay time calculation unit 103, an offset pattern determination unit 107, a transmission delay time pattern determination unit 108, and a fault location determination unit 111. The offset calculation unit 102 calculates an offset, which is the difference between the internal time of the higher-level device and the internal time of the local device. The transmission delay time calculation unit 103 calculates the transmission delay time of a packet transmitted and received between the higher-level device and the local device. The offset pattern determination unit 107 determines the offset fluctuation pattern. The transmission delay time pattern determination unit 108 determines the transmission delay time fluctuation pattern. The fault location determination unit 111 determines the location of a fault in time synchronization with the higher-level device based on the offset fluctuation pattern and the transmission delay time fluctuation pattern.

The time synchronization method according to the embodiment includes a step (step S101) in which the offset calculation unit 102 calculates an offset, which is the difference between the internal time of the host device and the internal time of the host device, and a step (step S106) in which the transmission delay time calculation unit 103 calculates the transmission delay time of a packet transmitted and received between the host device and the host device. The time synchronization method according to the embodiment also includes a step (steps S102 to S104) in which the offset pattern determination unit 107 determines the fluctuation pattern of the offset, a step (steps S107 to S109) in which the transmission delay time pattern determination unit 108 determines the fluctuation pattern of the transmission delay time, and a step (step S110) in which the fault location determination unit 111 determines the location of the fault in the time synchronization with the host device based on the fluctuation pattern of the offset and the fluctuation pattern of the transmission delay time.

By determining the location of a fault based on the offset fluctuation pattern and the transmission delay time fluctuation pattern, it is possible to more accurately determine the occurrence and location of a fault without being affected by the deviation of the internal time of the Grand Master Clock 2. As a result, it is possible to reduce the possibility of synchronizing the internal time of a lower-level device to an incorrect time.

Second Embodiment
FIG. 8 is a diagram illustrating an example of the configuration of a Boundary Clock 100A as a time synchronization device according to the second embodiment of the present disclosure.

8, the Boundary Clock 100A according to this embodiment includes packet transmission/reception units 101, 101A, 105, an offset calculation unit 102, a transmission delay time calculation unit 103, a time synchronization processing unit 104, a threshold storage unit 106, an offset pattern determination unit 107, a transmission delay time pattern determination unit 108, a count flag unit 109, a fault location determination unit 111A, and a time selection unit 112. The Boundary Clock 100A according to this embodiment differs from the Boundary Clock 100 according to the first embodiment in that the packet transmission/reception unit 101A and the time selection unit 112 are added, the Clock Class rewriting unit 110 is deleted, and the fault location determination unit 111 is changed to the fault location determination unit 111A.

The packet transmitter/receiver 101A transmits and receives packets to and from a Grand Master Clock 2A that is different from the Grand Master Clock 2 with which the packet transmitter/receiver 101 transmits and receives packets. That is, the Boundary Clock 100A according to this embodiment can communicate with multiple Grand Master Clocks 2 and 2A. The packet transmitter/receiver 101A outputs packets received from the Grand Master Clock 2A to the offset calculation unit 102 and the transmission delay time calculation unit 103.

The time selection unit 112 selects a clock with which the internal time of the device is to be synchronized from among a plurality of Grand Master Clocks 2, 2A with which the Boundary Clock 100A can communicate. The time selection unit 112 selects a clock with which the internal time of the device is to be synchronized, for example, in accordance with the Best Master Clock Algorithm (BMCA) defined in IEEE Std 1588 ^™ -2019.

Like the fault location determination unit 111, the fault location determination unit 111A determines the occurrence of a fault in time synchronization with a higher-level device and the location of the fault based on the offset fluctuation pattern and the transmission delay time fluctuation pattern. Then, when the fault location determination unit 111A determines that the location of the fault is the higher-level device with which the internal time of the device itself is synchronized, it causes the time selection unit 112 to switch the target with which the internal time of the device itself is synchronized.

Next, the operation of the Boundary Clock 100A in this embodiment will be described.

Figure 9 is a flowchart showing an example of the operation of the Boundary Clock 100A according to this embodiment. In Figure 9, the same processes as those in Figure 3 are given the same reference numerals and the description is omitted.

In parallel with the processes of steps S101 to S104 and steps S106 to S109 described with reference to Fig. 3, the time selection unit 112 selects a time synchronization target with which the internal time of the device itself is synchronized by the BMCA (step S201). The selection of the time synchronization target by the BMCA is described in IEEE Std 1588 ^™ -2019 and the like, so a detailed description will be omitted, but an overview will be described with reference to Fig. 10. In Fig. 10, an example will be described in which the time synchronization target is selected from two higher-level devices (Grand Master Clock A and Grand Master Clock B).

The time selection unit 112 acquires packets containing the following parameters transmitted from Grand Master Clock A and Grand Master Clock B via the packet transmission/reception units 101 and 101A, respectively.
GM Identity: Unique identification code for the Grand Master Clock GM priority 1: First priority for each Grand Master Clock set by the administrator GM class: Value indicating the traceability (traceability to UTC (index showing the reliability of time)) for each Grand Master Clock GM accuracy value: Value indicating the accuracy of the time for each Grand Master Clock GM offsetScaledLogVariance: Value indicating the stability for each Grand Master Clock GM priority 2: Second priority for each Grand Master Clock set by the administrator

First, the time selection unit 112 compares the identification codes of Grand Master Clock A and Grand Master Clock B to determine whether the identification codes of Grand Master Clock A and Grand Master Clock B are the same (step S301). If it is determined that the identification codes of Grand Master Clock A and Grand Master Clock B are the same (step S301: Yes), the time selection unit 112 selects the target for time synchronization by comparing the number of connection stages from each Grand Master Clock to Boundary Clock 100A, the upstream port number, the receiving port number, and the receiving port number of the same data set, although details will be omitted.

If it is determined that the identification codes of Grand Master Clock A and Grand Master Clock B are not the same (step S301: No), the time selection unit 112 compares the priority 1 of Grand Master Clock A and Grand Master Clock B (step S302).

If priority 1 of Grand Master Clock A is lower than priority 1 of Grand Master Clock B (A<B), the time selection unit 112 selects Grand Master Clock A as the target for time synchronization.

If priority 1 of Grand Master Clock B is lower than priority 1 of Grand Master Clock A (B<A), the time selection unit 112 selects Grand Master Clock B as the target for time synchronization.

If the priority 1 of Grand Master Clock A and Grand Master Clock B is the same (A=B), the time selection unit 112 compares the GM classes of Grand Master Clock A and Grand Master Clock B (step S303).

If the GM class of Grand Master Clock A is smaller than the GM class of Grand Master Clock B (A<B), the time selection unit 112 selects Grand Master Clock A as the target for time synchronization.

If the GM class of Grand Master Clock B is smaller than the GM class of Grand Master Clock A (B<A), the time selection unit 112 selects Grand Master Clock B as the target for time synchronization.

If the GM classes of Grand Master Clock A and Grand Master Clock B are the same (A=B), the time selection unit 112 compares the GM clock accuracy of Grand Master Clock A and Grand Master Clock B (step S304).

If the GM clock accuracy of Grand Master Clock A is smaller than the GM clock accuracy of Grand Master Clock B (A<B), the time selection unit 112 selects Grand Master Clock A as the target for time synchronization.

If the GM clock accuracy of Grand Master Clock B is smaller than the GM clock accuracy of Grand Master Clock A (B<A), the time selection unit 112 selects Grand Master Clock B as the target for time synchronization.

If the GM clock accuracy of Grand Master Clock A and Grand Master Clock B is the same (A=B), the time selection unit 112 compares the GM clock stability of Grand Master Clock A and Grand Master Clock B (step S305).

If the GM clock stability of Grand Master Clock A is less than the GM clock stability of Grand Master Clock B (A<B), the time selection unit 112 selects Grand Master Clock A as the target for time synchronization.

If the GM clock stability of Grand Master Clock B is less than the GM clock stability of Grand Master Clock A (B<A), the time selection unit 112 selects Grand Master Clock B as the target for time synchronization.

If the GM clock stability of Grand Master Clock A and Grand Master Clock B is the same (A=B), the time selection unit 112 compares the priority 2 of Grand Master Clock A and Grand Master Clock B (step S306).

If priority 2 of Grand Master Clock A is lower than priority 2 of Grand Master Clock B (A<B), the time selection unit 112 selects Grand Master Clock A as the target for time synchronization.

If priority 2 of Grand Master Clock B is lower than priority 2 of Grand Master Clock A (B<A), the time selection unit 112 selects Grand Master Clock B as the target for time synchronization.

If the priority 2 of Grand Master Clock A and Grand Master Clock B is the same (A=B), the time selection unit 112 compares the identification codes of Grand Master Clock A and Grand Master Clock B (step S307).

If the identification code of Grand Master Clock A is smaller than the identification code of Grand Master Clock B (A<B), the time selection unit 112 selects Grand Master Clock A as the target for time synchronization.

If the identification code of Grand Master Clock B is smaller than the identification code of Grand Master Clock A (B<A), the time selection unit 112 selects Grand Master Clock B as the target for time synchronization.

Through the above-described processing, the time selection unit 112 appropriately selects a higher-level device (Grand Master Clock 2 or Grand Master Clock 2A) with which to synchronize the internal time of the Boundary Clock 100A.

Referring again to Figure 9, when the fault location determination unit 111A determines that the location of the fault is a higher-level device (e.g., Grand Master Clock 2) that synchronizes the internal device time of the device itself, it notifies the time selection unit 112 that a fault has occurred in Grand Master Clock 2 (step S202).

Upon receiving a notification from the fault location determination unit 111A, the time selection unit 112 switches the target of time synchronization with which the internal time of the own device is synchronized. For example, when the internal time of the own device is synchronized with the internal time of Grand Master Clock 2 and the fault location determination unit 111A notifies the time selection unit 112 that a fault has occurred in Grand Master Clock 2, the time selection unit 112 switches the target of time synchronization from Grand Master Clock 2 to Grand Master Clock 2A. For example, when the time selection unit 112 determines that A=B in step S305 in the process of selecting the target of time synchronization by BMCA described with reference to FIG. 10, the time selection unit 112 switches the target of time synchronization.

Thus, the Boundary Clock 100A as a time synchronization device according to this embodiment further includes a time selection unit 112 that selects a higher-level device with which to synchronize the internal time of the device from among a plurality of higher-level devices (Grand Master Clocks 2, 2A). When the fault location determination unit 111A determines that the location of the fault is the higher-level device with which the internal time of the device is synchronized, it causes the time selection unit 112 to switch the higher-level device with which the internal time of the device is synchronized.

This reduces the possibility of synchronizing the internal time of a lower-level device to an incorrect time.

The Boundary Clock 100A relating to the second embodiment can also be configured by a computer having the hardware configuration described with reference to Figure 7.

The following notes are further disclosed with respect to the above embodiments.

[Additional Note 1]
A time synchronization device that synchronizes its own internal time with the internal time of a higher-level device and synchronizes the internal time of a lower-level device with the internal time of its own device by transmitting and receiving packets to and from the higher-level device,
Memory,
A control unit connected to the memory;
Equipped with
The control unit is
Calculating an offset, which is a difference between the device time of the higher-level device and the device time of the own device;
Calculating a transmission delay time of a packet transmitted and received between the higher-level device and the own device;
determining a variation pattern of the offset;
determining a variation pattern of the transmission delay time;
A time synchronization device that determines a location of an occurrence of a failure in time synchronization with the higher-level device based on a fluctuation pattern of the offset and a fluctuation pattern of the transmission delay time.

[Additional Note 2]
In the time synchronization device according to claim 1,
When the control unit determines that the location of the failure is the higher-level device, the control unit stops synchronization of the internal device time of the lower-level device with the internal device time of the own device.

[Additional Note 3]
In the time synchronization device according to claim 1,
The control unit is
selecting a host device with which to synchronize the internal time of the host device from among the plurality of host devices;
When it is determined that the location of the failure is the host device, the time synchronization device switches, from among a plurality of host devices, a host device with which the internal device time of the time synchronization device is synchronized.

[Additional Note 4]
In the time synchronization device according to claim 1,
The control unit is
determining whether an absolute value of the offset is greater than a first threshold value, and determining, as a fluctuation pattern of the offset, whether a time or a number of times that the absolute value of the offset is determined to be greater than the first threshold value is greater than a second threshold value;
A time synchronization device that determines whether the transmission delay time is greater than a third threshold value, and determines, as a fluctuation pattern of the transmission delay time, whether the time or number of times that the transmission delay time is determined to be greater than the third threshold value is greater than a fourth threshold value.

[Additional Note 5]
In the time synchronization device according to claim 4,
The control unit determines that the location of the fault is the higher-level device when the time or number of times that the absolute value of the offset is determined to be greater than the first threshold is greater than the second threshold and the transmission delay time is less than the third threshold, or when the time or number of times that the transmission delay time is determined to be greater than the third threshold is less than the fourth threshold.

[Additional Note 6]
1. A time synchronization method for synchronizing a device's internal time with a device's internal time of a higher-level device by transmitting and receiving packets to and from the higher-level device, and for synchronizing a device's internal time with the device's internal time, comprising:
Calculating an offset, which is a difference between the device time of the higher-level device and the device time of the own device;
Calculating a transmission delay time of a packet transmitted and received between the higher-level device and the device itself;
determining a variation pattern of the offset;
determining a variation pattern of the transmission delay time;
A time synchronization method for determining a location of a failure in time synchronization with the higher-level device based on a fluctuation pattern of the offset and a fluctuation pattern of the transmission delay time.

[Additional Note 7]
A non-transitory storage medium storing a program executable by a computer, the non-transitory storage medium storing the program causing the computer to operate as the time synchronization device according to claim 1.

Although the above-mentioned embodiment has been described as a representative example, it will be apparent to those skilled in the art that many modifications and substitutions can be made within the spirit and scope of the present disclosure. Therefore, the present invention should not be interpreted as being limited by the above-mentioned embodiment, and various modifications or changes are possible without departing from the scope of the claims. For example, it is possible to combine multiple configuration blocks shown in the configuration diagram of the embodiment into one, or to divide one configuration block.

1 Time Synchronization System 2, 2A Grand Master Clock (Higher-level device)
3. Client device (lower device)
11 processor 12 ROM
13 RAM
14 Storage 15 Input unit 16 Display unit 17 Communication I/F
19 Bus 100, 100A Boundary Clock (time synchronization device)
REFERENCE SIGNS LIST 101, 101A, 105 Packet transmitting/receiving unit 102 Offset calculation unit 103 Transmission delay time calculation unit 104 Time synchronization processing unit 106 Threshold storage unit 107 Offset pattern determination unit 108 Transmission delay time pattern determination unit 109 Count flag unit 110 Clock class rewriting unit 111, 111A Fault location determination unit 112 Time selection unit

Claims (7)

A time synchronization device that synchronizes its own internal time with the internal time of a higher-level device and synchronizes the internal time of a lower-level device with the internal time of its own device by transmitting and receiving packets to and from the higher-level device,
an offset calculation unit that calculates an offset, which is a difference between a device time of the higher-level device and a device time of the own device;
a transmission delay time calculation unit that calculates a transmission delay time of a packet transmitted and received between the higher-level device and the device itself;
an offset pattern determination unit that determines a fluctuation pattern of the offset;
A transmission delay time pattern determination unit that determines a fluctuation pattern of the transmission delay time;
A time synchronization device comprising: a failure location determination unit that determines a location of a failure in time synchronization with the higher-level device based on a fluctuation pattern of the offset and a fluctuation pattern of the transmission delay time. 2. The time synchronization device according to claim 1,
When the failure location determination unit determines that the location of the failure is the higher-level device, the failure location determination unit stops synchronization of the internal device time of the lower-level device with the internal device time of the own device. 2. The time synchronization device according to claim 1,
a time selection unit that selects, from among a plurality of higher-level devices, a higher-level device with which the internal time of the device is to be synchronized;
a time synchronization device, wherein when the failure location determination unit determines that the location of the failure is the higher-level device, the time selection unit switches the higher-level device with which the internal device time of the device is synchronized; 4. The time synchronization device according to claim 1,
the offset pattern determination unit determines whether an absolute value of the offset is greater than a first threshold, and determines, as a fluctuation pattern of the offset, whether a time or a number of times that the absolute value of the offset is determined to be greater than the first threshold is greater than a second threshold;
The transmission delay time pattern determination unit determines whether the transmission delay time is greater than a third threshold value, and determines, as a fluctuation pattern of the transmission delay time, whether the time or number of times the transmission delay time is determined to be greater than the third threshold value is greater than a fourth threshold value. 5. The time synchronization device according to claim 4,
The fault location determination unit is
The time or the number of times that the absolute value of the offset is determined to be greater than the first threshold is greater than the second threshold, and the transmission delay time is equal to or less than the third threshold, or
A time synchronization device that determines that the location of the fault is the higher-level device when the time or number of times that the absolute value of the offset is determined to be greater than the first threshold is greater than the second threshold, and when the time or number of times that the transmission delay time is determined to be greater than the third threshold is smaller than the fourth threshold. 1. A time synchronization method for synchronizing a device's internal time with a device's internal time of a higher-level device by transmitting and receiving packets to and from the higher-level device, and for synchronizing a device's internal time with the device's internal time, comprising:
calculating an offset which is a difference between a device time of the higher-level device and a device time of the own device;
calculating a transmission delay time of a packet transmitted and received between the higher-level device and the own device;
determining a variation pattern of the offset;
determining a fluctuation pattern of the transmission delay time;
and determining a location of a failure in time synchronization with the higher-level device based on a fluctuation pattern of the offset and a fluctuation pattern of the transmission delay time. A program that causes a computer to operate as a time synchronization device according to any one of claims 1 to 5.

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