JP7611685B2 - Semiconductor device and switching power supply device - Google Patents

Description

The present invention relates to a semiconductor device and a switching power supply device.

FIG. 11 is a cross-sectional view showing a mesa diode for voltage clamping in a conventional power clamper.
This voltage clamping mesa diode has an N ⁺⁺ type silicon substrate 101, and an N type epitaxial layer 102 is formed on the N ⁺⁺ type silicon substrate 101. Both ends of the N type epitaxial layer 102 are tapered. A P ⁺⁺ type diffusion layer 103 is formed on the surface side of the N type epitaxial layer 102, and an insulating layer 105 such as a glass passivation layer is formed on both ends of the tapered P ⁺⁺ type diffusion layer 103 and the N type epitaxial layer 102. A first metal film 104 made of a laminated film of a Ni layer and an Au layer or a Ni film is formed on the P ⁺⁺ type diffusion layer 103. A second metal film 106 made of a laminated film of a Ni layer and an Au layer or a Ni film is formed under the N ⁺⁺ type silicon substrate 101. A technology related to such a voltage clamping mesa diode is described in, for example, Patent Document 1.

The power clamper combines a voltage clamping mesa diode and a high-speed rectifier diode into a single element. With conventional power clampers, the generation of noise in the GHz range was not an issue.

However, the noise regulations of CISPR (Comite International Special des Perturbations Radioelectriques) have changed, and it is now required to suppress the generation of noise in the GHz band. It has been confirmed that GHz band noise is also generated from the mesa diode for voltage clamping of the power clamper shown in Figure 11.

CISPR is a special committee of the International Electrotechnical Commission (IEC) whose purpose is to promote international trade by reaching international agreement on the acceptable limits and measurement methods for unwanted radio waves (interference waves) from various devices that cause wireless interference.

JP 2014-192500 A

The various aspects of the present invention aim to provide a semiconductor device that can suppress the generation of noise in the GHz band and a switching power supply device equipped with the semiconductor device.

Various aspects of the present invention are described below.

[1] A semiconductor substrate of a first conductivity type;
a semiconductor layer of a first conductivity type located on the semiconductor substrate;
a first second conductivity type diffusion layer located on a surface side within the first conductivity type semiconductor layer;
a second second-conductivity-type diffusion layer that is located in the first-conductivity-type semiconductor layer, that is in contact with the first second-conductivity-type diffusion layer in a plan view, that is disposed so as to surround the first second-conductivity-type diffusion layer, and that is formed so as to have a higher breakdown voltage than the first second-conductivity-type diffusion layer;
an insulating layer located on the second second-conductivity type diffusion layer and on the semiconductor layer outside the second second-conductivity type diffusion layer in a plan view;
a metal plate located on the first second conductivity type diffusion layer, the second second conductivity type diffusion layer, and the insulating layer;
A semiconductor device comprising:

[2] In the above [1],
a second diffusion layer of the second conductivity type having an impurity concentration gradient that is gentler than that of the first diffusion layer of the second conductivity type;

[3] In the above [1] or [2],
The semiconductor device according to claim 1, wherein the second diffusion layer of the second conductivity type is deeper than the first diffusion layer of the second conductivity type.
[4] In the above [3],
a surface concentration of the second second-conductivity type diffusion layer being higher than that of the first second-conductivity type diffusion layer;
[5] In the above [3],
a surface concentration of the second second-conductivity type diffusion layer being equal to that of the first second-conductivity type diffusion layer;

[6] In the above [1] or [2],
a depth of the second diffusion layer of the second conductivity type is shallower than a depth of the first diffusion layer of the second conductivity type.
[7] In the above [3] or [6],
a surface concentration of the second second-conductivity type diffusion layer being lower than a surface concentration of the first second-conductivity type diffusion layer;

[8] A semiconductor substrate of a first conductivity type;
a semiconductor layer of a first conductivity type located on the semiconductor substrate;
a second conductive type diffusion layer located on a surface side within the first conductive type semiconductor layer;
a buried layer of a first conductivity type, which is located within the semiconductor layer of the first conductivity type, below the diffusion layer of the second conductivity type, in contact with the diffusion layer of the second conductivity type, and located inside the diffusion layer of the second conductivity type in a plan view, and has an impurity concentration higher than that of the semiconductor layer of the first conductivity type;
an insulating layer located on an end of the second conductive type diffusion layer outside the buried layer of the first conductive type and on the semiconductor layer outside the end of the second conductive type diffusion layer in a plan view;
a metal plate located on the second conductive type diffusion layer, an end of the second conductive type diffusion layer, and the insulating layer;
A semiconductor device comprising:

[9] In any one of the above [1] to [8],
The semiconductor device is characterized in that the metal plate has a first metal layer and a second metal layer located on the first metal layer, and the first metal layer is electrically connected to the second metal layer.

[10] In any one of the above [1] to [9],
A semiconductor device having solder located on said metal plate.

[11] In the above [10],
The semiconductor device according to claim 1, wherein the solder is located on the metal plate on each of the first second-conductivity type diffusion layer, the second second-conductivity type diffusion layer, and the insulating layer.

[12] In any one of the above [1] to [11],
a first lead wire electrically connected to the metal plate;
a second lead wire electrically connected to the semiconductor substrate;
a resin that seals a portion of each of the first lead wire and the second lead wire, the semiconductor substrate, and the metal plate;
a shielding film covering a surface of the resin;
having
The semiconductor device according to claim 1, wherein the shielding film is in contact with at least one of the first lead wire and the second lead wire.

[13] In any one of the above [1] to [11],
a first lead wire electrically connected to the metal plate;
a second lead wire electrically connected to the semiconductor substrate;
a resin that seals a portion of each of the first lead wire and the second lead wire, the semiconductor substrate, and the metal plate;
having
The semiconductor device according to the present invention is characterized in that the resin contains a material having a higher dielectric constant than the resin.

[14] A semiconductor substrate of a first conductivity type;
a semiconductor layer of a first conductivity type located on the semiconductor substrate;
a second conductive type diffusion layer located on a surface side within the first conductive type semiconductor layer;
a metal plate located on the second conductive type diffusion layer;
a first lead wire electrically connected to the metal plate;
a second lead wire electrically connected to the semiconductor substrate;
a resin that seals a portion of each of the first lead wire and the second lead wire, the semiconductor substrate, and the metal plate;
a shielding film covering a surface of the resin;
having
The semiconductor device according to claim 1, wherein the shielding film is in contact with at least one of the first lead wire and the second lead wire.

[15] In the above [12] or [14],
The semiconductor device according to the present invention is characterized in that the resin contains a material having a higher dielectric constant than the resin.

[16] A semiconductor substrate of a first conductivity type;
a semiconductor layer of a first conductivity type located on the semiconductor substrate;
a second conductive type diffusion layer located on a surface side within the first conductive type semiconductor layer;
a metal plate located on the second conductive type diffusion layer;
a first lead wire electrically connected to the metal plate;
a second lead wire electrically connected to the semiconductor substrate;
a resin that seals a portion of each of the first lead wire and the second lead wire, the semiconductor substrate, and the metal plate;
having
The semiconductor device according to the present invention is characterized in that the resin contains a material having a higher dielectric constant than the resin.

[17] In any one of the above [1] to [16],
The semiconductor device, wherein the metal plate has at least one metal layer selected from the group consisting of an Al layer, a Ni layer, a Ti layer, an Au layer, and a laminate of a Ni layer and an Al layer.

[18] A switching power supply device comprising a power clamper including a semiconductor device according to any one of [1] to [17] above.

Various aspects of the present invention provide a semiconductor device capable of suppressing the generation of noise in the GHz band, and a switching power supply device including the semiconductor device.

2. FIG. 2 is a cross-sectional view taken along line 2-2 shown in FIG. FIG. 1 is a plan view illustrating a semiconductor device according to one embodiment of the present invention. This is a modification in which the depth of the second P ⁺ -type impurity diffusion layer 14 shown in FIG. 1 is changed. This is a modification in which the depth of the second P ⁺ -type impurity diffusion layer 14 shown in FIG. 1 is changed. 2 is a cross-sectional view showing the structure above the N-type epitaxial layer 12 shown in FIG. 1. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 2 is a diagram showing a typical concentration distribution of an impurity introduced for forming a semiconductor device according to one embodiment of the present invention. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 1 is a cross-sectional view showing a mesa diode for voltage clamping of a conventional power clamper. FIG. 1 is a cross-sectional view showing a conventional planar diode. 1 is a circuit diagram illustrating a switching power supply device according to one embodiment of the present invention. FIG. 1 is a circuit diagram showing a switching power supply device using a DCR snubber of a comparative example. FIG. 2 is a diagram showing the results of an experiment conducted on the generation of noise in the GHz band (1 GHz to 6 GHz) from a sample of the voltage clamp planar diode shown in FIG. 1 .

The following describes in detail the embodiments of the present invention with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art will easily understand that the form and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

(First embodiment)
<Planar diode for voltage clamping>
Fig. 2 is a plan view showing a semiconductor device according to one embodiment of the present invention. Fig. 1 is a cross-sectional view taken along line 2-2 shown in Fig. 2. Reference characters A to F shown in Fig. 1 correspond to reference characters A to F shown in Fig. 2, and the dashed lines shown in Figs. 1 and 2 are intended to make the relationship between the cross-sectional view shown in Fig. 1 and the plan view shown in Fig. 2 easier to understand. However, Fig. 2 shows only the N ⁺⁺ type silicon substrate 11, the first P ⁺ type impurity diffusion layer 13, the second P ⁺ type impurity diffusion layer 14, and the Al layer 16, and does not show the other parts.

3 and 4 each show a modified example in which the depth of the second P ⁺ type impurity diffusion layer 14 shown in Fig. 1 is changed. However, Fig. 3 and Fig. 4 only show the first P ⁺ type impurity diffusion layer 13 and the second P ⁺ type impurity diffusion layers 14a and 14b, and the other configurations are the same as those in Fig. 1.

FIG. 5 shows the N-type epitaxial layer 12 and above shown in FIG. 1, and the rest of the configuration is the same as that shown in FIG.
FIG. 8 is a diagram for explaining that the impurity concentration gradient [0] of the second P ⁺ type impurity diffusion layers 14, 14a, 14b shown in FIGS. 1, 3, 4, 5, and 7 is formed more gently than the impurity concentration gradient [0] of the first P ⁺ type impurity diffusion layer 13.

The semiconductor device shown in FIG. 1 is a voltage clamp planar diode, and this voltage clamp planar diode has an N ⁺⁺ type silicon substrate 11 (also referred to as a "first conductivity type semiconductor substrate"). An N type epitaxial layer 12 (also referred to as a "first conductivity type semiconductor layer") is formed on this N ⁺⁺ type silicon substrate 11. A first P+ type impurity diffusion layer 13 (also referred to as a "first second conductivity type diffusion layer") is formed on the surface side of this N type epitaxial layer 12. In addition, a second P ⁺ type impurity diffusion layer 14 ( ^also referred to as a "second second conductivity type diffusion layer") is formed in the N type epitaxial layer 12. The second P ⁺ type impurity diffusion layer 14 is in contact with the first P ⁺ type impurity diffusion layer 13 in a plan view, and is arranged to surround the first P ⁺ type impurity diffusion layer 13 as shown in FIG. 2. During the clamping operation, a current flows in a semiconductor region located under a metal plate described later. That is, the second P ⁺ type impurity diffusion layer 14 is formed to have a higher breakdown voltage than the first P ⁺ type impurity diffusion layer 13. In detail, the second P ⁺ type impurity diffusion layer 14 is formed to cause a breakdown phenomenon (Zener breakdown phenomenon, avalanche breakdown phenomenon, or a breakdown phenomenon in which the Zener breakdown phenomenon and the avalanche ^{breakdown phenomenon are mixed) in the first P+ type} impurity diffusion layer 13 or in the vicinity of the contact portion between the second P ^{+ type impurity diffusion layer 14 and the first P+} type impurity diffusion layer 13. In order to realize this, as detailed typical examples, the impurity concentration gradient [0] of the second P + type impurity diffusion layer 14 is formed more gently [0] than the impurity concentration gradient of the first P ⁺ type impurity diffusion layer 13, as shown in the relationship between (2) shown in FIG. 8 and (1) shown in FIG. 8, (3) shown in FIG. 8 and (1) shown in FIG. 8, ⁽ 4) shown in FIG. 8 and (1) shown in FIG. 8, or (5) shown in FIG. 8 and (1) shown in FIG. 8. The impurity concentration gradient here refers to the absolute value of the rate of change of the impurity concentration that changes as it approaches the PN junction. Note that in FIG. 8, a typical Gaussian type change is assumed, and the impurity concentration simply decreases in the depth direction, but as long as the breakdown phenomenon occurs as described above, any distribution of the impurity concentration is acceptable, and is not limited to the example shown in FIG. 8. This is also true in other embodiments of the present invention. The second P ⁺ type impurity diffusion layer 14 may have a surface concentration higher, equal to, or lower than that of the first P ⁺ type impurity diffusion layer 13, and is preferably formed by diffusing deeper than the first P ⁺ type impurity diffusion layer 13.
In addition, each of the first and second P ⁺ type impurity diffusion layers 13 and 14 may be formed, for example, by arranging a diffusion source of a P type impurity on the surface of the N type epitaxial layer 12 and thermally diffusing the P type impurity into the N type epitaxial layer 12, or by ion-implanting the P type impurity into the N type epitaxial layer 12 and then thermally diffusing the P type impurity.

2, the planar shape of the first P ⁺ type impurity diffusion layer 13 viewed from above is a quadrangle with arcuate or rounded corners. The planar shape of the second P ⁺ type impurity diffusion layer 14 is a shape that surrounds the periphery of the first P ⁺ type impurity diffusion layer 13, and the outline of the planar shape of the second P ⁺ type impurity diffusion layer 14 is an enlarged outline of the planar shape of the first P ⁺ type impurity diffusion layer 13.

As shown in FIG. 1, the second P ⁺ type impurity diffusion layer 14 is preferably formed deeper than the first P ⁺ type impurity diffusion layer 13, but as shown in FIG. 3, the second P ⁺ type impurity diffusion layer 14a may be formed at the same depth as the first P ⁺ type impurity diffusion layer 13, or as shown in FIG. 4, the second P ⁺ type impurity diffusion layer 14b may be formed shallower than the first P ⁺ type impurity diffusion layer 13. Here, the second P+ type impurity diffusion layer 14a (corresponding to (4) in FIG. 8) shown in FIG. 3 has a more gentle impurity concentration gradient than the first P+ type impurity diffusion layer 13 (corresponding to (1) in FIG. 8) shown in FIG. 3. Also, the second P+ type impurity diffusion layer 14b (corresponding to (6) in FIG. 8) shown in FIG. 4 has a more gentle impurity concentration gradient than the first P+ type impurity diffusion layer 13 (corresponding to (1) in FIG. 8) shown in FIG. 4. The effect of suppressing the generation of noise in the 1 to 6 GHz band can be obtained whether the depth of the second P ⁺ type impurity diffusion layer 14 is deep or shallow. However, when the second P ⁺ type impurity diffusion layer 14 is formed deeper than the first P ⁺ type impurity diffusion layer 13, it is expected that the diode characteristics can be improved and the effect of suppressing the generation of noise in the 1 to 6 GHz band can be increased more than when the second P+ type impurity diffusion layer 14 is formed at the same depth or shallower.

As shown in Fig. 1, an insulating layer 15 is formed on the second P ⁺ type impurity diffusion layer 14 and on the N type epitaxial layer 12 on the outside of the second P ⁺ type impurity diffusion layer 14 in a plan view. This insulating layer 15 is formed of, for example, _SiO2 and PSG (Phospho-Silicate Glass). An Al layer 16 (also called a "metal plate") is formed on the first P ⁺ type impurity diffusion layer 13, the second P ⁺ type impurity diffusion layer 14, and the insulating layer 15. The Al layer 16 is formed to extend to the outside of the second P ⁺ type impurity diffusion layer 14 as shown in Fig. 2.

1, an N ⁺⁺ impurity diffusion layer 26 is formed in the N-type epitaxial layer 12. The N ⁺⁺ impurity diffusion layer 26 is located outside the second P ⁺ type impurity diffusion layer 14 in a plan view and is formed away from the second P ⁺ type impurity diffusion layer 14. The insulating layer 15 is located on the second P ⁺ type impurity diffusion layer 14, the N-type epitaxial layer 12, and the N ⁺⁺ impurity diffusion layer 26. An Al layer 32 is formed on the insulating layer 15 and the N ⁺⁺ impurity diffusion layer 26. A Ti/Ni metal layer 28 is formed under the N ⁺⁺ type silicon substrate 11, in which a Ti layer and a Ni layer are stacked in order.

On the Al layer 16 (also called the "first metal layer"), a Ti/Ni metal layer 17 (also called the "second metal layer") is formed by laminating a Ti layer and a Ni layer in order, and this Ti/Ni metal layer 17 is electrically connected to the Al layer 16. As mentioned above, the Al layer 16 may be a metal plate, but the Al layer 16 and the Ti/Ni metal layer 17 may be collectively called the metal plate 18.

A polyimide film 27 is formed on the N ⁺⁺ impurity diffusion layer 26, the insulating layer 15, and the Al layers 16 and 32. Solder 19 is formed on the Ti/Ni metal layer 17. In Fig. 1, the polyimide film 27 is not formed on the Ti/Ni metal layer 17, but the Ti/Ni metal layer 17 may be formed to extend toward the end of the Al layer 16, and the polyimide film 27 may also be formed on the Ti/Ni metal layer 17.

As described above, it is expected that the noise reduction effect can be increased by forming the Ti/Ni metal layer 17 so that it extends toward the edge of the Al layer 16.

As shown in FIG. 1, the solder 19 may be formed mainly in the opening 27a of the polyimide film 27 located on the first P ⁺ type impurity diffusion layer 13 (in other words, on the Ti/Ni metal layer 17 exposed from the polyimide film 27 located mainly on the first P ⁺ type impurity diffusion layer 13). However, as shown in FIG. 5, the opening 27b of the polyimide film 27 in which the solder 19 is formed may be formed so as to be widely spread toward the end of the Al layer 16, and the solder 19 may be formed in the opening 27b. In other words, the Ti/Ni metal layer 17 may be formed on each of the first P ⁺ type impurity diffusion layer 13, the second P ⁺ type impurity diffusion layer 14, and the insulating layer 15, and the solder 19 may be formed on the Ti/Ni metal layer 17. By forming the solder 19 so as to be widely spread toward the end of the Al layer 16, the effect of suppressing the generation of noise in the 1 to 6 GHz band can be further increased.

According to the above-mentioned voltage clamping planar diode, the first P ⁺ type impurity diffusion layer 13 is located on the surface side in the N-type epitaxial layer 12, and the second P ⁺ type impurity diffusion layer 14 having a higher breakdown voltage (e.g., a lower impurity concentration) than the first P ⁺ type impurity diffusion layer 13 is arranged so as to be in contact with the first P ⁺ type impurity diffusion layer 13 in a plan view and to surround the first P ⁺ type impurity diffusion layer 13. This allows a breakdown phenomenon to occur in the first P ⁺ type impurity diffusion layer 13 closer to the center than the second P ⁺ type impurity diffusion layer 14. In addition, by positioning the Al layer 16 as a metal plate on the first P ⁺ type impurity diffusion layer 13 and the insulating layer 15, the metal plate has a shielding effect. As a result, it is possible to suppress the generation of noise in the 1 to 6 GHz band from the above-mentioned voltage clamping planar diode, and a noise reduction effect is obtained.

1, the second P ⁺ type impurity diffusion layer 14 is made deeper than the first P ⁺ type impurity diffusion layer 13, so that the breakdown phenomenon location can be shifted closer to the center than to the end of the first P ⁺ type impurity diffusion layer 13. This can further increase the noise reduction effect.

In addition, in the voltage clamping planar diode shown in FIG. 1, a Ti/Ni metal layer 17 is formed as a second metal layer on an Al layer 16 as a first metal layer, and the Ti/Ni metal layer 17 is electrically connected to the Al layer 16. Therefore, the Al layer 16 and the Ti/Ni metal layer 17 are combined to form a metal plate 18, which provides a shielding effect. As a result, it is possible to prevent noise in the 1 to 6 GHz band from being emitted from the voltage clamping planar diode, and a noise reduction effect is obtained.

In addition, solder 19 is formed on the Ti/Ni metal layer 17 of the metal plate 18, and the metal plate 18 is electrically connected to the solder 19. Therefore, the solder 19 and the metal plate 18 together act as a shield, which can suppress the emission of noise in the 1 to 6 GHz band from the voltage clamp planar diode.

The impurity diffusion layer in the semiconductor device shown in Figures 1 to 5 is fabricated, for example, by patterning an oxide film by etching using a photoresist film as a mask, depositing and introducing impurities, and then performing a heat treatment. In addition, the layers and polyimide film located on the N-type epitaxial layer 12 are fabricated, for example, by sputtering, CVD (Chemical Vapor Deposition), coating, etching, etc.

Second Embodiment
<Planar diode for voltage clamping>
Fig. 6 is a cross-sectional view showing a semiconductor device according to one embodiment of the present invention, and the cross section corresponds to Fig. 1. In Fig. 6, the same parts as those in Fig. 1 are denoted by the same reference numerals, and description of the same parts will be omitted.

As shown in FIG. 6, a P ⁺ type impurity diffusion layer 13a (also referred to as a "second conductive type diffusion layer") is formed on the surface side of the N-type epitaxial layer 12 (also referred to as a "first conductive type semiconductor layer"). The P ⁺ type impurity diffusion layer 13a here includes the end portion 13b. An N-type buried layer 31 (also referred to as a "first conductive type buried layer") located in the N-type epitaxial layer 12 is formed below the P ⁺ type impurity diffusion layer 13a, and the N-type buried layer 31 has a higher impurity concentration than the N-type epitaxial layer 12. The N-type buried layer 31 is in contact with the P ⁺ type impurity diffusion layer 13a and is disposed inside the P ⁺ type impurity diffusion layer 13a in a plan view. In other words, end 13b of P ⁺ type impurity diffusion layer 13a does not contact N-type buried layer 31 but contacts N-type epitaxial layer 12, and is arranged so as to surround the portion where P ⁺ type impurity diffusion layer 13a contacts N-type buried layer 31 in a plan view.

In plan view, an insulating layer 15 is formed on the end 13b of the P ⁺ type impurity diffusion layer outside the N-type buried layer 31 and on the N-type epitaxial layer 12 outside the end 13b of the P ⁺ type impurity diffusion layer. An Al layer 16 (also called a "metal plate") is formed on the P ⁺ type impurity diffusion layer 13a, the end 13b of the P ⁺ type impurity diffusion layer, and the insulating layer 15.

According to this embodiment, the N-type buried layer 31 is formed inside the P ⁺ type impurity diffusion layer 13a in a plan view, and the P ⁺ type impurity diffusion layer 13a and the N-type buried layer 31 are in contact with each other. Therefore, the end 13b of the P ⁺ type impurity diffusion layer 13a located outside the N-type buried layer 31 in a plan view contacts the N-type epitaxial layer 12. Since the N-type epitaxial layer 12 has a lower impurity concentration than the N-type buried layer 31, the end 13b of the P ⁺ type impurity diffusion layer 13a located outside the N-type buried layer 31 has a higher breakdown voltage than the P ⁺ type impurity diffusion layer 13a in contact with the N-type buried layer 31. This allows a breakdown phenomenon to occur in the P ⁺ type impurity diffusion layer 13a closer to the center than the end 13b of the P ⁺ type impurity diffusion layer 13a. In addition, the Al layer 16 acts as a shielding effect by forming the Al layer 16 as a metal plate on the P ⁺ type impurity diffusion layer 13a and the insulating layer 15. As a result, it is possible to suppress the generation of noise in the 1 to 6 GHz band from the voltage clamp planar diode, thereby achieving a noise reduction effect.

Third Embodiment
<Mesa-type diode for voltage clamping>
Fig. 7 is a cross-sectional view showing a semiconductor device according to one aspect of the present invention. The semiconductor device shown in Fig. 7 is a voltage clamping mesa diode, and the same parts as those in Fig. 11 are given the same reference numerals and description of the same parts is omitted. The voltage clamping mesa diode shown in Fig. 7 is a mesa diode for voltage clamping according to the conventional voltage clamping mesa diode shown in Fig. 11 with the features of the first embodiment shown in Fig. 1 added thereto.

The voltage clamping mesa diode shown in FIG. 7 has an N ⁺⁺ type silicon substrate 101 (also referred to as a "first conductive type semiconductor substrate"). An N type epitaxial layer 102 (also referred to as a "first conductive type semiconductor layer") is formed on the N ⁺⁺ type silicon substrate 101. A first P ⁺⁺ type impurity diffusion layer 13 (also referred to as a "first second conductive type diffusion layer") is formed on the surface side of the N type epitaxial layer 102. A second P ⁺ type impurity diffusion layer 14 (also referred to as a "second second conductive type diffusion layer") is also formed in the N type epitaxial layer 102. The second P ⁺ type impurity diffusion layer 14 is arranged so as to be in contact with the first P ⁺ type impurity diffusion layer 13 in a plan view and to surround the first P ⁺ type impurity diffusion layer 13. The diode is configured so that a current flows in a semiconductor region located under a metal plate described later during clamping operation. The second P ⁺ type impurity diffusion layer 14 is formed to have a higher breakdown voltage than the first P ⁺ type impurity diffusion layer 13. In detail, the second P ⁺ type impurity diffusion layer 14 is formed to cause a breakdown phenomenon (Zener breakdown phenomenon, ^{avalanche breakdown phenomenon, or a mixture of Zener breakdown phenomenon and avalanche breakdown phenomenon) in the first P+ type} impurity diffusion layer 13 or in the vicinity of the contact portion between the second P+ type impurity diffusion layer 14 and the first P ⁺ type impurity diffusion layer 13. In order to realize this, as detailed typical examples, the impurity concentration gradient [0] of the second P + type impurity diffusion layer 14 is formed more gently [0] than the impurity concentration gradient of the first P ⁺ type impurity diffusion layer 13, as shown in the relationship between (2) shown in FIG. 3 and (1) shown in FIG. 3, (3) shown in FIG. 3 and (1) shown in FIG. 3, ⁽ 4) shown in FIG. 3 and (1) shown in FIG. 3, or (5) shown in FIG. 3 and (1) shown in FIG. 3. The impurity concentration gradient here refers to the absolute value of the rate of change of the impurity concentration that changes as it approaches the PN junction. Note that in FIG. 3, a typical Gaussian type change is assumed, and the impurity concentration simply decreases in the depth direction, but as long as the breakdown phenomenon occurs as described above, any distribution of the impurity concentration is acceptable, and is not limited to the example shown in FIG. 3. This is also true for other embodiments of the present invention. The second P ⁺ type impurity diffusion layer 14 may have a surface concentration higher, equal to, or lower than that of the first P ⁺ type impurity diffusion layer 13, and is preferably formed by diffusing deeper than the first P ⁺ type impurity diffusion layer 13.

7, an insulating layer 105 is formed on the second P ⁺ type impurity diffusion layer 14 and on the N-type epitaxial layer 102 on the outside of the second P ⁺ type impurity diffusion layer 14 in a plan view. An Al layer 16 (also called a "metal plate") is formed on the first P ⁺ type impurity diffusion layer 13, the second P ⁺ type impurity diffusion layer 14, and the insulating layer 15. The Al layer 16 is formed to extend to the outside of the second P ⁺ type impurity diffusion layer 14.

A Ti/Ni metal layer 17 (also referred to as a "second metal layer") is formed on the Al layer 16 (also referred to as a "first metal layer"), and the Ti/Ni metal layer 17 is electrically connected to the Al layer 16. As described above, the Al layer 16 may be a metal plate, but the Al layer 16 and the Ti/Ni metal layer 17 may be collectively referred to as a metal plate 18.

A polyimide film 27 is formed on the insulating layer 105 and the Al layer 16. Solder 19 is formed on the Ti/Ni metal layer 17.

This embodiment can achieve the same effects as the first embodiment.

(Fourth embodiment)
<Mesa-type diode for voltage clamping>
Fig. 9 is a cross-sectional view showing a semiconductor device according to one aspect of the present invention, in which the same parts as those in Fig. 7 are given the same reference numerals and the description of the same parts will be omitted. The semiconductor device shown in Fig. 9 is a voltage clamping mesa diode, which adds the features of the second embodiment shown in Fig. 6 to the conventional voltage clamping mesa diode shown in Fig. 11.

9, a P ⁺ type impurity diffusion layer 13a (also referred to as a "second conductive type diffusion layer") is formed on the surface side of an N-type epitaxial layer 102 (also referred to as a "first conductive type semiconductor layer"). An N-type buried layer 31 (also referred to as a "first conductive type buried layer") located in the N-type epitaxial layer 102 is formed below the P ⁺ type impurity diffusion layer 13a, and the N-type buried layer 31 has a higher impurity concentration than the N-type epitaxial layer 102. The N-type buried layer 31 is in contact with the P ⁺ type impurity diffusion layer 13a and is disposed inside the P ⁺ type impurity diffusion layer 13a in a plan view. In other words, the end 13b of the P ⁺ type impurity diffusion layer 13a does not contact the N-type buried layer 31 but contacts the N-type epitaxial layer 102, and is arranged so as to surround the portion where the P ⁺ type impurity diffusion layer 13a contacts the N-type buried layer 31 in a plan view.

In plan view, an insulating layer 105 is formed on the end 13b of the P ⁺ type impurity diffusion layer outside the N-type buried layer 31 and on the N-type epitaxial layer 102 outside the end 13b of the P ⁺ type impurity diffusion layer. An Al layer 16 (also called a "metal plate") is formed on the P ⁺ type impurity diffusion layer 13a, the end 13b of the P ⁺ type impurity diffusion layer, and the insulating layer 15.

This embodiment can achieve the same effects as the second embodiment.

Fifth Embodiment
<Resin-encapsulated semiconductor device>
FIG. 10 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.

10 includes an N ⁺⁺ type silicon substrate 11 (also referred to as a "first conductivity type semiconductor substrate"), a metal plate 18 formed on the N ⁺⁺ type silicon substrate 11, a first lead wire 21 formed on the metal plate 18 by electrically connecting it with a solder 19, and a second lead wire 22 electrically connected to the N ⁺⁺ type silicon substrate 11. The second lead wire 22 is electrically connected to an electrode 33 by a solder 34, and the electrode 33 is electrically connected to the N ⁺⁺ type silicon substrate 11. The metal plate 18 is preferably a plate having at least one metal layer selected from the group consisting of an Al layer, a Ni layer, a Ti layer, an Au layer, and a laminate of a Ni layer and an Al layer.

The N ⁺⁺ type silicon substrate 11, metal plate 18 and solder 19 shown in FIG. 10 can be applied to the semiconductor devices of the first to fourth embodiments shown in FIGS.

Furthermore, the N ⁺⁺ type silicon substrate 11 shown in Fig. 10 may be applied with a conventional voltage clamping mesa diode shown in Fig. 12. In detail, a voltage clamping mesa diode having an N ⁺⁺ type silicon substrate 101, an N type epitaxial layer 102 formed on the N ⁺⁺ type silicon substrate 101, a P ⁺⁺ type diffusion layer 103 formed on the front surface side of the N type epitaxial layer 102, and a first metal film 104 (also called a "metal plate") formed on the P ⁺⁺ type diffusion layer 103 may be applied.

Furthermore, a portion of each of the first lead wire 21 and the second lead wire 22 , the N ⁺⁺ type silicon substrate 11 , and the metal plate 18 are sealed with a resin 23 .

The surface of the resin 23 is covered with a shielding film 24, which is in contact with at least one of the first lead wire 21 and the second lead wire 22. The shielding film 24 is, for example, Shin-Etsu Resin: KMC140-9 or Kaken Tech shielding paste (CR-3911, 3913, 3915, 4000 to 4002).

In addition, the resin 23 is mixed with a material 35 having a higher dielectric constant than the resin 23. In FIG. 10, the material 35 having a higher dielectric constant is shown with three dots, but it is preferable that the material 35 having a higher dielectric constant is mixed with the resin 23 with good uniformity.

According to this embodiment, by covering the surface of the resin 23 with a shielding film 24 that contacts at least one of the first lead wire 21 and the second lead wire 22, the GHz-band noise emitted from the diode can be confined within the resin 23, thereby achieving a noise reduction effect.

In addition, in this embodiment, a portion of each of the first lead wire 21 and the second lead wire 22, the N ⁺⁺ type silicon substrate 11, and the metal plate 18 are sealed with resin 23, and a material with a high dielectric constant is mixed into this resin 23, so that this material with a high dielectric constant absorbs noise in the GHz band emitted from the diode and prevents the noise from being emitted outside the resin 23.

Sixth Embodiment
<Switching power supply unit>
Fig. 13 is a circuit diagram showing a switching power supply device according to one embodiment of the present invention, and Fig. 14 is a circuit diagram showing a switching power supply device using a DCR snubber 61 of a comparative example.
The switching power supply device shown in Fig. 13 includes a power clamper 51 including the semiconductor devices according to the first to fifth embodiments. The switching power supply device shown in Fig. 13 is obtained by replacing the DCR snubber 61 shown in Fig. 14 with the power clamper 51, and is mainly used in hard switching flyback power supply circuits and is applied to, for example, standby power supplies for televisions and copiers, indoor unit power supplies for air conditioners, etc.
The configurations of FIGS. 13 and 14 will be described below.
As shown in Fig. 14, the input voltage V _IN is applied between one electrode and the other electrode of the capacitor 54. One electrode of the capacitor 54 is electrically connected to one end of a resistor 62 of the DCR snubber 61 and one electrode of a capacitor 63. The other end of the resistor 62 is electrically connected to the other electrode of the capacitor 63 and the cathode of a fast recovery diode 64. The anode of the fast recovery diode 64 is electrically connected to one end of a primary winding of the transformer 56 and one electrode of a switching element 57. The other electrode of the switching element 57 is electrically connected to the other electrode of the capacitor 54. In addition, one electrode of the capacitor 63 is electrically connected to one end of a parasitic inductor 55, and the other end of the parasitic inductor 55 is electrically connected to the other end of the primary winding of the transformer 56. One end of a secondary winding of the transformer 56 is electrically connected to an anode of a diode 58, and the cathode of the diode 58 is electrically connected to one electrode of a capacitor 59. The other electrode of the capacitor 59 is electrically connected to the other end of the secondary winding of the transformer 56 , and an output voltage V _OUT is output between one electrode and the other electrode of the capacitor 59 .
The switching power supply device shown in FIG. 13 differs from the switching power supply device shown in FIG. 14 only in the following respects.
13, one electrode of the capacitor 54 is electrically connected to the anode of the Zener diode (avalanche diode) 53 of the power clamper 51 and one end of the parasitic inductor 55. The cathode of the Zener diode 53 is electrically connected to the cathode of the fast recovery diode 52. The anode of the fast recovery diode 52 is electrically connected to one end of the primary winding of the transformer 56 and one electrode of the switching element 57.

The first to sixth embodiments described above can also be implemented in combination with each other.

Figure 15 shows the results of an experiment conducted on the generation of noise in the GHz band (1 GHz to 6 GHz) from a sample of the voltage clamp planar diode shown in Figure 1. Details of the sample are shown in Table 1.

Ip shown in Figure 15 is the peak value of the breakdown current that flows due to the breakdown phenomenon of the diode. This graph plots the Ip value at which GHz-band noise begins to appear. It can be determined that the higher the Ip value, the greater the noise suppression effect.

The data in the box surrounded by (1) is the peak value of the breakdown current of the sample in which the second P ⁺ type impurity diffusion layer 14 shown in Fig. 1 has a ring structure as shown in Fig. 2, but the breakdown voltage of the second P ⁺ type impurity diffusion layer 14, which is the outer layer, is lower, and the breakdown occurs at the outer corner (ring portion) of the second P ⁺ type impurity diffusion layer 14. From the peak values of the breakdown current of these three samples, it can be seen that the noise suppression effect is improved when the metal plate (Al layer 16) which is the field plate (FP) is longer outward in a plan view (see Table 1 and Fig. 15). Note that the FP length is FP60<FP80.

The data in the box enclosed by (2) shows the peak value of the breakdown current of a sample that has breakdown in the first P ⁺ type impurity diffusion layer 13 shown in Figure 1, which is the inner shallow diffusion layer (bulk), but has no metal plate (Al layer 16). Comparing with the data of 1-1 in (1), it can be seen that the noise generation suppression effect is improved by causing breakdown on the inner side (first P ⁺ type impurity diffusion layer 13).

The data in the box marked with (3) is the peak value of the breakdown current of the sample that has breakdown in the first P ⁺ type impurity diffusion layer 13 shown in Fig. 1, which is the inner shallow diffusion layer (bulk), and has a metal plate (Al layer 16) that is an FP. From the peak values of the breakdown current of these four samples, it can be seen that the noise generation suppression effect is improved when the metal plate (Al layer 16) that is an FP is longer outward in a plan view (see Table 1 and Fig. 15).

The data in the box marked (4) is the result for the conventional planar diode structure shown in Figure 12, without FP. It is not subject to comparison with the present invention. Note that in Figure 12, the same reference numerals are used for the same parts as in Figure 6.

The data in the box (5) is the peak breakdown current value of samples (6-1st_B+FP60, 6-1st_B+FP80) with a FP (metal plate) attached to the planar diode shown in Figure 12 of the 6-1st_B sample (4).

The data in the box (6) is the peak value of the breakdown current of the sample with the longest FP pattern, which has a lower impurity concentration in the outer peripheral layer, the second P ⁺ type impurity diffusion layer 14 (secondary prototype), and a higher withstand voltage in the outer peripheral layer. In this sample, breakdown occurred in the inner layer (first P ⁺ type impurity diffusion layer 13), and the noise generation suppression effect was the highest.

The data in the box (7) is the result of comparing the fast recovery diode (FRD) to be combined with the voltage clamp planar diode of samples 6-9 in (3) when placed in a separate package with the same package. It is not subject to comparison with the present invention.

A comparison between sample 1-1 in (1) and sample 6-1 in (2) and a comparison between the six samples in (2) confirmed the effect of suppressing noise generation by causing breakdown on the inside (first P ⁺ type impurity diffusion layer 13).

It was confirmed that the longer the field plate is on the outside, the greater the effect of suppressing noise generation is, by comparing sample (1), sample (2) with sample (3), and sample (4) 6-1st_B with sample (5). The present invention has been described above based on the above embodiments and examples, but the present invention is not limited to the above embodiments. It is possible to implement the present invention in various aspects without departing from the spirit of the present invention.
The numbers, materials, shapes, positions, sizes, and other aspects of the components described in the above embodiments are merely examples and can be changed without impairing the effects of the present invention.

11 N ⁺⁺ type silicon substrate (first conductivity type semiconductor substrate)
12 N-type epitaxial layer (first conductivity type semiconductor layer)
13 First P ⁺ type impurity diffusion layer (first second conductive type diffusion layer)
13a P ⁺ type impurity diffusion layer (second conductive type diffusion layer)
13b End of P ⁺ type impurity diffusion layer (end of second conductive type diffusion layer)
14 Second P ⁺ type impurity diffusion layer (second second conductive type diffusion layer)
14b: second P ⁺ type impurity diffusion layer (second second conductive type diffusion layer)
15 Insulating layer 16 Al layer (first metal layer, metal plate)
17 Ti/Ni metal layer (second metal layer)
18 Metal plate 19 Solder 21 First lead wire 22 Second lead wire 23 Resin 24 Shielding film 31 N-type buried layer (first conductive type buried layer)
32 Al layer 101 N ⁺⁺ type silicon substrate (first conductivity type semiconductor substrate)
102 N-type epitaxial layer (first conductivity type semiconductor layer)
105 Insulating layer

Claims (15)

a semiconductor substrate of a first conductivity type;
a semiconductor layer of a first conductivity type located on the semiconductor substrate;
a first second conductivity type diffusion layer located on a surface side within the first conductivity type semiconductor layer;
a second second-conductivity-type diffusion layer that is located in the first-conductivity-type semiconductor layer, that is in contact with the first second-conductivity-type diffusion layer in a plan view, that is disposed so as to surround the first second-conductivity-type diffusion layer, and that is formed so as to have a higher breakdown voltage than the first second-conductivity-type diffusion layer;
an insulating layer located on the second second-conductivity type diffusion layer and on the semiconductor layer outside the second second-conductivity type diffusion layer in a plan view;
a metal plate located on the first second conductivity type diffusion layer, the second second conductivity type diffusion layer, and the insulating layer;
Including,
the second second-conductivity-type diffusion layer has a depth greater than that of the first second-conductivity-type diffusion layer;
a surface concentration of the second second-conductivity type diffusion layer being higher than that of the first second-conductivity type diffusion layer ; In claim 1,
a second diffusion layer of the second conductivity type having an impurity concentration gradient that is gentler than that of the first diffusion layer of the second conductivity type; a semiconductor substrate of a first conductivity type;
a semiconductor layer of a first conductivity type located on the semiconductor substrate;
a first second conductivity type diffusion layer located on a surface side within the first conductivity type semiconductor layer;
a second second-conductivity-type diffusion layer that is located in the first-conductivity-type semiconductor layer, that is in contact with the first second-conductivity-type diffusion layer in a plan view, that is disposed so as to surround the first second-conductivity-type diffusion layer, and that is formed so as to have a higher breakdown voltage than the first second-conductivity-type diffusion layer;
an insulating layer located on the second second-conductivity type diffusion layer and on the semiconductor layer outside the second second-conductivity type diffusion layer in a plan view;
a metal plate located on the first second conductivity type diffusion layer, the second second conductivity type diffusion layer, and the insulating layer;
Including ,
a depth of the second diffusion layer of the second conductivity type is shallower than a depth of the first diffusion layer of the second conductivity type. In claim 3 ,
a surface concentration of the second second-conductivity type diffusion layer being lower than a surface concentration of the first second-conductivity type diffusion layer; a semiconductor substrate of a first conductivity type;
a semiconductor layer of a first conductivity type located on the semiconductor substrate;
a first second conductivity type diffusion layer located on a surface side within the first conductivity type semiconductor layer;
a second second-conductivity-type diffusion layer that is located in the first-conductivity-type semiconductor layer, that is in contact with the first second-conductivity-type diffusion layer in a plan view, that is disposed so as to surround the first second-conductivity-type diffusion layer, and that is formed so as to have a higher breakdown voltage than the first second-conductivity-type diffusion layer;
an insulating layer located on the second second-conductivity type diffusion layer and on the semiconductor layer outside the second second-conductivity type diffusion layer in a plan view;
a metal plate located on the first second conductivity type diffusion layer, the second second conductivity type diffusion layer, and the insulating layer;
Including,
the second second-conductivity-type diffusion layer has a depth greater than that of the first second-conductivity-type diffusion layer;
a surface concentration of the second second-conductivity type diffusion layer being lower than a surface concentration of the first second-conductivity type diffusion layer; In any one of claims 1 to 5 ,
The semiconductor device is characterized in that the metal plate has a first metal layer and a second metal layer located on the first metal layer, and the first metal layer is electrically connected to the second metal layer. In any one of claims 1 to 6 ,
A semiconductor device having solder located on said metal plate. In claim 1 ,
solder located on the metal plate;
The semiconductor device according to claim 1, wherein the solder is located on the metal plate on each of the first second-conductivity type diffusion layer, the second second-conductivity type diffusion layer, and the insulating layer. In any one of claims 1 to 8 ,
a first lead wire electrically connected to the metal plate;
a second lead wire electrically connected to the semiconductor substrate;
a resin that seals a portion of each of the first lead wire and the second lead wire, the semiconductor substrate, and the metal plate;
a shielding film covering a surface of the resin;
having
The semiconductor device according to claim 1, wherein the shielding film is in contact with at least one of the first lead wire and the second lead wire. In any one of claims 1 to 8 ,
a first lead wire electrically connected to the metal plate;
a second lead wire electrically connected to the semiconductor substrate;
a resin that seals a portion of each of the first lead wire and the second lead wire, the semiconductor substrate, and the metal plate;
having
The semiconductor device according to the present invention is characterized in that the resin contains a material having a higher dielectric constant than the resin. a semiconductor substrate of a first conductivity type;
a semiconductor layer of a first conductivity type located on the semiconductor substrate;
a second conductive type diffusion layer located on a surface side within the first conductive type semiconductor layer;
a metal plate located on the second conductive type diffusion layer;
a first lead wire electrically connected to the metal plate;
a second lead wire electrically connected to the semiconductor substrate;
a resin that seals a portion of each of the first lead wire and the second lead wire, the semiconductor substrate, and the metal plate;
a shielding film covering a surface of the resin;
having
The semiconductor device according to claim 1, wherein the shielding film is in contact with at least one of the first lead wire and the second lead wire. In claim 9 or 11 ,
The semiconductor device according to the present invention is characterized in that the resin contains a material having a higher dielectric constant than the resin. a semiconductor substrate of a first conductivity type;
a semiconductor layer of a first conductivity type located on the semiconductor substrate;
a second conductive type diffusion layer located on a surface side within the first conductive type semiconductor layer;
a metal plate located on the second conductive type diffusion layer;
a first lead wire electrically connected to the metal plate;
a second lead wire electrically connected to the semiconductor substrate;
a resin that seals a portion of each of the first lead wire and the second lead wire, the semiconductor substrate, and the metal plate;
having
The semiconductor device according to the present invention is characterized in that the resin contains a material having a higher dielectric constant than the resin. In any one of claims 1 to 13 ,
The semiconductor device, wherein the metal plate has at least one metal layer selected from the group consisting of an Al layer, a Ni layer, a Ti layer, an Au layer, and a laminate of a Ni layer and an Al layer. A switching power supply comprising a power clamper including the semiconductor device according to claim 1 .

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